From: Gyorgy Sarvari <skandigraun@gmail.com>
To: mark.hatle@kernel.crashing.org, openembedded-core@lists.openembedded.org
Subject: Re: [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation
Date: Mon, 16 Jun 2025 12:11:14 +0200 [thread overview]
Message-ID: <56a9d083-72f6-44f2-be3a-29691745bcff@gmail.com> (raw)
In-Reply-To: <1750040965-15015-1-git-send-email-mark.hatle@kernel.crashing.org>
On 6/16/25 04:29, Mark Hatle via lists.openembedded.org wrote:
> From: Mark Hatle <mark.hatle@amd.com>
>
> The following implements the risc-v processor tune based on the ISA approach
> as documented in the oe-architecture post:
>
> https://lists.openembedded.org/g/openembedded-architecture/message/2155
>
> This set also attempts to make u-boot and kernel configurations dynamic
> based on the TUNE_FEATURES.
>
> For the linux-yocto, I suspect that the config fragments should be
> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and
> others before I do this.
>
> Additionally, this enables a new (optional) features_check for TUNE_FEATURES.
>
> I've found numerous items in the system have certain RISC-V ISA expectations
> that may need to be addressed over time, however the obvious one is the
> Linux kernel requires ima_zicsr_zifencei. Since it has it's own -march=
> setting this will ensure the processor defintion will be compatible.
>
> Also dynamically configure the QEMU cpu based on the tune_features. This
> is nice to ensure that what we're actually building should be able to run
> on real hardware. However, it does highlight some of the (extension)
> limitations in the current design. (limitations as in extension not yet
> enabled.)
>
> Note: OpenSBI _requires_ the 'c' extension or it will not execute. I
> suspect this can be fixed, but it's beyond my capabilities at this time.
>
I'm not a particularly advanced risc-v user, but I use qemuriscv64 to
run smoketests on Firefox, with a barely-extended core-image-sato.
After applying your this patch series, librsvg fails to compile with lot
of "undefined reference" errors[1]. I haven't looked into this at all
yet, hoping that someone would know the solution from the top of the
head. Does this need some magic Rust flag maybe?
Beside applying this series, I didn't do any other modifications, and
without these changes librsvg builds (did I miss some new config, or
another patch?) .
[1]: full log:
https://gist.githubusercontent.com/OldManYellsAtCloud/e9968f3c63df943e8fd54dc217ab15e6/raw
next prev parent reply other threads:[~2025-06-16 10:11 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-16 2:29 [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle
2025-06-16 2:29 ` [PATCH 1/6] riscv tunes: ISA Implementation of RISC-V tune features Mark Hatle
2025-06-16 10:11 ` [OE-core] " Richard Purdie
2025-06-16 14:21 ` Mark Hatle
2025-06-16 2:29 ` [PATCH 2/6] linux-yocto: Enable risc-v TUNE_FEATURES ISA selections Mark Hatle
2025-06-16 10:50 ` Bruce Ashfield
2025-06-16 2:29 ` [PATCH 3/6] u-boot: Dynamic RISC-V ISA configuration Mark Hatle
2025-06-16 2:29 ` [PATCH 4/6] qemuriscv: Dynamically configure qemu CPU Mark Hatle
2025-06-16 2:29 ` [PATCH 5/6] features_check.bbclass: Add support for required TUNE_FEATURES Mark Hatle
2025-06-16 2:29 ` [PATCH 6/6] linux-yocto.inc: State riscv required tune_features Mark Hatle
2025-06-16 11:05 ` [OE-core] " Bruce Ashfield
2025-06-16 14:07 ` Mark Hatle
2025-06-16 10:11 ` Gyorgy Sarvari [this message]
2025-06-16 14:12 ` [OE-core] [PATCH 0/6] ISA based RISC-V tune implementation Mark Hatle
[not found] ` <18498B713347A8EF.22186@lists.openembedded.org>
2025-06-16 16:00 ` Mark Hatle
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