[PATCH v3 0/6] ISA based RISC-V tune implementation

[PATCH v3 0/6] ISA based RISC-V tune implementation

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

The following implements the risc-v processor tune based on the ISA approach
as documented in the oe-architecture post:

https://lists.openembedded.org/g/openembedded-architecture/message/2155

This set also attempts to make u-boot and kernel configurations dynamic
based on the TUNE_FEATURES.

For the linux-yocto, I suspect that the config fragments should be
sent to the kmeta (kernel-cache), but I'd like a review from Bruce and
others before I do this.

Additionally, this enables a new (optional) features_check for TUNE_FEATURES.

I've found numerous items in the system have certain RISC-V ISA expectations
that may need to be addressed over time, however the obvious one is the
Linux kernel requires ima_zicsr_zifencei.  Since it has it's own -march=
setting this will ensure the processor defintion will be compatible.

Also dynamically configure the QEMU cpu based on the tune_features.  This
is nice to ensure that what we're actually building should be able to run
on real hardware.  However, it does highlight some of the (extension)
limitations in the current design.  (limitations as in extension not yet
enabled.)

Note: OpenSBI _requires_ the 'c' extension or it will not execute.  I
suspect this can be fixed, but it's beyond my capabilities at this time.

v3:
- The base implementation has been merged.  This is the remaining items for
  kernel dependencies, and linux.  (reworked to use yocto-kernel-cache)  as
  well as the u-boot and qemu items.  (These are the same as v2.)

As noted in 5/6, some of these dynamic ISA options seem to be adjusted by
other default settings.  Specifically CONFIG_ISA_C is enabled by CONFIG_EFI.

I did test various combinations with a custom defconfig (in qemu) to verify
that the code does what it should AND/OR reports any settings it couldn't
disable.

Tested combinations:

rv32ima_zicsr_zifencei
rv32imac_zicsr_zifencei
rv32gc
rv32imafdc_zicsr_zifencei

rv64ima_zicsr_zifencei
rv64imac_zicsr_zifencei
rv64gc
rv64gcv
rv64imafdc_zicsr_zifencei

Testing involved kernel disabling CONFIG_EFI, enabling CONFIG_NONPORTABLE
and the corresponding tune.

v2:

- Note: the linux-yocto change still needs further rework (noted in commit)
  (if everything else is merged, it will still work fine)

- Change the TUNE_FEATURES check to kernel.bbclass per review comments

- Add 7/7 patch for RUST configuration.

Mark Hatle (6):
  u-boot: Dynamic RISC-V ISA configuration
  features_check.bbclass: Add support for required TUNE_FEATURES
  kernel.bbclass: State riscv required tune_features for Linux
  linux-yocto/6.12: riscv: Enable dynamic ISA selection
  linux-yocto/6.12: riscv: Enable TUNE_FEATURES based KERNEL_FEATURES
  qemuriscv: Dynamically configure qemu CPU

 meta/classes-recipe/features_check.bbclass    |  2 +-
 meta/classes-recipe/kernel.bbclass            |  6 +++-
 meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
 .../u-boot/files/u-boot-riscv-isa_a.cfg       |  1 +
 .../u-boot/files/u-boot-riscv-isa_c.cfg       |  1 +
 .../u-boot/files/u-boot-riscv-isa_clear.cfg   |  6 ++++
 .../u-boot/files/u-boot-riscv-isa_d.cfg       |  1 +
 .../u-boot/files/u-boot-riscv-isa_f.cfg       |  1 +
 .../u-boot/files/u-boot-riscv-isa_zbb.cfg     |  1 +
 .../u-boot/files/u-boot-riscv-isa_zicbom.cfg  |  1 +
 meta/recipes-bsp/u-boot/u-boot-common.inc     | 12 +++++++
 .../linux/linux-yocto-rt_6.12.bb              |  2 +-
 .../linux/linux-yocto-tiny_6.12.bb            |  2 +-
 meta/recipes-kernel/linux/linux-yocto.inc     | 16 ++++++++++
 meta/recipes-kernel/linux/linux-yocto_6.12.bb |  2 +-
 15 files changed, 77 insertions(+), 8 deletions(-)
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg

-- 
2.34.1

[PATCH v3 1/6] u-boot: Dynamic RISC-V ISA configuration

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections
via config fragments.

This allows the following items to be selected dynamically:

    CONFIG_RISCV_ISA_C
    CONFIG_RISCV_ISA_F
    CONFIG_RISCV_ISA_D
    CONFIG_RISCV_ISA_ZBB
    CONFIG_RISCV_ISA_A
    CONFIG_RISCV_ISA_ZICBOM

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg |  1 +
 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg |  1 +
 .../u-boot/files/u-boot-riscv-isa_clear.cfg          |  6 ++++++
 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg |  1 +
 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg |  1 +
 .../u-boot/files/u-boot-riscv-isa_zbb.cfg            |  1 +
 .../u-boot/files/u-boot-riscv-isa_zicbom.cfg         |  1 +
 meta/recipes-bsp/u-boot/u-boot-common.inc            | 12 ++++++++++++
 8 files changed, 24 insertions(+)
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
 create mode 100644 meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg

diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
new file mode 100644
index 0000000000..fc45b64480
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_a.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_A=y
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
new file mode 100644
index 0000000000..1cb459f636
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_c.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_C=y
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
new file mode 100644
index 0000000000..ce90da23ce
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_clear.cfg
@@ -0,0 +1,6 @@
+# CONFIG_RISCV_ISA_C is not set
+# CONFIG_RISCV_ISA_F is not set
+# CONFIG_RISCV_ISA_D is not set
+# CONFIG_RISCV_ISA_ZBB is not set
+# CONFIG_RISCV_ISA_A is not set
+# CONFIG_RISCV_ISA_ZICBOM is not set
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
new file mode 100644
index 0000000000..fd25fa4e89
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_d.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_D=y
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
new file mode 100644
index 0000000000..dfa9876f82
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_f.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_F=y
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
new file mode 100644
index 0000000000..2b71b016f8
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zbb.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_ZBB=y
diff --git a/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg
new file mode 100644
index 0000000000..96daf04b20
--- /dev/null
+++ b/meta/recipes-bsp/u-boot/files/u-boot-riscv-isa_zicbom.cfg
@@ -0,0 +1 @@
+CONFIG_RISCV_ISA_ZICBOM=y
diff --git a/meta/recipes-bsp/u-boot/u-boot-common.inc b/meta/recipes-bsp/u-boot/u-boot-common.inc
index 617f5a60bb..8600d4bab6 100644
--- a/meta/recipes-bsp/u-boot/u-boot-common.inc
+++ b/meta/recipes-bsp/u-boot/u-boot-common.inc
@@ -16,6 +16,18 @@ SRCREV = "34820924edbc4ec7803eb89d9852f4b870fa760a"
 
 SRC_URI = "git://source.denx.de/u-boot/u-boot.git;protocol=https;branch=master;tag=v${PV}"
 
+SRC_URI_RISCV = "\
+    file://u-boot-riscv-isa_clear.cfg \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "a",      "file://u-boot-riscv-isa_a.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "f",      "file://u-boot-riscv-isa_f.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "d",      "file://u-boot-riscv-isa_d.cfg", "", d)} \
+    ${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",  "file://u-boot-riscv-isa_zbb.cfg", "", d)} \
+    ${@bb.utils.contains    ("TUNE_FEATURES", "zicbom", "file://u-boot-riscv-isa_zicbom.cfg", "", d)} \
+    "
+
+SRC_URI:append:riscv32 = "${SRC_URI_RISCV}"
+SRC_URI:append:riscv64 = "${SRC_URI_RISCV}"
+
 B = "${WORKDIR}/build"
 
 inherit pkgconfig
-- 
2.34.1

[PATCH v3 2/6] features_check.bbclass: Add support for required TUNE_FEATURES

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/classes-recipe/features_check.bbclass | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meta/classes-recipe/features_check.bbclass b/meta/classes-recipe/features_check.bbclass
index 4e122ecaef..1e0eaa4eed 100644
--- a/meta/classes-recipe/features_check.bbclass
+++ b/meta/classes-recipe/features_check.bbclass
@@ -21,7 +21,7 @@ python () {
 
     unused = True
 
-    for kind in ['DISTRO', 'MACHINE', 'COMBINED', 'IMAGE']:
+    for kind in ['DISTRO', 'MACHINE', 'COMBINED', 'IMAGE', 'TUNE']:
         if d.getVar('ANY_OF_' + kind + '_FEATURES') is None and not d.hasOverrides('ANY_OF_' + kind + '_FEATURES') and \
            d.getVar('REQUIRED_' + kind + '_FEATURES') is None and not d.hasOverrides('REQUIRED_' + kind + '_FEATURES') and \
            d.getVar('CONFLICT_' + kind + '_FEATURES') is None and not d.hasOverrides('CONFLICT_' + kind + '_FEATURES'):
-- 
2.34.1

[PATCH v3 3/6] kernel.bbclass: State riscv required tune_features for Linux

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

Required:
   rv32ima_zicsr_zifencei
   rv64ima_zicsr_zifencei

See the arch/riscv/Makefile:

riscv-march-$(CONFIG_ARCH_RV32I)	:= rv32ima
riscv-march-$(CONFIG_ARCH_RV64I)	:= rv64ima
riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/classes-recipe/kernel.bbclass | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/meta/classes-recipe/kernel.bbclass b/meta/classes-recipe/kernel.bbclass
index 2d9943c8a0..eb03424dfc 100644
--- a/meta/classes-recipe/kernel.bbclass
+++ b/meta/classes-recipe/kernel.bbclass
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: MIT
 #
 
-inherit linux-kernel-base kernel-module-split
+inherit linux-kernel-base kernel-module-split features_check
 
 COMPATIBLE_HOST = ".*-linux"
 
+# Linux has a minimum ISA requires on riscv, see arch/riscv/Makefile
+REQUIRED_TUNE_FEATURES:riscv32 = "rv 32 i m a zicsr zifencei"
+REQUIRED_TUNE_FEATURES:riscv64 = "rv 64 i m a zicsr zifencei"
+
 KERNEL_PACKAGE_NAME ??= "kernel"
 KERNEL_DEPLOYSUBDIR ??= "${@ "" if (d.getVar("KERNEL_PACKAGE_NAME") == "kernel") else d.getVar("KERNEL_PACKAGE_NAME") }"
 
-- 
2.34.1

[PATCH v3 4/6] linux-yocto/6.12: riscv: Enable dynamic ISA selection

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

The updated yocto-kernel-cache introduces risc-v ISA selection, move commit
to allow these KERNEL_FEATURES to be selected.

Changelog:
    arch/riscv/tunes: Implement RISC-V ISA selection
    amd-zynqmp: crypto: Kconfig: Obsolete DEV_XILINX_RSA config option
    bsp: add new bsp amd-zynq
    nxp-imx9: Enable NEUTRON for i.MX95-19x19-verdin
    kver: bumping to v6.12.33
    preempt-rt.scc: enable firmware loading support for rt kernel
    intel-socfpga: enable intel-socfpga support for yocto-6.12
    nxp-imx9: Enable enetc for nxp-imx95
    nxp-imx9: Enable multimedia related configs for nxp-imx95
    nxp-imx9: Enable devfreq governors
    fs/yaffs2: fix build warnings in yaffs_vfs.c when running make allyesconfig
    ti-am335x: add kernel-cache configuration for v6.12 kernel
    nvidia-orin: enable config to support EFI GUID Partition
    nvidia-orin: enable configs I2C GPIO expander tca9534
    nvidia-orin: enable configs to support efivarfs feature
    bsp: add new bsp amd-zynqmp
    kver: bumping to v6.12.32
    nxp-imx9: Enable PHY_FSL_IMX9_DPHY_RX for nxp-imx9

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/recipes-kernel/linux/linux-yocto-rt_6.12.bb   | 2 +-
 meta/recipes-kernel/linux/linux-yocto-tiny_6.12.bb | 2 +-
 meta/recipes-kernel/linux/linux-yocto_6.12.bb      | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/meta/recipes-kernel/linux/linux-yocto-rt_6.12.bb b/meta/recipes-kernel/linux/linux-yocto-rt_6.12.bb
index 5a7bad9017..da0dea21fb 100644
--- a/meta/recipes-kernel/linux/linux-yocto-rt_6.12.bb
+++ b/meta/recipes-kernel/linux/linux-yocto-rt_6.12.bb
@@ -15,7 +15,7 @@ python () {
 }
 
 SRCREV_machine ?= "7cb6d42c40de351ecab0a083aef260f84407de0d"
-SRCREV_meta ?= "60b8562e9989f268ad5d241989f56b71cfa1f648"
+SRCREV_meta ?= "d32aa55c8954b11e8e29627e82df6180b2efc4fd"
 
 SRC_URI = "git://git.yoctoproject.org/linux-yocto.git;branch=${KBRANCH};name=machine;protocol=https \
            git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-6.12;destsuffix=${KMETA};protocol=https"
diff --git a/meta/recipes-kernel/linux/linux-yocto-tiny_6.12.bb b/meta/recipes-kernel/linux/linux-yocto-tiny_6.12.bb
index 0fad73dddd..1e08082697 100644
--- a/meta/recipes-kernel/linux/linux-yocto-tiny_6.12.bb
+++ b/meta/recipes-kernel/linux/linux-yocto-tiny_6.12.bb
@@ -18,7 +18,7 @@ KMETA = "kernel-meta"
 KCONF_BSP_AUDIT_LEVEL = "2"
 
 SRCREV_machine ?= "298aefdf4112e7c0a84522e4acf2c722e433c8a0"
-SRCREV_meta ?= "60b8562e9989f268ad5d241989f56b71cfa1f648"
+SRCREV_meta ?= "d32aa55c8954b11e8e29627e82df6180b2efc4fd"
 
 PV = "${LINUX_VERSION}+git"
 
diff --git a/meta/recipes-kernel/linux/linux-yocto_6.12.bb b/meta/recipes-kernel/linux/linux-yocto_6.12.bb
index 262ae35704..5ad858df2a 100644
--- a/meta/recipes-kernel/linux/linux-yocto_6.12.bb
+++ b/meta/recipes-kernel/linux/linux-yocto_6.12.bb
@@ -29,7 +29,7 @@ SRCREV_machine:qemux86 ?= "298aefdf4112e7c0a84522e4acf2c722e433c8a0"
 SRCREV_machine:qemux86-64 ?= "298aefdf4112e7c0a84522e4acf2c722e433c8a0"
 SRCREV_machine:qemumips64 ?= "6470f58a8f04951f202cf85afb4421d2e7ec9995"
 SRCREV_machine ?= "298aefdf4112e7c0a84522e4acf2c722e433c8a0"
-SRCREV_meta ?= "60b8562e9989f268ad5d241989f56b71cfa1f648"
+SRCREV_meta ?= "d32aa55c8954b11e8e29627e82df6180b2efc4fd"
 
 # set your preferred provider of linux-yocto to 'linux-yocto-upstream', and you'll
 # get the <version>/base branch, which is pure upstream -stable, and the same
-- 
2.34.1

[PATCH v3 5/6] linux-yocto/6.12: riscv: Enable TUNE_FEATURES based KERNEL_FEATURES

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

Allow the risc-v TUNE_FEATURES to select specific ISA (kconfig) selections
in the kernel config via config fragments selected by KERNEL_FEATURES.

This allows the following items to be selected dynamically:

    CONFIG_ARCH_RV32I
    CONFIG_ARCH_RV64I
    CONFIG_FPU
    CONFIG_RISCV_ISA_C
    CONFIG_RISCV_ISA_V
    CONFIG_RISCV_ISA_ZBB
    CONFIG_RISCV_ISA_ZICBOM
    CONFIG_RISCV_ISA_ZICBOZ
    CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI

Note: Some ISA options, such as CONFIG_RISCV_ISA_C may be reenabled by other
options such as CONFIG_EFI.  This is properly reported by the configuration
tooling.

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/recipes-kernel/linux/linux-yocto.inc | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/meta/recipes-kernel/linux/linux-yocto.inc b/meta/recipes-kernel/linux/linux-yocto.inc
index 389329030d..4d0a726bb6 100644
--- a/meta/recipes-kernel/linux/linux-yocto.inc
+++ b/meta/recipes-kernel/linux/linux-yocto.inc
@@ -37,6 +37,22 @@ KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'efi', 'cfg/
 KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'numa', 'features/numa/numa.scc', '', d)}"
 KERNEL_FEATURES:append = " ${@bb.utils.contains('MACHINE_FEATURES', 'vfat', 'cfg/fs/vfat.scc', '', d)}"
 
+KERNEL_FEATURES_RISCV = "\
+    arch/riscv/tunes/riscv-isa-clear.scc \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'rv 32 i m a', 'arch/riscv/tunes/riscv-isa-rv32i.scc',  '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'rv 64 i m a', 'arch/riscv/tunes/riscv-isa-rv64i.scc',  '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'f d',         'arch/riscv/tunes/riscv-isa-fpu.scc',    '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'c',           'arch/riscv/tunes/riscv-isa-c.scc',      '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'v',           'arch/riscv/tunes/riscv-isa-v.scc',      '', d)} \
+    ${@bb.utils.contains_any('TUNE_FEATURES', 'b zba',       'arch/riscv/tunes/riscv-isa-zba.scc',    '', d)} \
+    ${@bb.utils.contains_any('TUNE_FEATURES', 'b zbb',       'arch/riscv/tunes/riscv-isa-zbb.scc',    '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'zbc',         'arch/riscv/tunes/riscv-isa-zbc.scc',    '', d)} \
+    ${@bb.utils.contains(    'TUNE_FEATURES', 'zicbom',      'arch/riscv/tunes/riscv-isa-zicbom.scc', '', d)} \
+    "
+
+KERNEL_FEATURES:append:riscv32 = " ${KERNEL_FEATURES_RISCV}"
+KERNEL_FEATURES:append:riscv64 = " ${KERNEL_FEATURES_RISCV}"
+
 # A KMACHINE is the mapping of a yocto $MACHINE to what is built
 # by the kernel. This is typically the branch that should be built,
 # and it can be specific to the machine or shared
-- 
2.34.1

[PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU

[Mark Hatle]

From: Mark Hatle <mark.hatle@amd.com>

Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
options selected by the DEFAULTTUNE.

Note: OpenSBI currently requires 'c' (compressed instructions) or it will
not work.

Change the base device configuration to use a different variable to select
the emulate devices.  This will allow a user to override or append the
QB_OPT_APPEND without the riscv32 override getting in the way.

Signed-off-by: Mark Hatle <mark.hatle@amd.com>
---
 meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
 1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/meta/conf/machine/include/riscv/qemuriscv.inc b/meta/conf/machine/include/riscv/qemuriscv.inc
index 65cbfd66ee..91a84cdd39 100644
--- a/meta/conf/machine/include/riscv/qemuriscv.inc
+++ b/meta/conf/machine/include/riscv/qemuriscv.inc
@@ -27,7 +27,6 @@ UBOOT_ENTRYPOINT:riscv64 = "0x80200000"
 # qemuboot options
 QB_SMP ?= "-smp 4"
 QB_KERNEL_CMDLINE_APPEND = "earlycon=sbi"
-QB_CPU:riscv64 ?= "-cpu rva22s64"
 QB_MACHINE = "-machine virt"
 QB_DEFAULT_BIOS = "fw_jump.elf"
 QB_TAP_OPT = "-netdev tap,id=net0,ifname=@TAP@,script=no,downscript=no"
@@ -36,5 +35,31 @@ QB_ROOTFS_OPT = "-drive id=disk0,file=@ROOTFS@,if=none,format=raw -device virtio
 QB_SERIAL_OPT = "-device virtio-serial-device -chardev null,id=virtcon -device virtconsole,chardev=virtcon"
 QB_TCPSERIAL_OPT = " -device virtio-serial-device -chardev socket,id=virtcon,port=@PORT@,host=127.0.0.1,nodelay=on -device virtconsole,chardev=virtcon"
 QB_GRAPHICS = "-device bochs-display"
-QB_OPT_APPEND = "-device qemu-xhci -device usb-tablet -device usb-kbd"
-QB_OPT_APPEND:riscv32 = "-device virtio-tablet-pci -device virtio-keyboard-pci"
+QB_OPT_APPEND = "${RV_QEMU_ISA} ${RV_QEMU_DEVICES}"
+
+RV_QEMU_DEVICES = "-device qemu-xhci -device usb-tablet -device usb-kbd"
+RV_QEMU_DEVICES:riscv32 = "-device virtio-tablet-pci -device virtio-keyboard-pci"
+
+RV_QEMU_ISA = "-cpu "
+# Choose rv32 or rv64
+RV_QEMU_ISA .= "${@bb.utils.contains("TUNE_FEATURES", "rv 32", "rv32", "", d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains("TUNE_FEATURES", "rv 64", "rv64", "", d)}"
+# Disable all of the default extensions we don't support
+RV_QEMU_ISA .= ",zihintntl=false,zihintpause=false,zawrs=false,zfa=false,svadu=false,zicntr=false,zihpm=false"
+RV_QEMU_ISA .= ",zicboz=false,zicbop=false,zmmul=false,sstc=false,h=false"
+# Dynamically enable the extensions based on TUNE_FEATURES
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "m",         ",m=true",        ",m=false",        d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "a",         ",a=true",        ",a=false",        d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d",       ",f=true",        ",f=false",        d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "d",         ",d=true",        ",d=false",        d)}"
+# OpenSBI fails to boot without 'c'
+#RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "c",         ",c=true",        ",c=false",        d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "v",         ",v=true",        ",v=false",        d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "zicbom",    ",zicbom=true",   ",zicbom=false",   d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", ",zicsr=true",    ",zicsr=false",    d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "zifencei",  ",zifencei=true", ",zifencei=false", d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba",     ",zba=true",      ",zba=false",      d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb",     ",zbb=true",      ",zbb=false",      d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains    ("TUNE_FEATURES", "zbc",       ",zbc=true",      ",zbc=false",      d)}"
+RV_QEMU_ISA .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs",     ",zbs=true",      ",zbs=false",      d)}"
+
-- 
2.34.1

Re: [OE-core] [PATCH v3 0/6] ISA based RISC-V tune implementation

[Richard Purdie]

Hi Mark,

On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
> From: Mark Hatle <mark.hatle@amd.com>
> 
> The following implements the risc-v processor tune based on the ISA approach
> as documented in the oe-architecture post:
> 
> https://lists.openembedded.org/g/openembedded-architecture/message/2155
> 
> This set also attempts to make u-boot and kernel configurations dynamic
> based on the TUNE_FEATURES.
> 
> For the linux-yocto, I suspect that the config fragments should be
> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and
> others before I do this.
> 
> Additionally, this enables a new (optional) features_check for TUNE_FEATURES.
> 
> I've found numerous items in the system have certain RISC-V ISA expectations
> that may need to be addressed over time, however the obvious one is the
> Linux kernel requires ima_zicsr_zifencei.  Since it has it's own -march=
> setting this will ensure the processor defintion will be compatible.
> 
> Also dynamically configure the QEMU cpu based on the tune_features.  This
> is nice to ensure that what we're actually building should be able to run
> on real hardware.  However, it does highlight some of the (extension)
> limitations in the current design.  (limitations as in extension not yet
> enabled.)
> 
> Note: OpenSBI _requires_ the 'c' extension or it will not execute.  I
> suspect this can be fixed, but it's beyond my capabilities at this time.

I've narrowed it down to something in these patches which causes these
ptest failures on qemuriscv64:

https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/187

We need to track down and fix those regressions before this can merge.

Cheers,

Richard

Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU

[Richard Purdie]

On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
> From: Mark Hatle <mark.hatle@amd.com>
> 
> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
> options selected by the DEFAULTTUNE.
> 
> Note: OpenSBI currently requires 'c' (compressed instructions) or it will
> not work.
> 
> Change the base device configuration to use a different variable to select
> the emulate devices.  This will allow a user to override or append the
> QB_OPT_APPEND without the riscv32 override getting in the way.
> 
> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
> ---
>  meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>  1 file changed, 28 insertions(+), 3 deletions(-)
> 

FWIW I narrowed down the ptest failures to this patch.

Cheers,

Richard

Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU

[Mark Hatle]

I will investigate.

I suspect SOME of this may be test cases with hard coded riscv assembly in them 
using extensions that we've not enabled.

The configuration listed in the logs for the kernel are:

rv64imafdc

  '[    0.000000] riscv: base ISA extensions acdfim\n'
  '[    0.000000] riscv: ELF capabilities acdfim\n'

The 'v' (vector) extension is intentionally not enabled to match the software 
configuration, but some tests may be trying to use it.

I'll walk through this and attempt to get this identified for real.

--Mark

On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
>> From: Mark Hatle <mark.hatle@amd.com>
>>
>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>> options selected by the DEFAULTTUNE.
>>
>> Note: OpenSBI currently requires 'c' (compressed instructions) or it will
>> not work.
>>
>> Change the base device configuration to use a different variable to select
>> the emulate devices.  This will allow a user to override or append the
>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>
>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>> ---
>>   meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>   1 file changed, 28 insertions(+), 3 deletions(-)
>>
> 
> FWIW I narrowed down the ptest failures to this patch.
> 
> Cheers,
> 
> Richard
> 
> 
> 
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> 

Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU

[Khem Raj]

On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote:
> I will investigate.
> 
> I suspect SOME of this may be test cases with hard coded riscv assembly 
> in them using extensions that we've not enabled.
> 
> The configuration listed in the logs for the kernel are:
> 
> rv64imafdc
> 
>   '[    0.000000] riscv: base ISA extensions acdfim\n'
>   '[    0.000000] riscv: ELF capabilities acdfim\n'
> 
> The 'v' (vector) extension is intentionally not enabled to match the 
> software configuration, but some tests may be trying to use it.
> 
> I'll walk through this and attempt to get this identified for real.


We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since
that is the baseline for a RISCV profile that OE will be used as base 
infrastructure and we should target that commonly, perhaps changing 
default tune for qemuriscv64 to consider that would be a good thing. I 
know there is
a value in constructing the ISA+extension set that qemu emulates based 
on tune selection and whatever rv64gcv devolves down in terms of 
extensions.

> 
> --Mark
> 
> On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
>> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via 
>> lists.openembedded.org wrote:
>>> From: Mark Hatle <mark.hatle@amd.com>
>>>
>>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>>> options selected by the DEFAULTTUNE.
>>>
>>> Note: OpenSBI currently requires 'c' (compressed instructions) or it 
>>> will
>>> not work.
>>>
>>> Change the base device configuration to use a different variable to 
>>> select
>>> the emulate devices.  This will allow a user to override or append the
>>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>>
>>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>>> ---
>>>   meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>>   1 file changed, 28 insertions(+), 3 deletions(-)
>>>
>>
>> FWIW I narrowed down the ptest failures to this patch.
>>
>> Cheers,
>>
>> Richard
>>
>>
>>
>>
>>
> 
> 
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> Mute This Topic: https://lists.openembedded.org/mt/113956553/1997914
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Re: [OE-core] [PATCH v3 0/6] ISA based RISC-V tune implementation

[Khem Raj]

On 7/9/25 12:42 AM, Richard Purdie via lists.openembedded.org wrote:
> Hi Mark,
> 
> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via lists.openembedded.org wrote:
>> From: Mark Hatle <mark.hatle@amd.com>
>>
>> The following implements the risc-v processor tune based on the ISA approach
>> as documented in the oe-architecture post:
>>
>> https://lists.openembedded.org/g/openembedded-architecture/message/2155
>>
>> This set also attempts to make u-boot and kernel configurations dynamic
>> based on the TUNE_FEATURES.
>>
>> For the linux-yocto, I suspect that the config fragments should be
>> sent to the kmeta (kernel-cache), but I'd like a review from Bruce and
>> others before I do this.
>>
>> Additionally, this enables a new (optional) features_check for TUNE_FEATURES.
>>
>> I've found numerous items in the system have certain RISC-V ISA expectations
>> that may need to be addressed over time, however the obvious one is the
>> Linux kernel requires ima_zicsr_zifencei.  Since it has it's own -march=
>> setting this will ensure the processor defintion will be compatible.
>>
>> Also dynamically configure the QEMU cpu based on the tune_features.  This
>> is nice to ensure that what we're actually building should be able to run
>> on real hardware.  However, it does highlight some of the (extension)
>> limitations in the current design.  (limitations as in extension not yet
>> enabled.)
>>
>> Note: OpenSBI _requires_ the 'c' extension or it will not execute.  I
>> suspect this can be fixed, but it's beyond my capabilities at this time.
> 
> I've narrowed it down to something in these patches which causes these
> ptest failures on qemuriscv64:
> 
> https://autobuilder.yoctoproject.org/valkyrie/#/builders/56/builds/187
> 
> We need to track down and fix those regressions before this can merge.
> 

I think the extension selection should match the base platform spec for
rvb23 profile for default qemu machine, perhaps something regressed 
there with Mark's extension based construction of default tunes.

> Cheers,
> 
> Richard
> 
> 
> 
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> Mute This Topic: https://lists.openembedded.org/mt/113956552/1997914
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> 

Re: [OE-core] [PATCH v3 6/6] qemuriscv: Dynamically configure qemu CPU

[Mark Hatle]

On 7/9/25 11:23 AM, Khem Raj wrote:
> 
> 
> On 7/9/25 7:54 AM, Mark Hatle via lists.openembedded.org wrote:
>> I will investigate.
>>
>> I suspect SOME of this may be test cases with hard coded riscv assembly
>> in them using extensions that we've not enabled.
>>
>> The configuration listed in the logs for the kernel are:
>>
>> rv64imafdc
>>
>>    '[    0.000000] riscv: base ISA extensions acdfim\n'
>>    '[    0.000000] riscv: ELF capabilities acdfim\n'
>>
>> The 'v' (vector) extension is intentionally not enabled to match the
>> software configuration, but some tests may be trying to use it.
>>
>> I'll walk through this and attempt to get this identified for real.
> 
> 
> We should be enabling the rvb23 (rv64gcv) profile as default for qemu, since
> that is the baseline for a RISCV profile that OE will be used as base
> infrastructure and we should target that commonly, perhaps changing

I disagree that the 'baseline' should be rv64gcv.  Because this is a variable 
ISA, we need the baseline to be something reasonably common across multiple 
vendors.  (Note, I didn't say all vendors).  rv64gc seems to be common from the 
research I did, the 'v' is also available, but not as widely available on 
non-workstation oriented chips.

> default tune for qemuriscv64 to consider that would be a good thing. I
> know there is
> a value in constructing the ISA+extension set that qemu emulates based
> on tune selection and whatever rv64gcv devolves down in terms of
> extensions.

BEFORE my work, the tune was "riscv64".  (I maintained this after as well)

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/arch-riscv.inc?h=walnascar

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/tune-riscv.inc?h=walnascar

This mapped to rv64gc (NO V), so that is what I implemented.  How did I 
determine it was rv64gc and not rv64gcv?  I queried the compiler to see what the 
default options were since the ISA was not defined anywhere.

If we want to move to rv64gcv, then that can be adjusted in:

https://git.yoctoproject.org/poky/tree/meta/conf/machine/include/riscv/tune-riscv.inc

Just change the 'riscv64' configuration to add the 'v'.

I don't really care what our default is as long as someone defined it and tests 
it.  BUT I do care that NOT using our default WILL continue to work.

Just moving to rv64gcv unconditionally isn't right.  Not all riscv cores have 
vector units, or even the compressed extension, let along f/d floating point. 
So we have to be flexible or there is no purpose to this work.


I believe it's key for the RISC-V sponsors who will end up owning this work to 
speak up.  I can say what I know, you can say when you know -- but ultimately 
I'm only going to be doing this work until it meets my needs and then I'm going 
to step back while other people implement what they need.  (I'm not going to 
abandon it, but I need the work _now_, so I had to step in to implement it.)

What we do NOT have to be is platform that runs portable code with Ubuntu/Red 
Hat and others.

For _MY_ purposes, _MY_ chips do not have a vector unit, my rv32 do not have 
double precision floating point (only single).  Additional the following items 
are all user selectable:

rv32i vs rv32e (e is not compatible with Linux, but is with baremetal!)
rv64i

m - optional
a - optional
f - optional
d - only available with rv64i
c - optional (not recommended)
(as well as some z extensions)

Linux REQUIRES rv<size>ima

It does not require fdc (or v) as well as the z extensions (except for zicsr and 
zifencei).

--Mark


>>
>> --Mark
>>
>> On 7/9/25 4:17 AM, Richard Purdie via lists.openembedded.org wrote:
>>> On Wed, 2025-07-02 at 16:44 -0500, Mark Hatle via
>>> lists.openembedded.org wrote:
>>>> From: Mark Hatle <mark.hatle@amd.com>
>>>>
>>>> Use TUNE_FEATURES to dynamically configure the QEMU emulated CPU for the
>>>> options selected by the DEFAULTTUNE.
>>>>
>>>> Note: OpenSBI currently requires 'c' (compressed instructions) or it
>>>> will
>>>> not work.
>>>>
>>>> Change the base device configuration to use a different variable to
>>>> select
>>>> the emulate devices.  This will allow a user to override or append the
>>>> QB_OPT_APPEND without the riscv32 override getting in the way.
>>>>
>>>> Signed-off-by: Mark Hatle <mark.hatle@amd.com>
>>>> ---
>>>>    meta/conf/machine/include/riscv/qemuriscv.inc | 31 +++++++++++++++++--
>>>>    1 file changed, 28 insertions(+), 3 deletions(-)
>>>>
>>>
>>> FWIW I narrowed down the ptest failures to this patch.
>>>
>>> Cheers,
>>>
>>> Richard
>>>
>>>
>>>
>>>
>>>
>>
>>
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>>