From: Rob Herring <robh@kernel.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 09/12] sh: Use of_get_cpu_hwid()
Date: Wed, 6 Oct 2021 11:43:29 -0500 [thread overview]
Message-ID: <20211006164332.1981454-10-robh@kernel.org> (raw)
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Rich Felker <dalias@libc.org>
Cc: linux-sh at vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/sh/boards/of-generic.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/sh/boards/of-generic.c b/arch/sh/boards/of-generic.c
index 921d76fc3358..f7f3e618e85b 100644
--- a/arch/sh/boards/of-generic.c
+++ b/arch/sh/boards/of-generic.c
@@ -62,9 +62,8 @@ static void sh_of_smp_probe(void)
init_cpu_possible(cpumask_of(0));
for_each_of_cpu_node(np) {
- const __be32 *cell = of_get_property(np, "reg", NULL);
- u64 id = -1;
- if (cell) id = of_read_number(cell, of_n_addr_cells(np));
+ u64 id = of_get_cpu_hwid(np, 0);
+
if (id < NR_CPUS) {
if (!method)
of_property_read_string(np, "enable-method", &method);
--
2.30.2
next prev parent reply other threads:[~2021-10-06 16:43 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 16:43 [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes Rob Herring
2021-10-18 13:26 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 02/12] ARM: Use of_get_cpu_hwid() Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 03/12] ARM: broadcom: " Rob Herring
2021-10-07 2:24 ` Florian Fainelli
2021-10-06 16:43 ` [OpenRISC] [PATCH 04/12] arm64: " Rob Herring
2021-10-07 8:07 ` Will Deacon
2021-10-18 13:27 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 05/12] csky: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 06/12] openrisc: " Rob Herring
2021-10-06 20:44 ` Stafford Horne
2021-10-06 21:08 ` Rob Herring
2021-10-06 21:25 ` Stafford Horne
2021-10-06 21:27 ` Segher Boessenkool
2021-10-06 22:37 ` Stafford Horne
2021-10-07 7:53 ` David Laight
2021-10-06 16:43 ` [OpenRISC] [PATCH 07/12] powerpc: " Rob Herring
2021-10-08 11:01 ` Michael Ellerman
2021-10-06 16:43 ` [OpenRISC] [PATCH 08/12] riscv: " Rob Herring
2021-10-06 16:43 ` Rob Herring [this message]
2021-10-27 14:26 ` [OpenRISC] [PATCH 09/12] sh: " Rich Felker
2021-10-06 16:43 ` [OpenRISC] [PATCH 10/12] x86: dt: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id' Rob Herring
2021-10-18 13:30 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 12/12] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-10-18 13:31 ` Sudeep Holla
2021-10-07 2:24 ` [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Florian Fainelli
2021-10-20 18:47 ` Rob Herring
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