From: Rob Herring <robh@kernel.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 04/12] arm64: Use of_get_cpu_hwid()
Date: Wed, 6 Oct 2021 11:43:24 -0500 [thread overview]
Message-ID: <20211006164332.1981454-5-robh@kernel.org> (raw)
In-Reply-To: <20211006164332.1981454-1-robh@kernel.org>
Replace the open coded parsing of CPU nodes' 'reg' property with
of_get_cpu_hwid().
This change drops an error message for missing 'reg' property, but that
should not be necessary as the DT tools will ensure 'reg' is present.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
---
arch/arm64/kernel/smp.c | 31 ++-----------------------------
1 file changed, 2 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
index 6f6ff072acbd..c5cebc406d24 100644
--- a/arch/arm64/kernel/smp.c
+++ b/arch/arm64/kernel/smp.c
@@ -466,33 +466,6 @@ void __init smp_prepare_boot_cpu(void)
kasan_init_hw_tags();
}
-static u64 __init of_get_cpu_mpidr(struct device_node *dn)
-{
- const __be32 *cell;
- u64 hwid;
-
- /*
- * A cpu node with missing "reg" property is
- * considered invalid to build a cpu_logical_map
- * entry.
- */
- cell = of_get_property(dn, "reg", NULL);
- if (!cell) {
- pr_err("%pOF: missing reg property\n", dn);
- return INVALID_HWID;
- }
-
- hwid = of_read_number(cell, of_n_addr_cells(dn));
- /*
- * Non affinity bits must be set to 0 in the DT
- */
- if (hwid & ~MPIDR_HWID_BITMASK) {
- pr_err("%pOF: invalid reg property\n", dn);
- return INVALID_HWID;
- }
- return hwid;
-}
-
/*
* Duplicate MPIDRs are a recipe for disaster. Scan all initialized
* entries and check for duplicates. If any is found just ignore the
@@ -656,9 +629,9 @@ static void __init of_parse_and_init_cpus(void)
struct device_node *dn;
for_each_of_cpu_node(dn) {
- u64 hwid = of_get_cpu_mpidr(dn);
+ u64 hwid = of_get_cpu_hwid(dn, 0);
- if (hwid == INVALID_HWID)
+ if (hwid & ~MPIDR_HWID_BITMASK)
goto next;
if (is_mpidr_duplicate(cpu_count, hwid)) {
--
2.30.2
next prev parent reply other threads:[~2021-10-06 16:43 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 16:43 [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes Rob Herring
2021-10-18 13:26 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 02/12] ARM: Use of_get_cpu_hwid() Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 03/12] ARM: broadcom: " Rob Herring
2021-10-07 2:24 ` Florian Fainelli
2021-10-06 16:43 ` Rob Herring [this message]
2021-10-07 8:07 ` [OpenRISC] [PATCH 04/12] arm64: " Will Deacon
2021-10-18 13:27 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 05/12] csky: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 06/12] openrisc: " Rob Herring
2021-10-06 20:44 ` Stafford Horne
2021-10-06 21:08 ` Rob Herring
2021-10-06 21:25 ` Stafford Horne
2021-10-06 21:27 ` Segher Boessenkool
2021-10-06 22:37 ` Stafford Horne
2021-10-07 7:53 ` David Laight
2021-10-06 16:43 ` [OpenRISC] [PATCH 07/12] powerpc: " Rob Herring
2021-10-08 11:01 ` Michael Ellerman
2021-10-06 16:43 ` [OpenRISC] [PATCH 08/12] riscv: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 09/12] sh: " Rob Herring
2021-10-27 14:26 ` Rich Felker
2021-10-06 16:43 ` [OpenRISC] [PATCH 10/12] x86: dt: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id' Rob Herring
2021-10-18 13:30 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 12/12] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-10-18 13:31 ` Sudeep Holla
2021-10-07 2:24 ` [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Florian Fainelli
2021-10-20 18:47 ` Rob Herring
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