From: Segher Boessenkool <segher@kernel.crashing.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH 06/12] openrisc: Use of_get_cpu_hwid()
Date: Wed, 6 Oct 2021 16:27:28 -0500 [thread overview]
Message-ID: <20211006212728.GM10333@gate.crashing.org> (raw)
In-Reply-To: <YV4KkAC2p9D4yCnH@antec>
On Thu, Oct 07, 2021 at 05:44:00AM +0900, Stafford Horne wrote:
> You have defined of_get_cpu_hwid to return u64, will this create compiler
> warnings when since we are storing a u64 into a u32?
>
> It seems only if we make with W=3.
Yes. This is done by -Wconversion, "Warn for implicit conversions that
may alter a value."
> I thought we usually warned on this.
This warning is not in -Wall or -Wextra either, it suffers too much from
false positives. It is very natural to just ignore the high bits of
modulo types (which is what "unsigned" types *are*). Or the bits that
"fall off" on a conversion. The C standard makes this required
behaviour, it is useful, and it is the only convenient way of getting
this!
Segher
next prev parent reply other threads:[~2021-10-06 21:27 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-06 16:43 [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 01/12] of: Add of_get_cpu_hwid() to read hardware ID from CPU nodes Rob Herring
2021-10-18 13:26 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 02/12] ARM: Use of_get_cpu_hwid() Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 03/12] ARM: broadcom: " Rob Herring
2021-10-07 2:24 ` Florian Fainelli
2021-10-06 16:43 ` [OpenRISC] [PATCH 04/12] arm64: " Rob Herring
2021-10-07 8:07 ` Will Deacon
2021-10-18 13:27 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 05/12] csky: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 06/12] openrisc: " Rob Herring
2021-10-06 20:44 ` Stafford Horne
2021-10-06 21:08 ` Rob Herring
2021-10-06 21:25 ` Stafford Horne
2021-10-06 21:27 ` Segher Boessenkool [this message]
2021-10-06 22:37 ` Stafford Horne
2021-10-07 7:53 ` David Laight
2021-10-06 16:43 ` [OpenRISC] [PATCH 07/12] powerpc: " Rob Herring
2021-10-08 11:01 ` Michael Ellerman
2021-10-06 16:43 ` [OpenRISC] [PATCH 08/12] riscv: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 09/12] sh: " Rob Herring
2021-10-27 14:26 ` Rich Felker
2021-10-06 16:43 ` [OpenRISC] [PATCH 10/12] x86: dt: " Rob Herring
2021-10-06 16:43 ` [OpenRISC] [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id' Rob Herring
2021-10-18 13:30 ` Sudeep Holla
2021-10-06 16:43 ` [OpenRISC] [PATCH 12/12] cacheinfo: Set cache 'id' based on DT data Rob Herring
2021-10-18 13:31 ` Sudeep Holla
2021-10-07 2:24 ` [OpenRISC] [PATCH 00/12] DT: CPU h/w id parsing clean-ups and cacheinfo id support Florian Fainelli
2021-10-20 18:47 ` Rob Herring
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