[PATCH v3 0/3] RISC-V Smstateen support

[PATCH v3 0/3] RISC-V Smstateen support

[Mayuresh Chitale]

This series adds support for the Smstateen specification which provides
a mechanism to plug potential covert channels which are opened by extensions
which add to processor state that may not get context-switched. Currently
access to AIA registers and *envcfg registers is controlled via
smstateen.

Changes in v3:
- Fix RV32 compilation issue

Changes in v2:
- Rebase on latest master branch
- Fix indentation issue

Mayuresh Chitale (3):
  lib: sbi: Add Smstateen extension defines
  lib: sbi: Detect Smstateen CSRs at boot-time
  lib: irqchip/imsic: configure mstateen

 include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
 include/sbi/sbi_hart.h       |  4 +++-
 lib/sbi/sbi_hart.c           | 31 +++++++++++++++++++++++++
 3 files changed, 78 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH v3 1/3] lib: sbi: Add Smstateen extension defines

[Mayuresh Chitale]

Smstateen extension provides a mechanism to plug potential
covert channels which are opened by extensions that add to
processor state that may not get context-switched.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
index c02aa8f..04d5621 100644
--- a/include/sbi/riscv_encoding.h
+++ b/include/sbi/riscv_encoding.h
@@ -345,6 +345,12 @@
 #define CSR_SIEH			0x114
 #define CSR_SIPH			0x154
 
+/* Supervisor stateen CSRs */
+#define CSR_SSTATEEN0			0x10C
+#define CSR_SSTATEEN1			0x10D
+#define CSR_SSTATEEN2			0x10E
+#define CSR_SSTATEEN3			0x10F
+
 /* ===== Hypervisor-level CSRs ===== */
 
 /* Hypervisor Trap Setup (H-extension) */
@@ -413,6 +419,16 @@
 #define CSR_VSIEH			0x214
 #define CSR_VSIPH			0x254
 
+/* Hypervisor stateen CSRs */
+#define CSR_HSTATEEN0			0x60C
+#define CSR_HSTATEEN0H			0x61C
+#define CSR_HSTATEEN1			0x60D
+#define CSR_HSTATEEN1H			0x61D
+#define CSR_HSTATEEN2			0x60E
+#define CSR_HSTATEEN2H			0x61E
+#define CSR_HSTATEEN3			0x60F
+#define CSR_HSTATEEN3H			0x61F
+
 /* ===== Machine-level CSRs ===== */
 
 /* Machine Information Registers */
@@ -686,6 +702,17 @@
 #define CSR_MVIEN			0x308
 #define CSR_MVIP			0x309
 
+/* Smstateen extension registers */
+/* Machine stateen CSRs */
+#define CSR_MSTATEEN0			0x30C
+#define CSR_MSTATEEN0H			0x31C
+#define CSR_MSTATEEN1			0x30D
+#define CSR_MSTATEEN1H			0x31D
+#define CSR_MSTATEEN2			0x30E
+#define CSR_MSTATEEN2H			0x31E
+#define CSR_MSTATEEN3			0x30F
+#define CSR_MSTATEEN3H			0x31F
+
 /* Machine-Level High-Half CSRs (AIA) */
 #define CSR_MIDELEGH			0x313
 #define CSR_MIEH			0x314
@@ -715,6 +742,23 @@
 #define CAUSE_VIRTUAL_INST_FAULT	0x16
 #define CAUSE_STORE_GUEST_PAGE_FAULT	0x17
 
+/* Common defines for all smstateen */
+#define SMSTATEEN_MAX_COUNT		4
+#define SMSTATEEN0_CS_SHIFT		0
+#define SMSTATEEN0_CS			(_ULL(1) << SMSTATEEN0_CS_SHIFT)
+#define SMSTATEEN0_FCSR_SHIFT		1
+#define SMSTATEEN0_FCSR			(_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
+#define SMSTATEEN0_IMSIC_SHIFT		58
+#define SMSTATEEN0_IMSIC		(_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
+#define SMSTATEEN0_AIA_SHIFT		59
+#define SMSTATEEN0_AIA			(_ULL(1) << SMSTATEEN0_AIA_SHIFT)
+#define SMSTATEEN0_SVSLCT_SHIFT		60
+#define SMSTATEEN0_SVSLCT		(_ULL(1) << SMSTATEEN0_SVSLCT_SHIFT)
+#define SMSTATEEN0_HSENVCFG_SHIFT	62
+#define SMSTATEEN0_HSENVCFG		(_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
+#define SMSTATEEN_STATEN_SHIFT		63
+#define SMSTATEEN_STATEN		(_ULL(1) << SMSTATEEN_STATEN_SHIFT)
+
 /* ===== Instruction Encodings ===== */
 
 #define INSN_MATCH_LB			0x3
-- 
2.17.1

[PATCH v3 1/3] lib: sbi: Add Smstateen extension defines

[Xiang W]

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???
> Smstateen extension provides a mechanism to plug potential
> covert channels which are opened by extensions that add to
> processor state that may not get context-switched.
> 
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz@126.com>
> ---
> ?include/sbi/riscv_encoding.h | 44
> ++++++++++++++++++++++++++++++++++++
> ?1 file changed, 44 insertions(+)
> 
> diff --git a/include/sbi/riscv_encoding.h
> b/include/sbi/riscv_encoding.h
> index c02aa8f..04d5621 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -345,6 +345,12 @@
> ?#define CSR_SIEH???????????????????????0x114
> ?#define CSR_SIPH???????????????????????0x154
> ?
> +/* Supervisor stateen CSRs */
> +#define CSR_SSTATEEN0??????????????????0x10C
> +#define CSR_SSTATEEN1??????????????????0x10D
> +#define CSR_SSTATEEN2??????????????????0x10E
> +#define CSR_SSTATEEN3??????????????????0x10F
> +
> ?/* ===== Hypervisor-level CSRs ===== */
> ?
> ?/* Hypervisor Trap Setup (H-extension) */
> @@ -413,6 +419,16 @@
> ?#define CSR_VSIEH??????????????????????0x214
> ?#define CSR_VSIPH??????????????????????0x254
> ?
> +/* Hypervisor stateen CSRs */
> +#define CSR_HSTATEEN0??????????????????0x60C
> +#define CSR_HSTATEEN0H?????????????????0x61C
> +#define CSR_HSTATEEN1??????????????????0x60D
> +#define CSR_HSTATEEN1H?????????????????0x61D
> +#define CSR_HSTATEEN2??????????????????0x60E
> +#define CSR_HSTATEEN2H?????????????????0x61E
> +#define CSR_HSTATEEN3??????????????????0x60F
> +#define CSR_HSTATEEN3H?????????????????0x61F
> +
> ?/* ===== Machine-level CSRs ===== */
> ?
> ?/* Machine Information Registers */
> @@ -686,6 +702,17 @@
> ?#define CSR_MVIEN??????????????????????0x308
> ?#define CSR_MVIP???????????????????????0x309
> ?
> +/* Smstateen extension registers */
> +/* Machine stateen CSRs */
> +#define CSR_MSTATEEN0??????????????????0x30C
> +#define CSR_MSTATEEN0H?????????????????0x31C
> +#define CSR_MSTATEEN1??????????????????0x30D
> +#define CSR_MSTATEEN1H?????????????????0x31D
> +#define CSR_MSTATEEN2??????????????????0x30E
> +#define CSR_MSTATEEN2H?????????????????0x31E
> +#define CSR_MSTATEEN3??????????????????0x30F
> +#define CSR_MSTATEEN3H?????????????????0x31F
> +
> ?/* Machine-Level High-Half CSRs (AIA) */
> ?#define CSR_MIDELEGH???????????????????0x313
> ?#define CSR_MIEH???????????????????????0x314
> @@ -715,6 +742,23 @@
> ?#define CAUSE_VIRTUAL_INST_FAULT???????0x16
> ?#define CAUSE_STORE_GUEST_PAGE_FAULT???0x17
> ?
> +/* Common defines for all smstateen */
> +#define SMSTATEEN_MAX_COUNT????????????4
> +#define SMSTATEEN0_CS_SHIFT????????????0
> +#define SMSTATEEN0_CS??????????????????(_ULL(1) <<
> SMSTATEEN0_CS_SHIFT)
> +#define SMSTATEEN0_FCSR_SHIFT??????????1
> +#define SMSTATEEN0_FCSR????????????????????????(_ULL(1) <<
> SMSTATEEN0_FCSR_SHIFT)
> +#define SMSTATEEN0_IMSIC_SHIFT?????????58
> +#define SMSTATEEN0_IMSIC???????????????(_ULL(1) <<
> SMSTATEEN0_IMSIC_SHIFT)
> +#define SMSTATEEN0_AIA_SHIFT???????????59
> +#define SMSTATEEN0_AIA?????????????????(_ULL(1) <<
> SMSTATEEN0_AIA_SHIFT)
> +#define SMSTATEEN0_SVSLCT_SHIFT????????????????60
> +#define SMSTATEEN0_SVSLCT??????????????(_ULL(1) <<
> SMSTATEEN0_SVSLCT_SHIFT)
> +#define SMSTATEEN0_HSENVCFG_SHIFT??????62
> +#define SMSTATEEN0_HSENVCFG????????????(_ULL(1) <<
> SMSTATEEN0_HSENVCFG_SHIFT)
> +#define SMSTATEEN_STATEN_SHIFT?????????63
> +#define SMSTATEEN_STATEN???????????????(_ULL(1) <<
> SMSTATEEN_STATEN_SHIFT)
> +
> ?/* ===== Instruction Encodings ===== */
> ?
> ?#define INSN_MATCH_LB??????????????????0x3
> -- 
> 2.17.1
> 
> 

[PATCH v3 1/3] lib: sbi: Add Smstateen extension defines

[Anup Patel]

On Wed, Apr 6, 2022 at 10:28 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Smstateen extension provides a mechanism to plug potential
> covert channels which are opened by extensions that add to
> processor state that may not get context-switched.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/riscv_encoding.h | 44 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> index c02aa8f..04d5621 100644
> --- a/include/sbi/riscv_encoding.h
> +++ b/include/sbi/riscv_encoding.h
> @@ -345,6 +345,12 @@
>  #define CSR_SIEH                       0x114
>  #define CSR_SIPH                       0x154
>
> +/* Supervisor stateen CSRs */
> +#define CSR_SSTATEEN0                  0x10C
> +#define CSR_SSTATEEN1                  0x10D
> +#define CSR_SSTATEEN2                  0x10E
> +#define CSR_SSTATEEN3                  0x10F
> +
>  /* ===== Hypervisor-level CSRs ===== */
>
>  /* Hypervisor Trap Setup (H-extension) */
> @@ -413,6 +419,16 @@
>  #define CSR_VSIEH                      0x214
>  #define CSR_VSIPH                      0x254
>
> +/* Hypervisor stateen CSRs */
> +#define CSR_HSTATEEN0                  0x60C
> +#define CSR_HSTATEEN0H                 0x61C
> +#define CSR_HSTATEEN1                  0x60D
> +#define CSR_HSTATEEN1H                 0x61D
> +#define CSR_HSTATEEN2                  0x60E
> +#define CSR_HSTATEEN2H                 0x61E
> +#define CSR_HSTATEEN3                  0x60F
> +#define CSR_HSTATEEN3H                 0x61F
> +
>  /* ===== Machine-level CSRs ===== */
>
>  /* Machine Information Registers */
> @@ -686,6 +702,17 @@
>  #define CSR_MVIEN                      0x308
>  #define CSR_MVIP                       0x309
>
> +/* Smstateen extension registers */
> +/* Machine stateen CSRs */
> +#define CSR_MSTATEEN0                  0x30C
> +#define CSR_MSTATEEN0H                 0x31C
> +#define CSR_MSTATEEN1                  0x30D
> +#define CSR_MSTATEEN1H                 0x31D
> +#define CSR_MSTATEEN2                  0x30E
> +#define CSR_MSTATEEN2H                 0x31E
> +#define CSR_MSTATEEN3                  0x30F
> +#define CSR_MSTATEEN3H                 0x31F
> +
>  /* Machine-Level High-Half CSRs (AIA) */
>  #define CSR_MIDELEGH                   0x313
>  #define CSR_MIEH                       0x314
> @@ -715,6 +742,23 @@
>  #define CAUSE_VIRTUAL_INST_FAULT       0x16
>  #define CAUSE_STORE_GUEST_PAGE_FAULT   0x17
>
> +/* Common defines for all smstateen */
> +#define SMSTATEEN_MAX_COUNT            4
> +#define SMSTATEEN0_CS_SHIFT            0
> +#define SMSTATEEN0_CS                  (_ULL(1) << SMSTATEEN0_CS_SHIFT)
> +#define SMSTATEEN0_FCSR_SHIFT          1
> +#define SMSTATEEN0_FCSR                        (_ULL(1) << SMSTATEEN0_FCSR_SHIFT)
> +#define SMSTATEEN0_IMSIC_SHIFT         58
> +#define SMSTATEEN0_IMSIC               (_ULL(1) << SMSTATEEN0_IMSIC_SHIFT)
> +#define SMSTATEEN0_AIA_SHIFT           59
> +#define SMSTATEEN0_AIA                 (_ULL(1) << SMSTATEEN0_AIA_SHIFT)
> +#define SMSTATEEN0_SVSLCT_SHIFT                60
> +#define SMSTATEEN0_SVSLCT              (_ULL(1) << SMSTATEEN0_SVSLCT_SHIFT)
> +#define SMSTATEEN0_HSENVCFG_SHIFT      62
> +#define SMSTATEEN0_HSENVCFG            (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT)
> +#define SMSTATEEN_STATEN_SHIFT         63
> +#define SMSTATEEN_STATEN               (_ULL(1) << SMSTATEEN_STATEN_SHIFT)
> +
>  /* ===== Instruction Encodings ===== */
>
>  #define INSN_MATCH_LB                  0x3
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

[PATCH v3 2/3] lib: sbi: Detect Smstateen CSRs at boot-time

[Mayuresh Chitale]

Extend HART feature detection to discover Smstateen CSRs at boot-time
and configure mstateen envcfg bit depending on availability of
menvcfg CSR.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 include/sbi/sbi_hart.h |  4 +++-
 lib/sbi/sbi_hart.c     | 25 +++++++++++++++++++++++++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 57f80bc..be3ad9f 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -28,9 +28,11 @@ enum sbi_hart_features {
 	SBI_HART_HAS_AIA = (1 << 5),
 	/** HART has menvcfg CSR */
 	SBI_HART_HAS_MENVCFG = (1 << 6),
+	/** HART has mstateen CSR **/
+	SBI_HART_HAS_SMSTATEEN = (1 << 7),
 
 	/** Last index of Hart features*/
-	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
+	SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
 };
 
 struct sbi_scratch;
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 6be9286..b0edf38 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
 	int cidx;
 	unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
 	uint64_t mhpmevent_init_val = 0;
+	uint64_t mstateen_val;
 
 	/* Enable FPU */
 	if (misa_extension('D') || misa_extension('F'))
@@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch *scratch)
 #endif
 	}
 
+	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
+		mstateen_val = csr_read(CSR_MSTATEEN0);
+#if __riscv_xlen == 32
+		mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
+#endif
+		mstateen_val |= SMSTATEEN_STATEN;
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
+			mstateen_val |= SMSTATEEN0_HSENVCFG;
+		else
+			mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+		csr_write(CSR_MSTATEEN0, mstateen_val);
+#if __riscv_xlen == 32
+		csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
+#endif
+	}
+
 	if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
 		menvcfg_val = csr_read(CSR_MENVCFG);
 
@@ -348,6 +365,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
 	case SBI_HART_HAS_MENVCFG:
 		fstr = "menvcfg";
 		break;
+	case SBI_HART_HAS_SMSTATEEN:
+		fstr = "smstateen";
+		break;
 	default:
 		break;
 	}
@@ -584,6 +604,11 @@ __aia_skip:
 	if (!trap.cause)
 		hfeatures->features |= SBI_HART_HAS_MENVCFG;
 
+	/* Detect if hart supports mstateen CSRs */
+	val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
+	if (!trap.cause)
+		hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
+
 	return;
 }
 
-- 
2.17.1

[PATCH v3 2/3] lib: sbi: Detect Smstateen CSRs at boot-time

[Xiang W]

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???
> Extend HART feature detection to discover Smstateen CSRs at boot-time
> and configure mstateen envcfg bit depending on availability of
> menvcfg CSR.
> 
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz@126.com>
> ---
> ?include/sbi/sbi_hart.h |? 4 +++-
> ?lib/sbi/sbi_hart.c???? | 25 +++++++++++++++++++++++++
> ?2 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 57f80bc..be3ad9f 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -28,9 +28,11 @@ enum sbi_hart_features {
> ????????SBI_HART_HAS_AIA = (1 << 5),
> ????????/** HART has menvcfg CSR */
> ????????SBI_HART_HAS_MENVCFG = (1 << 6),
> +???????/** HART has mstateen CSR **/
> +???????SBI_HART_HAS_SMSTATEEN = (1 << 7),
> ?
> ????????/** Last index of Hart features*/
> -???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
> +???????SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
> ?};
> ?
> ?struct sbi_scratch;
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 6be9286..b0edf38 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ????????int cidx;
> ????????unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
> ????????uint64_t mhpmevent_init_val = 0;
> +???????uint64_t mstateen_val;
> ?
> ????????/* Enable FPU */
> ????????if (misa_extension('D') || misa_extension('F'))
> @@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ?#endif
> ????????}
> ?
> +???????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
> +???????????????mstateen_val = csr_read(CSR_MSTATEEN0);
> +#if __riscv_xlen == 32
> +???????????????mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H))
> << 32;
> +#endif
> +???????????????mstateen_val |= SMSTATEEN_STATEN;
> +???????????????if (sbi_hart_has_feature(scratch,
> SBI_HART_HAS_MENVCFG))
> +???????????????????????mstateen_val |= SMSTATEEN0_HSENVCFG;
> +???????????????else
> +???????????????????????mstateen_val &= ~SMSTATEEN0_HSENVCFG;
> +???????????????csr_write(CSR_MSTATEEN0, mstateen_val);
> +#if __riscv_xlen == 32
> +???????????????csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
> +#endif
> +???????}
> +
> ????????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
> ????????????????menvcfg_val = csr_read(CSR_MENVCFG);
> ?
> @@ -348,6 +365,9 @@ static inline char
> *sbi_hart_feature_id2string(unsigned long feature)
> ????????case SBI_HART_HAS_MENVCFG:
> ????????????????fstr = "menvcfg";
> ????????????????break;
> +???????case SBI_HART_HAS_SMSTATEEN:
> +???????????????fstr = "smstateen";
> +???????????????break;
> ????????default:
> ????????????????break;
> ????????}
> @@ -584,6 +604,11 @@ __aia_skip:
> ????????if (!trap.cause)
> ????????????????hfeatures->features |= SBI_HART_HAS_MENVCFG;
> ?
> +???????/* Detect if hart supports mstateen CSRs */
> +???????val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
> +???????if (!trap.cause)
> +???????????????hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
> +
> ????????return;
> ?}
> ?
> -- 
> 2.17.1
> 
> 

[PATCH v3 2/3] lib: sbi: Detect Smstateen CSRs at boot-time

[Anup Patel]

On Wed, Apr 6, 2022 at 10:28 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> Extend HART feature detection to discover Smstateen CSRs at boot-time
> and configure mstateen envcfg bit depending on availability of
> menvcfg CSR.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  include/sbi/sbi_hart.h |  4 +++-
>  lib/sbi/sbi_hart.c     | 25 +++++++++++++++++++++++++
>  2 files changed, 28 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 57f80bc..be3ad9f 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -28,9 +28,11 @@ enum sbi_hart_features {
>         SBI_HART_HAS_AIA = (1 << 5),
>         /** HART has menvcfg CSR */
>         SBI_HART_HAS_MENVCFG = (1 << 6),
> +       /** HART has mstateen CSR **/
> +       SBI_HART_HAS_SMSTATEEN = (1 << 7),
>
>         /** Last index of Hart features*/
> -       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_MENVCFG,
> +       SBI_HART_HAS_LAST_FEATURE = SBI_HART_HAS_SMSTATEEN,
>  };
>
>  struct sbi_scratch;
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 6be9286..b0edf38 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -43,6 +43,7 @@ static void mstatus_init(struct sbi_scratch *scratch)
>         int cidx;
>         unsigned int num_mhpm = sbi_hart_mhpm_count(scratch);
>         uint64_t mhpmevent_init_val = 0;
> +       uint64_t mstateen_val;
>
>         /* Enable FPU */
>         if (misa_extension('D') || misa_extension('F'))
> @@ -87,6 +88,22 @@ static void mstatus_init(struct sbi_scratch *scratch)
>  #endif
>         }
>
> +       if (sbi_hart_has_feature(scratch, SBI_HART_HAS_SMSTATEEN)) {
> +               mstateen_val = csr_read(CSR_MSTATEEN0);
> +#if __riscv_xlen == 32
> +               mstateen_val |= ((uint64_t)csr_read(CSR_MSTATEEN0H)) << 32;
> +#endif
> +               mstateen_val |= SMSTATEEN_STATEN;
> +               if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG))
> +                       mstateen_val |= SMSTATEEN0_HSENVCFG;
> +               else
> +                       mstateen_val &= ~SMSTATEEN0_HSENVCFG;
> +               csr_write(CSR_MSTATEEN0, mstateen_val);
> +#if __riscv_xlen == 32
> +               csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
> +#endif
> +       }
> +
>         if (sbi_hart_has_feature(scratch, SBI_HART_HAS_MENVCFG)) {
>                 menvcfg_val = csr_read(CSR_MENVCFG);
>
> @@ -348,6 +365,9 @@ static inline char *sbi_hart_feature_id2string(unsigned long feature)
>         case SBI_HART_HAS_MENVCFG:
>                 fstr = "menvcfg";
>                 break;
> +       case SBI_HART_HAS_SMSTATEEN:
> +               fstr = "smstateen";
> +               break;
>         default:
>                 break;
>         }
> @@ -584,6 +604,11 @@ __aia_skip:
>         if (!trap.cause)
>                 hfeatures->features |= SBI_HART_HAS_MENVCFG;
>
> +       /* Detect if hart supports mstateen CSRs */
> +       val = csr_read_allowed(CSR_MSTATEEN0, (unsigned long)&trap);
> +       if (!trap.cause)
> +               hfeatures->features |= SBI_HART_HAS_SMSTATEEN;
> +
>         return;
>  }
>
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi

[PATCH v3 3/3] lib: irqchip/imsic: configure mstateen

[Mayuresh Chitale]

When mstateen registers are implemented, the AIA related
configurations need to be done in mstateen for the IMSIC
initialization to succeed.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
 lib/sbi/sbi_hart.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index b0edf38..7b602c3 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch)
 			mstateen_val |= SMSTATEEN0_HSENVCFG;
 		else
 			mstateen_val &= ~SMSTATEEN0_HSENVCFG;
+		if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
+			mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
+		else
+			mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
+					SMSTATEEN0_IMSIC);
 		csr_write(CSR_MSTATEEN0, mstateen_val);
 #if __riscv_xlen == 32
 		csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
-- 
2.17.1

[PATCH v3 3/3] lib: irqchip/imsic: configure mstateen

[Xiang W]

? 2022-04-06???? 22:27 +0530?Mayuresh Chitale???
> When mstateen registers are implemented, the AIA related
> configurations need to be done in mstateen for the IMSIC
> initialization to succeed.
> 
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Look good to me

Reviewed-by: Xiang W <wxjstz@126.com>
> ---
> ?lib/sbi/sbi_hart.c | 6 ++++++
> ?1 file changed, 6 insertions(+)
> 
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index b0edf38..7b602c3 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch
> *scratch)
> ????????????????????????mstateen_val |= SMSTATEEN0_HSENVCFG;
> ????????????????else
> ????????????????????????mstateen_val &= ~SMSTATEEN0_HSENVCFG;
> +???????????????if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
> +???????????????????????mstateen_val |= (SMSTATEEN0_AIA |
> SMSTATEEN0_SVSLCT |
> +???????????????????????????????????????SMSTATEEN0_IMSIC);
> +???????????????else
> +???????????????????????mstateen_val &= ~(SMSTATEEN0_AIA |
> SMSTATEEN0_SVSLCT |
> +???????????????????????????????????????SMSTATEEN0_IMSIC);
> ????????????????csr_write(CSR_MSTATEEN0, mstateen_val);
> ?#if __riscv_xlen == 32
> ????????????????csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
> -- 
> 2.17.1
> 
> 

[PATCH v3 3/3] lib: irqchip/imsic: configure mstateen

[Anup Patel]

On Wed, Apr 6, 2022 at 10:28 PM Mayuresh Chitale
<mchitale@ventanamicro.com> wrote:
>
> When mstateen registers are implemented, the AIA related
> configurations need to be done in mstateen for the IMSIC
> initialization to succeed.
>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>

Looks good to me.

Reviewed-by: Anup Patel <anup@brainfault.org>

Applied this patch to the riscv/opensbi repo.

Thanks,
Anup

> ---
>  lib/sbi/sbi_hart.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index b0edf38..7b602c3 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -98,6 +98,12 @@ static void mstatus_init(struct sbi_scratch *scratch)
>                         mstateen_val |= SMSTATEEN0_HSENVCFG;
>                 else
>                         mstateen_val &= ~SMSTATEEN0_HSENVCFG;
> +               if (sbi_hart_has_feature(scratch, SBI_HART_HAS_AIA))
> +                       mstateen_val |= (SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
> +                                       SMSTATEEN0_IMSIC);
> +               else
> +                       mstateen_val &= ~(SMSTATEEN0_AIA | SMSTATEEN0_SVSLCT |
> +                                       SMSTATEEN0_IMSIC);
>                 csr_write(CSR_MSTATEEN0, mstateen_val);
>  #if __riscv_xlen == 32
>                 csr_write(CSR_MSTATEEN0H, mstateen_val >> 32);
> --
> 2.17.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi