OpenSBI Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: opensbi@lists.infradead.org
Cc: zong.li@sifive.com, greentime.hu@sifive.com, anup@brainfault.org,
	scott@riscstar.com, conor@kernel.org, dave.patel@riscstar.com,
	raymond.mao@riscstar.com, robin.randhawa@sifive.com,
	samuel.holland@sifive.com,
	Yu-Chien Peter Lin <peter.lin@sifive.com>
Subject: [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI
Date: Fri, 26 Jun 2026 18:14:21 +0800	[thread overview]
Message-ID: <20260626101433.3133466-1-peter.lin@sifive.com> (raw)

This RFC patch series adds support for RISC-V Worlds ISA extensions,
enabling hardware-enforced isolation boundaries based on World IDs (WIDs)
by extending the OpenSBI domain framework.

Trust Model and Boot-time Roles
--------------------------------

The implementation follows the two-phase M-mode trust model:

- RoT M-mode phase: Prior boot stage (ROM/SPL) that may program mwid/
  mlwidlist and lock mwid before handing off to OpenSBI.

- Regular M-mode phase (OpenSBI): Treats pmwid/pmwidlist/pmlwidlist as
  read-only input policy from hardware/RoT. Locks mwid during feature
  detection to prevent later M-mode code from changing its own WID.
  Programs per-domain mlwid/mwiddeleg based on DT configuration.

Device Tree Bindings
---------------------

New CPU properties (per-hart):
- riscv,pmwid: Platform-defined M-mode World ID
- riscv,pmwidlist: M-mode permitted WID bitmap (u64, 2 cells)
- riscv,pmlwidlist: S/U-mode permitted WID bitmap (u64, 2 cells)

New domain properties (per-domain):
- next-wid: Override S-mode WID for this domain (u32, 1 cell)
- next-widlist: WID delegation bitmap for this domain (u64, 2 cells)

If a domain lacks next-wid, OpenSBI falls back to pmwid (M-mode and
S-mode run in the same World).

Example DT snippet:

    cpus {
        riscv,nworlds = <4>;
        cpu@0 {
            riscv,pmwid = <3>;
            riscv,pmwidlist = <0x0 0xf>;
            riscv,pmlwidlist = <0x0 0xf>;
        };
    };

    chosen {
        opensbi-domains {
            trusted-domain {
                next-wid = <1>;
                next-widlist = <0x0 0x2>;
            };
            untrusted-domain {
                next-wid = <0>;
                next-widlist = <0x0 0x1>;
            };
        };
    };

Known Limitations and Future Work
----------------------------------

This RFC implements core functionality but has several areas requiring
refinement in the future revisions:

1. WID Validation:
   - Domain next-wid is NOT validated against pmlwidlist
   - Domain next-widlist is NOT validated as subset of pmlwidlist
   - Invalid WID configuration fails at runtime with software-check
     exceptions rather than at domain registration time
   - Planned: Add validation in sanitize_domain() to catch errors early

2. Resume Path mwid Restoration:
   - Current implementation only re-locks mwid on resume, assuming RoT
     has already restored the correct WID value
   - No mechanism to verify or actively restore mwid to RoT-defined value

Specification References
-------------------------

- RISC-V Worlds ISA Spec: https://github.com/riscv/riscv-worlds
  (Release: riscv-isa-release-4c81a3f-2026-04-14)
- Device Tree Proposal: https://lore.kernel.org/all/20260619105834.1277302-1-peter.lin@sifive.com/

Yu-Chien Peter Lin (12):
  lib: sbi_hart: detect RISC-V Worlds ISA extensions
  lib: utils: fdt_helper: parse RISC-V Worlds DT properties
  lib: sbi_hart: enforce riscv,pmwid for Worlds ISA
  lib: sbi_hart: lock mwid CSR for RoT immutability
  include: sbi_domain: add Worlds WID fields
  include: sbi_types: add PRIx64 format macro
  lib: sbi_domain: print World ID config at boot
  lib: sbi_init: print M-mode World ID at boot
  platform: generic: parse root domain WID config from DT
  lib: utils: fdt_domain: parse per-domain WID properties
  lib: sbi_domain: add Worlds CSR config on domain entry
  docs: add RISC-V Worlds next-wid/next-widlist DT properties

 docs/domain_support.md             | 13 ++++++
 docs/opensbi_config.md             | 13 ++++++
 include/sbi/riscv_encoding.h       | 12 +++++
 include/sbi/sbi_domain.h           |  9 ++++
 include/sbi/sbi_hart.h             | 25 +++++++++++
 include/sbi/sbi_types.h            |  2 +
 include/sbi_utils/fdt/fdt_helper.h |  2 +
 lib/sbi/sbi_domain.c               | 50 +++++++++++++++++++++
 lib/sbi/sbi_domain_context.c       |  3 ++
 lib/sbi/sbi_hart.c                 | 71 ++++++++++++++++++++++++++++++
 lib/sbi/sbi_hsm.c                  |  4 ++
 lib/sbi/sbi_init.c                 | 13 ++++++
 lib/utils/fdt/fdt_domain.c         | 15 +++++++
 lib/utils/fdt/fdt_helper.c         | 61 +++++++++++++++++++++++++
 platform/generic/platform.c        | 33 +++++++++++++-
 15 files changed, 324 insertions(+), 2 deletions(-)

-- 
2.43.7


-- 
opensbi mailing list
opensbi@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/opensbi

             reply	other threads:[~2026-06-26 10:16 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-26 10:14 Yu-Chien Peter Lin [this message]
2026-06-26 10:14 ` [RFC PATCH 01/12] lib: sbi_hart: detect RISC-V Worlds ISA extensions Yu-Chien Peter Lin
2026-07-13 20:58   ` Pawandeep Oza
2026-07-20  3:14     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties Yu-Chien Peter Lin
2026-07-09  0:36   ` Pawandeep Oza
2026-07-09  0:42     ` Pawandeep Oza
2026-07-13 21:13       ` Pawandeep Oza
2026-07-20  6:41         ` Yu-Chien Peter Lin
2026-07-20  5:55       ` Yu-Chien Peter Lin
2026-07-20  3:29     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 03/12] lib: sbi_hart: enforce riscv,pmwid for Worlds ISA Yu-Chien Peter Lin
2026-07-13 21:26   ` Pawandeep Oza
2026-07-20  7:01     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 04/12] lib: sbi_hart: lock mwid CSR for RoT immutability Yu-Chien Peter Lin
2026-07-13 21:28   ` Pawandeep Oza
2026-07-20  7:36     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 05/12] include: sbi_domain: add Worlds WID fields Yu-Chien Peter Lin
2026-07-13 21:52   ` Pawandeep Oza
2026-07-20  7:55     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 06/12] include: sbi_types: add PRIx64 format macro Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 07/12] lib: sbi_domain: print World ID config at boot Yu-Chien Peter Lin
2026-07-13 23:48   ` Pawandeep Oza
2026-07-20  8:24     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 08/12] lib: sbi_init: print M-mode World ID " Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 09/12] platform: generic: parse root domain WID config from DT Yu-Chien Peter Lin
2026-07-09  0:39   ` Pawandeep Oza
2026-07-20  8:54     ` Yu-Chien Peter Lin
2026-07-20 10:39       ` Anup Patel
2026-07-20 21:14         ` Pawandeep Oza
2026-07-21  6:24           ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 10/12] lib: utils: fdt_domain: parse per-domain WID properties Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 11/12] lib: sbi_domain: add Worlds CSR config on domain entry Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 12/12] docs: add RISC-V Worlds next-wid/next-widlist DT properties Yu-Chien Peter Lin
2026-07-09  0:44 ` [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Pawandeep Oza
2026-07-14  0:33   ` Pawandeep Oza

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20260626101433.3133466-1-peter.lin@sifive.com \
    --to=peter.lin@sifive.com \
    --cc=anup@brainfault.org \
    --cc=conor@kernel.org \
    --cc=dave.patel@riscstar.com \
    --cc=greentime.hu@sifive.com \
    --cc=opensbi@lists.infradead.org \
    --cc=raymond.mao@riscstar.com \
    --cc=robin.randhawa@sifive.com \
    --cc=samuel.holland@sifive.com \
    --cc=scott@riscstar.com \
    --cc=zong.li@sifive.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox