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From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Pawandeep Oza <pawandeep.oza@oss.qualcomm.com>
Cc: opensbi@lists.infradead.org, zong.li@sifive.com,
	greentime.hu@sifive.com, anup@brainfault.org, scott@riscstar.com,
	conor@kernel.org, dave.patel@riscstar.com,
	raymond.mao@riscstar.com, robin.randhawa@sifive.com,
	samuel.holland@sifive.com
Subject: Re: [RFC PATCH 01/12] lib: sbi_hart: detect RISC-V Worlds ISA extensions
Date: Mon, 20 Jul 2026 11:14:46 +0800	[thread overview]
Message-ID: <al2Spp2N7ONH/il/@plin-1878> (raw)
In-Reply-To: <CAAVgOkKCxOJU1jfc3q-y5JgvXXmkpGKo3HnmmmZOmSKSq3cZmA@mail.gmail.com>

Hi Oza,

On Mon, Jul 13, 2026 at 01:58:42PM -0700, Pawandeep Oza wrote:
> On Fri, Jun 26, 2026 at 3:16 AM Yu-Chien Peter Lin <peter.lin@sifive.com> wrote:
> >
> > Add detection for RISC-V Worlds ISA extensions (Smwid, Smlwid,
> > Smlwidlist, Smwiddeleg, Sswid) via ISA string detection and
> > CSR probes.
> >
> > These feature flags enable subsequent patches to conditionally
> > configure World ID CSRs and print boot-time Worlds status.
> >
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> > ---
> >  include/sbi/riscv_encoding.h | 12 +++++++++
> >  include/sbi/sbi_hart.h       | 10 +++++++
> >  lib/sbi/sbi_hart.c           | 51 ++++++++++++++++++++++++++++++++++++
> >  3 files changed, 73 insertions(+)
> >
> > diff --git a/include/sbi/riscv_encoding.h b/include/sbi/riscv_encoding.h
> > index ffe7666c..271820fd 100644
> > --- a/include/sbi/riscv_encoding.h
> > +++ b/include/sbi/riscv_encoding.h
> > @@ -400,6 +400,9 @@
> >  /* Supervisor Resource Management Configuration CSRs */
> >  #define CSR_SRMCFG                     0x181
> >
> > +/* Supervisor World-ID CSR (Sswid) */
> > +#define CSR_SLWID                      0x190
> Oza: Misleading comment -
> should be
> Supervisor WID value for lower privilege modes Register

Okay, will improve wording.

> > +
> >  /* Machine-Level Control transfer records CSRs */
> >  #define CSR_MCTRCTL                     0x34e
> >
> > @@ -520,6 +523,15 @@
> >  #define CSR_MTINST                     0x34a
> >  #define CSR_MTVAL2                     0x34b
> >
> > +/* Machine World-ID CSRs (Smwid, Smlwid, Smlwidlist, Smwiddeleg) */
> > +#define CSR_MLWID                      0x390
> > +#define CSR_MWID                       0x391
> > +#define CSR_MWIDDELEG                  0x748
> > +#define CSR_MLWIDLIST                  0x749
> > +
> > +/* mwid lock bit */
> > +#define MWID_LOCK                      (_UL(1) << (__riscv_xlen - 1))
> > +
> >  /* Machine Memory Protection */
> >  #define CSR_PMPCFG0                    0x3a0
> >  #define CSR_PMPCFG1                    0x3a1
> > diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> > index 543393bb..2941809e 100644
> > --- a/include/sbi/sbi_hart.h
> > +++ b/include/sbi/sbi_hart.h
> > @@ -95,6 +95,16 @@ enum sbi_hart_extensions {
> >         SBI_HART_EXT_F,
> >         /** Hart has D extension */
> >         SBI_HART_EXT_D,
> > +       /** Hart has Smwid extension */
> > +       SBI_HART_EXT_SMWID,
> > +       /** Hart has Smlwid extension */
> > +       SBI_HART_EXT_SMLWID,
> > +       /** Hart has Smlwidlist extension */
> > +       SBI_HART_EXT_SMLWIDLIST,
> > +       /** Hart has Smwiddeleg extension */
> > +       SBI_HART_EXT_SMWIDDELEG,
> > +       /** Hart has Sswid extension */
> > +       SBI_HART_EXT_SSWID,
> >
> >         /** Maximum index of Hart extension */
> >         SBI_HART_EXT_MAX,
> > diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> > index 21713816..0c584bfc 100644
> > --- a/lib/sbi/sbi_hart.c
> > +++ b/lib/sbi/sbi_hart.c
> > @@ -402,6 +402,11 @@ const struct sbi_hart_ext_data sbi_hart_ext[] = {
> >         __SBI_HART_EXT_DATA(v, SBI_HART_EXT_V),
> >         __SBI_HART_EXT_DATA(f, SBI_HART_EXT_F),
> >         __SBI_HART_EXT_DATA(d, SBI_HART_EXT_D),
> > +       __SBI_HART_EXT_DATA(smwid, SBI_HART_EXT_SMWID),
> > +       __SBI_HART_EXT_DATA(smlwid, SBI_HART_EXT_SMLWID),
> > +       __SBI_HART_EXT_DATA(smlwidlist, SBI_HART_EXT_SMLWIDLIST),
> > +       __SBI_HART_EXT_DATA(smwiddeleg, SBI_HART_EXT_SMWIDDELEG),
> > +       __SBI_HART_EXT_DATA(sswid, SBI_HART_EXT_SSWID),
> >  };
> >
> >  _Static_assert(SBI_HART_EXT_MAX == array_size(sbi_hart_ext),
> > @@ -689,6 +694,52 @@ __pmp_skip:
> >         /* Detect if hart support sdtrig (debug triggers) */
> >         __check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
> >                         CSR_TSELECT, SBI_HART_EXT_SDTRIG);
> > +       /* Detect if hart supports Smwid (mwid CSR) */
> > +       __check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
> > +                       CSR_MWID, SBI_HART_EXT_SMWID);
> > +       /* Detect if hart supports Smlwid (mlwid CSR) */
> > +       __check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
> > +                       CSR_MLWID, SBI_HART_EXT_SMLWID);
> > +       /* Detect if hart supports Smlwidlist (mlwidlist CSR). */
> > +       __check_ext_csr(SBI_HART_PRIV_VER_UNKNOWN,
> > +                       CSR_MLWIDLIST, SBI_HART_EXT_SMLWIDLIST);
> > +       /*
> > +        * Detect if hart supports Smwiddeleg & Sswid.
> > +        * Smwiddeleg requires Smlwid. Sswid requires Smwiddeleg.
> > +        */
> > +       if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMLWID)) {
> > +               unsigned long old_mwiddeleg, new_mwiddeleg;
> > +
> > +               old_mwiddeleg = csr_read_allowed(CSR_MWIDDELEG, &trap);
> Oza: why not use __check_ext_csr at all the following ?

Yes, __check_ext_csr(CSR_MWIDDELEG, SBI_HART_EXT_SMWIDDELEG) is
sufficient Smwiddeleg which also implies Sswid.

Will update the ISA detection here.

Thanks,
Peter Lin

> > +               if (trap.cause)
> > +                       goto skip_smwiddeleg;
> > +
> > +               csr_write_allowed(CSR_MWIDDELEG, &trap, ~0UL);
> > +               if (trap.cause)
> > +                       goto skip_smwiddeleg;
> > +
> > +               new_mwiddeleg = csr_read_allowed(CSR_MWIDDELEG, &trap);
> > +               if (trap.cause) {
> > +                       csr_write(CSR_MWIDDELEG, old_mwiddeleg);
> > +                       goto skip_smwiddeleg;
> > +               }
> > +
> > +               if (new_mwiddeleg) {
> > +                       __sbi_hart_update_extension(hfeatures,
> > +                                                   SBI_HART_EXT_SMWIDDELEG, true);
> > +
> > +                       csr_read_allowed(CSR_SLWID, &trap);
> > +                       if (!trap.cause) {
> > +                               __sbi_hart_update_extension(hfeatures,
> > +                                                           SBI_HART_EXT_SSWID, true);
> > +                       }
> > +               }
> > +
> > +               csr_write(CSR_MWIDDELEG, old_mwiddeleg);
> > +
> > +skip_smwiddeleg:
> > +               ;
> > +       }
> >
> >  #undef __check_ext_csr
> >
> > --
> > 2.43.7
> >
> >
> > --
> > opensbi mailing list
> > opensbi@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi

-- 
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  reply	other threads:[~2026-07-20  3:15 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-26 10:14 [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 01/12] lib: sbi_hart: detect RISC-V Worlds ISA extensions Yu-Chien Peter Lin
2026-07-13 20:58   ` Pawandeep Oza
2026-07-20  3:14     ` Yu-Chien Peter Lin [this message]
2026-06-26 10:14 ` [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties Yu-Chien Peter Lin
2026-07-09  0:36   ` Pawandeep Oza
2026-07-09  0:42     ` Pawandeep Oza
2026-07-13 21:13       ` Pawandeep Oza
2026-07-20  6:41         ` Yu-Chien Peter Lin
2026-07-20  5:55       ` Yu-Chien Peter Lin
2026-07-20  3:29     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 03/12] lib: sbi_hart: enforce riscv,pmwid for Worlds ISA Yu-Chien Peter Lin
2026-07-13 21:26   ` Pawandeep Oza
2026-07-20  7:01     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 04/12] lib: sbi_hart: lock mwid CSR for RoT immutability Yu-Chien Peter Lin
2026-07-13 21:28   ` Pawandeep Oza
2026-07-20  7:36     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 05/12] include: sbi_domain: add Worlds WID fields Yu-Chien Peter Lin
2026-07-13 21:52   ` Pawandeep Oza
2026-07-20  7:55     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 06/12] include: sbi_types: add PRIx64 format macro Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 07/12] lib: sbi_domain: print World ID config at boot Yu-Chien Peter Lin
2026-07-13 23:48   ` Pawandeep Oza
2026-07-20  8:24     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 08/12] lib: sbi_init: print M-mode World ID " Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 09/12] platform: generic: parse root domain WID config from DT Yu-Chien Peter Lin
2026-07-09  0:39   ` Pawandeep Oza
2026-07-20  8:54     ` Yu-Chien Peter Lin
2026-07-20 10:39       ` Anup Patel
2026-07-20 21:14         ` Pawandeep Oza
2026-07-21  6:24           ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 10/12] lib: utils: fdt_domain: parse per-domain WID properties Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 11/12] lib: sbi_domain: add Worlds CSR config on domain entry Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 12/12] docs: add RISC-V Worlds next-wid/next-widlist DT properties Yu-Chien Peter Lin
2026-07-09  0:44 ` [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Pawandeep Oza
2026-07-14  0:33   ` Pawandeep Oza

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