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From: Yu-Chien Peter Lin <peter.lin@sifive.com>
To: Pawandeep Oza <pawandeep.oza@oss.qualcomm.com>
Cc: opensbi@lists.infradead.org, zong.li@sifive.com,
	greentime.hu@sifive.com, anup@brainfault.org, scott@riscstar.com,
	conor@kernel.org, dave.patel@riscstar.com,
	raymond.mao@riscstar.com, robin.randhawa@sifive.com,
	samuel.holland@sifive.com
Subject: Re: [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties
Date: Mon, 20 Jul 2026 11:29:47 +0800	[thread overview]
Message-ID: <al2WK5I7kHAOmKpS@plin-1878> (raw)
In-Reply-To: <CAAVgOkJ31PoMz7rkeW9STXWCDGyEU7ttkeJxyyoSK7BCmFd-9w@mail.gmail.com>

On Wed, Jul 08, 2026 at 05:36:23PM -0700, Pawandeep Oza wrote:
> On Fri, Jun 26, 2026 at 3:16 AM Yu-Chien Peter Lin <peter.lin@sifive.com> wrote:
> >
> > Add fdt_parse_worlds_all_harts() to parse RISC-V Worlds device tree
> > properties from CPU nodes:
> >   - riscv,pmwid (u32): Physical Machine World ID for this hart
> >   - riscv,pmwidlist (u64): Bitmap of permitted M-mode World IDs
> >   - riscv,pmlwidlist (u64): Bitmap of permitted S/U-mode World IDs
> >
> > This patch extends the sbi_hart_features struct with new fields to
> > store the parsed World ID configuration (has_pmwid, pmwid, pmwidlist,
> > and pmlwidlist).
> >
> > Link: https://lore.kernel.org/all/20260619105834.1277302-3-peter.lin@sifive.com/
> > Signed-off-by: Yu-Chien Peter Lin <peter.lin@sifive.com>
> > ---
> >  include/sbi/sbi_hart.h             | 15 ++++++++
> >  include/sbi_utils/fdt/fdt_helper.h |  2 +
> >  lib/utils/fdt/fdt_helper.c         | 61 ++++++++++++++++++++++++++++++
> >  platform/generic/platform.c        | 13 ++++++-
> >  4 files changed, 90 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> > index 2941809e..97072c09 100644
> > --- a/include/sbi/sbi_hart.h
> > +++ b/include/sbi/sbi_hart.h
> > @@ -135,6 +135,21 @@ struct sbi_hart_features {
> >         unsigned int pmp_log2gran;
> >         unsigned int mhpm_mask;
> >         unsigned int mhpm_bits;
> > +       /** True if riscv,pmwid was present in DT */
> > +       bool has_pmwid;
> > +       u32 pmwid;
> > +       /**
> > +        * Platform-defined bitmap of M-mode WIDs
> > +        * (from DT riscv,pmwidlist). Zero means
> > +        * absent/unrestricted.
> > +        */
> > +       u64 pmwidlist;
> > +       /**
> > +        * Platform-defined bitmap of S/U-mode WIDs
> > +        * (from DT riscv,pmlwidlist). Zero means
> > +        * absent/unrestricted.
> > +        */
> > +       u64 pmlwidlist;
> >  };
> >
> >  extern unsigned long hart_features_offset;
> > diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
> > index 75a564d1..3f3d091b 100644
> > --- a/include/sbi_utils/fdt/fdt_helper.h
> > +++ b/include/sbi_utils/fdt/fdt_helper.h
> > @@ -56,6 +56,8 @@ int fdt_parse_timebase_frequency(const void *fdt, unsigned long *freq);
> >
> >  int fdt_parse_isa_extensions_all_harts(const void *fdt);
> >
> > +int fdt_parse_worlds_all_harts(const void *fdt);
> > +
> >  int fdt_parse_gaisler_uart_node(const void *fdt, int nodeoffset,
> >                                 struct platform_uart_data *uart);
> >
> > diff --git a/lib/utils/fdt/fdt_helper.c b/lib/utils/fdt/fdt_helper.c
> > index ad4efaaf..8b40cd28 100644
> > --- a/lib/utils/fdt/fdt_helper.c
> > +++ b/lib/utils/fdt/fdt_helper.c
> > @@ -457,6 +457,67 @@ int fdt_parse_isa_extensions_all_harts(const void *fdt)
> >         return 0;
> >  }
> >
> > +int fdt_parse_worlds_all_harts(const void *fdt)
> > +{
> > +       u32 hartid;
> > +       const fdt32_t *val;
> > +       struct sbi_scratch *scratch;
> > +       struct sbi_hart_features *hfeatures;
> > +       int err, cpu_offset, cpus_offset, len;
> > +
> > +       if (!fdt)
> > +               return SBI_EINVAL;
> > +
> > +       cpus_offset = fdt_path_offset(fdt, "/cpus");
> > +       if (cpus_offset < 0)
> > +               return cpus_offset;
> > +
> > +       fdt_for_each_subnode(cpu_offset, fdt, cpus_offset) {
> what about riscv,nworlds ? I think you should parse this and based on
> that assume wid range - and rest of the wids should be rejected.

Sure, will check against riscv,nworlds.

> > +               err = fdt_parse_hart_id(fdt, cpu_offset, &hartid);
> > +               if (err)
> > +                       continue;
> > +
> > +               if (!fdt_node_is_enabled(fdt, cpu_offset))
> > +                       continue;
> > +
> > +               scratch = sbi_hartid_to_scratch(hartid);
> > +               if (!scratch)
> > +                       return SBI_ENOENT;
> > +
> > +               hfeatures = sbi_hart_features_ptr(scratch);
> > +               if (!hfeatures)
> > +                       return SBI_ENOENT;
> > +
> > +               val = fdt_getprop(fdt, cpu_offset, "riscv,pmwid", &len);
> > +               if (val && len == sizeof(fdt32_t)) {
> > +                       hfeatures->pmwid = fdt32_to_cpu(*val);
> > +                       hfeatures->has_pmwid = true;
> > +               }
> > +
> > +               val = fdt_getprop(fdt, cpu_offset, "riscv,pmwidlist", &len);
> > +               if (val && len == 2 * sizeof(fdt32_t)) {
> > +                       hfeatures->pmwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) |
> > +                                               fdt32_to_cpu(val[1]);
> > +               }
> Oza: provide some defines for magic numbers.

Okay.

> > +
> > +               val = fdt_getprop(fdt, cpu_offset, "riscv,pmlwidlist", &len);
> > +               if (val && len == 2 * sizeof(fdt32_t)) {
> > +                       hfeatures->pmlwidlist = ((u64)fdt32_to_cpu(val[0]) << 32) |
> > +                                                fdt32_to_cpu(val[1]);
> > +               }
> > +
> > +               /* Sanity checks */
> > +               if (hfeatures->has_pmwid && (hfeatures->pmwid >= 64))
> Oza:  features->pmwid >=nworlds ?

Okay.

> > +                       return SBI_EINVAL;
> > +               if (hfeatures->has_pmwid && hfeatures->pmwidlist &&
> > +                   !(hfeatures->pmwidlist & BIT_ULL(hfeatures->pmwid))) {
> > +                       return SBI_EINVAL;
> > +               }
> > +       }
> > +
> > +       return 0;
> > +}
> > +
> >  static int fdt_parse_uart_node_common(const void *fdt, int nodeoffset,
> >                                       struct platform_uart_data *uart,
> >                                       unsigned long default_freq,
> > diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> > index 1df0280d..51e9f342 100644
> > --- a/platform/generic/platform.c
> > +++ b/platform/generic/platform.c
> > @@ -255,11 +255,22 @@ int generic_final_init(bool cold_boot)
> >
> >  int generic_extensions_init(bool cold_boot)
> >  {
> > +       int rc;
> > +
> >         if (!cold_boot)
> >                 return 0;
> >
> >         /* Parse the ISA string from FDT and enable the listed extensions */
> > -       return fdt_parse_isa_extensions_all_harts(fdt_get_address());
> > +       rc = fdt_parse_isa_extensions_all_harts(fdt_get_address());
> > +       if (rc)
> > +               return rc;
> > +
> > +       /* Parse RISC-V Worlds CPU properties from FDT */
> > +       rc = fdt_parse_worlds_all_harts(fdt_get_address());
> > +       if (rc)
> > +               return rc;
> > +
> > +       return 0;
> >  }
> >
> >  int generic_domains_init(void)
> > --
> > 2.43.7
> >
> >
> > --
> > opensbi mailing list
> > opensbi@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/opensbi

-- 
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  parent reply	other threads:[~2026-07-20  3:30 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-26 10:14 [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 01/12] lib: sbi_hart: detect RISC-V Worlds ISA extensions Yu-Chien Peter Lin
2026-07-13 20:58   ` Pawandeep Oza
2026-07-20  3:14     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 02/12] lib: utils: fdt_helper: parse RISC-V Worlds DT properties Yu-Chien Peter Lin
2026-07-09  0:36   ` Pawandeep Oza
2026-07-09  0:42     ` Pawandeep Oza
2026-07-13 21:13       ` Pawandeep Oza
2026-07-20  6:41         ` Yu-Chien Peter Lin
2026-07-20  5:55       ` Yu-Chien Peter Lin
2026-07-20  3:29     ` Yu-Chien Peter Lin [this message]
2026-06-26 10:14 ` [RFC PATCH 03/12] lib: sbi_hart: enforce riscv,pmwid for Worlds ISA Yu-Chien Peter Lin
2026-07-13 21:26   ` Pawandeep Oza
2026-07-20  7:01     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 04/12] lib: sbi_hart: lock mwid CSR for RoT immutability Yu-Chien Peter Lin
2026-07-13 21:28   ` Pawandeep Oza
2026-07-20  7:36     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 05/12] include: sbi_domain: add Worlds WID fields Yu-Chien Peter Lin
2026-07-13 21:52   ` Pawandeep Oza
2026-07-20  7:55     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 06/12] include: sbi_types: add PRIx64 format macro Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 07/12] lib: sbi_domain: print World ID config at boot Yu-Chien Peter Lin
2026-07-13 23:48   ` Pawandeep Oza
2026-07-20  8:24     ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 08/12] lib: sbi_init: print M-mode World ID " Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 09/12] platform: generic: parse root domain WID config from DT Yu-Chien Peter Lin
2026-07-09  0:39   ` Pawandeep Oza
2026-07-20  8:54     ` Yu-Chien Peter Lin
2026-07-20 10:39       ` Anup Patel
2026-07-20 21:14         ` Pawandeep Oza
2026-07-21  6:24           ` Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 10/12] lib: utils: fdt_domain: parse per-domain WID properties Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 11/12] lib: sbi_domain: add Worlds CSR config on domain entry Yu-Chien Peter Lin
2026-06-26 10:14 ` [RFC PATCH 12/12] docs: add RISC-V Worlds next-wid/next-widlist DT properties Yu-Chien Peter Lin
2026-07-09  0:44 ` [RFC PATCH 00/12] Add RISC-V Worlds ISA support to OpenSBI Pawandeep Oza
2026-07-14  0:33   ` Pawandeep Oza

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