* [PATCH 1/6] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 2/6] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
` (5 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
include/sbi/sbi_pmu.h | 6 ++++++
lib/sbi/sbi_pmu.c | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
index 16f6877..d63149c 100644
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -89,6 +89,12 @@ struct sbi_pmu_device {
* Custom function returning the machine-specific irq-bit.
*/
int (*hw_counter_irq_bit)(void);
+
+ /**
+ * Custom function to inhibit counting of events while in
+ * specified mode.
+ */
+ void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
};
/** Get the PMU platform device */
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index e8bed49..cfe9b0c 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -594,7 +594,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
pmu_dev->hw_counter_disable_irq(ctr_idx);
/* Update the inhibit flags based on inhibit flags received from supervisor */
- pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+ pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (pmu_dev && pmu_dev->hw_counter_filter_mode)
+ pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
#if __riscv_xlen == 32
csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 2/6] platform: include: andes45: Add PMU related CSR defines
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 1/6] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 3/6] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
` (4 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
This patch adds CSR for Andes PMU extension.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index f570994..6b141cf 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -12,6 +12,17 @@
#define CSR_MDCM_CFG 0xfc1
#define CSR_MMSC_CFG 0xfc2
+/* Machine Trap Related Registers */
+#define CSR_MSLIDELEG 0x7d5
+
+/* Counter Related Registers */
+#define CSR_MCOUNTERWEN 0x7ce
+#define CSR_MCOUNTERINTEN 0x7cf
+#define CSR_MCOUNTERMASK_M 0x7d1
+#define CSR_MCOUNTERMASK_S 0x7d2
+#define CSR_MCOUNTERMASK_U 0x7d3
+#define CSR_MCOUNTEROVF 0x7d4
+
#define MICM_CFG_ISZ_OFFSET 6
#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
@@ -26,4 +37,19 @@
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
+/* Performance monitor */
+#define MMSC_CFG_PMNDS_MASK (1 << 15)
+#define MIP_PMOVI (1 << 18)
+
+#ifndef __ASSEMBLER__
+
+#define andes_pmu() \
+({ \
+ (((csr_read(CSR_MMSC_CFG) & \
+ MMSC_CFG_PMNDS_MASK) \
+ && misa_extension('S')) ? true : false); \
+})
+
+#endif /* __ASSEMBLER__ */
+
#endif /* _RISCV_ANDES45_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/6] platform: andes: Add Andes custom PMU support
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 1/6] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 2/6] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-09-18 14:03 ` Lad, Prabhakar
2023-09-06 9:40 ` [PATCH 4/6] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
Before the ratification of Sscofpmf, the Andes PMU extension was
designed to support the sampling and filtering of hardware performance
counters, compatible with the current SBI PMU extension and Linux perf
driver.
This patch implements the PMU extension platform callback and PMU device
callbacks to update the corresponding custom CSRs.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
platform/generic/andes/Kconfig | 4 +
platform/generic/andes/andes_pmu.c | 85 ++++++++++++++++++++++
platform/generic/andes/objects.mk | 1 +
platform/generic/include/andes/andes_pmu.h | 12 +++
4 files changed, 102 insertions(+)
create mode 100644 platform/generic/andes/andes_pmu.c
create mode 100644 platform/generic/include/andes/andes_pmu.h
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index a91fb9c..056327b 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -7,3 +7,7 @@ config ANDES45_PMA
config ANDES_SBI
bool "Andes SBI support"
default n
+
+config ANDES_PMU
+ bool "Andes PMU support"
+ default n
diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
new file mode 100644
index 0000000..d2574c7
--- /dev/null
+++ b/platform/generic/andes/andes_pmu.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2022 Andes Technology Corporation
+ *
+ */
+#include <andes/andes45.h>
+#include <andes/andes_pmu.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_pmu.h>
+#include <sbi/sbi_scratch.h>
+
+static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
+{
+ unsigned long mip_val;
+
+ if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+ return;
+
+ mip_val = csr_read(CSR_MIP);
+ if (!(mip_val & MIP_PMOVI))
+ csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
+
+ csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
+{
+ csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
+{
+ if (!flags) {
+ csr_write(CSR_MCOUNTERMASK_S, 0);
+ csr_write(CSR_MCOUNTERMASK_U, 0);
+ }
+ if (flags & SBI_PMU_CFG_FLAG_SET_UINH) {
+ csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+ csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+ }
+ if (flags & SBI_PMU_CFG_FLAG_SET_SINH) {
+ csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+ csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+ }
+}
+
+static struct sbi_pmu_device andes_pmu = {
+ .name = "andes_pmu",
+ .hw_counter_enable_irq = andes_hw_counter_enable_irq,
+ .hw_counter_disable_irq = andes_hw_counter_disable_irq,
+ /*
+ * In andes_pmu_extensions_init(), we set mslideleg[18] for each
+ * hart instead of mideleg, so leave hw_counter_irq_bit() hook
+ * unimplemented.
+ */
+ .hw_counter_irq_bit = NULL,
+ .hw_counter_filter_mode = andes_hw_counter_filter_mode
+};
+
+int andes_pmu_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ if (andes_pmu()) {
+ /*
+ * It is not rational for a hardware to support
+ * both Andes PMU and standard Sscofpmf, as they
+ * serve the same purpose.
+ */
+ if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+ SBI_HART_EXT_SSCOFPMF))
+ ebreak();
+
+ /* Machine counter write enable */
+ csr_write(CSR_MCOUNTERWEN, 0xfffffffd);
+ /* disable HPM counter in M-mode */
+ csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
+ /* delegate S-mode local interrupt to S-mode */
+ csr_write(CSR_MSLIDELEG, MIP_PMOVI);
+
+ sbi_pmu_set_device(&andes_pmu);
+ }
+
+ return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index e8f86ea..6a8c66c 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
+platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h
new file mode 100644
index 0000000..8a2e136
--- /dev/null
+++ b/platform/generic/include/andes/andes_pmu.h
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: BSD-2-Clause
+
+#ifndef _RISCV_ANDES_PMU_H
+#define _RISCV_ANDES_PMU_H
+
+#include <sbi/sbi_hart.h>
+#include <sbi_utils/fdt/fdt_helper.h>
+
+int andes_pmu_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures);
+
+#endif /* _RISCV_ANDES_PMU_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 3/6] platform: andes: Add Andes custom PMU support
2023-09-06 9:40 ` [PATCH 3/6] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-09-18 14:03 ` Lad, Prabhakar
2023-09-18 19:12 ` Conor Dooley
2023-09-21 5:40 ` Yu-Chien Peter Lin
0 siblings, 2 replies; 16+ messages in thread
From: Lad, Prabhakar @ 2023-09-18 14:03 UTC (permalink / raw)
To: opensbi
Hi Lin-san,
Thank you for the patch.
On Wed, Sep 6, 2023 at 10:43?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Before the ratification of Sscofpmf, the Andes PMU extension was
> designed to support the sampling and filtering of hardware performance
> counters, compatible with the current SBI PMU extension and Linux perf
> driver.
>
> This patch implements the PMU extension platform callback and PMU device
> callbacks to update the corresponding custom CSRs.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> platform/generic/andes/Kconfig | 4 +
> platform/generic/andes/andes_pmu.c | 85 ++++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_pmu.h | 12 +++
> 4 files changed, 102 insertions(+)
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> index a91fb9c..056327b 100644
> --- a/platform/generic/andes/Kconfig
> +++ b/platform/generic/andes/Kconfig
> @@ -7,3 +7,7 @@ config ANDES45_PMA
> config ANDES_SBI
> bool "Andes SBI support"
> default n
> +
> +config ANDES_PMU
> + bool "Andes PMU support"
> + default n
> diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> new file mode 100644
> index 0000000..d2574c7
> --- /dev/null
> +++ b/platform/generic/andes/andes_pmu.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2022 Andes Technology Corporation
2023?
> + *
> + */
> +#include <andes/andes45.h>
> +#include <andes/andes_pmu.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_pmu.h>
> +#include <sbi/sbi_scratch.h>
> +
> +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> +{
> + unsigned long mip_val;
> +
> + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> + return;
> +
> + mip_val = csr_read(CSR_MIP);
> + if (!(mip_val & MIP_PMOVI))
> + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> +
> + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> +{
Any reason why we dont check for ctr_idx >= SBI_PMU_HW_CTR_MAX?
> + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> +{
> + if (!flags) {
> + csr_write(CSR_MCOUNTERMASK_S, 0);
> + csr_write(CSR_MCOUNTERMASK_U, 0);
> + }
> + if (flags & SBI_PMU_CFG_FLAG_SET_UINH) {
> + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> + }
> + if (flags & SBI_PMU_CFG_FLAG_SET_SINH) {
> + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> + }
> +}
> +
> +static struct sbi_pmu_device andes_pmu = {
> + .name = "andes_pmu",
> + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> + /*
> + * In andes_pmu_extensions_init(), we set mslideleg[18] for each
> + * hart instead of mideleg, so leave hw_counter_irq_bit() hook
> + * unimplemented.
> + */
> + .hw_counter_irq_bit = NULL,
> + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> +};
> +
> +int andes_pmu_extensions_init(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures)
> +{
> + if (andes_pmu()) {
You can reverse the check here and return early?
> + /*
> + * It is not rational for a hardware to support
> + * both Andes PMU and standard Sscofpmf, as they
> + * serve the same purpose.
> + */
> + if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
> + SBI_HART_EXT_SSCOFPMF))
> + ebreak();
> +
> + /* Machine counter write enable */
> + csr_write(CSR_MCOUNTERWEN, 0xfffffffd);
> + /* disable HPM counter in M-mode */
> + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> + /* delegate S-mode local interrupt to S-mode */
> + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> +
> + sbi_pmu_set_device(&andes_pmu);
In my opinion we might want to append the PMU node to DT here and pass
that DT fragment to the higher stack instead of adding it in Linux.
Cheers,
Prabhakar
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/6] platform: andes: Add Andes custom PMU support
2023-09-18 14:03 ` Lad, Prabhakar
@ 2023-09-18 19:12 ` Conor Dooley
2023-09-21 5:40 ` Yu-Chien Peter Lin
1 sibling, 0 replies; 16+ messages in thread
From: Conor Dooley @ 2023-09-18 19:12 UTC (permalink / raw)
To: opensbi
On Mon, Sep 18, 2023 at 03:03:00PM +0100, Lad, Prabhakar wrote:
> Hi Lin-san,
>
> Thank you for the patch.
>
> On Wed, Sep 6, 2023 at 10:43?AM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Before the ratification of Sscofpmf, the Andes PMU extension was
> > designed to support the sampling and filtering of hardware performance
> > counters, compatible with the current SBI PMU extension and Linux perf
> > driver.
> >
> > This patch implements the PMU extension platform callback and PMU device
> > callbacks to update the corresponding custom CSRs.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > platform/generic/andes/Kconfig | 4 +
> > platform/generic/andes/andes_pmu.c | 85 ++++++++++++++++++++++
> > platform/generic/andes/objects.mk | 1 +
> > platform/generic/include/andes/andes_pmu.h | 12 +++
> > 4 files changed, 102 insertions(+)
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> > index a91fb9c..056327b 100644
> > --- a/platform/generic/andes/Kconfig
> > +++ b/platform/generic/andes/Kconfig
> > @@ -7,3 +7,7 @@ config ANDES45_PMA
> > config ANDES_SBI
> > bool "Andes SBI support"
> > default n
> > +
> > +config ANDES_PMU
> > + bool "Andes PMU support"
> > + default n
> > diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> > new file mode 100644
> > index 0000000..d2574c7
> > --- /dev/null
> > +++ b/platform/generic/andes/andes_pmu.c
> > @@ -0,0 +1,85 @@
> > +// SPDX-License-Identifier: BSD-2-Clause
> > +/*
> > + * Copyright (C) 2022 Andes Technology Corporation
> 2023?
> > + *
> > + */
> > +#include <andes/andes45.h>
> > +#include <andes/andes_pmu.h>
> > +#include <sbi/riscv_asm.h>
> > +#include <sbi/sbi_error.h>
> > +#include <sbi/sbi_pmu.h>
> > +#include <sbi/sbi_scratch.h>
> > +
> > +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> > +{
> > + unsigned long mip_val;
> > +
> > + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> > + return;
> > +
> > + mip_val = csr_read(CSR_MIP);
> > + if (!(mip_val & MIP_PMOVI))
> > + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> > +
> > + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> > +{
> Any reason why we dont check for ctr_idx >= SBI_PMU_HW_CTR_MAX?
>
> > + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> > +{
> > + if (!flags) {
> > + csr_write(CSR_MCOUNTERMASK_S, 0);
> > + csr_write(CSR_MCOUNTERMASK_U, 0);
> > + }
> > + if (flags & SBI_PMU_CFG_FLAG_SET_UINH) {
> > + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > + }
> > + if (flags & SBI_PMU_CFG_FLAG_SET_SINH) {
> > + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > + }
> > +}
> > +
> > +static struct sbi_pmu_device andes_pmu = {
> > + .name = "andes_pmu",
> > + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> > + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> > + /*
> > + * In andes_pmu_extensions_init(), we set mslideleg[18] for each
> > + * hart instead of mideleg, so leave hw_counter_irq_bit() hook
> > + * unimplemented.
> > + */
> > + .hw_counter_irq_bit = NULL,
> > + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> > +};
> > +
> > +int andes_pmu_extensions_init(const struct fdt_match *match,
> > + struct sbi_hart_features *hfeatures)
> > +{
> > + if (andes_pmu()) {
> You can reverse the check here and return early?
>
> > + /*
> > + * It is not rational for a hardware to support
> > + * both Andes PMU and standard Sscofpmf, as they
> > + * serve the same purpose.
> > + */
> > + if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
> > + SBI_HART_EXT_SSCOFPMF))
> > + ebreak();
> > +
> > + /* Machine counter write enable */
> > + csr_write(CSR_MCOUNTERWEN, 0xfffffffd);
> > + /* disable HPM counter in M-mode */
> > + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> > + /* delegate S-mode local interrupt to S-mode */
> > + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> > +
> > + sbi_pmu_set_device(&andes_pmu);
> In my opinion we might want to append the PMU node to DT here and pass
> that DT fragment to the higher stack instead of adding it in Linux.
Hmm, with you saying that it reminded me of something - this wouldn't be
just a "riscv,pmu" compatible either would it, it'd need to have some
sort of custom Andes entry AFAICT.
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 3/6] platform: andes: Add Andes custom PMU support
2023-09-18 14:03 ` Lad, Prabhakar
2023-09-18 19:12 ` Conor Dooley
@ 2023-09-21 5:40 ` Yu-Chien Peter Lin
2023-09-22 0:58 ` Yu-Chien Peter Lin
1 sibling, 1 reply; 16+ messages in thread
From: Yu-Chien Peter Lin @ 2023-09-21 5:40 UTC (permalink / raw)
To: opensbi
Hi Prabhakar,
On Mon, Sep 18, 2023 at 03:03:00PM +0100, Lad, Prabhakar wrote:
> Hi Lin-san,
>
> Thank you for the patch.
>
> On Wed, Sep 6, 2023 at 10:43?AM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Before the ratification of Sscofpmf, the Andes PMU extension was
> > designed to support the sampling and filtering of hardware performance
> > counters, compatible with the current SBI PMU extension and Linux perf
> > driver.
> >
> > This patch implements the PMU extension platform callback and PMU device
> > callbacks to update the corresponding custom CSRs.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > platform/generic/andes/Kconfig | 4 +
> > platform/generic/andes/andes_pmu.c | 85 ++++++++++++++++++++++
> > platform/generic/andes/objects.mk | 1 +
> > platform/generic/include/andes/andes_pmu.h | 12 +++
> > 4 files changed, 102 insertions(+)
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> > index a91fb9c..056327b 100644
> > --- a/platform/generic/andes/Kconfig
> > +++ b/platform/generic/andes/Kconfig
> > @@ -7,3 +7,7 @@ config ANDES45_PMA
> > config ANDES_SBI
> > bool "Andes SBI support"
> > default n
> > +
> > +config ANDES_PMU
> > + bool "Andes PMU support"
> > + default n
> > diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> > new file mode 100644
> > index 0000000..d2574c7
> > --- /dev/null
> > +++ b/platform/generic/andes/andes_pmu.c
> > @@ -0,0 +1,85 @@
> > +// SPDX-License-Identifier: BSD-2-Clause
> > +/*
> > + * Copyright (C) 2022 Andes Technology Corporation
> 2023?
OK, will update.
> > + *
> > + */
> > +#include <andes/andes45.h>
> > +#include <andes/andes_pmu.h>
> > +#include <sbi/riscv_asm.h>
> > +#include <sbi/sbi_error.h>
> > +#include <sbi/sbi_pmu.h>
> > +#include <sbi/sbi_scratch.h>
> > +
> > +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> > +{
> > + unsigned long mip_val;
> > +
> > + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> > + return;
> > +
> > + mip_val = csr_read(CSR_MIP);
> > + if (!(mip_val & MIP_PMOVI))
> > + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> > +
> > + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> > +{
> Any reason why we dont check for ctr_idx >= SBI_PMU_HW_CTR_MAX?
Its function caller [1] has done the check.
> > + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> > +{
> > + if (!flags) {
> > + csr_write(CSR_MCOUNTERMASK_S, 0);
> > + csr_write(CSR_MCOUNTERMASK_U, 0);
> > + }
> > + if (flags & SBI_PMU_CFG_FLAG_SET_UINH) {
> > + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > + }
> > + if (flags & SBI_PMU_CFG_FLAG_SET_SINH) {
> > + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > + }
> > +}
> > +
> > +static struct sbi_pmu_device andes_pmu = {
> > + .name = "andes_pmu",
> > + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> > + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> > + /*
> > + * In andes_pmu_extensions_init(), we set mslideleg[18] for each
> > + * hart instead of mideleg, so leave hw_counter_irq_bit() hook
> > + * unimplemented.
> > + */
> > + .hw_counter_irq_bit = NULL,
> > + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> > +};
> > +
> > +int andes_pmu_extensions_init(const struct fdt_match *match,
> > + struct sbi_hart_features *hfeatures)
> > +{
> > + if (andes_pmu()) {
> You can reverse the check here and return early?
Sure, will do.
> > + /*
> > + * It is not rational for a hardware to support
> > + * both Andes PMU and standard Sscofpmf, as they
> > + * serve the same purpose.
> > + */
> > + if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
> > + SBI_HART_EXT_SSCOFPMF))
> > + ebreak();
> > +
> > + /* Machine counter write enable */
> > + csr_write(CSR_MCOUNTERWEN, 0xfffffffd);
> > + /* disable HPM counter in M-mode */
> > + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> > + /* delegate S-mode local interrupt to S-mode */
> > + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> > +
> > + sbi_pmu_set_device(&andes_pmu);
> In my opinion we might want to append the PMU node to DT here
Sure, I will add fdt fixup so RZ/Five users won't need to manually
append the PMU node.
> and pass that DT fragment to the higher stack instead of adding it in Linux.
The PMU node is not visible to S-mode SW (U-Boot proper or Linux) since
it is only used to initialize the event counter mappings and erased in
the generic_final_init() [2].
Thanks,
Peter Lin
[1] https://github.com/riscv-software-src/opensbi/blob/v1.3.1/lib/sbi/sbi_pmu.c#L583
[2] https://github.com/riscv-software-src/opensbi/blob/master/platform/generic/platform.c#L172
> Cheers,
> Prabhakar
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/6] platform: andes: Enable Andes PMU for AE350
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
` (2 preceding siblings ...)
2023-09-06 9:40 ` [PATCH 3/6] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 5/6] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
` (2 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for AE350 platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
platform/generic/Kconfig | 1 +
platform/generic/andes/ae350.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 72768ed..16c28fe 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
config PLATFORM_ANDES_AE350
bool "Andes AE350 support"
select SYS_ATCSMU
+ select ANDES_PMU
default n
config PLATFORM_RENESAS_RZFIVE
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 01bd02d..c8adb0d 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -8,6 +8,7 @@
*/
#include <platform_override.h>
+#include <andes/andes_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/sys/atcsmu.h>
@@ -118,4 +119,5 @@ static const struct fdt_match andes_ae350_match[] = {
const struct platform_override andes_ae350 = {
.match_table = andes_ae350_match,
.final_init = ae350_final_init,
+ .extensions_init = andes_pmu_extensions_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 5/6] platform: rzfive: Enable Andes PMU for RZ/Five
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
` (3 preceding siblings ...)
2023-09-06 9:40 ` [PATCH 4/6] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-09-06 9:40 ` [PATCH 6/6] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
2023-10-06 12:17 ` [PATCH 0/6] Add Andes PMU extension support Anup Patel
6 siblings, 0 replies; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for RZ/Five.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
platform/generic/Kconfig | 1 +
platform/generic/renesas/rzfive/rzfive.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 16c28fe..e6e7e94 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -38,6 +38,7 @@ config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES45_PMA
select ANDES_SBI
+ select ANDES_PMU
default n
config PLATFORM_SIFIVE_FU540
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index a69797b..7b65a50 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,6 +5,7 @@
*/
#include <andes/andes45_pma.h>
+#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
#include <sbi/sbi_domain.h>
@@ -57,4 +58,5 @@ const struct platform_override renesas_rzfive = {
.early_init = renesas_rzfive_early_init,
.final_init = renesas_rzfive_final_init,
.vendor_ext_provider = andes_sbi_vendor_ext_provider,
+ .extensions_init = andes_pmu_extensions_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 6/6] docs: pmu: Add Andes PMU node example
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
` (4 preceding siblings ...)
2023-09-06 9:40 ` [PATCH 5/6] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
@ 2023-09-06 9:40 ` Yu Chien Peter Lin
2023-10-06 12:17 ` [PATCH 0/6] Add Andes PMU extension support Anup Patel
6 siblings, 0 replies; 16+ messages in thread
From: Yu Chien Peter Lin @ 2023-09-06 9:40 UTC (permalink / raw)
To: opensbi
Add PMU node example for event index to counter index mapping
and selector value translation of Andes' CPUs.
Currently, there are 4 HPM counters that can be used to monitor
all of the events for each hart.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
docs/pmu_support.md | 87 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 8cfa08c..6d8fa9d 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -125,3 +125,90 @@ pmu {
<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
};
```
+
+### Example 3
+
+```
+/*
+ * For Andes 45-series platforms. The encodings can be found in the
+ * "Machine Performance Monitoring Event Selector" section
+ * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ */
+pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmevent =
+ <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */
+ <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */
+ <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */
+ <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */
+ <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
+ <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */
+ <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */
+ <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */
+ <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */
+ <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */
+ <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */
+ <0x10009 0x0000 0x31>, /* L1I_READ_MISS -> I-Cache miss */
+ <0x10018 0x0000 0x131>, /* DTLB_READ_ACCESS -> Main DTLB access */
+ <0x10020 0x0000 0x111>; /* ITLB_READ_ACCESS -> Main ITLB access */
+ riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
+ <0x10000 0x10003 0x78>,
+ <0x10008 0x10009 0x78>,
+ <0x10018 0x10018 0x78>,
+ <0x10020 0x10020 0x78>;
+ riscv,raw-event-to-mhpmcounters =
+ <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
+ <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
+ <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
+ <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
+ <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
+ <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
+ <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
+ <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
+ <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
+ <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
+ <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
+ <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
+ <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
+ <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
+ <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
+ <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
+ <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
+ <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
+ <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
+ <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
+ <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
+ <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
+ <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
+ <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
+ <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
+ <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
+ <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
+ <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
+ <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
+ <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
+ <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
+ <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
+ <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
+ <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
+ <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
+ <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
+ <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
+ <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
+ <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
+ <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
+ <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
+ <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
+ <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
+ <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
+ <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
+ <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
+ <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
+ <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
+ <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
+ <0x0 0x181 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for source operand ready in the integer register file scoreboard */
+ <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
+ <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
+ <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
+};
+```
--
2.34.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 0/6] Add Andes PMU extension support
2023-09-06 9:40 [PATCH 0/6] Add Andes PMU extension support Yu Chien Peter Lin
` (5 preceding siblings ...)
2023-09-06 9:40 ` [PATCH 6/6] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
@ 2023-10-06 12:17 ` Anup Patel
2023-10-07 6:04 ` Yu-Chien Peter Lin
6 siblings, 1 reply; 16+ messages in thread
From: Anup Patel @ 2023-10-06 12:17 UTC (permalink / raw)
To: opensbi
Hi Yu Chien Peter Lin,
On Wed, Sep 6, 2023 at 3:12?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch series enables perf tool to utilize Andes PMU
> extension via PMU SBI calls, provides PMU device callbacks
> for event sampling and mode filtering.
>
> We also provide a PMU node example of AX45MP in the last
> patch.
>
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support
> - https://github.com/andestech/linux/commits/andes-pmu-support
>
> Yu Chien Peter Lin (6):
> sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> platform: include: andes45: Add PMU related CSR defines
> platform: andes: Add Andes custom PMU support
> platform: andes: Enable Andes PMU for AE350
> platform: rzfive: Enable Andes PMU for RZ/Five
> docs: pmu: Add Andes PMU node example
I assume there is going to be a v2 due to comments on PATCH3 ?
Regards,
Anup
>
> docs/pmu_support.md | 87 ++++++++++++++++++++++
> include/sbi/sbi_pmu.h | 6 ++
> lib/sbi/sbi_pmu.c | 5 +-
> platform/generic/Kconfig | 2 +
> platform/generic/andes/Kconfig | 4 +
> platform/generic/andes/ae350.c | 2 +
> platform/generic/andes/andes_pmu.c | 85 +++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes45.h | 26 +++++++
> platform/generic/include/andes/andes_pmu.h | 12 +++
> platform/generic/renesas/rzfive/rzfive.c | 2 +
> 11 files changed, 231 insertions(+), 1 deletion(-)
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 0/6] Add Andes PMU extension support
2023-10-06 12:17 ` [PATCH 0/6] Add Andes PMU extension support Anup Patel
@ 2023-10-07 6:04 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 16+ messages in thread
From: Yu-Chien Peter Lin @ 2023-10-07 6:04 UTC (permalink / raw)
To: opensbi
Hi Anup,
On Fri, Oct 06, 2023 at 05:47:16PM +0530, Anup Patel wrote:
> Hi Yu Chien Peter Lin,
>
> On Wed, Sep 6, 2023 at 3:12?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > This patch series enables perf tool to utilize Andes PMU
> > extension via PMU SBI calls, provides PMU device callbacks
> > for event sampling and mode filtering.
> >
> > We also provide a PMU node example of AX45MP in the last
> > patch.
> >
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support
> > - https://github.com/andestech/linux/commits/andes-pmu-support
> >
> > Yu Chien Peter Lin (6):
> > sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> > platform: include: andes45: Add PMU related CSR defines
> > platform: andes: Add Andes custom PMU support
> > platform: andes: Enable Andes PMU for AE350
> > platform: rzfive: Enable Andes PMU for RZ/Five
> > docs: pmu: Add Andes PMU node example
>
> I assume there is going to be a v2 due to comments on PATCH3 ?
Yes we are working on this.
Thanks.
Peter Lin
> Regards,
> Anup
>
> >
> > docs/pmu_support.md | 87 ++++++++++++++++++++++
> > include/sbi/sbi_pmu.h | 6 ++
> > lib/sbi/sbi_pmu.c | 5 +-
> > platform/generic/Kconfig | 2 +
> > platform/generic/andes/Kconfig | 4 +
> > platform/generic/andes/ae350.c | 2 +
> > platform/generic/andes/andes_pmu.c | 85 +++++++++++++++++++++
> > platform/generic/andes/objects.mk | 1 +
> > platform/generic/include/andes/andes45.h | 26 +++++++
> > platform/generic/include/andes/andes_pmu.h | 12 +++
> > platform/generic/renesas/rzfive/rzfive.c | 2 +
> > 11 files changed, 231 insertions(+), 1 deletion(-)
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > --
> > 2.34.1
> >
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