* [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-24 14:43 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
` (14 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
From: Leo Yu-Chi Liang <ycliang@andestech.com>
The old scheme doesn't allow sending hart0 self-IPI as the
corresponding bit on pending register is hardwired to 0, this
could lead to unhandle IPIs on SMP systems, esp. on single-core.
Furthermore, the limitation of old scheme is 8-core, instead of
reserving source hart information, we assign bit (x + 1) as the
enable and pending bit of hartx, this also expands the bootable
hart number.
The following diagram shows the enable bits of the new scheme
on 32-core Andes platform.
Pending regs: 0x1000 x---0---0---0---0------0---0
Pending hart ID: 0 1 2 3 ... 30 31
Interrupt ID: 0 1 2 3 4 ... 31 32
| | | | | | |
Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
| | | | | | |
0x2080 x---0---1---0---0-...--0---0---> hart1
| | | | | | |
0x2100 x---0---0---1---0-...--0---0---> hart2
| | | | | | |
0x2180 x---0---0---0---1-...--0---0---> hart3
. . . . . . .
. . . . . . .
. . . . . . .
0x2f00 x---0---0---0---0-...--1---0---> hart30
| | | | | | |
0x2f80 x---0---0---0---0-...--0---1---> hart31
<-------- word 0 -------><--- word 1 --->
To send IPI to hart0, for example, another hart (including hart0
itself) will set bit 1 of first word on the pending register.
We also fix indentation in andes_plicsw.h along with this patch.
Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support")
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Randolph <randolph@andestech.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
---
Changes v2 -> v3:
- New patch
---
include/sbi_utils/ipi/andes_plicsw.h | 23 +++---
lib/utils/ipi/andes_plicsw.c | 104 ++++++++++-----------------
2 files changed, 46 insertions(+), 81 deletions(-)
diff --git a/include/sbi_utils/ipi/andes_plicsw.h b/include/sbi_utils/ipi/andes_plicsw.h
index e93cda0..0d18444 100644
--- a/include/sbi_utils/ipi/andes_plicsw.h
+++ b/include/sbi_utils/ipi/andes_plicsw.h
@@ -13,30 +13,23 @@
#ifndef _IPI_ANDES_PLICSW_H_
#define _IPI_ANDES_PLICSW_H_
-#define PLICSW_PRIORITY_BASE 0x4
+#define PLICSW_PRIORITY_BASE 0x4
-#define PLICSW_PENDING_BASE 0x1000
-#define PLICSW_PENDING_STRIDE 0x8
+#define PLICSW_PENDING_BASE 0x1000
-#define PLICSW_ENABLE_BASE 0x2000
-#define PLICSW_ENABLE_STRIDE 0x80
+#define PLICSW_ENABLE_BASE 0x2000
+#define PLICSW_ENABLE_STRIDE 0x80
-#define PLICSW_CONTEXT_BASE 0x200000
-#define PLICSW_CONTEXT_STRIDE 0x1000
-#define PLICSW_CONTEXT_CLAIM 0x4
+#define PLICSW_CONTEXT_BASE 0x200000
+#define PLICSW_CONTEXT_STRIDE 0x1000
+#define PLICSW_CONTEXT_CLAIM 0x4
-#define PLICSW_HART_MASK 0x01010101
-
-#define PLICSW_HART_MAX_NR 8
-
-#define PLICSW_REGION_ALIGN 0x1000
+#define PLICSW_REGION_ALIGN 0x1000
struct plicsw_data {
unsigned long addr;
unsigned long size;
uint32_t hart_count;
- /* hart id to source id table */
- uint32_t source_id[PLICSW_HART_MAX_NR];
};
int plicsw_warm_ipi_init(void);
diff --git a/lib/utils/ipi/andes_plicsw.c b/lib/utils/ipi/andes_plicsw.c
index 5693efb..413ac20 100644
--- a/lib/utils/ipi/andes_plicsw.c
+++ b/lib/utils/ipi/andes_plicsw.c
@@ -18,77 +18,45 @@
struct plicsw_data plicsw;
-static inline void plicsw_claim(void)
+static void plicsw_ipi_send(u32 hart_index)
{
- u32 hartid = current_hartid();
+ ulong pending_reg;
+ u32 interrupt_id, word_index, pending_bit;
+ u32 target_hart = sbi_hartindex_to_hartid(hart_index);
- if (plicsw.hart_count <= hartid)
+ if (plicsw.hart_count <= target_hart)
ebreak();
- plicsw.source_id[hartid] =
- readl((void *)plicsw.addr + PLICSW_CONTEXT_BASE +
- PLICSW_CONTEXT_CLAIM + PLICSW_CONTEXT_STRIDE * hartid);
-}
-
-static inline void plicsw_complete(void)
-{
- u32 hartid = current_hartid();
- u32 source = plicsw.source_id[hartid];
-
- writel(source, (void *)plicsw.addr + PLICSW_CONTEXT_BASE +
- PLICSW_CONTEXT_CLAIM +
- PLICSW_CONTEXT_STRIDE * hartid);
-}
-
-static inline void plic_sw_pending(u32 target_hart)
-{
/*
- * The pending array registers are w1s type.
- * IPI pending array mapping as following:
- *
- * Pending array start address: base + 0x1000
- * ---------------------------------
- * | hart3 | hart2 | hart1 | hart0 |
- * ---------------------------------
- * Each hartX can send IPI to another hart by setting the
- * bitY to its own region (see the below).
- *
- * In each hartX region:
- * <---------- PICSW_PENDING_STRIDE -------->
- * | bit7 | ... | bit3 | bit2 | bit1 | bit0 |
- * ------------------------------------------
- * The bitY of hartX region indicates that hartX sends an
- * IPI to hartY.
+ * We assign a single bit for each hart.
+ * Bit 0 is hardwired to 0, thus unavailable.
+ * Bit(X+1) indicates that IPI is sent to hartX.
*/
- u32 hartid = current_hartid();
- u32 word_index = hartid / 4;
- u32 per_hart_offset = PLICSW_PENDING_STRIDE * hartid;
- u32 val = 1 << target_hart << per_hart_offset;
+ interrupt_id = target_hart + 1;
+ word_index = interrupt_id / 32;
+ pending_bit = interrupt_id % 32;
+ pending_reg = plicsw.addr + PLICSW_PENDING_BASE + word_index * 4;
- writel(val, (void *)plicsw.addr + PLICSW_PENDING_BASE + word_index * 4);
+ /* Set target hart's mip.MSIP */
+ writel_relaxed(BIT(pending_bit), (void *)pending_reg);
}
-static void plicsw_ipi_send(u32 hart_index)
+static void plicsw_ipi_clear(u32 hart_index)
{
u32 target_hart = sbi_hartindex_to_hartid(hart_index);
+ ulong reg = plicsw.addr + PLICSW_CONTEXT_BASE + PLICSW_CONTEXT_CLAIM +
+ PLICSW_CONTEXT_STRIDE * target_hart;
if (plicsw.hart_count <= target_hart)
ebreak();
- /* Set PLICSW IPI */
- plic_sw_pending(target_hart);
-}
+ /* Claim */
+ u32 source = readl((void *)reg);
-static void plicsw_ipi_clear(u32 hart_index)
-{
- u32 target_hart = sbi_hartindex_to_hartid(hart_index);
-
- if (plicsw.hart_count <= target_hart)
- ebreak();
+ /* A successful claim will clear mip.MSIP */
- /* Clear PLICSW IPI */
- plicsw_claim();
- plicsw_complete();
+ /* Complete */
+ writel(source, (void *)reg);
}
static struct sbi_ipi_device plicsw_ipi = {
@@ -110,22 +78,26 @@ int plicsw_warm_ipi_init(void)
int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
{
int rc;
+ u32 interrupt_id, word_index, enable_bit;
+ ulong enable_reg, priority_reg;
/* Setup source priority */
- uint32_t *priority = (void *)plicsw->addr + PLICSW_PRIORITY_BASE;
-
- for (int i = 0; i < plicsw->hart_count; i++)
- writel(1, &priority[i]);
-
- /* Setup target enable */
- uint32_t enable_mask = PLICSW_HART_MASK;
+ for (int i = 0; i < plicsw->hart_count; i++) {
+ priority_reg = plicsw->addr + PLICSW_PRIORITY_BASE + i * 4;
+ writel(1, (void *)priority_reg);
+ }
+ /*
+ * Setup enable for each hart, skip non-existent interrupt ID 0
+ * which is hardwired to 0.
+ */
for (int i = 0; i < plicsw->hart_count; i++) {
- uint32_t *enable = (void *)plicsw->addr + PLICSW_ENABLE_BASE +
- PLICSW_ENABLE_STRIDE * i;
- writel(enable_mask, enable);
- writel(enable_mask, enable + 1);
- enable_mask <<= 1;
+ interrupt_id = i + 1;
+ word_index = interrupt_id / 32;
+ enable_bit = interrupt_id % 32;
+ enable_reg = plicsw->addr + PLICSW_ENABLE_BASE +
+ PLICSW_ENABLE_STRIDE * i + 4 * word_index;
+ writel(BIT(enable_bit), (void *)enable_reg);
}
/* Add PLICSW region to the root domain */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
2023-11-22 7:36 ` [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme Yu Chien Peter Lin
@ 2023-11-24 14:43 ` Lad, Prabhakar
0 siblings, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:43 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:40?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> From: Leo Yu-Chi Liang <ycliang@andestech.com>
>
> The old scheme doesn't allow sending hart0 self-IPI as the
> corresponding bit on pending register is hardwired to 0, this
> could lead to unhandle IPIs on SMP systems, esp. on single-core.
>
> Furthermore, the limitation of old scheme is 8-core, instead of
> reserving source hart information, we assign bit (x + 1) as the
> enable and pending bit of hartx, this also expands the bootable
> hart number.
>
> The following diagram shows the enable bits of the new scheme
> on 32-core Andes platform.
>
> Pending regs: 0x1000 x---0---0---0---0------0---0
> Pending hart ID: 0 1 2 3 ... 30 31
> Interrupt ID: 0 1 2 3 4 ... 31 32
> | | | | | | |
> Enable regs: 0x2000 x---1---0---0---0-...--0---0---> hart0
> | | | | | | |
> 0x2080 x---0---1---0---0-...--0---0---> hart1
> | | | | | | |
> 0x2100 x---0---0---1---0-...--0---0---> hart2
> | | | | | | |
> 0x2180 x---0---0---0---1-...--0---0---> hart3
> . . . . . . .
> . . . . . . .
> . . . . . . .
> 0x2f00 x---0---0---0---0-...--1---0---> hart30
> | | | | | | |
> 0x2f80 x---0---0---0---0-...--0---1---> hart31
> <-------- word 0 -------><--- word 1 --->
>
> To send IPI to hart0, for example, another hart (including hart0
> itself) will set bit 1 of first word on the pending register.
>
> We also fix indentation in andes_plicsw.h along with this patch.
>
> Fixes: ce7c490719ed ("lib: utils/ipi: Add Andes fdt ipi driver support")
> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Randolph <randolph@andestech.com>
> Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005665.html
> ---
> Changes v2 -> v3:
> - New patch
> ---
> include/sbi_utils/ipi/andes_plicsw.h | 23 +++---
> lib/utils/ipi/andes_plicsw.c | 104 ++++++++++-----------------
> 2 files changed, 46 insertions(+), 81 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/include/sbi_utils/ipi/andes_plicsw.h b/include/sbi_utils/ipi/andes_plicsw.h
> index e93cda0..0d18444 100644
> --- a/include/sbi_utils/ipi/andes_plicsw.h
> +++ b/include/sbi_utils/ipi/andes_plicsw.h
> @@ -13,30 +13,23 @@
> #ifndef _IPI_ANDES_PLICSW_H_
> #define _IPI_ANDES_PLICSW_H_
>
> -#define PLICSW_PRIORITY_BASE 0x4
> +#define PLICSW_PRIORITY_BASE 0x4
>
> -#define PLICSW_PENDING_BASE 0x1000
> -#define PLICSW_PENDING_STRIDE 0x8
> +#define PLICSW_PENDING_BASE 0x1000
>
> -#define PLICSW_ENABLE_BASE 0x2000
> -#define PLICSW_ENABLE_STRIDE 0x80
> +#define PLICSW_ENABLE_BASE 0x2000
> +#define PLICSW_ENABLE_STRIDE 0x80
>
> -#define PLICSW_CONTEXT_BASE 0x200000
> -#define PLICSW_CONTEXT_STRIDE 0x1000
> -#define PLICSW_CONTEXT_CLAIM 0x4
> +#define PLICSW_CONTEXT_BASE 0x200000
> +#define PLICSW_CONTEXT_STRIDE 0x1000
> +#define PLICSW_CONTEXT_CLAIM 0x4
>
> -#define PLICSW_HART_MASK 0x01010101
> -
> -#define PLICSW_HART_MAX_NR 8
> -
> -#define PLICSW_REGION_ALIGN 0x1000
> +#define PLICSW_REGION_ALIGN 0x1000
>
> struct plicsw_data {
> unsigned long addr;
> unsigned long size;
> uint32_t hart_count;
> - /* hart id to source id table */
> - uint32_t source_id[PLICSW_HART_MAX_NR];
> };
>
> int plicsw_warm_ipi_init(void);
> diff --git a/lib/utils/ipi/andes_plicsw.c b/lib/utils/ipi/andes_plicsw.c
> index 5693efb..413ac20 100644
> --- a/lib/utils/ipi/andes_plicsw.c
> +++ b/lib/utils/ipi/andes_plicsw.c
> @@ -18,77 +18,45 @@
>
> struct plicsw_data plicsw;
>
> -static inline void plicsw_claim(void)
> +static void plicsw_ipi_send(u32 hart_index)
> {
> - u32 hartid = current_hartid();
> + ulong pending_reg;
> + u32 interrupt_id, word_index, pending_bit;
> + u32 target_hart = sbi_hartindex_to_hartid(hart_index);
>
> - if (plicsw.hart_count <= hartid)
> + if (plicsw.hart_count <= target_hart)
> ebreak();
>
> - plicsw.source_id[hartid] =
> - readl((void *)plicsw.addr + PLICSW_CONTEXT_BASE +
> - PLICSW_CONTEXT_CLAIM + PLICSW_CONTEXT_STRIDE * hartid);
> -}
> -
> -static inline void plicsw_complete(void)
> -{
> - u32 hartid = current_hartid();
> - u32 source = plicsw.source_id[hartid];
> -
> - writel(source, (void *)plicsw.addr + PLICSW_CONTEXT_BASE +
> - PLICSW_CONTEXT_CLAIM +
> - PLICSW_CONTEXT_STRIDE * hartid);
> -}
> -
> -static inline void plic_sw_pending(u32 target_hart)
> -{
> /*
> - * The pending array registers are w1s type.
> - * IPI pending array mapping as following:
> - *
> - * Pending array start address: base + 0x1000
> - * ---------------------------------
> - * | hart3 | hart2 | hart1 | hart0 |
> - * ---------------------------------
> - * Each hartX can send IPI to another hart by setting the
> - * bitY to its own region (see the below).
> - *
> - * In each hartX region:
> - * <---------- PICSW_PENDING_STRIDE -------->
> - * | bit7 | ... | bit3 | bit2 | bit1 | bit0 |
> - * ------------------------------------------
> - * The bitY of hartX region indicates that hartX sends an
> - * IPI to hartY.
> + * We assign a single bit for each hart.
> + * Bit 0 is hardwired to 0, thus unavailable.
> + * Bit(X+1) indicates that IPI is sent to hartX.
> */
> - u32 hartid = current_hartid();
> - u32 word_index = hartid / 4;
> - u32 per_hart_offset = PLICSW_PENDING_STRIDE * hartid;
> - u32 val = 1 << target_hart << per_hart_offset;
> + interrupt_id = target_hart + 1;
> + word_index = interrupt_id / 32;
> + pending_bit = interrupt_id % 32;
> + pending_reg = plicsw.addr + PLICSW_PENDING_BASE + word_index * 4;
>
> - writel(val, (void *)plicsw.addr + PLICSW_PENDING_BASE + word_index * 4);
> + /* Set target hart's mip.MSIP */
> + writel_relaxed(BIT(pending_bit), (void *)pending_reg);
> }
>
> -static void plicsw_ipi_send(u32 hart_index)
> +static void plicsw_ipi_clear(u32 hart_index)
> {
> u32 target_hart = sbi_hartindex_to_hartid(hart_index);
> + ulong reg = plicsw.addr + PLICSW_CONTEXT_BASE + PLICSW_CONTEXT_CLAIM +
> + PLICSW_CONTEXT_STRIDE * target_hart;
>
> if (plicsw.hart_count <= target_hart)
> ebreak();
>
> - /* Set PLICSW IPI */
> - plic_sw_pending(target_hart);
> -}
> + /* Claim */
> + u32 source = readl((void *)reg);
>
> -static void plicsw_ipi_clear(u32 hart_index)
> -{
> - u32 target_hart = sbi_hartindex_to_hartid(hart_index);
> -
> - if (plicsw.hart_count <= target_hart)
> - ebreak();
> + /* A successful claim will clear mip.MSIP */
>
> - /* Clear PLICSW IPI */
> - plicsw_claim();
> - plicsw_complete();
> + /* Complete */
> + writel(source, (void *)reg);
> }
>
> static struct sbi_ipi_device plicsw_ipi = {
> @@ -110,22 +78,26 @@ int plicsw_warm_ipi_init(void)
> int plicsw_cold_ipi_init(struct plicsw_data *plicsw)
> {
> int rc;
> + u32 interrupt_id, word_index, enable_bit;
> + ulong enable_reg, priority_reg;
>
> /* Setup source priority */
> - uint32_t *priority = (void *)plicsw->addr + PLICSW_PRIORITY_BASE;
> -
> - for (int i = 0; i < plicsw->hart_count; i++)
> - writel(1, &priority[i]);
> -
> - /* Setup target enable */
> - uint32_t enable_mask = PLICSW_HART_MASK;
> + for (int i = 0; i < plicsw->hart_count; i++) {
> + priority_reg = plicsw->addr + PLICSW_PRIORITY_BASE + i * 4;
> + writel(1, (void *)priority_reg);
> + }
>
> + /*
> + * Setup enable for each hart, skip non-existent interrupt ID 0
> + * which is hardwired to 0.
> + */
> for (int i = 0; i < plicsw->hart_count; i++) {
> - uint32_t *enable = (void *)plicsw->addr + PLICSW_ENABLE_BASE +
> - PLICSW_ENABLE_STRIDE * i;
> - writel(enable_mask, enable);
> - writel(enable_mask, enable + 1);
> - enable_mask <<= 1;
> + interrupt_id = i + 1;
> + word_index = interrupt_id / 32;
> + enable_bit = interrupt_id % 32;
> + enable_reg = plicsw->addr + PLICSW_ENABLE_BASE +
> + PLICSW_ENABLE_STRIDE * i + 4 * word_index;
> + writel(BIT(enable_bit), (void *)enable_reg);
> }
>
> /* Add PLICSW region to the root domain */
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-22 23:47 ` Atish Patra
2023-11-24 14:45 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions Yu Chien Peter Lin
` (13 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
This patch makes the following changes:
- As sbi_platform_pmu_init() returns a negative error code on
failure, let sbi_pmu_init() to hang by propagating the error
code.
- In order to distinguish the SBI_EFAIL error returned by
sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
generic_pmu_init() ignores such case.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Include Anup's RB tag
---
lib/sbi/sbi_pmu.c | 5 ++++-
lib/utils/fdt/fdt_pmu.c | 2 +-
platform/generic/platform.c | 8 +++++++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index f4c8fc4..3cbd4ff 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
struct sbi_pmu_hart_state *phs;
const struct sbi_platform *plat;
+ int rc;
if (cold_boot) {
hw_event_map = sbi_calloc(sizeof(*hw_event_map),
@@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
plat = sbi_platform_ptr(scratch);
/* Initialize hw pmu events */
- sbi_platform_pmu_init(plat);
+ rc = sbi_platform_pmu_init(plat);
+ if (rc)
+ return rc;
/* mcycle & minstret is available always */
if (!hpm_count)
diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
index 83301bb..a8d7648 100644
--- a/lib/utils/fdt/fdt_pmu.c
+++ b/lib/utils/fdt/fdt_pmu.c
@@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
if (pmu_offset < 0)
- return SBI_EFAIL;
+ return SBI_ENOENT;
event_ctr_map = fdt_getprop(fdt, pmu_offset,
"riscv,event-to-mhpmcounters", &len);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 85acecd..fa400b9 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
static int generic_pmu_init(void)
{
- return fdt_pmu_setup(fdt_get_address());
+ int rc;
+
+ rc = fdt_pmu_setup(fdt_get_address());
+ if (rc && rc != SBI_ENOENT)
+ return rc;
+
+ return 0;
}
static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-11-22 7:36 ` [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
@ 2023-11-22 23:47 ` Atish Patra
2023-11-28 5:33 ` Yu-Chien Peter Lin
2023-11-24 14:45 ` Lad, Prabhakar
1 sibling, 1 reply; 43+ messages in thread
From: Atish Patra @ 2023-11-22 23:47 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:39?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch makes the following changes:
>
> - As sbi_platform_pmu_init() returns a negative error code on
> failure, let sbi_pmu_init() to hang by propagating the error
> code.
>
Why ? PMU is not a critical resource for booting the system. A system
can function without it.
Do we really want to hang the system booting in case sbi_pmu_init fails ?
> - In order to distinguish the SBI_EFAIL error returned by
> sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
> that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
> generic_pmu_init() ignores such case.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Include Anup's RB tag
> ---
> lib/sbi/sbi_pmu.c | 5 ++++-
> lib/utils/fdt/fdt_pmu.c | 2 +-
> platform/generic/platform.c | 8 +++++++-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index f4c8fc4..3cbd4ff 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
> int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
> struct sbi_pmu_hart_state *phs;
> const struct sbi_platform *plat;
> + int rc;
>
> if (cold_boot) {
> hw_event_map = sbi_calloc(sizeof(*hw_event_map),
> @@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
>
> plat = sbi_platform_ptr(scratch);
> /* Initialize hw pmu events */
> - sbi_platform_pmu_init(plat);
> + rc = sbi_platform_pmu_init(plat);
> + if (rc)
> + return rc;
>
> /* mcycle & minstret is available always */
> if (!hpm_count)
> diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
> index 83301bb..a8d7648 100644
> --- a/lib/utils/fdt/fdt_pmu.c
> +++ b/lib/utils/fdt/fdt_pmu.c
> @@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
>
> pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
> if (pmu_offset < 0)
> - return SBI_EFAIL;
> + return SBI_ENOENT;
>
> event_ctr_map = fdt_getprop(fdt, pmu_offset,
> "riscv,event-to-mhpmcounters", &len);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 85acecd..fa400b9 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
>
> static int generic_pmu_init(void)
> {
> - return fdt_pmu_setup(fdt_get_address());
> + int rc;
> +
> + rc = fdt_pmu_setup(fdt_get_address());
> + if (rc && rc != SBI_ENOENT)
> + return rc;
> +
> + return 0;
> }
>
> static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
> --
> 2.34.1
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-11-22 23:47 ` Atish Patra
@ 2023-11-28 5:33 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 43+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-28 5:33 UTC (permalink / raw)
To: opensbi
Hi Atish,
Thanks for the review.
On Wed, Nov 22, 2023 at 03:47:43PM -0800, Atish Patra wrote:
> On Tue, Nov 21, 2023 at 11:39?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > This patch makes the following changes:
> >
> > - As sbi_platform_pmu_init() returns a negative error code on
> > failure, let sbi_pmu_init() to hang by propagating the error
> > code.
> >
>
> Why ? PMU is not a critical resource for booting the system. A system
> can function without it.
> Do we really want to hang the system booting in case sbi_pmu_init fails ?
Agreed, I will simply print the error code with sbi_dprintf() rather
than returning error.
Best regards,
Peter Lin
> > - In order to distinguish the SBI_EFAIL error returned by
> > sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
> > that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
> > generic_pmu_init() ignores such case.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > Changes v2 -> v3:
> > - Include Anup's RB tag
> > ---
> > lib/sbi/sbi_pmu.c | 5 ++++-
> > lib/utils/fdt/fdt_pmu.c | 2 +-
> > platform/generic/platform.c | 8 +++++++-
> > 3 files changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> > index f4c8fc4..3cbd4ff 100644
> > --- a/lib/sbi/sbi_pmu.c
> > +++ b/lib/sbi/sbi_pmu.c
> > @@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
> > int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
> > struct sbi_pmu_hart_state *phs;
> > const struct sbi_platform *plat;
> > + int rc;
> >
> > if (cold_boot) {
> > hw_event_map = sbi_calloc(sizeof(*hw_event_map),
> > @@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
> >
> > plat = sbi_platform_ptr(scratch);
> > /* Initialize hw pmu events */
> > - sbi_platform_pmu_init(plat);
> > + rc = sbi_platform_pmu_init(plat);
> > + if (rc)
> > + return rc;
> >
> > /* mcycle & minstret is available always */
> > if (!hpm_count)
> > diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
> > index 83301bb..a8d7648 100644
> > --- a/lib/utils/fdt/fdt_pmu.c
> > +++ b/lib/utils/fdt/fdt_pmu.c
> > @@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
> >
> > pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
> > if (pmu_offset < 0)
> > - return SBI_EFAIL;
> > + return SBI_ENOENT;
> >
> > event_ctr_map = fdt_getprop(fdt, pmu_offset,
> > "riscv,event-to-mhpmcounters", &len);
> > diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> > index 85acecd..fa400b9 100644
> > --- a/platform/generic/platform.c
> > +++ b/platform/generic/platform.c
> > @@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
> >
> > static int generic_pmu_init(void)
> > {
> > - return fdt_pmu_setup(fdt_get_address());
> > + int rc;
> > +
> > + rc = fdt_pmu_setup(fdt_get_address());
> > + if (rc && rc != SBI_ENOENT)
> > + return rc;
> > +
> > + return 0;
> > }
> >
> > static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-11-22 7:36 ` [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
2023-11-22 23:47 ` Atish Patra
@ 2023-11-24 14:45 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:45 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:40?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch makes the following changes:
>
> - As sbi_platform_pmu_init() returns a negative error code on
> failure, let sbi_pmu_init() to hang by propagating the error
> code.
>
> - In order to distinguish the SBI_EFAIL error returned by
> sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
> that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
> generic_pmu_init() ignores such case.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Include Anup's RB tag
> ---
> lib/sbi/sbi_pmu.c | 5 ++++-
> lib/utils/fdt/fdt_pmu.c | 2 +-
> platform/generic/platform.c | 8 +++++++-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index f4c8fc4..3cbd4ff 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
> int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
> struct sbi_pmu_hart_state *phs;
> const struct sbi_platform *plat;
> + int rc;
>
> if (cold_boot) {
> hw_event_map = sbi_calloc(sizeof(*hw_event_map),
> @@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
>
> plat = sbi_platform_ptr(scratch);
> /* Initialize hw pmu events */
> - sbi_platform_pmu_init(plat);
> + rc = sbi_platform_pmu_init(plat);
> + if (rc)
> + return rc;
>
> /* mcycle & minstret is available always */
> if (!hpm_count)
> diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
> index 83301bb..a8d7648 100644
> --- a/lib/utils/fdt/fdt_pmu.c
> +++ b/lib/utils/fdt/fdt_pmu.c
> @@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
>
> pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
> if (pmu_offset < 0)
> - return SBI_EFAIL;
> + return SBI_ENOENT;
>
> event_ctr_map = fdt_getprop(fdt, pmu_offset,
> "riscv,event-to-mhpmcounters", &len);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 85acecd..fa400b9 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
>
> static int generic_pmu_init(void)
> {
> - return fdt_pmu_setup(fdt_get_address());
> + int rc;
> +
> + rc = fdt_pmu_setup(fdt_get_address());
> + if (rc && rc != SBI_ENOENT)
> + return rc;
> +
> + return 0;
> }
>
> static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 01/15] lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 02/15] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 0:02 ` Atish Patra
2023-11-24 14:45 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
` (12 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
When SBI PMU updates inhibit bits on mcyclecfg and
minstretcfg, it will check if Smcntrpmf extension
is supported, we need to check Xandespmu similarly
in the pmu_fixed_ctr_update_inhibit_bits() so add
the custom extension to hart extension list.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v2 -> v3:
- New patch
---
include/sbi/sbi_hart.h | 2 ++
lib/sbi/sbi_hart.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
index 6ee49ff..811e5f5 100644
--- a/include/sbi/sbi_hart.h
+++ b/include/sbi/sbi_hart.h
@@ -45,6 +45,8 @@ enum sbi_hart_extensions {
SBI_HART_EXT_ZKR,
/** Hart has Smcntrpmf extension */
SBI_HART_EXT_SMCNTRPMF,
+ /** Hart has Xandespmu extension */
+ SBI_HART_EXT_XANDESPMU,
/** Maximum index of Hart extension */
SBI_HART_EXT_MAX,
diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
index 77eef49..d372af1 100644
--- a/lib/sbi/sbi_hart.c
+++ b/lib/sbi/sbi_hart.c
@@ -693,6 +693,9 @@ static inline char *sbi_hart_extension_id2string(int ext)
case SBI_HART_EXT_SMCNTRPMF:
estr = "smcntrpmf";
break;
+ case SBI_HART_EXT_XANDESPMU:
+ estr = "xandespmu";
+ break;
default:
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions
2023-11-22 7:36 ` [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions Yu Chien Peter Lin
@ 2023-11-23 0:02 ` Atish Patra
2023-11-24 14:45 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-23 0:02 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> When SBI PMU updates inhibit bits on mcyclecfg and
> minstretcfg, it will check if Smcntrpmf extension
> is supported, we need to check Xandespmu similarly
> in the pmu_fixed_ctr_update_inhibit_bits() so add
> the custom extension to hart extension list.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> ---
> include/sbi/sbi_hart.h | 2 ++
> lib/sbi/sbi_hart.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 6ee49ff..811e5f5 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -45,6 +45,8 @@ enum sbi_hart_extensions {
> SBI_HART_EXT_ZKR,
> /** Hart has Smcntrpmf extension */
> SBI_HART_EXT_SMCNTRPMF,
> + /** Hart has Xandespmu extension */
> + SBI_HART_EXT_XANDESPMU,
>
> /** Maximum index of Hart extension */
> SBI_HART_EXT_MAX,
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 77eef49..d372af1 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -693,6 +693,9 @@ static inline char *sbi_hart_extension_id2string(int ext)
> case SBI_HART_EXT_SMCNTRPMF:
> estr = "smcntrpmf";
> break;
> + case SBI_HART_EXT_XANDESPMU:
> + estr = "xandespmu";
> + break;
> default:
> break;
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions
2023-11-22 7:36 ` [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions Yu Chien Peter Lin
2023-11-23 0:02 ` Atish Patra
@ 2023-11-24 14:45 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:45 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:41?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> When SBI PMU updates inhibit bits on mcyclecfg and
> minstretcfg, it will check if Smcntrpmf extension
> is supported, we need to check Xandespmu similarly
> in the pmu_fixed_ctr_update_inhibit_bits() so add
> the custom extension to hart extension list.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> ---
> include/sbi/sbi_hart.h | 2 ++
> lib/sbi/sbi_hart.c | 3 +++
> 2 files changed, 5 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/include/sbi/sbi_hart.h b/include/sbi/sbi_hart.h
> index 6ee49ff..811e5f5 100644
> --- a/include/sbi/sbi_hart.h
> +++ b/include/sbi/sbi_hart.h
> @@ -45,6 +45,8 @@ enum sbi_hart_extensions {
> SBI_HART_EXT_ZKR,
> /** Hart has Smcntrpmf extension */
> SBI_HART_EXT_SMCNTRPMF,
> + /** Hart has Xandespmu extension */
> + SBI_HART_EXT_XANDESPMU,
>
> /** Maximum index of Hart extension */
> SBI_HART_EXT_MAX,
> diff --git a/lib/sbi/sbi_hart.c b/lib/sbi/sbi_hart.c
> index 77eef49..d372af1 100644
> --- a/lib/sbi/sbi_hart.c
> +++ b/lib/sbi/sbi_hart.c
> @@ -693,6 +693,9 @@ static inline char *sbi_hart_extension_id2string(int ext)
> case SBI_HART_EXT_SMCNTRPMF:
> estr = "smcntrpmf";
> break;
> + case SBI_HART_EXT_XANDESPMU:
> + estr = "xandespmu";
> + break;
> default:
> break;
> }
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (2 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 03/15] lib: sbi: Add Xandespmu in hart extensions Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 0:24 ` Atish Patra
2023-11-22 7:36 ` [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
` (11 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- No change
Changes v2 -> v3:
- Add pmu_dev->hw_counter_filter_mode() in pmu_fixed_ctr_update_inhibit_bits()
---
include/sbi/sbi_pmu.h | 6 ++++++
lib/sbi/sbi_pmu.c | 20 ++++++++++++++------
2 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
index 16f6877..d63149c 100644
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -89,6 +89,12 @@ struct sbi_pmu_device {
* Custom function returning the machine-specific irq-bit.
*/
int (*hw_counter_irq_bit)(void);
+
+ /**
+ * Custom function to inhibit counting of events while in
+ * specified mode.
+ */
+ void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
};
/** Get the PMU platform device */
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 3cbd4ff..2f255de 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
pmu_dev->hw_counter_disable_irq(ctr_idx);
/* Update the inhibit flags based on inhibit flags received from supervisor */
- pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+ pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (pmu_dev && pmu_dev->hw_counter_filter_mode)
+ pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
#if __riscv_xlen == 32
csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
@@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
#if __riscv_xlen == 32
uint64_t cfgh_csr_no;
#endif
- if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
+ if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
+ !sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
return fixed_ctr;
switch (fixed_ctr) {
@@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
}
cfg_val |= MHPMEVENT_MINH;
- pmu_update_inhibit_flags(flags, &cfg_val);
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
+ pmu_update_inhibit_flags(flags, &cfg_val);
#if __riscv_xlen == 32
- csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
- csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
+ csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
+ csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
#else
- csr_write_num(cfg_csr_no, cfg_val);
+ csr_write_num(cfg_csr_no, cfg_val);
#endif
+ }
+ if (pmu_dev && pmu_dev->hw_counter_filter_mode)
+ pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
return fixed_ctr;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-11-22 7:36 ` [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
@ 2023-11-23 0:24 ` Atish Patra
2023-11-28 6:10 ` Yu-Chien Peter Lin
0 siblings, 1 reply; 43+ messages in thread
From: Atish Patra @ 2023-11-23 0:24 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add support for custom PMU extensions to set inhibit bits
> on custom CSRs by introducing the PMU device callback
> hw_counter_filter_mode(). This allows the perf tool to
> restrict event counting under a specified privileged
> mode by appending a modifier, e.g. perf record -e event:k
> to count events only happening in kernel mode.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - No change
> Changes v2 -> v3:
> - Add pmu_dev->hw_counter_filter_mode() in pmu_fixed_ctr_update_inhibit_bits()
> ---
> include/sbi/sbi_pmu.h | 6 ++++++
> lib/sbi/sbi_pmu.c | 20 ++++++++++++++------
> 2 files changed, 20 insertions(+), 6 deletions(-)
>
> diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
> index 16f6877..d63149c 100644
> --- a/include/sbi/sbi_pmu.h
> +++ b/include/sbi/sbi_pmu.h
> @@ -89,6 +89,12 @@ struct sbi_pmu_device {
> * Custom function returning the machine-specific irq-bit.
> */
> int (*hw_counter_irq_bit)(void);
> +
> + /**
> + * Custom function to inhibit counting of events while in
> + * specified mode.
> + */
> + void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
> };
>
> /** Get the PMU platform device */
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index 3cbd4ff..2f255de 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
> pmu_dev->hw_counter_disable_irq(ctr_idx);
>
> /* Update the inhibit flags based on inhibit flags received from supervisor */
> - pmu_update_inhibit_flags(flags, &mhpmevent_val);
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> + pmu_update_inhibit_flags(flags, &mhpmevent_val);
> + if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> + pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
>
> #if __riscv_xlen == 32
> csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
> @@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> #if __riscv_xlen == 32
> uint64_t cfgh_csr_no;
> #endif
> - if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
> + if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
> + !sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
Instead of adding a check for vendor extension, we can just check for
platform specific hw_counter_filter_mode() availability.
I would prefer to avoid any vendor specific code if possible. Ideally,
all vendor specific details should be abstracted out via pmu-dev.
> return fixed_ctr;
>
> switch (fixed_ctr) {
> @@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> }
>
> cfg_val |= MHPMEVENT_MINH;
> - pmu_update_inhibit_flags(flags, &cfg_val);
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
> + pmu_update_inhibit_flags(flags, &cfg_val);
> #if __riscv_xlen == 32
> - csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> - csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> + csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> + csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> #else
> - csr_write_num(cfg_csr_no, cfg_val);
> + csr_write_num(cfg_csr_no, cfg_val);
> #endif
> + }
> + if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> + pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
> return fixed_ctr;
> }
>
> --
> 2.34.1
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-11-23 0:24 ` Atish Patra
@ 2023-11-28 6:10 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 43+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-28 6:10 UTC (permalink / raw)
To: opensbi
Hi Atish,
On Wed, Nov 22, 2023 at 04:24:35PM -0800, Atish Patra wrote:
> On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add support for custom PMU extensions to set inhibit bits
> > on custom CSRs by introducing the PMU device callback
> > hw_counter_filter_mode(). This allows the perf tool to
> > restrict event counting under a specified privileged
> > mode by appending a modifier, e.g. perf record -e event:k
> > to count events only happening in kernel mode.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - No change
> > Changes v2 -> v3:
> > - Add pmu_dev->hw_counter_filter_mode() in pmu_fixed_ctr_update_inhibit_bits()
> > ---
> > include/sbi/sbi_pmu.h | 6 ++++++
> > lib/sbi/sbi_pmu.c | 20 ++++++++++++++------
> > 2 files changed, 20 insertions(+), 6 deletions(-)
> >
> > diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
> > index 16f6877..d63149c 100644
> > --- a/include/sbi/sbi_pmu.h
> > +++ b/include/sbi/sbi_pmu.h
> > @@ -89,6 +89,12 @@ struct sbi_pmu_device {
> > * Custom function returning the machine-specific irq-bit.
> > */
> > int (*hw_counter_irq_bit)(void);
> > +
> > + /**
> > + * Custom function to inhibit counting of events while in
> > + * specified mode.
> > + */
> > + void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
> > };
> >
> > /** Get the PMU platform device */
> > diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> > index 3cbd4ff..2f255de 100644
> > --- a/lib/sbi/sbi_pmu.c
> > +++ b/lib/sbi/sbi_pmu.c
> > @@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
> > pmu_dev->hw_counter_disable_irq(ctr_idx);
> >
> > /* Update the inhibit flags based on inhibit flags received from supervisor */
> > - pmu_update_inhibit_flags(flags, &mhpmevent_val);
> > + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> > + pmu_update_inhibit_flags(flags, &mhpmevent_val);
> > + if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> > + pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
> >
> > #if __riscv_xlen == 32
> > csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
> > @@ -620,7 +623,8 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> > #if __riscv_xlen == 32
> > uint64_t cfgh_csr_no;
> > #endif
> > - if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
> > + if (!sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF) &&
> > + !sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
>
> Instead of adding a check for vendor extension, we can just check for
> platform specific hw_counter_filter_mode() availability.
Sure, will do.
Regards,
Peter Lin
> I would prefer to avoid any vendor specific code if possible. Ideally,
> all vendor specific details should be abstracted out via pmu-dev.
>
> > return fixed_ctr;
> >
> > switch (fixed_ctr) {
> > @@ -641,13 +645,17 @@ static int pmu_fixed_ctr_update_inhibit_bits(int fixed_ctr, unsigned long flags)
> > }
> >
> > cfg_val |= MHPMEVENT_MINH;
> > - pmu_update_inhibit_flags(flags, &cfg_val);
> > + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF)) {
> > + pmu_update_inhibit_flags(flags, &cfg_val);
> > #if __riscv_xlen == 32
> > - csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> > - csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> > + csr_write_num(cfg_csr_no, cfg_val & 0xFFFFFFFF);
> > + csr_write_num(cfgh_csr_no, cfg_val >> BITS_PER_LONG);
> > #else
> > - csr_write_num(cfg_csr_no, cfg_val);
> > + csr_write_num(cfg_csr_no, cfg_val);
> > #endif
> > + }
> > + if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> > + pmu_dev->hw_counter_filter_mode(flags, fixed_ctr);
> > return fixed_ctr;
> > }
> >
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (3 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 04/15] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 16:53 ` Atish Patra
2023-11-24 14:47 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override Yu Chien Peter Lin
` (10 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
This patch adds CSR for Andes PMU extension.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- Rename andes_pmu() -> has_andes_pmu()
Changes v2 -> v3:
- Include Anup's RB tag
---
platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index f570994..ce31617 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -12,6 +12,17 @@
#define CSR_MDCM_CFG 0xfc1
#define CSR_MMSC_CFG 0xfc2
+/* Machine Trap Related Registers */
+#define CSR_MSLIDELEG 0x7d5
+
+/* Counter Related Registers */
+#define CSR_MCOUNTERWEN 0x7ce
+#define CSR_MCOUNTERINTEN 0x7cf
+#define CSR_MCOUNTERMASK_M 0x7d1
+#define CSR_MCOUNTERMASK_S 0x7d2
+#define CSR_MCOUNTERMASK_U 0x7d3
+#define CSR_MCOUNTEROVF 0x7d4
+
#define MICM_CFG_ISZ_OFFSET 6
#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
@@ -26,4 +37,19 @@
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
+/* Performance monitor */
+#define MMSC_CFG_PMNDS_MASK (1 << 15)
+#define MIP_PMOVI (1 << 18)
+
+#ifndef __ASSEMBLER__
+
+#define has_andes_pmu() \
+({ \
+ (((csr_read(CSR_MMSC_CFG) & \
+ MMSC_CFG_PMNDS_MASK) \
+ && misa_extension('S')) ? true : false); \
+})
+
+#endif /* __ASSEMBLER__ */
+
#endif /* _RISCV_ANDES45_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines
2023-11-22 7:36 ` [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
@ 2023-11-23 16:53 ` Atish Patra
2023-11-24 14:47 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-23 16:53 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch adds CSR for Andes PMU extension.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - Rename andes_pmu() -> has_andes_pmu()
> Changes v2 -> v3:
> - Include Anup's RB tag
> ---
> platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index f570994..ce31617 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -12,6 +12,17 @@
> #define CSR_MDCM_CFG 0xfc1
> #define CSR_MMSC_CFG 0xfc2
>
> +/* Machine Trap Related Registers */
> +#define CSR_MSLIDELEG 0x7d5
> +
> +/* Counter Related Registers */
> +#define CSR_MCOUNTERWEN 0x7ce
> +#define CSR_MCOUNTERINTEN 0x7cf
> +#define CSR_MCOUNTERMASK_M 0x7d1
> +#define CSR_MCOUNTERMASK_S 0x7d2
> +#define CSR_MCOUNTERMASK_U 0x7d3
> +#define CSR_MCOUNTEROVF 0x7d4
> +
> #define MICM_CFG_ISZ_OFFSET 6
> #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
>
> @@ -26,4 +37,19 @@
> #define MCACHE_CTL_CCTL_SUEN_OFFSET 8
> #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
>
> +/* Performance monitor */
> +#define MMSC_CFG_PMNDS_MASK (1 << 15)
> +#define MIP_PMOVI (1 << 18)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define has_andes_pmu() \
> +({ \
> + (((csr_read(CSR_MMSC_CFG) & \
> + MMSC_CFG_PMNDS_MASK) \
> + && misa_extension('S')) ? true : false); \
> +})
> +
> +#endif /* __ASSEMBLER__ */
> +
> #endif /* _RISCV_ANDES45_H */
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines
2023-11-22 7:36 ` [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
2023-11-23 16:53 ` Atish Patra
@ 2023-11-24 14:47 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:47 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:40?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch adds CSR for Andes PMU extension.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - Rename andes_pmu() -> has_andes_pmu()
> Changes v2 -> v3:
> - Include Anup's RB tag
> ---
> platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index f570994..ce31617 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -12,6 +12,17 @@
> #define CSR_MDCM_CFG 0xfc1
> #define CSR_MMSC_CFG 0xfc2
>
> +/* Machine Trap Related Registers */
> +#define CSR_MSLIDELEG 0x7d5
> +
> +/* Counter Related Registers */
> +#define CSR_MCOUNTERWEN 0x7ce
> +#define CSR_MCOUNTERINTEN 0x7cf
> +#define CSR_MCOUNTERMASK_M 0x7d1
> +#define CSR_MCOUNTERMASK_S 0x7d2
> +#define CSR_MCOUNTERMASK_U 0x7d3
> +#define CSR_MCOUNTEROVF 0x7d4
> +
> #define MICM_CFG_ISZ_OFFSET 6
> #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
>
> @@ -26,4 +37,19 @@
> #define MCACHE_CTL_CCTL_SUEN_OFFSET 8
> #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
>
> +/* Performance monitor */
> +#define MMSC_CFG_PMNDS_MASK (1 << 15)
> +#define MIP_PMOVI (1 << 18)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define has_andes_pmu() \
> +({ \
> + (((csr_read(CSR_MMSC_CFG) & \
> + MMSC_CFG_PMNDS_MASK) \
> + && misa_extension('S')) ? true : false); \
> +})
> +
> +#endif /* __ASSEMBLER__ */
> +
> #endif /* _RISCV_ANDES45_H */
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (4 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 05/15] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 0:25 ` Atish Patra
2023-11-24 14:49 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 07/15] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
` (9 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Add pmu_init() platform override which will be used to register
PMU device and populate event mappings.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v2 -> v3:
- New patch
---
platform/generic/include/platform_override.h | 1 +
platform/generic/platform.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index bf4b112..f2a4327 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -27,6 +27,7 @@ struct platform_override {
int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
int (*extensions_init)(const struct fdt_match *match,
struct sbi_hart_features *hfeatures);
+ int (*pmu_init)(const struct fdt_match *match);
void (*fw_init)(void *fdt, const struct fdt_match *match);
int (*vendor_ext_provider)(long funcid,
const struct sbi_trap_regs *regs,
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index fa400b9..54a913b 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -267,6 +267,9 @@ static int generic_pmu_init(void)
{
int rc;
+ if (generic_plat && generic_plat->pmu_init)
+ return generic_plat->pmu_init(generic_plat_match);
+
rc = fdt_pmu_setup(fdt_get_address());
if (rc && rc != SBI_ENOENT)
return rc;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override
2023-11-22 7:36 ` [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override Yu Chien Peter Lin
@ 2023-11-23 0:25 ` Atish Patra
2023-11-24 14:49 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-23 0:25 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add pmu_init() platform override which will be used to register
> PMU device and populate event mappings.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> ---
> platform/generic/include/platform_override.h | 1 +
> platform/generic/platform.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index bf4b112..f2a4327 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -27,6 +27,7 @@ struct platform_override {
> int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
> int (*extensions_init)(const struct fdt_match *match,
> struct sbi_hart_features *hfeatures);
> + int (*pmu_init)(const struct fdt_match *match);
> void (*fw_init)(void *fdt, const struct fdt_match *match);
> int (*vendor_ext_provider)(long funcid,
> const struct sbi_trap_regs *regs,
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index fa400b9..54a913b 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -267,6 +267,9 @@ static int generic_pmu_init(void)
> {
> int rc;
>
> + if (generic_plat && generic_plat->pmu_init)
> + return generic_plat->pmu_init(generic_plat_match);
> +
Reviewed-by: Atish Patra <atishp@rivosinc.com>
> rc = fdt_pmu_setup(fdt_get_address());
> if (rc && rc != SBI_ENOENT)
> return rc;
> --
> 2.34.1
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override
2023-11-22 7:36 ` [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override Yu Chien Peter Lin
2023-11-23 0:25 ` Atish Patra
@ 2023-11-24 14:49 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:49 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:41?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add pmu_init() platform override which will be used to register
> PMU device and populate event mappings.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> ---
> platform/generic/include/platform_override.h | 1 +
> platform/generic/platform.c | 3 +++
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index bf4b112..f2a4327 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -27,6 +27,7 @@ struct platform_override {
> int (*fdt_fixup)(void *fdt, const struct fdt_match *match);
> int (*extensions_init)(const struct fdt_match *match,
> struct sbi_hart_features *hfeatures);
> + int (*pmu_init)(const struct fdt_match *match);
> void (*fw_init)(void *fdt, const struct fdt_match *match);
> int (*vendor_ext_provider)(long funcid,
> const struct sbi_trap_regs *regs,
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index fa400b9..54a913b 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -267,6 +267,9 @@ static int generic_pmu_init(void)
> {
> int rc;
>
> + if (generic_plat && generic_plat->pmu_init)
> + return generic_plat->pmu_init(generic_plat_match);
> +
> rc = fdt_pmu_setup(fdt_get_address());
> if (rc && rc != SBI_ENOENT)
> return rc;
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 07/15] platform: andes: Add Andes custom PMU support
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (5 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 06/15] platform: generic: Introduce pmu_init() platform override Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 2:24 ` Samuel Holland
2023-11-22 7:36 ` [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
` (8 subsequent siblings)
15 siblings, 1 reply; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Before the ratification of Sscofpmf, the Andes PMU extension
was designed to support the sampling and filtering with hardware
performance counters (zihpm), it works with the current SBI PMU
extension and Linux SBI PMU driver.
We implement 1) the PMU device callbacks that update the
corresponding bits on custom CSRs, 2) extentions_init() to detect
the hardware support of Andes PMU and initialize the per-hart
PMU related CSR, and 3) pmu_init() to register PMU device and
populate event mappings (only called by coldboot hart).
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Fix mode filtering in andes_hw_counter_filter_mode()
- Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
- Don't grant write permissions via CSR_MCOUNTERWEN as not needed
Changes v2 -> v3:
- Drop Anup's RB tag as we add andes_pmu_extensions_init() to initialize per-hart
extension on scratch and move andes_pmu_init() to new added platform override pmu_init()
---
platform/generic/andes/Kconfig | 8 ++
platform/generic/andes/andes_pmu.c | 102 +++++++++++++++++++++
platform/generic/andes/objects.mk | 1 +
platform/generic/include/andes/andes_pmu.h | 33 +++++++
4 files changed, 144 insertions(+)
create mode 100644 platform/generic/andes/andes_pmu.c
create mode 100644 platform/generic/include/andes/andes_pmu.h
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index a91fb9c..5b2ed91 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -7,3 +7,11 @@ config ANDES45_PMA
config ANDES_SBI
bool "Andes SBI support"
default n
+
+config ANDES_PMU
+ bool "Andes PMU extension (xandespmu) support"
+ default n
+ help
+ Andes PMU extension supports the event counter overflow
+ interrupt and mode filtering, similar to the standard
+ Sscofpmf and Smcntrpmf.
diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
new file mode 100644
index 0000000..72003fd
--- /dev/null
+++ b/platform/generic/andes/andes_pmu.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * andes_pmu.c - Andes PMU device callbacks and platform overrides
+ *
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+
+#include <andes/andes45.h>
+#include <andes/andes_hpm.h>
+#include <andes/andes_pmu.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_pmu.h>
+
+static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
+{
+ unsigned long mip_val;
+
+ if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+ return;
+
+ mip_val = csr_read(CSR_MIP);
+ if (!(mip_val & MIP_PMOVI))
+ csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
+
+ csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
+{
+ csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
+{
+ if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
+ csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+ else
+ csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+
+ if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
+ csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+ else
+ csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+}
+
+static struct sbi_pmu_device andes_pmu = {
+ .name = "andes_pmu",
+ .hw_counter_enable_irq = andes_hw_counter_enable_irq,
+ .hw_counter_disable_irq = andes_hw_counter_disable_irq,
+ /*
+ * We set delegation of supervisor local interrupts via
+ * 18th bit on mslideleg instead of mideleg, so leave
+ * hw_counter_irq_bit() callback unimplemented.
+ */
+ .hw_counter_irq_bit = NULL,
+ .hw_counter_filter_mode = andes_hw_counter_filter_mode
+};
+
+int andes_pmu_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+ if (!has_andes_pmu())
+ return 0;
+
+ /*
+ * Don't expect both Andes PMU and standard Sscofpmf/Smcntrpmf,
+ * are supported as they serve the same purpose.
+ */
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF) ||
+ sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
+ return SBI_EINVAL;
+ sbi_hart_update_extension(scratch, SBI_HART_EXT_XANDESPMU, true);
+
+ /* Inhibit all HPM counters in M-mode */
+ csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
+ /* Delegate counter overflow interrupt to S-mode */
+ csr_write(CSR_MSLIDELEG, MIP_PMOVI);
+
+ return 0;
+}
+
+int andes_pmu_init(const struct fdt_match *match)
+{
+ int rc;
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
+ sbi_pmu_set_device(&andes_pmu);
+
+ rc = fdt_pmu_setup(fdt_get_address());
+ /*
+ * Populate default mappings if device-tree doesn't
+ * provide a valid pmu node.
+ */
+ if (rc == SBI_ENOENT)
+ return andes_pmu_setup();
+
+ return rc;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index e8f86ea..6a8c66c 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
+platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h
new file mode 100644
index 0000000..c4281fe
--- /dev/null
+++ b/platform/generic/include/andes/andes_pmu.h
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _RISCV_ANDES_PMU_H
+#define _RISCV_ANDES_PMU_H
+
+#include <sbi/sbi_hart.h>
+#include <sbi_utils/fdt/fdt_pmu.h>
+
+#ifdef CONFIG_ANDES_PMU
+
+int andes_pmu_init(const struct fdt_match *match);
+int andes_pmu_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures);
+
+#else
+
+int andes_pmu_init(const struct fdt_match *match)
+{
+ return 0;
+}
+int andes_pmu_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ return 0;
+}
+
+#endif /* CONFIG_ANDES_PMU */
+
+#endif /* _RISCV_ANDES_PMU_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 07/15] platform: andes: Add Andes custom PMU support
2023-11-22 7:36 ` [PATCH v3 07/15] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-11-23 2:24 ` Samuel Holland
2023-11-28 11:02 ` Yu-Chien Peter Lin
0 siblings, 1 reply; 43+ messages in thread
From: Samuel Holland @ 2023-11-23 2:24 UTC (permalink / raw)
To: opensbi
On 2023-11-22 1:36 AM, Yu Chien Peter Lin wrote:
> Before the ratification of Sscofpmf, the Andes PMU extension
> was designed to support the sampling and filtering with hardware
> performance counters (zihpm), it works with the current SBI PMU
> extension and Linux SBI PMU driver.
>
> We implement 1) the PMU device callbacks that update the
> corresponding bits on custom CSRs, 2) extentions_init() to detect
> the hardware support of Andes PMU and initialize the per-hart
> PMU related CSR, and 3) pmu_init() to register PMU device and
> populate event mappings (only called by coldboot hart).
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Fix mode filtering in andes_hw_counter_filter_mode()
> - Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
> - Don't grant write permissions via CSR_MCOUNTERWEN as not needed
> Changes v2 -> v3:
> - Drop Anup's RB tag as we add andes_pmu_extensions_init() to initialize per-hart
> extension on scratch and move andes_pmu_init() to new added platform override pmu_init()
> ---
> platform/generic/andes/Kconfig | 8 ++
> platform/generic/andes/andes_pmu.c | 102 +++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_pmu.h | 33 +++++++
> 4 files changed, 144 insertions(+)
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> index a91fb9c..5b2ed91 100644
> --- a/platform/generic/andes/Kconfig
> +++ b/platform/generic/andes/Kconfig
> @@ -7,3 +7,11 @@ config ANDES45_PMA
> config ANDES_SBI
> bool "Andes SBI support"
> default n
> +
> +config ANDES_PMU
> + bool "Andes PMU extension (xandespmu) support"
> + default n
> + help
> + Andes PMU extension supports the event counter overflow
> + interrupt and mode filtering, similar to the standard
> + Sscofpmf and Smcntrpmf.
> diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> new file mode 100644
> index 0000000..72003fd
> --- /dev/null
> +++ b/platform/generic/andes/andes_pmu.c
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * andes_pmu.c - Andes PMU device callbacks and platform overrides
> + *
> + * Copyright (C) 2023 Andes Technology Corporation
> + */
> +
> +#include <andes/andes45.h>
> +#include <andes/andes_hpm.h>
> +#include <andes/andes_pmu.h>
> +#include <sbi/sbi_bitops.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_pmu.h>
> +
> +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> +{
> + unsigned long mip_val;
> +
> + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> + return;
> +
> + mip_val = csr_read(CSR_MIP);
> + if (!(mip_val & MIP_PMOVI))
> + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> +
> + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> +{
> + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> +{
> + if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
> + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> + else
> + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> +
> + if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
> + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> + else
> + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> +}
> +
> +static struct sbi_pmu_device andes_pmu = {
> + .name = "andes_pmu",
> + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> + /*
> + * We set delegation of supervisor local interrupts via
> + * 18th bit on mslideleg instead of mideleg, so leave
> + * hw_counter_irq_bit() callback unimplemented.
> + */
> + .hw_counter_irq_bit = NULL,
> + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> +};
> +
> +int andes_pmu_extensions_init(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures)
> +{
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> + if (!has_andes_pmu())
> + return 0;
> +
> + /*
> + * Don't expect both Andes PMU and standard Sscofpmf/Smcntrpmf,
> + * are supported as they serve the same purpose.
> + */
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF) ||
> + sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
> + return SBI_EINVAL;
If Sscofpmf is supported, don't you want to successfully do nothing?
> + sbi_hart_update_extension(scratch, SBI_HART_EXT_XANDESPMU, true);
> +
> + /* Inhibit all HPM counters in M-mode */
> + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> + /* Delegate counter overflow interrupt to S-mode */
> + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> +
> + return 0;
> +}
> +
> +int andes_pmu_init(const struct fdt_match *match)
> +{
> + int rc;
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
> + sbi_pmu_set_device(&andes_pmu);
> +
> + rc = fdt_pmu_setup(fdt_get_address());
generic_pmu_init() already calls fdt_pmu_setup().
> + /*
> + * Populate default mappings if device-tree doesn't
> + * provide a valid pmu node.
> + */
> + if (rc == SBI_ENOENT)
> + return andes_pmu_setup();
This function isn't added until patch 14, so this won't compile. Please make
sure each patch compiles individually.
Regards,
Samuel
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 07/15] platform: andes: Add Andes custom PMU support
2023-11-23 2:24 ` Samuel Holland
@ 2023-11-28 11:02 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 43+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-28 11:02 UTC (permalink / raw)
To: opensbi
Hi Samuel,
Thanks for the review.
On Wed, Nov 22, 2023 at 08:24:49PM -0600, Samuel Holland wrote:
> On 2023-11-22 1:36 AM, Yu Chien Peter Lin wrote:
> > Before the ratification of Sscofpmf, the Andes PMU extension
> > was designed to support the sampling and filtering with hardware
> > performance counters (zihpm), it works with the current SBI PMU
> > extension and Linux SBI PMU driver.
> >
> > We implement 1) the PMU device callbacks that update the
> > corresponding bits on custom CSRs, 2) extentions_init() to detect
> > the hardware support of Andes PMU and initialize the per-hart
> > PMU related CSR, and 3) pmu_init() to register PMU device and
> > populate event mappings (only called by coldboot hart).
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - Fix mode filtering in andes_hw_counter_filter_mode()
> > - Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
> > - Don't grant write permissions via CSR_MCOUNTERWEN as not needed
> > Changes v2 -> v3:
> > - Drop Anup's RB tag as we add andes_pmu_extensions_init() to initialize per-hart
> > extension on scratch and move andes_pmu_init() to new added platform override pmu_init()
> > ---
> > platform/generic/andes/Kconfig | 8 ++
> > platform/generic/andes/andes_pmu.c | 102 +++++++++++++++++++++
> > platform/generic/andes/objects.mk | 1 +
> > platform/generic/include/andes/andes_pmu.h | 33 +++++++
> > 4 files changed, 144 insertions(+)
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> > index a91fb9c..5b2ed91 100644
> > --- a/platform/generic/andes/Kconfig
> > +++ b/platform/generic/andes/Kconfig
> > @@ -7,3 +7,11 @@ config ANDES45_PMA
> > config ANDES_SBI
> > bool "Andes SBI support"
> > default n
> > +
> > +config ANDES_PMU
> > + bool "Andes PMU extension (xandespmu) support"
> > + default n
> > + help
> > + Andes PMU extension supports the event counter overflow
> > + interrupt and mode filtering, similar to the standard
> > + Sscofpmf and Smcntrpmf.
> > diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> > new file mode 100644
> > index 0000000..72003fd
> > --- /dev/null
> > +++ b/platform/generic/andes/andes_pmu.c
> > @@ -0,0 +1,102 @@
> > +// SPDX-License-Identifier: BSD-2-Clause
> > +/*
> > + * andes_pmu.c - Andes PMU device callbacks and platform overrides
> > + *
> > + * Copyright (C) 2023 Andes Technology Corporation
> > + */
> > +
> > +#include <andes/andes45.h>
> > +#include <andes/andes_hpm.h>
> > +#include <andes/andes_pmu.h>
> > +#include <sbi/sbi_bitops.h>
> > +#include <sbi/sbi_error.h>
> > +#include <sbi/sbi_pmu.h>
> > +
> > +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> > +{
> > + unsigned long mip_val;
> > +
> > + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> > + return;
> > +
> > + mip_val = csr_read(CSR_MIP);
> > + if (!(mip_val & MIP_PMOVI))
> > + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> > +
> > + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> > +{
> > + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> > +}
> > +
> > +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> > +{
> > + if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
> > + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > + else
> > + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> > +
> > + if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
> > + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > + else
> > + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> > +}
> > +
> > +static struct sbi_pmu_device andes_pmu = {
> > + .name = "andes_pmu",
> > + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> > + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> > + /*
> > + * We set delegation of supervisor local interrupts via
> > + * 18th bit on mslideleg instead of mideleg, so leave
> > + * hw_counter_irq_bit() callback unimplemented.
> > + */
> > + .hw_counter_irq_bit = NULL,
> > + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> > +};
> > +
> > +int andes_pmu_extensions_init(const struct fdt_match *match,
> > + struct sbi_hart_features *hfeatures)
> > +{
> > + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> > +
> > + if (!has_andes_pmu())
> > + return 0;
> > +
> > + /*
> > + * Don't expect both Andes PMU and standard Sscofpmf/Smcntrpmf,
> > + * are supported as they serve the same purpose.
> > + */
> > + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF) ||
> > + sbi_hart_has_extension(scratch, SBI_HART_EXT_SMCNTRPMF))
> > + return SBI_EINVAL;
>
> If Sscofpmf is supported, don't you want to successfully do nothing?
If Sscofpmf is supported, it will return early as has_andes_pmu() above
is false.
> > + sbi_hart_update_extension(scratch, SBI_HART_EXT_XANDESPMU, true);
> > +
> > + /* Inhibit all HPM counters in M-mode */
> > + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> > + /* Delegate counter overflow interrupt to S-mode */
> > + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> > +
> > + return 0;
> > +}
> > +
> > +int andes_pmu_init(const struct fdt_match *match)
> > +{
> > + int rc;
> > + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> > +
> > + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_XANDESPMU))
> > + sbi_pmu_set_device(&andes_pmu);
> > +
> > + rc = fdt_pmu_setup(fdt_get_address());
>
> generic_pmu_init() already calls fdt_pmu_setup().
OK will remove fdt_pmu_setup() here.
> > + /*
> > + * Populate default mappings if device-tree doesn't
> > + * provide a valid pmu node.
> > + */
> > + if (rc == SBI_ENOENT)
> > + return andes_pmu_setup();
>
> This function isn't added until patch 14, so this won't compile. Please make
> sure each patch compiles individually.
Sure, thank you for catching this.
Regards,
Peter Lin
> Regards,
> Samuel
>
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (6 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 07/15] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 16:55 ` Atish Patra
2023-11-24 14:52 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
` (7 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for AE350 platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Implement ae350_extensions_init()
Changes v2 -> v3:
- Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
We have no plan to introduce other extensions in near future so extensions_init()
bind with andes_pmu_extensions_init() directly.
---
platform/generic/Kconfig | 1 +
platform/generic/andes/ae350.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index a902cf3..89e5603 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -32,6 +32,7 @@ config PLATFORM_ALLWINNER_D1
config PLATFORM_ANDES_AE350
bool "Andes AE350 support"
select SYS_ATCSMU
+ select ANDES_PMU
default n
config PLATFORM_RENESAS_RZFIVE
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 80eca05..dc769b7 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -8,6 +8,7 @@
*/
#include <platform_override.h>
+#include <andes/andes_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/sys/atcsmu.h>
@@ -118,4 +119,6 @@ static const struct fdt_match andes_ae350_match[] = {
const struct platform_override andes_ae350 = {
.match_table = andes_ae350_match,
.final_init = ae350_final_init,
+ .extensions_init = andes_pmu_extensions_init,
+ .pmu_init = andes_pmu_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350
2023-11-22 7:36 ` [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
@ 2023-11-23 16:55 ` Atish Patra
2023-11-24 14:52 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-23 16:55 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for AE350 platforms.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement ae350_extensions_init()
> Changes v2 -> v3:
> - Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
> We have no plan to introduce other extensions in near future so extensions_init()
> bind with andes_pmu_extensions_init() directly.
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/andes/ae350.c | 3 +++
> 2 files changed, 4 insertions(+)
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index a902cf3..89e5603 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -32,6 +32,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
> + select ANDES_PMU
> default n
>
> config PLATFORM_RENESAS_RZFIVE
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> index 80eca05..dc769b7 100644
> --- a/platform/generic/andes/ae350.c
> +++ b/platform/generic/andes/ae350.c
> @@ -8,6 +8,7 @@
> */
>
> #include <platform_override.h>
> +#include <andes/andes_pmu.h>
> #include <sbi_utils/fdt/fdt_helper.h>
> #include <sbi_utils/fdt/fdt_fixup.h>
> #include <sbi_utils/sys/atcsmu.h>
> @@ -118,4 +119,6 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> .match_table = andes_ae350_match,
> .final_init = ae350_final_init,
> + .extensions_init = andes_pmu_extensions_init,
> + .pmu_init = andes_pmu_init,
> };
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350
2023-11-22 7:36 ` [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
2023-11-23 16:55 ` Atish Patra
@ 2023-11-24 14:52 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:52 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:41?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for AE350 platforms.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement ae350_extensions_init()
> Changes v2 -> v3:
> - Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
> We have no plan to introduce other extensions in near future so extensions_init()
> bind with andes_pmu_extensions_init() directly.
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/andes/ae350.c | 3 +++
> 2 files changed, 4 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index a902cf3..89e5603 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -32,6 +32,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
> + select ANDES_PMU
> default n
>
> config PLATFORM_RENESAS_RZFIVE
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> index 80eca05..dc769b7 100644
> --- a/platform/generic/andes/ae350.c
> +++ b/platform/generic/andes/ae350.c
> @@ -8,6 +8,7 @@
> */
>
> #include <platform_override.h>
> +#include <andes/andes_pmu.h>
> #include <sbi_utils/fdt/fdt_helper.h>
> #include <sbi_utils/fdt/fdt_fixup.h>
> #include <sbi_utils/sys/atcsmu.h>
> @@ -118,4 +119,6 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> .match_table = andes_ae350_match,
> .final_init = ae350_final_init,
> + .extensions_init = andes_pmu_extensions_init,
> + .pmu_init = andes_pmu_init,
> };
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (7 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 08/15] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-23 16:56 ` Atish Patra
2023-11-24 14:53 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
` (6 subsequent siblings)
15 siblings, 2 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for RZ/Five.
We also staticize renesas_rzfive_early_init() as
it is not used outside of this unit.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Implement renesas_rzfive_extensions_init()
- staticize renesas_rzfive_early_init()
Changes v2 -> v3:
- Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
We have no plan to introduce other extensions in near future so extensions_init()
bind with andes_pmu_extensions_init() directly.
---
platform/generic/Kconfig | 1 +
platform/generic/renesas/rzfive/rzfive.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 89e5603..c9b6011 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -39,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES45_PMA
select ANDES_SBI
+ select ANDES_PMU
default n
config PLATFORM_SIFIVE_FU540
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index a69797b..b5b5e65 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,6 +5,7 @@
*/
#include <andes/andes45_pma.h>
+#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
#include <sbi/sbi_domain.h>
@@ -29,7 +30,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
array_size(renesas_rzfive_pma_regions));
}
-int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
+static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
{
/*
* Renesas RZ/Five RISC-V SoC has Instruction local memory and
@@ -57,4 +58,6 @@ const struct platform_override renesas_rzfive = {
.early_init = renesas_rzfive_early_init,
.final_init = renesas_rzfive_final_init,
.vendor_ext_provider = andes_sbi_vendor_ext_provider,
+ .extensions_init = andes_pmu_extensions_init,
+ .pmu_init = andes_pmu_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five
2023-11-22 7:36 ` [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
@ 2023-11-23 16:56 ` Atish Patra
2023-11-24 14:53 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-23 16:56 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for RZ/Five.
> We also staticize renesas_rzfive_early_init() as
> it is not used outside of this unit.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement renesas_rzfive_extensions_init()
> - staticize renesas_rzfive_early_init()
> Changes v2 -> v3:
> - Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
> We have no plan to introduce other extensions in near future so extensions_init()
> bind with andes_pmu_extensions_init() directly.
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/renesas/rzfive/rzfive.c | 5 ++++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 89e5603..c9b6011 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -39,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
> + select ANDES_PMU
> default n
>
> config PLATFORM_SIFIVE_FU540
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> index a69797b..b5b5e65 100644
> --- a/platform/generic/renesas/rzfive/rzfive.c
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -5,6 +5,7 @@
> */
>
> #include <andes/andes45_pma.h>
> +#include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
> #include <sbi/sbi_domain.h>
> @@ -29,7 +30,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
> array_size(renesas_rzfive_pma_regions));
> }
>
> -int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> +static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> {
> /*
> * Renesas RZ/Five RISC-V SoC has Instruction local memory and
> @@ -57,4 +58,6 @@ const struct platform_override renesas_rzfive = {
> .early_init = renesas_rzfive_early_init,
> .final_init = renesas_rzfive_final_init,
> .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> + .extensions_init = andes_pmu_extensions_init,
> + .pmu_init = andes_pmu_init,
> };
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five
2023-11-22 7:36 ` [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
2023-11-23 16:56 ` Atish Patra
@ 2023-11-24 14:53 ` Lad, Prabhakar
1 sibling, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:53 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:41?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for RZ/Five.
> We also staticize renesas_rzfive_early_init() as
> it is not used outside of this unit.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement renesas_rzfive_extensions_init()
> - staticize renesas_rzfive_early_init()
> Changes v2 -> v3:
> - Use the andes_pmu_extensions_init() and andes_pmu_init() provided by andes_pmu.c
> We have no plan to introduce other extensions in near future so extensions_init()
> bind with andes_pmu_extensions_init() directly.
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/renesas/rzfive/rzfive.c | 5 ++++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 89e5603..c9b6011 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -39,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
> + select ANDES_PMU
> default n
>
> config PLATFORM_SIFIVE_FU540
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> index a69797b..b5b5e65 100644
> --- a/platform/generic/renesas/rzfive/rzfive.c
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -5,6 +5,7 @@
> */
>
> #include <andes/andes45_pma.h>
> +#include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
> #include <sbi/sbi_domain.h>
> @@ -29,7 +30,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
> array_size(renesas_rzfive_pma_regions));
> }
>
> -int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> +static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> {
> /*
> * Renesas RZ/Five RISC-V SoC has Instruction local memory and
> @@ -57,4 +58,6 @@ const struct platform_override renesas_rzfive = {
> .early_init = renesas_rzfive_early_init,
> .final_init = renesas_rzfive_final_init,
> .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> + .extensions_init = andes_pmu_extensions_init,
> + .pmu_init = andes_pmu_init,
> };
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (8 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 09/15] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-22 23:41 ` Atish Patra
` (2 more replies)
2023-11-22 7:36 ` [PATCH v3 11/15] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
` (5 subsequent siblings)
15 siblings, 3 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Add a scratch option to control PMU fixup, so the next
stage software can dump the PMU node including event
mapping information for debugging purposes.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Rename to SBI_SCRATCH_PRESERVE_PMU_NODE (suggested by Anup)
- Include Anup's RB tag
---
include/sbi/sbi_scratch.h | 2 ++
lib/utils/fdt/fdt_fixup.c | 6 +++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index e6a33ba..0f67cde 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -151,6 +151,8 @@ enum sbi_scratch_options {
SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
/** Enable runtime debug prints */
SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
+ /** Preserve PMU node properties */
+ SBI_SCRATCH_PRESERVE_PMU_NODE = (1 << 2),
};
/** Get pointer to sbi_scratch for current HART */
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index e213ded..cf20edf 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -387,6 +387,8 @@ int fdt_reserved_memory_fixup(void *fdt)
void fdt_fixups(void *fdt)
{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
fdt_aplic_fixup(fdt);
fdt_imsic_fixup(fdt);
@@ -394,5 +396,7 @@ void fdt_fixups(void *fdt)
fdt_plic_fixup(fdt);
fdt_reserved_memory_fixup(fdt);
- fdt_pmu_fixup(fdt);
+
+ if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_NODE))
+ fdt_pmu_fixup(fdt);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-11-22 7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
@ 2023-11-22 23:41 ` Atish Patra
2023-11-24 14:54 ` Lad, Prabhakar
2023-11-25 4:42 ` Anup Patel
2 siblings, 0 replies; 43+ messages in thread
From: Atish Patra @ 2023-11-22 23:41 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:40?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add a scratch option to control PMU fixup, so the next
> stage software can dump the PMU node including event
> mapping information for debugging purposes.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Rename to SBI_SCRATCH_PRESERVE_PMU_NODE (suggested by Anup)
> - Include Anup's RB tag
> ---
> include/sbi/sbi_scratch.h | 2 ++
> lib/utils/fdt/fdt_fixup.c | 6 +++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> index e6a33ba..0f67cde 100644
> --- a/include/sbi/sbi_scratch.h
> +++ b/include/sbi/sbi_scratch.h
> @@ -151,6 +151,8 @@ enum sbi_scratch_options {
> SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
> /** Enable runtime debug prints */
> SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
> + /** Preserve PMU node properties */
> + SBI_SCRATCH_PRESERVE_PMU_NODE = (1 << 2),
> };
>
> /** Get pointer to sbi_scratch for current HART */
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index e213ded..cf20edf 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -387,6 +387,8 @@ int fdt_reserved_memory_fixup(void *fdt)
>
> void fdt_fixups(void *fdt)
> {
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> fdt_aplic_fixup(fdt);
>
> fdt_imsic_fixup(fdt);
> @@ -394,5 +396,7 @@ void fdt_fixups(void *fdt)
> fdt_plic_fixup(fdt);
>
> fdt_reserved_memory_fixup(fdt);
> - fdt_pmu_fixup(fdt);
> +
> + if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_NODE))
> + fdt_pmu_fixup(fdt);
> }
> --
> 2.34.1
>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-11-22 7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
2023-11-22 23:41 ` Atish Patra
@ 2023-11-24 14:54 ` Lad, Prabhakar
2023-11-25 4:42 ` Anup Patel
2 siblings, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:54 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:41?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add a scratch option to control PMU fixup, so the next
> stage software can dump the PMU node including event
> mapping information for debugging purposes.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Rename to SBI_SCRATCH_PRESERVE_PMU_NODE (suggested by Anup)
> - Include Anup's RB tag
> ---
> include/sbi/sbi_scratch.h | 2 ++
> lib/utils/fdt/fdt_fixup.c | 6 +++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> index e6a33ba..0f67cde 100644
> --- a/include/sbi/sbi_scratch.h
> +++ b/include/sbi/sbi_scratch.h
> @@ -151,6 +151,8 @@ enum sbi_scratch_options {
> SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
> /** Enable runtime debug prints */
> SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
> + /** Preserve PMU node properties */
> + SBI_SCRATCH_PRESERVE_PMU_NODE = (1 << 2),
> };
>
> /** Get pointer to sbi_scratch for current HART */
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index e213ded..cf20edf 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -387,6 +387,8 @@ int fdt_reserved_memory_fixup(void *fdt)
>
> void fdt_fixups(void *fdt)
> {
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> fdt_aplic_fixup(fdt);
>
> fdt_imsic_fixup(fdt);
> @@ -394,5 +396,7 @@ void fdt_fixups(void *fdt)
> fdt_plic_fixup(fdt);
>
> fdt_reserved_memory_fixup(fdt);
> - fdt_pmu_fixup(fdt);
> +
> + if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_NODE))
> + fdt_pmu_fixup(fdt);
> }
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-11-22 7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
2023-11-22 23:41 ` Atish Patra
2023-11-24 14:54 ` Lad, Prabhakar
@ 2023-11-25 4:42 ` Anup Patel
2023-11-28 9:57 ` Yu-Chien Peter Lin
2 siblings, 1 reply; 43+ messages in thread
From: Anup Patel @ 2023-11-25 4:42 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 1:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add a scratch option to control PMU fixup, so the next
> stage software can dump the PMU node including event
> mapping information for debugging purposes.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - New patch
> Changes v2 -> v3:
> - Rename to SBI_SCRATCH_PRESERVE_PMU_NODE (suggested by Anup)
> - Include Anup's RB tag
> ---
> include/sbi/sbi_scratch.h | 2 ++
> lib/utils/fdt/fdt_fixup.c | 6 +++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> index e6a33ba..0f67cde 100644
> --- a/include/sbi/sbi_scratch.h
> +++ b/include/sbi/sbi_scratch.h
> @@ -151,6 +151,8 @@ enum sbi_scratch_options {
> SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
> /** Enable runtime debug prints */
> SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
> + /** Preserve PMU node properties */
> + SBI_SCRATCH_PRESERVE_PMU_NODE = (1 << 2),
I have second thoughts about using the scratch option for this.
Let's not waste a bit in the scratch option just for debugging the PMU node.
I suggest adding the kconfig option FDT_FIXUPS_PRESERVE_PMU_NODE
in <opensbi>lib/utils/fdt/Kconfig and use it in fdt_fixups() function.
Regards,
Anup
> };
>
> /** Get pointer to sbi_scratch for current HART */
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index e213ded..cf20edf 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -387,6 +387,8 @@ int fdt_reserved_memory_fixup(void *fdt)
>
> void fdt_fixups(void *fdt)
> {
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> fdt_aplic_fixup(fdt);
>
> fdt_imsic_fixup(fdt);
> @@ -394,5 +396,7 @@ void fdt_fixups(void *fdt)
> fdt_plic_fixup(fdt);
>
> fdt_reserved_memory_fixup(fdt);
> - fdt_pmu_fixup(fdt);
> +
> + if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_NODE))
> + fdt_pmu_fixup(fdt);
> }
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-11-25 4:42 ` Anup Patel
@ 2023-11-28 9:57 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 43+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-28 9:57 UTC (permalink / raw)
To: opensbi
Hi Anup,
On Sat, Nov 25, 2023 at 10:12:06AM +0530, Anup Patel wrote:
> On Wed, Nov 22, 2023 at 1:10?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add a scratch option to control PMU fixup, so the next
> > stage software can dump the PMU node including event
> > mapping information for debugging purposes.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Reviewed-by: Anup Patel <anup@brainfault.org>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > Changes v2 -> v3:
> > - Rename to SBI_SCRATCH_PRESERVE_PMU_NODE (suggested by Anup)
> > - Include Anup's RB tag
> > ---
> > include/sbi/sbi_scratch.h | 2 ++
> > lib/utils/fdt/fdt_fixup.c | 6 +++++-
> > 2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> > index e6a33ba..0f67cde 100644
> > --- a/include/sbi/sbi_scratch.h
> > +++ b/include/sbi/sbi_scratch.h
> > @@ -151,6 +151,8 @@ enum sbi_scratch_options {
> > SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
> > /** Enable runtime debug prints */
> > SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
> > + /** Preserve PMU node properties */
> > + SBI_SCRATCH_PRESERVE_PMU_NODE = (1 << 2),
>
> I have second thoughts about using the scratch option for this.
>
> Let's not waste a bit in the scratch option just for debugging the PMU node.
>
> I suggest adding the kconfig option FDT_FIXUPS_PRESERVE_PMU_NODE
> in <opensbi>lib/utils/fdt/Kconfig and use it in fdt_fixups() function.
OK, will do.
Best regards,
Peter Lin
> Regards,
> Anup
>
> > };
> >
> > /** Get pointer to sbi_scratch for current HART */
> > diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> > index e213ded..cf20edf 100644
> > --- a/lib/utils/fdt/fdt_fixup.c
> > +++ b/lib/utils/fdt/fdt_fixup.c
> > @@ -387,6 +387,8 @@ int fdt_reserved_memory_fixup(void *fdt)
> >
> > void fdt_fixups(void *fdt)
> > {
> > + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> > +
> > fdt_aplic_fixup(fdt);
> >
> > fdt_imsic_fixup(fdt);
> > @@ -394,5 +396,7 @@ void fdt_fixups(void *fdt)
> > fdt_plic_fixup(fdt);
> >
> > fdt_reserved_memory_fixup(fdt);
> > - fdt_pmu_fixup(fdt);
> > +
> > + if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_NODE))
> > + fdt_pmu_fixup(fdt);
> > }
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 11/15] platform: andes: Factor out is_andes() helper
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (9 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 10/15] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 12/15] lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable Yu Chien Peter Lin
` (4 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
We will need is_andes(45) in the following patch,
so factor out the code that parses marchid to make
it reusable for checking any Andes CPU variants.
Also improves the comment in ae350_hart_start().
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- New patch
Changes v2 -> v3:
- Include Anup's RB tag
---
platform/generic/andes/ae350.c | 16 +++++++---------
platform/generic/include/andes/andes45.h | 6 ++++++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index dc769b7..088ec07 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -24,16 +24,14 @@ static struct smu_data smu = { 0 };
extern void __ae350_enable_coherency_warmboot(void);
extern void __ae350_disable_coherency(void);
-static __always_inline bool is_andes25(void)
-{
- ulong marchid = csr_read(CSR_MARCHID);
- return !!(EXTRACT_FIELD(marchid, CSR_MARCHID_MICROID) == 0xa25);
-}
-
static int ae350_hart_start(u32 hartid, ulong saddr)
{
- /* Don't send wakeup command at boot-time */
- if (!sbi_init_count(hartid) || (is_andes25() && hartid == 0))
+ /*
+ * Don't send wakeup command when:
+ * 1) boot-time
+ * 2) the target hart is non-sleepable 25-series hart0
+ */
+ if (!sbi_init_count(hartid) || (is_andes(25) && hartid == 0))
return sbi_ipi_raw_send(sbi_hartid_to_hartindex(hartid));
/* Write wakeup command to the sleep hart */
@@ -52,7 +50,7 @@ static int ae350_hart_stop(void)
* L2-cache, instead of turning it off, it should fall
* through and jump to warmboot_addr.
*/
- if (is_andes25() && hartid == 0)
+ if (is_andes(25) && hartid == 0)
return SBI_ENOTSUPP;
if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index ce31617..01f63d4 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -43,6 +43,12 @@
#ifndef __ASSEMBLER__
+#define is_andes(series) \
+({ \
+ char value = csr_read(CSR_MARCHID) & 0xff; \
+ (series) == (value >> 4) * 10 + (value & 0x0f); \
+})
+
#define has_andes_pmu() \
({ \
(((csr_read(CSR_MMSC_CFG) & \
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 12/15] lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (10 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 11/15] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 13/15] lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table Yu Chien Peter Lin
` (3 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
To allow platform override pmu_init() filling the translation table
fdt_pmu_evt_select[] when PMU node doesn't provide such information,
we need to share the table and its entry counter with other .c file.
We also define the structures of PMU property in fdt_helper.h, so we
can initialize the mappings in arrays.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v2 -> v3:
- New patch
---
include/sbi_utils/fdt/fdt_helper.h | 17 +++++++++++++++++
include/sbi_utils/fdt/fdt_pmu.h | 6 ++++++
lib/utils/fdt/fdt_pmu.c | 13 ++++---------
3 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/include/sbi_utils/fdt/fdt_helper.h b/include/sbi_utils/fdt/fdt_helper.h
index 5c928ff..f6f505b 100644
--- a/include/sbi_utils/fdt/fdt_helper.h
+++ b/include/sbi_utils/fdt/fdt_helper.h
@@ -34,6 +34,23 @@ struct platform_uart_data {
unsigned long reg_offset;
};
+struct fdt_pmu_hw_event_select_map {
+ uint32_t eidx;
+ uint64_t select;
+};
+
+struct fdt_pmu_hw_event_counter_map {
+ uint32_t eidx_start;
+ uint32_t eidx_end;
+ uint32_t ctr_map;
+};
+
+struct fdt_pmu_raw_event_counter_map {
+ uint64_t select;
+ uint64_t select_mask;
+ uint32_t ctr_map;
+};
+
const struct fdt_match *fdt_match_node(void *fdt, int nodeoff,
const struct fdt_match *match_table);
diff --git a/include/sbi_utils/fdt/fdt_pmu.h b/include/sbi_utils/fdt/fdt_pmu.h
index c65cad7..9a13487 100644
--- a/include/sbi_utils/fdt/fdt_pmu.h
+++ b/include/sbi_utils/fdt/fdt_pmu.h
@@ -12,6 +12,7 @@
#define __FDT_PMU_H__
#include <sbi/sbi_types.h>
+#include <sbi_utils/fdt/fdt_helper.h>
#ifdef CONFIG_FDT_PMU
@@ -45,6 +46,11 @@ int fdt_pmu_setup(void *fdt);
*/
uint64_t fdt_pmu_get_select_value(uint32_t event_idx);
+/** The event index to selector value table instance */
+extern struct fdt_pmu_hw_event_select_map fdt_pmu_evt_select[];
+/** The number of valid entries in fdt_pmu_evt_select[] */
+extern uint32_t hw_event_count;
+
#else
static inline void fdt_pmu_fixup(void *fdt) { }
diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
index a8d7648..cf3220f 100644
--- a/lib/utils/fdt/fdt_pmu.c
+++ b/lib/utils/fdt/fdt_pmu.c
@@ -17,18 +17,13 @@
#define FDT_PMU_HW_EVENT_MAX (SBI_PMU_HW_EVENT_MAX * 2)
-struct fdt_pmu_hw_event_select {
- uint32_t eidx;
- uint64_t select;
-};
-
-static struct fdt_pmu_hw_event_select fdt_pmu_evt_select[FDT_PMU_HW_EVENT_MAX] = {0};
-static uint32_t hw_event_count;
+struct fdt_pmu_hw_event_select_map fdt_pmu_evt_select[FDT_PMU_HW_EVENT_MAX] = {0};
+uint32_t hw_event_count;
uint64_t fdt_pmu_get_select_value(uint32_t event_idx)
{
int i;
- struct fdt_pmu_hw_event_select *event;
+ struct fdt_pmu_hw_event_select_map *event;
for (i = 0; i < SBI_PMU_HW_EVENT_MAX; i++) {
event = &fdt_pmu_evt_select[i];
@@ -65,7 +60,7 @@ int fdt_pmu_setup(void *fdt)
int i, pmu_offset, len, result;
const u32 *event_val;
const u32 *event_ctr_map;
- struct fdt_pmu_hw_event_select *event;
+ struct fdt_pmu_hw_event_select_map *event;
uint64_t raw_selector, select_mask;
u32 event_idx_start, event_idx_end, ctr_map;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 13/15] lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (11 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 12/15] lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-22 7:36 ` [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support Yu Chien Peter Lin
` (2 subsequent siblings)
15 siblings, 0 replies; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
The valid entry count is tracking by hw_event_count so there
is no need to check the whole table.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v2 -> v3:
- New patch
---
lib/utils/fdt/fdt_pmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
index cf3220f..c531b9a 100644
--- a/lib/utils/fdt/fdt_pmu.c
+++ b/lib/utils/fdt/fdt_pmu.c
@@ -25,7 +25,7 @@ uint64_t fdt_pmu_get_select_value(uint32_t event_idx)
int i;
struct fdt_pmu_hw_event_select_map *event;
- for (i = 0; i < SBI_PMU_HW_EVENT_MAX; i++) {
+ for (i = 0; i < hw_event_count; i++) {
event = &fdt_pmu_evt_select[i];
if (event->eidx == event_idx)
return event->select;
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (12 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 13/15] lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-24 14:55 ` Lad, Prabhakar
2023-11-22 7:36 ` [PATCH v3 15/15] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
2023-11-23 0:07 ` [PATCH v3 00/15] Add Andes PMU extension support Atish Patra
15 siblings, 1 reply; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Provide the andes_pmu_setup() to populate default mappings in
hw_event_map[] and fdt_pmu_evt_select[] when fdt_pmu_setup()
cannot find the PMU node.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v2 -> v3:
- New patch
- Drop fdt_add_pmu_mappings() (suggested by Anup [1])
[1] https://patchwork.ozlabs.org/project/opensbi/patch/20231019113713.3508153-11-peterlin at andestech.com/
---
include/sbi/sbi_ecall_interface.h | 5 +
platform/generic/Kconfig | 2 +
platform/generic/andes/Kconfig | 7 +
platform/generic/andes/andes_hpm.c | 405 +++++++++++++++++++++
platform/generic/andes/objects.mk | 1 +
platform/generic/include/andes/andes_hpm.h | 81 +++++
6 files changed, 501 insertions(+)
create mode 100644 platform/generic/andes/andes_hpm.c
create mode 100644 platform/generic/include/andes/andes_hpm.h
diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index 1fe469e..89187e7 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
SBI_PMU_HW_CACHE_RESULT_MAX,
};
+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
+ (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
+ SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
+ SBI_PMU_HW_CACHE_RESULT_##res)
+
/**
* Special "firmware" events provided by the OpenSBI, even if the hardware
* does not support performance events. These events are encoded as a raw
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index c9b6011..e652645 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -32,6 +32,7 @@ config PLATFORM_ALLWINNER_D1
config PLATFORM_ANDES_AE350
bool "Andes AE350 support"
select SYS_ATCSMU
+ select ANDES_HPM
select ANDES_PMU
default n
@@ -39,6 +40,7 @@ config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES45_PMA
select ANDES_SBI
+ select ANDES_HPM
select ANDES_PMU
default n
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index 5b2ed91..de0d752 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -8,6 +8,13 @@ config ANDES_SBI
bool "Andes SBI support"
default n
+config ANDES_HPM
+ bool "Andes HPM support"
+ default n
+ help
+ This provides default HPM event counter mappings
+ when a pmu node is missing.
+
config ANDES_PMU
bool "Andes PMU extension (xandespmu) support"
default n
diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
new file mode 100644
index 0000000..7fe5ac5
--- /dev/null
+++ b/platform/generic/andes/andes_hpm.c
@@ -0,0 +1,405 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * andes_hpm.c - Default event mappings and helper routine
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#include <andes/andes45.h>
+#include <andes/andes_hpm.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi/sbi_pmu.h>
+#include <sbi_utils/fdt/fdt_pmu.h>
+
+static const struct fdt_pmu_hw_event_select_map andes45_hw_evt_selects[] = {
+ /* Hardware general events (Type #0) */
+ {
+ /* perf: cycles (eidx: 0x1) */
+ .eidx = SBI_PMU_HW_CPU_CYCLES,
+ .select = ANDES_CYCLES
+ },
+ {
+ /* perf: instructions (eidx: 0x2) */
+ .eidx = SBI_PMU_HW_INSTRUCTIONS,
+ .select = ANDES_INSTRET
+ },
+ {
+ /* perf: cache-references (eidx: 0x3) */
+ .eidx = SBI_PMU_HW_CACHE_REFERENCES,
+ .select = ANDES_DCACHE_ACCESS
+ },
+ {
+ /* perf: cache-misses (eidx: 0x4) */
+ .eidx = SBI_PMU_HW_CACHE_MISSES,
+ .select = ANDES_DCACHE_MISS
+ },
+ {
+ /* perf: branches (eidx: 0x5) */
+ .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
+ .select = ANDES_CONDITION_BR,
+ },
+ {
+ /* perf: branch-misses (eidx: 0x6) */
+ .eidx = SBI_PMU_HW_BRANCH_MISSES,
+ .select = ANDES_MISPREDICT_CONDITION_BR,
+ },
+ /* Hardware cache events (Type #1) */
+ {
+ /* perf: L1-dcache-loads (eidx: 0x10000) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+ .select = ANDES_DCACHE_LOAD_ACCESS
+ },
+ {
+ /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
+ .select = ANDES_DCACHE_LOAD_MISS
+ },
+ {
+ /* perf: L1-dcache-stores (eidx: 0x10002) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
+ .select = ANDES_DCACHE_STORE_ACCESS
+ },
+ {
+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+ .select = ANDES_DCACHE_STORE_MISS
+ },
+ {
+ /* perf: L1-icache-load (eidx: 0x10008) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+ .select = ANDES_ICACHE_ACCESS
+ },
+ {
+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+ .select = ANDES_ICACHE_MISS
+ },
+};
+
+static const struct fdt_pmu_hw_event_counter_map andes45_hw_evt_counters[] = {
+ {
+ /* perf: cycles (eidx: 0x1) */
+ .eidx_start = SBI_PMU_HW_CPU_CYCLES,
+ /* perf: branch-misses (eidx: 0x6) */
+ .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+ {
+ /* perf: L1-dcache-loads (eidx: 0x10000) */
+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+ {
+ /* perf: L1-icache-load (eidx: 0x10008) */
+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+};
+
+static const struct fdt_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
+ {
+ .select = ANDES_CYCLES,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INSTRET,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_LOAD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_STORE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ATOMIC_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_SYS_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_COMPUTE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_TAKEN_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_JAL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_JALR_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_RET_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CONTROL_TRANS_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_EX9_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_MUL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_DIV_REMAINDER_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_LOAD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_STORE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_ADD_SUB_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_MUL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_FUSED_MULADD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_OTHER_FLOAT_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_MUL_AND_SUB_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_RETIRED_OP,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ILM_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DLM_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ICACHE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ICACHE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_LOAD_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_LOAD_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_STORE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_STORE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_WB,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_UNCACHED_LOAD_FROM_BUS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_ITLB_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_ITLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_DTLB_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_DTLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_ITLB_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_HW_PREFETCH_BUS_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_TARGET_RET_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+};
+
+int andes_pmu_setup(void)
+{
+ int i, rc;
+ struct fdt_pmu_hw_event_select_map *event;
+
+ /*
+ * At the moment, simply create mapping for any 45-series core
+ * based on marchid, we may check and differentiate the mapping
+ * by mimpid.
+ */
+ if (!is_andes(45))
+ return 0;
+
+ for (i = 0; i < array_size(andes45_hw_evt_counters); i++) {
+ rc = sbi_pmu_add_hw_event_counter_map(
+ andes45_hw_evt_counters[i].eidx_start,
+ andes45_hw_evt_counters[i].eidx_end,
+ andes45_hw_evt_counters[i].ctr_map);
+ if (rc)
+ return rc;
+ }
+
+ for (i = 0; i < array_size(andes45_hw_evt_selects); i++) {
+ event = &fdt_pmu_evt_select[hw_event_count];
+ event->eidx = andes45_hw_evt_selects[i].eidx;
+ event->select = andes45_hw_evt_selects[i].select;
+ hw_event_count++;
+ }
+
+ for (i = 0; i < array_size(andes45_raw_evt_counters); i++) {
+ rc = sbi_pmu_add_raw_event_counter_map(
+ andes45_raw_evt_counters[i].select,
+ andes45_raw_evt_counters[i].select_mask,
+ andes45_raw_evt_counters[i].ctr_map);
+ if (rc)
+ return rc;
+ }
+
+ return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index 6a8c66c..57caaf6 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
new file mode 100644
index 0000000..79c75f6
--- /dev/null
+++ b/platform/generic/include/andes/andes_hpm.h
@@ -0,0 +1,81 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _ANDES_HPM_H_
+#define _ANDES_HPM_H_
+
+#define ANDES_MHPM_MAP 0x78
+#define ANDES_RAW_EVENT_MASK ~0ULL
+
+/* Event selector for instruction commit events */
+#define ANDES_CYCLES 0x10
+#define ANDES_INSTRET 0x20
+#define ANDES_INT_LOAD_INST 0x30
+#define ANDES_INT_STORE_INST 0x40
+#define ANDES_ATOMIC_INST 0x50
+#define ANDES_SYS_INST 0x60
+#define ANDES_INT_COMPUTE_INST 0x70
+#define ANDES_CONDITION_BR 0x80
+#define ANDES_TAKEN_CONDITION_BR 0x90
+#define ANDES_JAL_INST 0xA0
+#define ANDES_JALR_INST 0xB0
+#define ANDES_RET_INST 0xC0
+#define ANDES_CONTROL_TRANS_INST 0xD0
+#define ANDES_EX9_INST 0xE0
+#define ANDES_INT_MUL_INST 0xF0
+#define ANDES_INT_DIV_REMAINDER_INST 0x100
+#define ANDES_FLOAT_LOAD_INST 0x110
+#define ANDES_FLOAT_STORE_INST 0x120
+#define ANDES_FLOAT_ADD_SUB_INST 0x130
+#define ANDES_FLOAT_MUL_INST 0x140
+#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
+#define ANDES_OTHER_FLOAT_INST 0x170
+#define ANDES_INT_MUL_AND_SUB_INST 0x180
+#define ANDES_RETIRED_OP 0x190
+
+/* Event selector for memory system events */
+#define ANDES_ILM_ACCESS 0x01
+#define ANDES_DLM_ACCESS 0x11
+#define ANDES_ICACHE_ACCESS 0x21
+#define ANDES_ICACHE_MISS 0x31
+#define ANDES_DCACHE_ACCESS 0x41
+#define ANDES_DCACHE_MISS 0x51
+#define ANDES_DCACHE_LOAD_ACCESS 0x61
+#define ANDES_DCACHE_LOAD_MISS 0x71
+#define ANDES_DCACHE_STORE_ACCESS 0x81
+#define ANDES_DCACHE_STORE_MISS 0x91
+#define ANDES_DCACHE_WB 0xA1
+#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
+#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
+#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
+#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
+#define ANDES_MAIN_ITLB_ACCESS 0x111
+#define ANDES_MAIN_ITLB_MISS 0x121
+#define ANDES_MAIN_DTLB_ACCESS 0x131
+#define ANDES_MAIN_DTLB_MISS 0x141
+#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
+#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
+
+/* Event selector for microarchitecture events */
+#define ANDES_MISPREDICT_CONDITION_BR 0x02
+#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
+#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
+
+#ifdef CONFIG_ANDES_HPM
+
+int andes_pmu_setup(void);
+
+#else
+
+int andes_pmu_setup(void) { return 0; }
+
+#endif /* CONFIG_ANDES_HPM */
+
+#endif /* _ANDES_HPM_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support
2023-11-22 7:36 ` [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support Yu Chien Peter Lin
@ 2023-11-24 14:55 ` Lad, Prabhakar
0 siblings, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:55 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:42?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Provide the andes_pmu_setup() to populate default mappings in
> hw_event_map[] and fdt_pmu_evt_select[] when fdt_pmu_setup()
> cannot find the PMU node.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v2 -> v3:
> - New patch
> - Drop fdt_add_pmu_mappings() (suggested by Anup [1])
>
> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20231019113713.3508153-11-peterlin at andestech.com/
> ---
> include/sbi/sbi_ecall_interface.h | 5 +
> platform/generic/Kconfig | 2 +
> platform/generic/andes/Kconfig | 7 +
> platform/generic/andes/andes_hpm.c | 405 +++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_hpm.h | 81 +++++
> 6 files changed, 501 insertions(+)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index 1fe469e..89187e7 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> SBI_PMU_HW_CACHE_RESULT_MAX,
> };
>
> +#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
> + (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
> + SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
> + SBI_PMU_HW_CACHE_RESULT_##res)
> +
> /**
> * Special "firmware" events provided by the OpenSBI, even if the hardware
> * does not support performance events. These events are encoded as a raw
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index c9b6011..e652645 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -32,6 +32,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
> + select ANDES_HPM
> select ANDES_PMU
> default n
>
> @@ -39,6 +40,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
> + select ANDES_HPM
> select ANDES_PMU
> default n
>
> diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> index 5b2ed91..de0d752 100644
> --- a/platform/generic/andes/Kconfig
> +++ b/platform/generic/andes/Kconfig
> @@ -8,6 +8,13 @@ config ANDES_SBI
> bool "Andes SBI support"
> default n
>
> +config ANDES_HPM
> + bool "Andes HPM support"
> + default n
> + help
> + This provides default HPM event counter mappings
> + when a pmu node is missing.
> +
> config ANDES_PMU
> bool "Andes PMU extension (xandespmu) support"
> default n
> diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
> new file mode 100644
> index 0000000..7fe5ac5
> --- /dev/null
> +++ b/platform/generic/andes/andes_hpm.c
> @@ -0,0 +1,405 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * andes_hpm.c - Default event mappings and helper routine
> + *
> + * Copyright (c) 2023 Andes Technology Corporation
> + */
> +
> +#include <andes/andes45.h>
> +#include <andes/andes_hpm.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi/sbi_pmu.h>
> +#include <sbi_utils/fdt/fdt_pmu.h>
> +
> +static const struct fdt_pmu_hw_event_select_map andes45_hw_evt_selects[] = {
> + /* Hardware general events (Type #0) */
> + {
> + /* perf: cycles (eidx: 0x1) */
> + .eidx = SBI_PMU_HW_CPU_CYCLES,
> + .select = ANDES_CYCLES
> + },
> + {
> + /* perf: instructions (eidx: 0x2) */
> + .eidx = SBI_PMU_HW_INSTRUCTIONS,
> + .select = ANDES_INSTRET
> + },
> + {
> + /* perf: cache-references (eidx: 0x3) */
> + .eidx = SBI_PMU_HW_CACHE_REFERENCES,
> + .select = ANDES_DCACHE_ACCESS
> + },
> + {
> + /* perf: cache-misses (eidx: 0x4) */
> + .eidx = SBI_PMU_HW_CACHE_MISSES,
> + .select = ANDES_DCACHE_MISS
> + },
> + {
> + /* perf: branches (eidx: 0x5) */
> + .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
> + .select = ANDES_CONDITION_BR,
> + },
> + {
> + /* perf: branch-misses (eidx: 0x6) */
> + .eidx = SBI_PMU_HW_BRANCH_MISSES,
> + .select = ANDES_MISPREDICT_CONDITION_BR,
> + },
> + /* Hardware cache events (Type #1) */
> + {
> + /* perf: L1-dcache-loads (eidx: 0x10000) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> + .select = ANDES_DCACHE_LOAD_ACCESS
> + },
> + {
> + /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
> + .select = ANDES_DCACHE_LOAD_MISS
> + },
> + {
> + /* perf: L1-dcache-stores (eidx: 0x10002) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
> + .select = ANDES_DCACHE_STORE_ACCESS
> + },
> + {
> + /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> + .select = ANDES_DCACHE_STORE_MISS
> + },
> + {
> + /* perf: L1-icache-load (eidx: 0x10008) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> + .select = ANDES_ICACHE_ACCESS
> + },
> + {
> + /* perf: L1-icache-load-misses (eidx: 0x10009) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> + .select = ANDES_ICACHE_MISS
> + },
> +};
> +
> +static const struct fdt_pmu_hw_event_counter_map andes45_hw_evt_counters[] = {
> + {
> + /* perf: cycles (eidx: 0x1) */
> + .eidx_start = SBI_PMU_HW_CPU_CYCLES,
> + /* perf: branch-misses (eidx: 0x6) */
> + .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> + {
> + /* perf: L1-dcache-loads (eidx: 0x10000) */
> + .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> + /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> + .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> + {
> + /* perf: L1-icache-load (eidx: 0x10008) */
> + .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> + /* perf: L1-icache-load-misses (eidx: 0x10009) */
> + .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> +};
> +
> +static const struct fdt_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
> + {
> + .select = ANDES_CYCLES,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INSTRET,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_LOAD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_STORE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ATOMIC_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_SYS_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_COMPUTE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_TAKEN_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_JAL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_JALR_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_RET_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CONTROL_TRANS_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_EX9_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_MUL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_DIV_REMAINDER_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_LOAD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_STORE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_ADD_SUB_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_MUL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_FUSED_MULADD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_OTHER_FLOAT_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_MUL_AND_SUB_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_RETIRED_OP,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ILM_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DLM_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ICACHE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ICACHE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_LOAD_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_LOAD_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_STORE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_STORE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_WB,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_UNCACHED_LOAD_FROM_BUS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_ITLB_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_ITLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_DTLB_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_DTLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_ITLB_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_HW_PREFETCH_BUS_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_TARGET_RET_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> +};
> +
> +int andes_pmu_setup(void)
> +{
> + int i, rc;
> + struct fdt_pmu_hw_event_select_map *event;
> +
> + /*
> + * At the moment, simply create mapping for any 45-series core
> + * based on marchid, we may check and differentiate the mapping
> + * by mimpid.
> + */
> + if (!is_andes(45))
> + return 0;
> +
> + for (i = 0; i < array_size(andes45_hw_evt_counters); i++) {
> + rc = sbi_pmu_add_hw_event_counter_map(
> + andes45_hw_evt_counters[i].eidx_start,
> + andes45_hw_evt_counters[i].eidx_end,
> + andes45_hw_evt_counters[i].ctr_map);
> + if (rc)
> + return rc;
> + }
> +
> + for (i = 0; i < array_size(andes45_hw_evt_selects); i++) {
> + event = &fdt_pmu_evt_select[hw_event_count];
> + event->eidx = andes45_hw_evt_selects[i].eidx;
> + event->select = andes45_hw_evt_selects[i].select;
> + hw_event_count++;
> + }
> +
> + for (i = 0; i < array_size(andes45_raw_evt_counters); i++) {
> + rc = sbi_pmu_add_raw_event_counter_map(
> + andes45_raw_evt_counters[i].select,
> + andes45_raw_evt_counters[i].select_mask,
> + andes45_raw_evt_counters[i].ctr_map);
> + if (rc)
> + return rc;
> + }
> +
> + return 0;
> +}
> diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> index 6a8c66c..57caaf6 100644
> --- a/platform/generic/andes/objects.mk
> +++ b/platform/generic/andes/objects.mk
> @@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
> +platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
> diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
> new file mode 100644
> index 0000000..79c75f6
> --- /dev/null
> +++ b/platform/generic/include/andes/andes_hpm.h
> @@ -0,0 +1,81 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2023 Andes Technology Corporation
> + */
> +
> +#ifndef _ANDES_HPM_H_
> +#define _ANDES_HPM_H_
> +
> +#define ANDES_MHPM_MAP 0x78
> +#define ANDES_RAW_EVENT_MASK ~0ULL
> +
> +/* Event selector for instruction commit events */
> +#define ANDES_CYCLES 0x10
> +#define ANDES_INSTRET 0x20
> +#define ANDES_INT_LOAD_INST 0x30
> +#define ANDES_INT_STORE_INST 0x40
> +#define ANDES_ATOMIC_INST 0x50
> +#define ANDES_SYS_INST 0x60
> +#define ANDES_INT_COMPUTE_INST 0x70
> +#define ANDES_CONDITION_BR 0x80
> +#define ANDES_TAKEN_CONDITION_BR 0x90
> +#define ANDES_JAL_INST 0xA0
> +#define ANDES_JALR_INST 0xB0
> +#define ANDES_RET_INST 0xC0
> +#define ANDES_CONTROL_TRANS_INST 0xD0
> +#define ANDES_EX9_INST 0xE0
> +#define ANDES_INT_MUL_INST 0xF0
> +#define ANDES_INT_DIV_REMAINDER_INST 0x100
> +#define ANDES_FLOAT_LOAD_INST 0x110
> +#define ANDES_FLOAT_STORE_INST 0x120
> +#define ANDES_FLOAT_ADD_SUB_INST 0x130
> +#define ANDES_FLOAT_MUL_INST 0x140
> +#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
> +#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
> +#define ANDES_OTHER_FLOAT_INST 0x170
> +#define ANDES_INT_MUL_AND_SUB_INST 0x180
> +#define ANDES_RETIRED_OP 0x190
> +
> +/* Event selector for memory system events */
> +#define ANDES_ILM_ACCESS 0x01
> +#define ANDES_DLM_ACCESS 0x11
> +#define ANDES_ICACHE_ACCESS 0x21
> +#define ANDES_ICACHE_MISS 0x31
> +#define ANDES_DCACHE_ACCESS 0x41
> +#define ANDES_DCACHE_MISS 0x51
> +#define ANDES_DCACHE_LOAD_ACCESS 0x61
> +#define ANDES_DCACHE_LOAD_MISS 0x71
> +#define ANDES_DCACHE_STORE_ACCESS 0x81
> +#define ANDES_DCACHE_STORE_MISS 0x91
> +#define ANDES_DCACHE_WB 0xA1
> +#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
> +#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
> +#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
> +#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
> +#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
> +#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
> +#define ANDES_MAIN_ITLB_ACCESS 0x111
> +#define ANDES_MAIN_ITLB_MISS 0x121
> +#define ANDES_MAIN_DTLB_ACCESS 0x131
> +#define ANDES_MAIN_DTLB_MISS 0x141
> +#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
> +#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
> +#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
> +
> +/* Event selector for microarchitecture events */
> +#define ANDES_MISPREDICT_CONDITION_BR 0x02
> +#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
> +#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
> +
> +#ifdef CONFIG_ANDES_HPM
> +
> +int andes_pmu_setup(void);
> +
> +#else
> +
> +int andes_pmu_setup(void) { return 0; }
> +
> +#endif /* CONFIG_ANDES_HPM */
> +
> +#endif /* _ANDES_HPM_H_ */
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 15/15] docs: pmu: Add Andes PMU node example
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (13 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 14/15] platform: andes: Add Andes default PMU mapping support Yu Chien Peter Lin
@ 2023-11-22 7:36 ` Yu Chien Peter Lin
2023-11-24 14:56 ` Lad, Prabhakar
2023-11-23 0:07 ` [PATCH v3 00/15] Add Andes PMU extension support Atish Patra
15 siblings, 1 reply; 43+ messages in thread
From: Yu Chien Peter Lin @ 2023-11-22 7:36 UTC (permalink / raw)
To: opensbi
Add PMU node example for event index to counter index mapping
and selector value translation of Andes' CPUs.
Currently, there are 4 HPM counters that can be used to monitor
all of the events for each hart.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
---
Changes v1 -> v2:
- sync up with datasheet
Changes v2 -> v3:
- Include Anup's RB tag
---
docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 8cfa08c..9b48f1e 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -125,3 +125,85 @@ pmu {
<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
};
```
+
+### Example 3
+
+```
+/*
+ * For Andes 45-series platforms. The encodings can be found in the
+ * "Machine Performance Monitoring Event Selector" section
+ * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ */
+pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmevent =
+ <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */
+ <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */
+ <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */
+ <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */
+ <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
+ <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */
+ <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */
+ <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */
+ <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */
+ <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */
+ <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */
+ <0x10009 0x0000 0x31>; /* L1I_READ_MISS -> I-Cache miss */
+ riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
+ <0x10000 0x10003 0x78>,
+ <0x10008 0x10009 0x78>;
+ riscv,raw-event-to-mhpmcounters =
+ <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
+ <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
+ <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
+ <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
+ <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
+ <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
+ <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
+ <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
+ <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
+ <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
+ <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
+ <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
+ <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
+ <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
+ <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
+ <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
+ <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
+ <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
+ <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
+ <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
+ <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
+ <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
+ <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
+ <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
+ <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
+ <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
+ <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
+ <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
+ <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
+ <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
+ <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
+ <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
+ <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
+ <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
+ <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
+ <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
+ <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
+ <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
+ <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
+ <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
+ <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
+ <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
+ <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
+ <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
+ <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
+ <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
+ <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
+ <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
+ <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
+ <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
+ <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
+ <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
+};
+```
--
2.34.1
^ permalink raw reply related [flat|nested] 43+ messages in thread* [PATCH v3 15/15] docs: pmu: Add Andes PMU node example
2023-11-22 7:36 ` [PATCH v3 15/15] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
@ 2023-11-24 14:56 ` Lad, Prabhakar
0 siblings, 0 replies; 43+ messages in thread
From: Lad, Prabhakar @ 2023-11-24 14:56 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 7:42?AM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add PMU node example for event index to counter index mapping
> and selector value translation of Andes' CPUs.
>
> Currently, there are 4 HPM counters that can be used to monitor
> all of the events for each hart.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Locus Wei-Han Chen <locus84@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> ---
> Changes v1 -> v2:
> - sync up with datasheet
> Changes v2 -> v3:
> - Include Anup's RB tag
> ---
> docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 82 insertions(+)
>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers,
Prabhakar
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 8cfa08c..9b48f1e 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -125,3 +125,85 @@ pmu {
> <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
> };
> ```
> +
> +### Example 3
> +
> +```
> +/*
> + * For Andes 45-series platforms. The encodings can be found in the
> + * "Machine Performance Monitoring Event Selector" section
> + * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> + */
> +pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmevent =
> + <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */
> + <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */
> + <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */
> + <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */
> + <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
> + <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */
> + <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */
> + <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */
> + <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */
> + <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */
> + <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */
> + <0x10009 0x0000 0x31>; /* L1I_READ_MISS -> I-Cache miss */
> + riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
> + <0x10000 0x10003 0x78>,
> + <0x10008 0x10009 0x78>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
> + <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
> + <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
> + <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
> + <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
> + <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
> + <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
> + <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
> + <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
> + <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
> + <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
> + <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
> + <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
> + <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
> + <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
> + <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
> + <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
> + <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
> + <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
> + <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
> + <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
> + <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
> + <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
> + <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
> + <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
> + <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
> + <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
> + <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
> + <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
> + <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
> + <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
> + <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
> + <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
> + <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
> + <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
> + <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
> + <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
> + <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
> + <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
> + <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
> + <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
> + <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
> + <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
> + <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
> + <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
> + <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
> + <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
> + <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
> + <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
> + <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
> + <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
> + <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
> +};
> +```
> --
> 2.34.1
>
>
> --
> opensbi mailing list
> opensbi at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/opensbi
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 00/15] Add Andes PMU extension support
2023-11-22 7:36 [PATCH v3 00/15] Add Andes PMU extension support Yu Chien Peter Lin
` (14 preceding siblings ...)
2023-11-22 7:36 ` [PATCH v3 15/15] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
@ 2023-11-23 0:07 ` Atish Patra
2023-11-23 0:27 ` Atish Patra
15 siblings, 1 reply; 43+ messages in thread
From: Atish Patra @ 2023-11-23 0:07 UTC (permalink / raw)
To: opensbi
On Tue, Nov 21, 2023 at 11:39?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch series enables perf tool to utilize Andes PMU
> extension via PMU SBI calls, provides PMU device callbacks
> to achieve event sampling and mode filtering.
>
> This version mainly fixes single-core freeze when quitting
> 'perf top', adds andes_pmu_setup() to provide default event
> mappings when fdt_pmu_setup() can't find PMU node. And add
> Xandespmu to hart extension list so that the inhibit bits
> can be updated in a similar way to how Smcntrpmf does.
>
> The last patch provides a PMU node example used on AX45MP cores.
>
Do you have a publicly available spec that describes what XAndesPMU does ?
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support-v3
> - https://github.com/andestech/linux/commits/andes-pmu-support-v4
>
> Leo Yu-Chi Liang (1):
> lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
>
> Yu Chien Peter Lin (14):
> sbi: sbi_pmu: Improve sbi_pmu_init() error handling
> lib: sbi: Add Xandespmu in hart extensions
> sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> platform: include: andes45: Add PMU related CSR defines
> platform: generic: Introduce pmu_init() platform override
> platform: andes: Add Andes custom PMU support
> platform: andes: Enable Andes PMU for AE350
> platform: rzfive: Enable Andes PMU for RZ/Five
> lib: utils: fdt_fixup: Allow preserving PMU properties
> platform: andes: Factor out is_andes() helper
> lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable
> lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table
> platform: andes: Add Andes default PMU mapping support
> docs: pmu: Add Andes PMU node example
>
> docs/pmu_support.md | 82 ++++
> include/sbi/sbi_ecall_interface.h | 5 +
> include/sbi/sbi_hart.h | 2 +
> include/sbi/sbi_pmu.h | 6 +
> include/sbi/sbi_scratch.h | 2 +
> include/sbi_utils/fdt/fdt_helper.h | 17 +
> include/sbi_utils/fdt/fdt_pmu.h | 6 +
> include/sbi_utils/ipi/andes_plicsw.h | 23 +-
> lib/sbi/sbi_hart.c | 3 +
> lib/sbi/sbi_pmu.c | 25 +-
> lib/utils/fdt/fdt_fixup.c | 6 +-
> lib/utils/fdt/fdt_pmu.c | 17 +-
> lib/utils/ipi/andes_plicsw.c | 104 ++---
> platform/generic/Kconfig | 4 +
> platform/generic/andes/Kconfig | 15 +
> platform/generic/andes/ae350.c | 19 +-
> platform/generic/andes/andes_hpm.c | 405 +++++++++++++++++++
> platform/generic/andes/andes_pmu.c | 102 +++++
> platform/generic/andes/objects.mk | 2 +
> platform/generic/include/andes/andes45.h | 32 ++
> platform/generic/include/andes/andes_hpm.h | 81 ++++
> platform/generic/include/andes/andes_pmu.h | 33 ++
> platform/generic/include/platform_override.h | 1 +
> platform/generic/platform.c | 11 +-
> platform/generic/renesas/rzfive/rzfive.c | 5 +-
> 25 files changed, 897 insertions(+), 111 deletions(-)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> --
> 2.34.1
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread* [PATCH v3 00/15] Add Andes PMU extension support
2023-11-23 0:07 ` [PATCH v3 00/15] Add Andes PMU extension support Atish Patra
@ 2023-11-23 0:27 ` Atish Patra
2023-11-28 5:23 ` Yu-Chien Peter Lin
0 siblings, 1 reply; 43+ messages in thread
From: Atish Patra @ 2023-11-23 0:27 UTC (permalink / raw)
To: opensbi
On Wed, Nov 22, 2023 at 4:07?PM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Tue, Nov 21, 2023 at 11:39?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > This patch series enables perf tool to utilize Andes PMU
> > extension via PMU SBI calls, provides PMU device callbacks
> > to achieve event sampling and mode filtering.
> >
> > This version mainly fixes single-core freeze when quitting
> > 'perf top', adds andes_pmu_setup() to provide default event
> > mappings when fdt_pmu_setup() can't find PMU node. And add
> > Xandespmu to hart extension list so that the inhibit bits
> > can be updated in a similar way to how Smcntrpmf does.
> >
> > The last patch provides a PMU node example used on AX45MP cores.
> >
>
> Do you have a publicly available spec that describes what XAndesPMU does ?
Never mind. I found it in the last patch. It would be good to include
it in the cover letter as well.
http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support-v3
> > - https://github.com/andestech/linux/commits/andes-pmu-support-v4
> >
> > Leo Yu-Chi Liang (1):
> > lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
> >
> > Yu Chien Peter Lin (14):
> > sbi: sbi_pmu: Improve sbi_pmu_init() error handling
> > lib: sbi: Add Xandespmu in hart extensions
> > sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> > platform: include: andes45: Add PMU related CSR defines
> > platform: generic: Introduce pmu_init() platform override
> > platform: andes: Add Andes custom PMU support
> > platform: andes: Enable Andes PMU for AE350
> > platform: rzfive: Enable Andes PMU for RZ/Five
> > lib: utils: fdt_fixup: Allow preserving PMU properties
> > platform: andes: Factor out is_andes() helper
> > lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable
> > lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table
> > platform: andes: Add Andes default PMU mapping support
> > docs: pmu: Add Andes PMU node example
> >
> > docs/pmu_support.md | 82 ++++
> > include/sbi/sbi_ecall_interface.h | 5 +
> > include/sbi/sbi_hart.h | 2 +
> > include/sbi/sbi_pmu.h | 6 +
> > include/sbi/sbi_scratch.h | 2 +
> > include/sbi_utils/fdt/fdt_helper.h | 17 +
> > include/sbi_utils/fdt/fdt_pmu.h | 6 +
> > include/sbi_utils/ipi/andes_plicsw.h | 23 +-
> > lib/sbi/sbi_hart.c | 3 +
> > lib/sbi/sbi_pmu.c | 25 +-
> > lib/utils/fdt/fdt_fixup.c | 6 +-
> > lib/utils/fdt/fdt_pmu.c | 17 +-
> > lib/utils/ipi/andes_plicsw.c | 104 ++---
> > platform/generic/Kconfig | 4 +
> > platform/generic/andes/Kconfig | 15 +
> > platform/generic/andes/ae350.c | 19 +-
> > platform/generic/andes/andes_hpm.c | 405 +++++++++++++++++++
> > platform/generic/andes/andes_pmu.c | 102 +++++
> > platform/generic/andes/objects.mk | 2 +
> > platform/generic/include/andes/andes45.h | 32 ++
> > platform/generic/include/andes/andes_hpm.h | 81 ++++
> > platform/generic/include/andes/andes_pmu.h | 33 ++
> > platform/generic/include/platform_override.h | 1 +
> > platform/generic/platform.c | 11 +-
> > platform/generic/renesas/rzfive/rzfive.c | 5 +-
> > 25 files changed, 897 insertions(+), 111 deletions(-)
> > create mode 100644 platform/generic/andes/andes_hpm.c
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_hpm.h
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish
--
Regards,
Atish
^ permalink raw reply [flat|nested] 43+ messages in thread
* [PATCH v3 00/15] Add Andes PMU extension support
2023-11-23 0:27 ` Atish Patra
@ 2023-11-28 5:23 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 43+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-28 5:23 UTC (permalink / raw)
To: opensbi
Hi Atish,
On Wed, Nov 22, 2023 at 04:27:02PM -0800, Atish Patra wrote:
> On Wed, Nov 22, 2023 at 4:07?PM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Tue, Nov 21, 2023 at 11:39?PM Yu Chien Peter Lin
> > <peterlin@andestech.com> wrote:
> > >
> > > This patch series enables perf tool to utilize Andes PMU
> > > extension via PMU SBI calls, provides PMU device callbacks
> > > to achieve event sampling and mode filtering.
> > >
> > > This version mainly fixes single-core freeze when quitting
> > > 'perf top', adds andes_pmu_setup() to provide default event
> > > mappings when fdt_pmu_setup() can't find PMU node. And add
> > > Xandespmu to hart extension list so that the inhibit bits
> > > can be updated in a similar way to how Smcntrpmf does.
> > >
> > > The last patch provides a PMU node example used on AX45MP cores.
> > >
> >
> > Do you have a publicly available spec that describes what XAndesPMU does ?
>
> Never mind. I found it in the last patch. It would be good to include
> it in the cover letter as well.
> http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
Sure, will add the link in the v4 cover letter.
Thanks,
Peter Lin
>
> >
> > > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > > - https://github.com/andestech/opensbi/commits/andes-pmu-support-v3
> > > - https://github.com/andestech/linux/commits/andes-pmu-support-v4
> > >
> > > Leo Yu-Chi Liang (1):
> > > lib: ipi: Adjust Andes PLICSW to single-bit-per-hart scheme
> > >
> > > Yu Chien Peter Lin (14):
> > > sbi: sbi_pmu: Improve sbi_pmu_init() error handling
> > > lib: sbi: Add Xandespmu in hart extensions
> > > sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> > > platform: include: andes45: Add PMU related CSR defines
> > > platform: generic: Introduce pmu_init() platform override
> > > platform: andes: Add Andes custom PMU support
> > > platform: andes: Enable Andes PMU for AE350
> > > platform: rzfive: Enable Andes PMU for RZ/Five
> > > lib: utils: fdt_fixup: Allow preserving PMU properties
> > > platform: andes: Factor out is_andes() helper
> > > lib: utils: fdt_pmu: Make the fdt_pmu_evt_select table global variable
> > > lib: utils: fdt_pmu: Do not iterate over the fdt_pmu_evt_select table
> > > platform: andes: Add Andes default PMU mapping support
> > > docs: pmu: Add Andes PMU node example
> > >
> > > docs/pmu_support.md | 82 ++++
> > > include/sbi/sbi_ecall_interface.h | 5 +
> > > include/sbi/sbi_hart.h | 2 +
> > > include/sbi/sbi_pmu.h | 6 +
> > > include/sbi/sbi_scratch.h | 2 +
> > > include/sbi_utils/fdt/fdt_helper.h | 17 +
> > > include/sbi_utils/fdt/fdt_pmu.h | 6 +
> > > include/sbi_utils/ipi/andes_plicsw.h | 23 +-
> > > lib/sbi/sbi_hart.c | 3 +
> > > lib/sbi/sbi_pmu.c | 25 +-
> > > lib/utils/fdt/fdt_fixup.c | 6 +-
> > > lib/utils/fdt/fdt_pmu.c | 17 +-
> > > lib/utils/ipi/andes_plicsw.c | 104 ++---
> > > platform/generic/Kconfig | 4 +
> > > platform/generic/andes/Kconfig | 15 +
> > > platform/generic/andes/ae350.c | 19 +-
> > > platform/generic/andes/andes_hpm.c | 405 +++++++++++++++++++
> > > platform/generic/andes/andes_pmu.c | 102 +++++
> > > platform/generic/andes/objects.mk | 2 +
> > > platform/generic/include/andes/andes45.h | 32 ++
> > > platform/generic/include/andes/andes_hpm.h | 81 ++++
> > > platform/generic/include/andes/andes_pmu.h | 33 ++
> > > platform/generic/include/platform_override.h | 1 +
> > > platform/generic/platform.c | 11 +-
> > > platform/generic/renesas/rzfive/rzfive.c | 5 +-
> > > 25 files changed, 897 insertions(+), 111 deletions(-)
> > > create mode 100644 platform/generic/andes/andes_hpm.c
> > > create mode 100644 platform/generic/andes/andes_pmu.c
> > > create mode 100644 platform/generic/include/andes/andes_hpm.h
> > > create mode 100644 platform/generic/include/andes/andes_pmu.h
> > >
> > > --
> > > 2.34.1
> > >
> >
> >
> > --
> > Regards,
> > Atish
>
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 43+ messages in thread