From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Cc: Hans de Goede <hansg@kernel.org>,
platform-driver-x86@vger.kernel.org, mario.limonciello@amd.com,
Sanket.Goswami@amd.com
Subject: Re: [PATCH v2 2/2] platform/x86/amd/pmc: Add PMC driver support for AMD 1Ah M80H SoC
Date: Mon, 8 Jun 2026 12:18:40 +0300 (EEST) [thread overview]
Message-ID: <13db00fa-ec6b-4de7-d5ec-c9d9895af7d4@linux.intel.com> (raw)
In-Reply-To: <20260601112103.1690951-3-Shyam-sundar.S-k@amd.com>
On Mon, 1 Jun 2026, Shyam Sundar S K wrote:
> The 1Ah M80H SoC uses a different set of SMU mailbox register offsets
> compared to the existing 1Ah variants: message at 0xA10, argument at
> 0xA18, and response at 0xA14.
>
> Add amd_1ah_m80_cpu_info with these offsets, wire it into the PCI ID
> table via PCI_DEVICE_DATA(), handle it in amd_pmc_set_cpu_info() and
> amd_pmc_idlemask_read(), and add the corresponding ACPI ID AMDI000C.
>
> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> drivers/platform/x86/amd/pmc/pmc.c | 15 +++++++++++++++
> drivers/platform/x86/amd/pmc/pmc.h | 6 ++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index 6c7fa80c7f09..8da988016661 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -131,6 +131,15 @@ static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = {
> .os_hint = MSG_OS_HINT_RN,
> };
>
> +static const struct amd_pmc_cpu_info amd_1ah_m80_cpu_info = {
> + .smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H,
> + .smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H,
> + .smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H,
> + .num_ips = ARRAY_SIZE(soc15_ip_blk),
> + .ips_ptr = soc15_ip_blk,
> + .os_hint = MSG_OS_HINT_RN,
> +};
> +
> static bool disable_workarounds;
> module_param(disable_workarounds, bool, 0644);
> MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
> @@ -172,6 +181,9 @@ static void amd_pmc_set_cpu_info(struct amd_pmc_dev *dev)
> else
> info = &amd_1ah_cpu_info;
> break;
> + case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
> + info = &amd_1ah_m80_cpu_info;
This shouldn't be necessary if you get it directly from the match.
> + break;
> default:
> dev_err(dev->dev, "Unknown CPU ID: 0x%x\n", dev->cpu_id);
> return;
> @@ -415,6 +427,7 @@ static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
> break;
> case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
> case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> + case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
> val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
I guess the scratch register too could come from the info, you just
need to handle the AMD_CPU_ID_CZN version check prior to that.
I really like how clean adding new platforms becomes with the info
infrastructure in place. Thanks.
> break;
> default:
> @@ -763,6 +776,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
> { PCI_DEVICE_DATA(AMD, CPU_ID_SHP, NULL) },
> { PCI_DEVICE_DATA(AMD, 1AH_M20H_ROOT, NULL) },
> { PCI_DEVICE_DATA(AMD, 1AH_M60H_ROOT, NULL) },
> + { PCI_DEVICE_DATA(AMD, 1AH_M80H_ROOT, &amd_1ah_m80_cpu_info) },
> { }
> };
>
> @@ -882,6 +896,7 @@ static const struct acpi_device_id amd_pmc_acpi_ids[] = {
> {"AMDI0009", 0},
> {"AMDI000A", 0},
> {"AMDI000B", 0},
> + {"AMDI000C", 0},
> {"AMD0004", 0},
> {"AMD0005", 0},
> { }
> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
> index 0fd0ced21831..0a3b81944920 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.h
> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> @@ -22,6 +22,11 @@
> /* SMU communication registers for 1Ah 20h SoC */
> #define AMD_PMC_REGISTER_MSG_1AH_20H 0x938
>
> +/* SMU communication registers for 1Ah 80h SoC */
> +#define AMD_PMC_REGISTER_MSG_1AH_80H 0xA10
> +#define AMD_PMC_REGISTER_ARG_1AH_80H 0xA18
> +#define AMD_PMC_REGISTER_RSP_1AH_80H 0xA14
> +
> /* PMC Scratch Registers */
> #define AMD_PMC_SCRATCH_REG_CZN 0x94
> #define AMD_PMC_SCRATCH_REG_YC 0xD14
> @@ -189,6 +194,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
>
> #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
> #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
> +#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT 0x115b
> #define PCI_DEVICE_ID_AMD_MP2_STB 0x172c
>
> int amd_stb_s2d_init(struct amd_pmc_dev *dev);
>
--
i.
next prev parent reply other threads:[~2026-06-08 9:18 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-01 11:21 [PATCH v2 0/2] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC Shyam Sundar S K
2026-06-01 11:21 ` [PATCH v2 1/2] platform/x86/amd/pmc: Use per-SoC cpu_info struct for SMU mailbox and IP info Shyam Sundar S K
2026-06-08 9:08 ` Ilpo Järvinen
2026-06-09 5:54 ` Shyam Sundar S K
2026-06-09 8:13 ` Ilpo Järvinen
2026-06-01 11:21 ` [PATCH v2 2/2] platform/x86/amd/pmc: Add PMC driver support for AMD 1Ah M80H SoC Shyam Sundar S K
2026-06-08 9:18 ` Ilpo Järvinen [this message]
2026-06-09 7:23 ` Shyam Sundar S K
2026-06-02 13:58 ` [PATCH v2 0/2] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC Mario Limonciello
2026-06-09 7:38 ` Shyam Sundar S K
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