From: Mario Limonciello <mario.limonciello@amd.com>
To: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>,
hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com,
markgross@kernel.org
Cc: Sanket.Goswami@amd.com, platform-driver-x86@vger.kernel.org
Subject: Re: [PATCH 2/2] platform/x86/amd/pmc: Move structures to pmc header
Date: Mon, 9 Oct 2023 09:56:07 -0500 [thread overview]
Message-ID: <41b8ebc4-78c9-4321-8062-9793fac10835@amd.com> (raw)
In-Reply-To: <20231009144748.24054-2-Shyam-sundar.S-k@amd.com>
On 10/9/2023 09:47, Shyam Sundar S K wrote:
> As we have a separate header for amd_pmc driver, move the common strutures,
> enums, and macros to the header file.
>
> Suggested-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
> based on review-ilpo, can be added on top of recent stb changes
This also splits it up nicely to be able to potentially re-organize the
driver more logically.
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
>
> drivers/platform/x86/amd/pmc/pmc.c | 103 -----------------------------
> drivers/platform/x86/amd/pmc/pmc.h | 103 +++++++++++++++++++++++++++++
> 2 files changed, 103 insertions(+), 103 deletions(-)
>
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index 92adf4523736..943fb85af91d 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -30,109 +30,6 @@
>
> #include "pmc.h"
>
> -/* SMU communication registers */
> -#define AMD_PMC_REGISTER_MESSAGE 0x538
> -#define AMD_PMC_REGISTER_RESPONSE 0x980
> -#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
> -
> -/* PMC Scratch Registers */
> -#define AMD_PMC_SCRATCH_REG_CZN 0x94
> -#define AMD_PMC_SCRATCH_REG_YC 0xD14
> -
> -/* STB Registers */
> -#define AMD_PMC_STB_PMI_0 0x03E30600
> -#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
> -#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
> -#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
> -#define AMD_PMC_STB_DUMMY_PC 0xC6000007
> -
> -/* STB S2D(Spill to DRAM) has different message port offset */
> -#define AMD_S2D_REGISTER_MESSAGE 0xA20
> -#define AMD_S2D_REGISTER_RESPONSE 0xA80
> -#define AMD_S2D_REGISTER_ARGUMENT 0xA88
> -
> -/* STB Spill to DRAM Parameters */
> -#define S2D_TELEMETRY_BYTES_MAX 0x100000
> -#define S2D_RSVD_RAM_SPACE 0x100000
> -#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
> -
> -/* STB Spill to DRAM Message Definition */
> -#define STB_FORCE_FLUSH_DATA 0xCF
> -
> -/* Base address of SMU for mapping physical address to virtual address */
> -#define AMD_PMC_MAPPING_SIZE 0x01000
> -#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
> -#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
> -#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
> -#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
> -#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
> -
> -/* SMU Response Codes */
> -#define AMD_PMC_RESULT_OK 0x01
> -#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
> -#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
> -#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
> -#define AMD_PMC_RESULT_FAILED 0xFF
> -
> -/* FCH SSC Registers */
> -#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
> -#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
> -#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
> -#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
> -#define FCH_SSC_MAPPING_SIZE 0x800
> -#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
> -#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
> -
> -/* SMU Message Definations */
> -#define SMU_MSG_GETSMUVERSION 0x02
> -#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
> -#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
> -#define SMU_MSG_LOG_START 0x06
> -#define SMU_MSG_LOG_RESET 0x07
> -#define SMU_MSG_LOG_DUMP_DATA 0x08
> -#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
> -/* List of supported CPU ids */
> -#define AMD_CPU_ID_RV 0x15D0
> -#define AMD_CPU_ID_RN 0x1630
> -#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
> -#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
> -#define AMD_CPU_ID_YC 0x14B5
> -#define AMD_CPU_ID_CB 0x14D8
> -#define AMD_CPU_ID_PS 0x14E8
> -#define AMD_CPU_ID_SP 0x14A4
> -#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
> -
> -#define PMC_MSG_DELAY_MIN_US 50
> -#define RESPONSE_REGISTER_LOOP_MAX 20000
> -
> -#define DELAY_MIN_US 2000
> -#define DELAY_MAX_US 3000
> -#define FIFO_SIZE 4096
> -
> -enum amd_pmc_def {
> - MSG_TEST = 0x01,
> - MSG_OS_HINT_PCO,
> - MSG_OS_HINT_RN,
> -};
> -
> -enum s2d_arg {
> - S2D_TELEMETRY_SIZE = 0x01,
> - S2D_PHYS_ADDR_LOW,
> - S2D_PHYS_ADDR_HIGH,
> - S2D_NUM_SAMPLES,
> - S2D_DRAM_SIZE,
> -};
> -
> -struct amd_pmc_stb_v2_data {
> - size_t size;
> - u8 data[] __counted_by(size);
> -};
> -
> -struct amd_pmc_bit_map {
> - const char *name;
> - u32 bit_mask;
> -};
> -
> static const struct amd_pmc_bit_map soc15_ip_blk[] = {
> {"DISPLAY", BIT(0)},
> {"CPU", BIT(1)},
> diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
> index 12728eedecda..704256b07ef4 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.h
> +++ b/drivers/platform/x86/amd/pmc/pmc.h
> @@ -14,6 +14,109 @@
> #include <linux/types.h>
> #include <linux/mutex.h>
>
> +/* SMU communication registers */
> +#define AMD_PMC_REGISTER_MESSAGE 0x538
> +#define AMD_PMC_REGISTER_RESPONSE 0x980
> +#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
> +
> +/* PMC Scratch Registers */
> +#define AMD_PMC_SCRATCH_REG_CZN 0x94
> +#define AMD_PMC_SCRATCH_REG_YC 0xD14
> +
> +/* STB Registers */
> +#define AMD_PMC_STB_PMI_0 0x03E30600
> +#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
> +#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
> +#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
> +#define AMD_PMC_STB_DUMMY_PC 0xC6000007
> +
> +/* STB S2D(Spill to DRAM) has different message port offset */
> +#define AMD_S2D_REGISTER_MESSAGE 0xA20
> +#define AMD_S2D_REGISTER_RESPONSE 0xA80
> +#define AMD_S2D_REGISTER_ARGUMENT 0xA88
> +
> +/* STB Spill to DRAM Parameters */
> +#define S2D_TELEMETRY_BYTES_MAX 0x100000
> +#define S2D_RSVD_RAM_SPACE 0x100000
> +#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
> +
> +/* STB Spill to DRAM Message Definition */
> +#define STB_FORCE_FLUSH_DATA 0xCF
> +
> +/* Base address of SMU for mapping physical address to virtual address */
> +#define AMD_PMC_MAPPING_SIZE 0x01000
> +#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
> +#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
> +#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
> +#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
> +#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
> +
> +/* SMU Response Codes */
> +#define AMD_PMC_RESULT_OK 0x01
> +#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
> +#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
> +#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
> +#define AMD_PMC_RESULT_FAILED 0xFF
> +
> +/* FCH SSC Registers */
> +#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
> +#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
> +#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
> +#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
> +#define FCH_SSC_MAPPING_SIZE 0x800
> +#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
> +#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
> +
> +/* SMU Message Definations */
> +#define SMU_MSG_GETSMUVERSION 0x02
> +#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
> +#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
> +#define SMU_MSG_LOG_START 0x06
> +#define SMU_MSG_LOG_RESET 0x07
> +#define SMU_MSG_LOG_DUMP_DATA 0x08
> +#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
> +/* List of supported CPU ids */
> +#define AMD_CPU_ID_RV 0x15D0
> +#define AMD_CPU_ID_RN 0x1630
> +#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
> +#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
> +#define AMD_CPU_ID_YC 0x14B5
> +#define AMD_CPU_ID_CB 0x14D8
> +#define AMD_CPU_ID_PS 0x14E8
> +#define AMD_CPU_ID_SP 0x14A4
> +#define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
> +
> +#define PMC_MSG_DELAY_MIN_US 50
> +#define RESPONSE_REGISTER_LOOP_MAX 20000
> +
> +#define DELAY_MIN_US 2000
> +#define DELAY_MAX_US 3000
> +#define FIFO_SIZE 4096
> +
> +enum amd_pmc_def {
> + MSG_TEST = 0x01,
> + MSG_OS_HINT_PCO,
> + MSG_OS_HINT_RN,
> +};
> +
> +enum s2d_arg {
> + S2D_TELEMETRY_SIZE = 0x01,
> + S2D_PHYS_ADDR_LOW,
> + S2D_PHYS_ADDR_HIGH,
> + S2D_NUM_SAMPLES,
> + S2D_DRAM_SIZE,
> +};
> +
> +struct amd_pmc_stb_v2_data {
> + size_t size;
> + u8 data[] __counted_by(size);
> +};
> +
> +struct amd_pmc_bit_map {
> + const char *name;
> + u32 bit_mask;
> +};
> +
> struct amd_pmc_dev {
> void __iomem *regbase;
> void __iomem *smu_virt_addr;
next prev parent reply other threads:[~2023-10-09 14:56 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 14:47 [PATCH 1/2] platform/x86/amd/pmc: Fix fetching DRAM size mechanism Shyam Sundar S K
2023-10-09 14:47 ` [PATCH 2/2] platform/x86/amd/pmc: Move structures to pmc header Shyam Sundar S K
2023-10-09 14:56 ` Mario Limonciello [this message]
2023-10-09 15:39 ` Ilpo Järvinen
2023-10-09 15:47 ` Shyam Sundar S K
2023-10-09 15:49 ` Ilpo Järvinen
2023-10-09 14:55 ` [PATCH 1/2] platform/x86/amd/pmc: Fix fetching DRAM size mechanism Mario Limonciello
2023-10-09 15:39 ` Shyam Sundar S K
2023-10-09 15:42 ` Mario Limonciello
2023-10-09 14:59 ` Ilpo Järvinen
2023-10-09 15:42 ` Shyam Sundar S K
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