From: Chao Liu <chao.liu@processmission.com>
To: Bin Meng <bin.meng@processmission.com>
Cc: QEMU <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Conor Dooley <conor@kernel.org>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sebastian Huber <sebastian.huber@embedded-brains.de>,
Weiwei Li <liwei1518@gmail.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 02/26] hw/riscv: pfsoc: Map the L2 zero device window
Date: Mon, 27 Jul 2026 13:24:00 +0800 [thread overview]
Message-ID: <ambrZ5BsrYjIAUcP@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260723151853.2143177-3-bin.meng@processmission.com>
On Thu, Jul 23, 2026 at 11:18:29PM +0800, Bin Meng wrote:
> HSS uses a window at 0x0a000000 while setting up the L2 cache,
> decompressing its runtime image, and executing that image.
> The missing mapping causes the E51 to trap before firmware can
> initialize its UART.
>
> Represent the window with RAM to provide its persistent read,
> write, and execute effects without claiming to model the L2
> cache itself.
>
> Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
Thanks,
Chao
> ---
>
> include/hw/riscv/microchip_pfsoc.h | 1 +
> hw/riscv/microchip_pfsoc.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
> index a30b944afa..612fd2b69c 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -90,6 +90,7 @@ enum {
> MICROCHIP_PFSOC_L2CC,
> MICROCHIP_PFSOC_DMA,
> MICROCHIP_PFSOC_L2LIM,
> + MICROCHIP_PFSOC_L2ZERO,
> MICROCHIP_PFSOC_PLIC,
> MICROCHIP_PFSOC_MMUART0,
> MICROCHIP_PFSOC_WDOG0,
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 218cccab69..fd28ee75fe 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -97,6 +97,7 @@ static const MemMapEntry microchip_pfsoc_memmap[] = {
> [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
> [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
> [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x200000 },
> + [MICROCHIP_PFSOC_L2ZERO] = { 0xa000000, 0x200000 },
> [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
> [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
> [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
> @@ -201,6 +202,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
> MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
> MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
> + MemoryRegion *l2zero_mem = g_new(MemoryRegion, 1);
> MemoryRegion *envm_data = g_new(MemoryRegion, 1);
> MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
> char *plic_hart_config;
> @@ -277,6 +279,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
> memmap[MICROCHIP_PFSOC_L2LIM].base,
> l2lim_mem);
>
> + /*
> + * HSS decompresses into the L2 zero-device window and executes there.
> + * Model it as RAM because QEMU does not model the backing L2 cache.
> + */
> + memory_region_init_ram(l2zero_mem, NULL, "microchip.pfsoc.l2zero",
> + memmap[MICROCHIP_PFSOC_L2ZERO].size,
> + &error_fatal);
> + memory_region_add_subregion(system_memory,
> + memmap[MICROCHIP_PFSOC_L2ZERO].base,
> + l2zero_mem);
> +
> /* create PLIC hart topology configuration string */
> plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-07-27 5:24 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 15:18 [PATCH 00/26] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-07-23 15:18 ` [PATCH 01/26] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-07-27 5:23 ` Chao Liu
2026-07-23 15:18 ` [PATCH 02/26] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-07-27 5:24 ` Chao Liu [this message]
2026-07-23 15:18 ` [PATCH 03/26] hw/misc: pfsoc: Support PolarFire SoC DDR training with newer version HSS Bin Meng
2026-07-23 15:18 ` [PATCH 04/26] hw/misc: pfsoc: Model L2 cache controller registers Bin Meng
2026-07-23 15:18 ` [PATCH 05/26] hw/riscv: pfsoc: Couple L2CC to L2-LIM Bin Meng
2026-07-27 5:30 ` Chao Liu
2026-07-23 15:18 ` [PATCH 06/26] tests/qtest: Add PolarFire SoC L2CC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 15/26] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-07-23 15:18 ` [PATCH 16/26] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-07-23 15:28 ` Conor Dooley
2026-07-23 15:55 ` Bin Meng
2026-07-23 15:58 ` Conor Dooley
2026-07-23 16:07 ` Bin Meng
2026-07-23 15:18 ` [PATCH 17/26] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-07-27 5:31 ` Chao Liu
2026-07-23 15:18 ` [PATCH 18/26] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 19/26] hw/misc: pfsoc: Honor PolarFire service notification requests Bin Meng
2026-07-27 5:32 ` Chao Liu
2026-07-23 15:18 ` [PATCH 20/26] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-07-27 5:33 ` Chao Liu
2026-07-23 15:18 ` [PATCH 21/26] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-07-27 5:33 ` Chao Liu
2026-07-23 15:18 ` [PATCH 22/26] hw/riscv: pfsoc: Fix Icicle Kit hart count at five Bin Meng
2026-07-27 5:37 ` Chao Liu
2026-07-23 15:18 ` [PATCH 23/26] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-07-23 15:18 ` [PATCH 24/26] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-07-23 15:18 ` [PATCH 25/26] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-07-27 5:38 ` Chao Liu
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