From: Chao Liu <chao.liu@processmission.com>
To: Bin Meng <bin.meng@processmission.com>
Cc: QEMU <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Conor Dooley <conor@kernel.org>,
Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,
Sebastian Huber <sebastian.huber@embedded-brains.de>,
Weiwei Li <liwei1518@gmail.com>,
qemu-riscv@nongnu.org
Subject: Re: [PATCH 22/26] hw/riscv: pfsoc: Fix Icicle Kit hart count at five
Date: Mon, 27 Jul 2026 13:37:26 +0800 [thread overview]
Message-ID: <ambuj94hAZZur6F3@ChaodeMacBook-Pro.local> (raw)
In-Reply-To: <20260723151853.2143177-23-bin.meng@processmission.com>
On Thu, Jul 23, 2026 at 11:18:49PM +0800, Bin Meng wrote:
> The Icicle Kit always contains one E51 management hart and four U54
> application harts. The model currently accepts two to five harts and
> defaults to two, allowing configurations that cannot match the board.
>
> Set the minimum and default CPU counts to the five-hart maximum.
> Update the documentation to state that other hart counts are rejected.
>
> Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
Thanks,
Chao
> ---
>
> docs/system/riscv/microchip-icicle-kit.rst | 1 +
> hw/riscv/microchip_pfsoc.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst
> index 3db2b3c7e3..38352cc62b 100644
> --- a/docs/system/riscv/microchip-icicle-kit.rst
> +++ b/docs/system/riscv/microchip-icicle-kit.rst
> @@ -27,6 +27,7 @@ The ``microchip-icicle-kit`` machine supports the following devices:
> * 1 SDHC storage controller
>
> The machine has a fixed 2 GiB of RAM. Other memory sizes are rejected.
> +The machine always exposes all five harts. Other CPU counts are rejected.
>
> Boot options
> ------------
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index b604f7008b..1562423930 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -765,8 +765,8 @@ static void microchip_icicle_kit_machine_class_init(ObjectClass *oc,
> mc->init = microchip_icicle_kit_machine_init;
> mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
> MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
> - mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
> - mc->default_cpus = mc->min_cpus;
> + mc->min_cpus = mc->max_cpus;
> + mc->default_cpus = mc->max_cpus;
> mc->default_ram_id = "microchip.icicle.kit.ram";
> mc->auto_create_sdcard = true;
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-07-27 5:38 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-23 15:18 [PATCH 00/26] hw/riscv: Restore Microchip PolarFire SoC Icicle Kit firmware boot Bin Meng
2026-07-23 15:18 ` [PATCH 01/26] hw/riscv: pfsoc: Correct the L2LIM maximum mapped size Bin Meng
2026-07-27 5:23 ` Chao Liu
2026-07-23 15:18 ` [PATCH 02/26] hw/riscv: pfsoc: Map the L2 zero device window Bin Meng
2026-07-27 5:24 ` Chao Liu
2026-07-23 15:18 ` [PATCH 03/26] hw/misc: pfsoc: Support PolarFire SoC DDR training with newer version HSS Bin Meng
2026-07-23 15:18 ` [PATCH 04/26] hw/misc: pfsoc: Model L2 cache controller registers Bin Meng
2026-07-23 15:18 ` [PATCH 05/26] hw/riscv: pfsoc: Couple L2CC to L2-LIM Bin Meng
2026-07-27 5:30 ` Chao Liu
2026-07-23 15:18 ` [PATCH 06/26] tests/qtest: Add PolarFire SoC L2CC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 15/26] hw/misc: pfsoc: Model PolarFire SoC serial number service Bin Meng
2026-07-23 15:18 ` [PATCH 16/26] hw/rtc: Add PolarFire SoC RTC model Bin Meng
2026-07-23 15:28 ` Conor Dooley
2026-07-23 15:55 ` Bin Meng
2026-07-23 15:58 ` Conor Dooley
2026-07-23 16:07 ` Bin Meng
2026-07-23 15:18 ` [PATCH 17/26] hw/riscv: pfsoc: Add PolarFire SoC RTC to Icicle Kit Bin Meng
2026-07-27 5:31 ` Chao Liu
2026-07-23 15:18 ` [PATCH 18/26] tests/qtest: Add PolarFire SoC RTC coverage Bin Meng
2026-07-23 15:18 ` [PATCH 19/26] hw/misc: pfsoc: Honor PolarFire service notification requests Bin Meng
2026-07-27 5:32 ` Chao Liu
2026-07-23 15:18 ` [PATCH 20/26] hw/riscv: pfsoc: Correct PolarFire SoC DDR aliases Bin Meng
2026-07-27 5:33 ` Chao Liu
2026-07-23 15:18 ` [PATCH 21/26] hw/riscv: pfsoc: Fix Icicle Kit RAM size at 2 GiB Bin Meng
2026-07-27 5:33 ` Chao Liu
2026-07-23 15:18 ` [PATCH 22/26] hw/riscv: pfsoc: Fix Icicle Kit hart count at five Bin Meng
2026-07-27 5:37 ` Chao Liu [this message]
2026-07-23 15:18 ` [PATCH 23/26] docs/system/riscv: Document Icicle Kit HSS boot Bin Meng
2026-07-23 15:18 ` [PATCH 24/26] docs/system/riscv: pfsoc: Document CLINT topology for direct Linux boot Bin Meng
2026-07-23 15:18 ` [PATCH 25/26] tests/functional/riscv64: Add Icicle Kit firmware boot test Bin Meng
2026-07-27 5:38 ` Chao Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ambuj94hAZZur6F3@ChaodeMacBook-Pro.local \
--to=chao.liu@processmission.com \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@processmission.com \
--cc=conor@kernel.org \
--cc=daniel.barboza@oss.qualcomm.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=pierrick.bouvier@oss.qualcomm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sebastian.huber@embedded-brains.de \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox