* [PATCH 01/26] drm/amd/display: Check NULL before accessing
[not found] <20251120181527.317107-1-alex.hung@amd.com>
@ 2025-11-20 18:02 ` Alex Hung
2025-11-20 18:03 ` [PATCH 10/26] drm/amd/display: Don't change brightness for disabled connectors Alex Hung
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:02 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, Mario Limonciello, Alex Deucher, stable
[WHAT]
IGT kms_cursor_legacy's long-nonblocking-modeset-vs-cursor-atomic
fails with NULL pointer dereference. This can be reproduced with
both an eDP panel and a DP monitors connected.
BUG: kernel NULL pointer dereference, address: 0000000000000000
#PF: supervisor read access in kernel mode
#PF: error_code(0x0000) - not-present page
PGD 0 P4D 0
Oops: Oops: 0000 [#1] SMP NOPTI
CPU: 13 UID: 0 PID: 2960 Comm: kms_cursor_lega Not tainted
6.16.0-99-custom #8 PREEMPT(voluntary)
Hardware name: AMD ........
RIP: 0010:dc_stream_get_scanoutpos+0x34/0x130 [amdgpu]
Code: 57 4d 89 c7 41 56 49 89 ce 41 55 49 89 d5 41 54 49
89 fc 53 48 83 ec 18 48 8b 87 a0 64 00 00 48 89 75 d0 48 c7 c6 e0 41 30
c2 <48> 8b 38 48 8b 9f 68 06 00 00 e8 8d d7 fd ff 31 c0 48 81 c3 e0 02
RSP: 0018:ffffd0f3c2bd7608 EFLAGS: 00010292
RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffd0f3c2bd7668
RDX: ffffd0f3c2bd7664 RSI: ffffffffc23041e0 RDI: ffff8b32494b8000
RBP: ffffd0f3c2bd7648 R08: ffffd0f3c2bd766c R09: ffffd0f3c2bd7760
R10: ffffd0f3c2bd7820 R11: 0000000000000000 R12: ffff8b32494b8000
R13: ffffd0f3c2bd7664 R14: ffffd0f3c2bd7668 R15: ffffd0f3c2bd766c
FS: 000071f631b68700(0000) GS:ffff8b399f114000(0000)
knlGS:0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
CR2: 0000000000000000 CR3: 00000001b8105000 CR4: 0000000000f50ef0
PKRU: 55555554
Call Trace:
<TASK>
dm_crtc_get_scanoutpos+0xd7/0x180 [amdgpu]
amdgpu_display_get_crtc_scanoutpos+0x86/0x1c0 [amdgpu]
? __pfx_amdgpu_crtc_get_scanout_position+0x10/0x10[amdgpu]
amdgpu_crtc_get_scanout_position+0x27/0x50 [amdgpu]
drm_crtc_vblank_helper_get_vblank_timestamp_internal+0xf7/0x400
drm_crtc_vblank_helper_get_vblank_timestamp+0x1c/0x30
drm_crtc_get_last_vbltimestamp+0x55/0x90
drm_crtc_next_vblank_start+0x45/0xa0
drm_atomic_helper_wait_for_fences+0x81/0x1f0
...
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 6d309c320253..129cd5f84983 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -737,9 +737,14 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
{
uint8_t i;
bool ret = false;
- struct dc *dc = stream->ctx->dc;
- struct resource_context *res_ctx =
- &dc->current_state->res_ctx;
+ struct dc *dc;
+ struct resource_context *res_ctx;
+
+ if (!stream->ctx)
+ return false;
+
+ dc = stream->ctx->dc;
+ res_ctx = &dc->current_state->res_ctx;
dc_exit_ips_for_hw_access(dc);
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 10/26] drm/amd/display: Don't change brightness for disabled connectors
[not found] <20251120181527.317107-1-alex.hung@amd.com>
2025-11-20 18:02 ` [PATCH 01/26] drm/amd/display: Check NULL before accessing Alex Hung
@ 2025-11-20 18:03 ` Alex Hung
2025-11-20 18:03 ` [PATCH 15/26] drm/amd/display: Increase EDID read retries Alex Hung
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:03 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, Mario Limonciello (AMD), Mario Limonciello,
Alex Deucher, stable, Ray Wu
From: "Mario Limonciello (AMD)" <superm1@kernel.org>
[WHY]
When a laptop lid is closed the connector is disabled but userspace
can still try to change brightness. This doesn't work because the
panel is turned off. It will eventually time out, but there is a lot
of stutter along the way.
[How]
Iterate all connectors to check whether the matching one for the backlight
index is enabled.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4675
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Ray Wu <ray.wu@amd.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8a0555365719..424020c0756d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5108,6 +5108,21 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
struct dc_link *link;
u32 brightness;
bool rc, reallow_idle = false;
+ struct drm_connector *connector;
+
+ list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) {
+ struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
+
+ if (aconnector->bl_idx != bl_idx)
+ continue;
+
+ /* if connector is off, save the brightness for next time it's on */
+ if (!aconnector->base.encoder) {
+ dm->brightness[bl_idx] = user_brightness;
+ dm->actual_brightness[bl_idx] = 0;
+ return;
+ }
+ }
amdgpu_dm_update_backlight_caps(dm, bl_idx);
caps = &dm->backlight_caps[bl_idx];
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 15/26] drm/amd/display: Increase EDID read retries
[not found] <20251120181527.317107-1-alex.hung@amd.com>
2025-11-20 18:02 ` [PATCH 01/26] drm/amd/display: Check NULL before accessing Alex Hung
2025-11-20 18:03 ` [PATCH 10/26] drm/amd/display: Don't change brightness for disabled connectors Alex Hung
@ 2025-11-20 18:03 ` Alex Hung
2025-11-20 18:03 ` [PATCH 19/26] drm/amd/display: Add cursor offload abort to the new HWSS path Alex Hung
2025-11-20 18:03 ` [PATCH 23/26] drm/amd/display: Correct DSC padding accounting Alex Hung
4 siblings, 0 replies; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:03 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, Mario Limonciello (AMD), Mario Limonciello,
Alex Deucher, stable
From: "Mario Limonciello (AMD)" <superm1@kernel.org>
[WHY]
When monitor is still booting EDID read can fail while DPCD read
is successful. In this case no EDID data will be returned, and this
could happen for a while.
[HOW]
Increase number of attempts to read EDID in dm_helpers_read_local_edid()
to 25.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4672
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
index 582a1c04f035..e5e993d3ef74 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
@@ -1006,8 +1006,8 @@ enum dc_edid_status dm_helpers_read_local_edid(
struct amdgpu_dm_connector *aconnector = link->priv;
struct drm_connector *connector = &aconnector->base;
struct i2c_adapter *ddc;
- int retry = 3;
- enum dc_edid_status edid_status;
+ int retry = 25;
+ enum dc_edid_status edid_status = EDID_NO_RESPONSE;
const struct drm_edid *drm_edid;
const struct edid *edid;
@@ -1037,7 +1037,7 @@ enum dc_edid_status dm_helpers_read_local_edid(
}
if (!drm_edid)
- return EDID_NO_RESPONSE;
+ continue;
edid = drm_edid_raw(drm_edid); // FIXME: Get rid of drm_edid_raw()
if (!edid ||
@@ -1055,7 +1055,7 @@ enum dc_edid_status dm_helpers_read_local_edid(
&sink->dc_edid,
&sink->edid_caps);
- } while (edid_status == EDID_BAD_CHECKSUM && --retry > 0);
+ } while ((edid_status == EDID_BAD_CHECKSUM || edid_status == EDID_NO_RESPONSE) && --retry > 0);
if (edid_status != EDID_OK)
DRM_ERROR("EDID err: %d, on connector: %s",
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 19/26] drm/amd/display: Add cursor offload abort to the new HWSS path
[not found] <20251120181527.317107-1-alex.hung@amd.com>
` (2 preceding siblings ...)
2025-11-20 18:03 ` [PATCH 15/26] drm/amd/display: Increase EDID read retries Alex Hung
@ 2025-11-20 18:03 ` Alex Hung
2025-11-20 18:03 ` [PATCH 23/26] drm/amd/display: Correct DSC padding accounting Alex Hung
4 siblings, 0 replies; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:03 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, Nicholas Kazlauskas, Mario Limonciello, Alex Deucher,
stable, Dillon Varone
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[HOW]
If cursor attributes or position are passed into DC via a stream update
and we take the newer HWSS paths then it's possible that the update
races with cursor offloading if it's enabled.
This can cause the cursor to remain on the screen if no further updates
come in if it results in HW cursor support being disabled.
[HOW]
Add the abort into the HWSS path so that cursor offloading doesn't
attempt to reprogram the cursor with outdated params.
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 24 +++++++++++++++++++
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 ++
.../drm/amd/display/dc/hwss/hw_sequencer.h | 13 ++++++++++
3 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index a01cb2897aab..e2763b60482a 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1293,6 +1293,9 @@ void hwss_execute_sequence(struct dc *dc,
case HUBP_MEM_PROGRAM_VIEWPORT:
hwss_hubp_mem_program_viewport(params);
break;
+ case ABORT_CURSOR_OFFLOAD_UPDATE:
+ hwss_abort_cursor_offload_update(params);
+ break;
case SET_CURSOR_ATTRIBUTE:
hwss_set_cursor_attribute(params);
break;
@@ -3076,6 +3079,15 @@ void hwss_hubp_mem_program_viewport(union block_sequence_params *params)
hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);
}
+void hwss_abort_cursor_offload_update(union block_sequence_params *params)
+{
+ struct dc *dc = params->abort_cursor_offload_update_params.dc;
+ struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;
+
+ if (dc && dc->hwss.abort_cursor_offload_update)
+ dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
+}
+
void hwss_set_cursor_attribute(union block_sequence_params *params)
{
struct dc *dc = params->set_cursor_attribute_params.dc;
@@ -3934,6 +3946,18 @@ void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,
}
}
+void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx)
+{
+ if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+ seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;
+ (*seq_state->num_steps)++;
+ }
+}
+
void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
struct dc *dc,
struct pipe_ctx *pipe_ctx)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index f02edc9371b0..01b0f72b6623 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -3675,6 +3675,8 @@ void dcn401_update_dchubp_dpp_sequence(struct dc *dc,
pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
+ hwss_add_abort_cursor_offload_update(seq_state, dc, pipe_ctx);
+
hwss_add_set_cursor_attribute(seq_state, dc, pipe_ctx);
/* Step 15: Cursor position setup */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index 3772b4aa11cc..8ed9eea40c56 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -696,6 +696,11 @@ struct hubp_program_mcache_id_and_split_coordinate_params {
struct mcache_regs_struct *mcache_regs;
};
+struct abort_cursor_offload_update_params {
+ struct dc *dc;
+ struct pipe_ctx *pipe_ctx;
+};
+
struct set_cursor_attribute_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
@@ -842,6 +847,7 @@ union block_sequence_params {
struct mpc_insert_plane_params mpc_insert_plane_params;
struct dpp_set_scaler_params dpp_set_scaler_params;
struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params;
+ struct abort_cursor_offload_update_params abort_cursor_offload_update_params;
struct set_cursor_attribute_params set_cursor_attribute_params;
struct set_cursor_position_params set_cursor_position_params;
struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params;
@@ -960,6 +966,7 @@ enum block_sequence_func {
MPC_INSERT_PLANE,
DPP_SET_SCALER,
HUBP_MEM_PROGRAM_VIEWPORT,
+ ABORT_CURSOR_OFFLOAD_UPDATE,
SET_CURSOR_ATTRIBUTE,
SET_CURSOR_POSITION,
SET_CURSOR_SDR_WHITE_LEVEL,
@@ -1565,6 +1572,8 @@ void hwss_dpp_set_scaler(union block_sequence_params *params);
void hwss_hubp_mem_program_viewport(union block_sequence_params *params);
+void hwss_abort_cursor_offload_update(union block_sequence_params *params);
+
void hwss_set_cursor_attribute(union block_sequence_params *params);
void hwss_set_cursor_position(union block_sequence_params *params);
@@ -1961,6 +1970,10 @@ void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,
const struct rect *viewport,
const struct rect *viewport_c);
+void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx);
+
void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
struct dc *dc,
struct pipe_ctx *pipe_ctx);
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 23/26] drm/amd/display: Correct DSC padding accounting
[not found] <20251120181527.317107-1-alex.hung@amd.com>
` (3 preceding siblings ...)
2025-11-20 18:03 ` [PATCH 19/26] drm/amd/display: Add cursor offload abort to the new HWSS path Alex Hung
@ 2025-11-20 18:03 ` Alex Hung
2025-11-20 18:33 ` Mario Limonciello
4 siblings, 1 reply; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:03 UTC (permalink / raw)
To: amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Alex Hung, Relja Vojvodic, Mario Limonciello, Alex Deucher,
stable, Chris Park, Wenjing Liu
From: Relja Vojvodic <rvojvodi@amd.com>
[WHY]
- After the addition of all OVT patches, DSC padding was being accounted
for multiple times, effectively doubling the padding
- This caused compliance failures or corruption
[HOW]
- Add padding to DSC pic width when required by HW, and do not re-add
when calculating reg values
- Do not add padding when computing PPS values, and instead track padding
separately to add when calculating slice width values
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Chris Park <chris.park@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 ++-
.../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 6 +++---
5 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 4ee6ed610de0..3e239124c17d 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
- dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
+ dsc_cfg.dsc_padding = 0;
dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index bf19ba65d09a..b213a2ac827a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1061,7 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
- dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
+ dsc_cfg.dsc_padding = 0;
if (should_use_dto_dscclk)
dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 7aa0f452e8f7..cb2dfd34b5e2 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
- dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
+ dsc_cfg.dsc_padding = 0;
dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 1b1ce3839922..77e049917c4d 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -841,7 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
- dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
+ dsc_cfg.dsc_padding = 0;
if (should_use_dto_dscclk)
dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
@@ -857,6 +857,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
}
dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
dsc_cfg.pic_width *= opp_cnt;
+ dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index 6679c1a14f2f..8d10aac9c510 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1660,8 +1660,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
continue;
- dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
- + stream->timing.h_border_right) / opp_cnt;
+ dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding
+ + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
+ stream->timing.v_border_bottom;
dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
@@ -1669,7 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
- dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
+ dsc_cfg.dsc_padding = 0;
if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
return false;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 23/26] drm/amd/display: Correct DSC padding accounting
2025-11-20 18:03 ` [PATCH 23/26] drm/amd/display: Correct DSC padding accounting Alex Hung
@ 2025-11-20 18:33 ` Mario Limonciello
2025-11-20 18:35 ` Alex Hung
0 siblings, 1 reply; 7+ messages in thread
From: Mario Limonciello @ 2025-11-20 18:33 UTC (permalink / raw)
To: Alex Hung, amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Relja Vojvodic, Alex Deucher, stable, Chris Park, Wenjing Liu
On 11/20/2025 12:03 PM, Alex Hung wrote:
> From: Relja Vojvodic <rvojvodi@amd.com>
>
> [WHY]
> - After the addition of all OVT patches, DSC padding was being accounted
> for multiple times, effectively doubling the padding
Can you double check when the OVT patches were submitted and if they
were CC @stable? If not; I think the stable tag should be dropped on
this patch.
> - This caused compliance failures or corruption
>
> [HOW]
> - Add padding to DSC pic width when required by HW, and do not re-add
> when calculating reg values
> - Do not add padding when computing PPS values, and instead track padding
> separately to add when calculating slice width values
>
> Cc: Mario Limonciello <mario.limonciello@amd.com>
> Cc: Alex Deucher <alexander.deucher@amd.com>
> Cc: stable@vger.kernel.org
> Reviewed-by: Chris Park <chris.park@amd.com>
> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
> Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
> Signed-off-by: Alex Hung <alex.hung@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
> drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
> drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
> drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 ++-
> .../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 6 +++---
> 5 files changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
> index 4ee6ed610de0..3e239124c17d 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
> @@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
> + dsc_cfg.dsc_padding = 0;
>
> dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
> dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
> index bf19ba65d09a..b213a2ac827a 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
> @@ -1061,7 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
> + dsc_cfg.dsc_padding = 0;
>
> if (should_use_dto_dscclk)
> dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> index 7aa0f452e8f7..cb2dfd34b5e2 100644
> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
> @@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
> + dsc_cfg.dsc_padding = 0;
>
> dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
> dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> index 1b1ce3839922..77e049917c4d 100644
> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
> @@ -841,7 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
> + dsc_cfg.dsc_padding = 0;
>
> if (should_use_dto_dscclk)
> dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h);
> @@ -857,6 +857,7 @@ void link_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable)
> }
> dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
> dsc_cfg.pic_width *= opp_cnt;
> + dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
>
> optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ? OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
>
> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
> index 6679c1a14f2f..8d10aac9c510 100644
> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
> @@ -1660,8 +1660,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
> if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
> continue;
>
> - dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
> - + stream->timing.h_border_right) / opp_cnt;
> + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx->dsc_padding_params.dsc_hactive_padding
> + + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt;
> dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
> + stream->timing.v_border_bottom;
> dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
> @@ -1669,7 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
> dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
> - dsc_cfg.dsc_padding = pipe_ctx->dsc_padding_params.dsc_hactive_padding;
> + dsc_cfg.dsc_padding = 0;
>
> if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
> return false;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 23/26] drm/amd/display: Correct DSC padding accounting
2025-11-20 18:33 ` Mario Limonciello
@ 2025-11-20 18:35 ` Alex Hung
0 siblings, 0 replies; 7+ messages in thread
From: Alex Hung @ 2025-11-20 18:35 UTC (permalink / raw)
To: Mario Limonciello, amd-gfx
Cc: Harry Wentland, Leo Li, Aurabindo Pillai, Roman Li, Wayne Lin,
Tom Chung, Fangzhi Zuo, Dan Wheeler, Ray Wu, Ivan Lipski,
Relja Vojvodic, Alex Deucher, stable, Chris Park, Wenjing Liu
On 11/20/25 11:33, Mario Limonciello wrote:
>
>
> On 11/20/2025 12:03 PM, Alex Hung wrote:
>> From: Relja Vojvodic <rvojvodi@amd.com>
>>
>> [WHY]
>> - After the addition of all OVT patches, DSC padding was being accounted
>> for multiple times, effectively doubling the padding
>
> Can you double check when the OVT patches were submitted and if they
> were CC @stable? If not; I think the stable tag should be dropped on
> this patch.
Thanks. I will remove the Cc stable.
>
>> - This caused compliance failures or corruption
>>
>> [HOW]
>> - Add padding to DSC pic width when required by HW, and do not re-add
>> when calculating reg values
>> - Do not add padding when computing PPS values, and instead track padding
>> separately to add when calculating slice width values
>>
>> Cc: Mario Limonciello <mario.limonciello@amd.com>
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Cc: stable@vger.kernel.org
>> Reviewed-by: Chris Park <chris.park@amd.com>
>> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
>> Signed-off-by: Relja Vojvodic <rvojvodi@amd.com>
>> Signed-off-by: Alex Hung <alex.hung@amd.com>
>> ---
>> drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +-
>> drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 +-
>> drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 2 +-
>> drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 3 ++-
>> .../gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 6 +++---
>> 5 files changed, 8 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
>> b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
>> index 4ee6ed610de0..3e239124c17d 100644
>> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
>> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
>> @@ -108,7 +108,7 @@ static void update_dsc_on_stream(struct pipe_ctx
>> *pipe_ctx, bool enable)
>> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
>> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
>> - dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> + dsc_cfg.dsc_padding = 0;
>> dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
>> dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
>> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
>> b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
>> index bf19ba65d09a..b213a2ac827a 100644
>> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
>> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
>> @@ -1061,7 +1061,7 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx
>> *pipe_ctx, bool enable)
>> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
>> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
>> - dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> + dsc_cfg.dsc_padding = 0;
>> if (should_use_dto_dscclk)
>> dccg->funcs->set_dto_dscclk(dccg, dsc->inst,
>> dsc_cfg.dc_dsc_cfg.num_slices_h);
>> diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
>> b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
>> index 7aa0f452e8f7..cb2dfd34b5e2 100644
>> --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
>> +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
>> @@ -364,7 +364,7 @@ static void update_dsc_on_stream(struct pipe_ctx
>> *pipe_ctx, bool enable)
>> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
>> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
>> - dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> + dsc_cfg.dsc_padding = 0;
>> dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
>> dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
>> diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/
>> drivers/gpu/drm/amd/display/dc/link/link_dpms.c
>> index 1b1ce3839922..77e049917c4d 100644
>> --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
>> +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
>> @@ -841,7 +841,7 @@ void link_set_dsc_on_stream(struct pipe_ctx
>> *pipe_ctx, bool enable)
>> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>> ASSERT(dsc_cfg.dc_dsc_cfg.num_slices_h % opp_cnt == 0);
>> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
>> - dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> + dsc_cfg.dsc_padding = 0;
>> if (should_use_dto_dscclk)
>> dccg->funcs->set_dto_dscclk(dccg, dsc->inst,
>> dsc_cfg.dc_dsc_cfg.num_slices_h);
>> @@ -857,6 +857,7 @@ void link_set_dsc_on_stream(struct pipe_ctx
>> *pipe_ctx, bool enable)
>> }
>> dsc_cfg.dc_dsc_cfg.num_slices_h *= opp_cnt;
>> dsc_cfg.pic_width *= opp_cnt;
>> + dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> optc_dsc_mode = dsc_optc_cfg.is_pixel_format_444 ?
>> OPTC_DSC_ENABLED_444 : OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED;
>> diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/
>> dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/
>> dcn20_resource.c
>> index 6679c1a14f2f..8d10aac9c510 100644
>> --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
>> @@ -1660,8 +1660,8 @@ bool dcn20_validate_dsc(struct dc *dc, struct
>> dc_state *new_ctx)
>> if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream
>> || !stream->timing.flags.DSC)
>> continue;
>> - dsc_cfg.pic_width = (stream->timing.h_addressable + stream-
>> >timing.h_border_left
>> - + stream->timing.h_border_right) / opp_cnt;
>> + dsc_cfg.pic_width = (stream->timing.h_addressable + pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding
>> + + stream->timing.h_border_left + stream-
>> >timing.h_border_right) / opp_cnt;
>> dsc_cfg.pic_height = stream->timing.v_addressable + stream-
>> >timing.v_border_top
>> + stream->timing.v_border_bottom;
>> dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
>> @@ -1669,7 +1669,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct
>> dc_state *new_ctx)
>> dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
>> dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
>> dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
>> - dsc_cfg.dsc_padding = pipe_ctx-
>> >dsc_padding_params.dsc_hactive_padding;
>> + dsc_cfg.dsc_padding = 0;
>> if (!pipe_ctx->stream_res.dsc->funcs-
>> >dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
>> return false;
>
^ permalink raw reply [flat|nested] 7+ messages in thread