From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Wenjing Liu <wenjing.liu@amd.com>, Alvin Lee <alvin.lee2@amd.com>,
Mario Limonciello <mario.limonciello@amd.com>,
"Alex Deucher" <alexander.deucher@amd.com>,
<stable@vger.kernel.org>, Wayne Lin <Wayne.Lin@amd.com>
Subject: [PATCH 64/74] drm/amd/display: Report QoS latency bounds and request
Date: Wed, 11 Nov 2026 09:29:10 +0800 [thread overview]
Message-ID: <20261111014100.3596072-65-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com>
From: Wenjing Liu <wenjing.liu@amd.com>
[Why]
The requested QoS values returned by the QoS query read zero. The
latency upper bounds and the calculated average bandwidth were never
filled, and clearing the memory bandwidth override zeroed the
bandwidth request instead of restoring the request of the committed
mode.
[How]
Fill the avg and max nominal latency upper bounds from the DML
qos_bound, converting from microseconds to nanoseconds. Fill the
average active bandwidth from the DML informative qos output,
converting from MBps to KBps. Report these from the committed state
in dc_get_qos_info(). Restore the bandwidth lower bounds from the
committed state when the override is cleared.
Cc: Alvin Lee <alvin.lee2@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
.../drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c | 7 +++++--
drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +++++---
.../dml21_wrapper/dml21_translation_helper.c | 11 +++++++++++
3 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
index c5d56757eafd..f801f3337e5d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn60/dcn60_clk_mgr.c
@@ -1619,8 +1619,11 @@ static unsigned int dcn60_override_memory_bandwidth_request(
memcpy(&new_clocks, &clk_mgr_base->clks, sizeof(struct dc_clocks));
if (bw_kbps == 0) {
- new_clocks.utm_nominal_bandwidth_lb_KBps = 0;
- new_clocks.utm_urgent_bandwidth_lb_KBps = 0;
+ /* Clearing the override restores the request of the committed mode. */
+ new_clocks.utm_nominal_bandwidth_lb_KBps =
+ dc->current_state->bw_ctx.bw.dcn.clk.utm_nominal_bandwidth_lb_KBps;
+ new_clocks.utm_urgent_bandwidth_lb_KBps =
+ dc->current_state->bw_ctx.bw.dcn.clk.utm_urgent_bandwidth_lb_KBps;
} else {
max_bw_kbps = dcn60_get_max_active_utm_bandwidth_kbps(clk_mgr_base);
capped_bw_kbps = (bw_kbps > max_bw_kbps) ? max_bw_kbps : bw_kbps;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 656a941b1ba0..8a02bcbb9649 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -8105,12 +8105,14 @@ bool dc_get_qos_info(struct dc *dc, struct dc_qos_info *info)
if (dc->clk_mgr && dc->clk_mgr->funcs->get_requested_memory_qos) {
dc->clk_mgr->funcs->get_requested_memory_qos(dc->clk_mgr, &requested);
info->qos_bandwidth_lb_in_mbps = requested.bandwidth_lb_in_mbps;
- info->calculated_avg_bw_in_mbps = requested.calculated_avg_bw_in_mbps;
- info->qos_max_latency_ub_in_ns = requested.max_latency_ub_in_ns;
- info->qos_avg_latency_ub_in_ns = requested.avg_latency_ub_in_ns;
info->qos_max_bw_budget_in_mbps = requested.max_bw_budget_in_mbps;
}
+ /* The clk_mgr does not track these, so report the ones of the committed state. */
+ info->calculated_avg_bw_in_mbps = clk->required_avg_active_bandwidth_KBps / 1000;
+ info->qos_max_latency_ub_in_ns = clk->utm_nominal_max_latency_ub_ns;
+ info->qos_avg_latency_ub_in_ns = clk->utm_nominal_avg_latency_ub_ns;
+
return true;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
index a7d6ff59870a..31292a70a84e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_wrapper/dml21_wrapper/dml21_translation_helper.c
@@ -1036,6 +1036,14 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
context->bw_ctx.bw.dcn.clk.utm_latency_ub_index = 0; /* TODO - derive from qos model */
context->bw_ctx.bw.dcn.clk.utm_nominal_bandwidth_lb_KBps = (unsigned int) in_ctx->v21.mode_programming.programming->qos_bound.bandwidth_lb.dcn5.non_urgent_bandwidth_kbps;
context->bw_ctx.bw.dcn.clk.utm_urgent_bandwidth_lb_KBps = (unsigned int) in_ctx->v21.mode_programming.programming->qos_bound.bandwidth_lb.dcn5.urgent_bandwidth_kbps;
+ /* DML latency upper bounds are in microseconds, the dc clocks fields are in nanoseconds. */
+ context->bw_ctx.bw.dcn.clk.utm_nominal_avg_latency_ub_ns = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->qos_bound.latency_ub.dcn5.avg_req_latency_non_urg * 1000);
+ context->bw_ctx.bw.dcn.clk.utm_nominal_max_latency_ub_ns = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->qos_bound.latency_ub.dcn5.max_req_latency_non_urg * 1000);
+ /* The average bandwidth DML calculated for the active state, converted from MBps to KBps. */
+ context->bw_ctx.bw.dcn.clk.required_avg_active_bandwidth_KBps = (unsigned int)(
+ in_ctx->v21.mode_programming.programming->informative.qos.avg_bw_required.sys_active.sdp_bw_mbps * 1000);
context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
@@ -1177,6 +1185,9 @@ void dml21_init_min_clocks_for_dc_state(struct dml2_context *in_ctx, struct dc_s
min_clocks->utm_latency_ub_index = 0; /* TODO - derive from qos model */
min_clocks->utm_nominal_bandwidth_lb_KBps = 0;
min_clocks->utm_urgent_bandwidth_lb_KBps = 0;
+ min_clocks->utm_nominal_max_latency_ub_ns = 0;
+ min_clocks->utm_nominal_avg_latency_ub_ns = 0;
+ min_clocks->required_avg_active_bandwidth_KBps = 0;
min_clocks->stutter_efficiency.base_efficiency = 1;
min_clocks->stutter_efficiency.low_power_efficiency = 1;
min_clocks->stutter_efficiency.z8_stutter_efficiency = 1;
--
2.43.0
next prev parent reply other threads:[~2026-11-11 1:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20261111014100.3596072-1-Wayne.Lin@amd.com>
2026-11-11 1:29 ` [PATCH 58/74] drm/amd/display: Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs Wayne Lin
2026-11-11 1:29 ` [PATCH 61/74] drm/amd/display: Read DRAM channel width from SMU init table Wayne Lin
2026-11-11 1:29 ` [PATCH 62/74] drm/amd/display: Update DCN42B stutter latency to match DCN42 Wayne Lin
2026-11-11 1:29 ` Wayne Lin [this message]
2026-11-11 1:29 ` [PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks Wayne Lin
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