[PATCH 68/74] drm/amd/display: Seed boot clocks to avoid lowering pre-OS display clocks

[Wayne Lin <Wayne.Lin@amd.com>]

From: Jing Zhou <Jing.Zhou@amd.com>

[WHY]
USB4 DPIA HPD can arrive early in boot, before the first stream commit.
Its link detection runs prepare_phy_clocks(), which goes through
clk_mgr_exit_optimized_pwr_state() and clk_mgr_optimize_pwr_state()
and calls update_clocks(dc->current_state).

At that point both dc->current_state->bw_ctx.bw.dcn.clk and
clk_mgr->clks are still zero, because init_clocks() memsets them. On the
safe_to_lower path, dcn42_update_clocks() clamps the requested DPPCLK to
the 100MHz floor and programs it. This drops DPPCLK below what the
GOP-lit eDP pipe needs, and the panel flashes white.

[HOW]
1. In dcn42_init_clocks() and dcn42b_init_clocks(), seed clk_mgr->clks
   dispclk/dppclk from the boot snapshot(10kHz units, x10).
2. Add a DC core helper, sync_current_state_clocks_from_clk_mgr().
   After every hwss.init_hw() call (legacy_hardware_init, D0 entry in
   dc_set_power_state, and dc_reinitialize_hardware), it copies
   clk_mgr->clks into dc->current_state->bw_ctx.bw.dcn.clk for DCN.
   A later update_clocks() before the first commit then sees the real
   pre-OS clocks and does not lower them. Raising clocks is still
   allowed and does not cause a flash.

Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Cc: Charlene Liu <charlene.liu@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Jing Zhou <Jing.Zhou@amd.com>
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
---
 .../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c |  3 +++
 .../display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c   |  4 ++++
 drivers/gpu/drm/amd/display/dc/core/dc.c         | 16 +++++++++++++++-
 3 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index b1fbadd0d885..054eab1e0cb9 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -643,6 +643,9 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
 	DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz);
 	dcn42_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);
 
+	/* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */
+	clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10;
+	clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10;
 	clk_mgr_base->clks.ref_dtbclk_khz =  clk_mgr_base->boot_snapshot.dtbclk * 10;
 	clk_mgr_base->clks.dtbclk_en = clk_mgr_base->boot_snapshot.dtbclk > 59000;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
index 57291c10c917..5e8a65f1ee68 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42b/dcn42b_clk_mgr.c
@@ -251,6 +251,10 @@ DC_LOGGER_INIT(clk_mgr_base->ctx->logger);
 
 	DC_LOG_SMU("dp_dto_source_clock %d, dprefclk %d\n", clk_mgr_base->dp_dto_source_clock_in_khz, clk_mgr_base->dprefclk_khz);
 	dcn42b_dump_clk_registers(&clk_mgr_base->boot_snapshot, clk_mgr);
+
+	/* Snapshot is in 10kHz units; seed clks so update_clocks() does not lower the pre-OS clocks */
+	clk_mgr_base->clks.dispclk_khz = clk_mgr_base->boot_snapshot.dispclk * 10;
+	clk_mgr_base->clks.dppclk_khz = clk_mgr_base->boot_snapshot.dppclk * 10;
 }
 
 static struct clk_bw_params dcn42b_bw_params = {
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 8a02bcbb9649..463a3fc2d8c2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1728,12 +1728,25 @@ static void detect_edp_presence(struct dc *dc)
 	}
 }
 
+static void sync_current_state_clocks_from_clk_mgr(struct dc *dc)
+{
+	if (!dc->current_state || !dc->clk_mgr)
+		return;
+
+	if (!(dc->ctx->dce_version == DCN_VERSION_4_2 || dc->ctx->dce_version == DCN_VERSION_4_2B))
+		return;
+
+	dc->current_state->bw_ctx.bw.dcn.clk = dc->clk_mgr->clks;
+}
+
 void legacy_hardware_init(struct dc *dc)
 {
 
 	detect_edp_presence(dc);
-	if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW)
+	if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) {
 		dc->hwss.init_hw(dc);
+		sync_current_state_clocks_from_clk_mgr(dc);
+	}
 	dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0);
 }
 
@@ -6435,6 +6448,7 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state)
 		dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state);
 
 		dc->hwss.init_hw(dc);
+		sync_current_state_clocks_from_clk_mgr(dc);
 
 		invalidate_drr_adjust(dc);
 
-- 
2.43.0