[PATCH] serial: tegra: Change lower tolerance baud rate limit for tegra20 and tegra30

[PATCH] serial: tegra: Change lower tolerance baud rate limit for tegra20 and tegra30

[Patrik John]

commit b40de7469ef135161c80af0e8c462298cc5dac00 upstream.

The current implementation uses 0 as lower limit for the baud rate
tolerance for tegra20 and tegra30 chips which causes isses on UART
initialization as soon as baud rate clock is lower than required even
when within the standard UART tolerance of +/- 4%.

This fix aligns the implementation with the initial commit description
of +/- 4% tolerance for tegra chips other than tegra186 and tegra194.

Fixes: d781ec21bae6 ("serial: tegra: report clk rate errors")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Patrik John <patrik.john@u-blox.com>
Link: https://lore.kernel.org/r/sig.19614244f8.20211123132737.88341-1-patrik.john@u-blox.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Backport for 5.4-stable 

 drivers/tty/serial/serial-tegra.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 64f18bf1e694..74c21152367a 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -1494,7 +1494,7 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data = {
 	.fifo_mode_enable_status	= false,
 	.uart_max_port			= 5,
 	.max_dma_burst_bytes		= 4,
-	.error_tolerance_low_range	= 0,
+	.error_tolerance_low_range	= -4,
 	.error_tolerance_high_range	= 4,
 };
 
@@ -1505,7 +1505,7 @@ static struct tegra_uart_chip_data tegra30_uart_chip_data = {
 	.fifo_mode_enable_status	= false,
 	.uart_max_port			= 5,
 	.max_dma_burst_bytes		= 4,
-	.error_tolerance_low_range	= 0,
+	.error_tolerance_low_range	= -4,
 	.error_tolerance_high_range	= 4,
 };
 
-- 
2.25.1

Re: [PATCH] serial: tegra: Change lower tolerance baud rate limit for tegra20 and tegra30

[Greg Kroah-Hartman]

On Mon, Dec 06, 2021 at 06:14:57PM +0100, Patrik John wrote:
> commit b40de7469ef135161c80af0e8c462298cc5dac00 upstream.
> 
> The current implementation uses 0 as lower limit for the baud rate
> tolerance for tegra20 and tegra30 chips which causes isses on UART
> initialization as soon as baud rate clock is lower than required even
> when within the standard UART tolerance of +/- 4%.
> 
> This fix aligns the implementation with the initial commit description
> of +/- 4% tolerance for tegra chips other than tegra186 and tegra194.
> 
> Fixes: d781ec21bae6 ("serial: tegra: report clk rate errors")
> Cc: stable <stable@vger.kernel.org>
> Signed-off-by: Patrik John <patrik.john@u-blox.com>
> Link: https://lore.kernel.org/r/sig.19614244f8.20211123132737.88341-1-patrik.john@u-blox.com
> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
> Backport for 5.4-stable 

Now queued up, thanks.

greg k-h