* [PATCH 2/2] drm/xe: move DPT l2 flush to a more sensible place
2025-06-06 10:45 [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place Matthew Auld
@ 2025-06-06 10:45 ` Matthew Auld
2025-06-17 16:35 ` Ville Syrjälä
2025-06-18 18:59 ` Lucas De Marchi
2025-06-06 15:19 ` [PATCH 1/2] drm/xe: Move DSB " Matthew Auld
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Matthew Auld @ 2025-06-06 10:45 UTC (permalink / raw)
To: intel-xe; +Cc: Maarten Lankhorst, stable
Only need the flush for DPT host updates here. Normal GGTT updates don't
need special flush.
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: <stable@vger.kernel.org> # v6.12+
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 461ecdfdb742..b16a6e3ff4b4 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -165,6 +165,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
vma->dpt = dpt;
vma->node = dpt->ggtt_node[tile0->id];
+
+ /* Ensure DPT writes are flushed */
+ xe_device_l2_flush(xe);
return 0;
}
@@ -334,8 +337,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
if (ret)
goto err_unpin;
- /* Ensure DPT writes are flushed */
- xe_device_l2_flush(xe);
return vma;
err_unpin:
--
2.49.0
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] drm/xe: move DPT l2 flush to a more sensible place
2025-06-06 10:45 ` [PATCH 2/2] drm/xe: move DPT " Matthew Auld
@ 2025-06-17 16:35 ` Ville Syrjälä
2025-06-18 18:59 ` Lucas De Marchi
1 sibling, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2025-06-17 16:35 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst, stable
On Fri, Jun 06, 2025 at 11:45:48AM +0100, Matthew Auld wrote:
> Only need the flush for DPT host updates here. Normal GGTT updates don't
> need special flush.
>
> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> index 461ecdfdb742..b16a6e3ff4b4 100644
> --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
> +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
> @@ -165,6 +165,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>
> vma->dpt = dpt;
> vma->node = dpt->ggtt_node[tile0->id];
> +
> + /* Ensure DPT writes are flushed */
> + xe_device_l2_flush(xe);
> return 0;
> }
>
> @@ -334,8 +337,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
> if (ret)
> goto err_unpin;
>
> - /* Ensure DPT writes are flushed */
> - xe_device_l2_flush(xe);
> return vma;
>
> err_unpin:
> --
> 2.49.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] drm/xe: move DPT l2 flush to a more sensible place
2025-06-06 10:45 ` [PATCH 2/2] drm/xe: move DPT " Matthew Auld
2025-06-17 16:35 ` Ville Syrjälä
@ 2025-06-18 18:59 ` Lucas De Marchi
1 sibling, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2025-06-18 18:59 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst, stable
On Fri, Jun 06, 2025 at 11:45:48AM +0100, Matthew Auld wrote:
>Only need the flush for DPT host updates here. Normal GGTT updates don't
>need special flush.
>
>Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>Cc: <stable@vger.kernel.org> # v6.12+
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Lucas De Marchi
>---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>index 461ecdfdb742..b16a6e3ff4b4 100644
>--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>@@ -165,6 +165,9 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
>
> vma->dpt = dpt;
> vma->node = dpt->ggtt_node[tile0->id];
>+
>+ /* Ensure DPT writes are flushed */
>+ xe_device_l2_flush(xe);
> return 0;
> }
>
>@@ -334,8 +337,6 @@ static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb,
> if (ret)
> goto err_unpin;
>
>- /* Ensure DPT writes are flushed */
>- xe_device_l2_flush(xe);
> return vma;
>
> err_unpin:
>--
>2.49.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place
2025-06-06 10:45 [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place Matthew Auld
2025-06-06 10:45 ` [PATCH 2/2] drm/xe: move DPT " Matthew Auld
@ 2025-06-06 15:19 ` Matthew Auld
2025-06-17 16:26 ` Ville Syrjälä
2025-06-18 19:06 ` Lucas De Marchi
3 siblings, 0 replies; 8+ messages in thread
From: Matthew Auld @ 2025-06-06 15:19 UTC (permalink / raw)
To: intel-xe; +Cc: Maarten Lankhorst, stable
On 06/06/2025 11:45, Matthew Auld wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Flushing l2 is only needed after all data has been written.
>
> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Tested this locally and noticed a pretty big improvement just playing
around in the desktop environment, where stuff feels way smoother.
> ---
> drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> index f95375451e2f..9f941fc2e36b 100644
> --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> @@ -17,10 +17,7 @@ u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
> {
> - struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> -
> iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
> - xe_device_l2_flush(xe);
> }
>
> u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
> @@ -30,12 +27,9 @@ u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>
> void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
> {
> - struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> -
> WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
>
> iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
> - xe_device_l2_flush(xe);
> }
>
> bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
> @@ -74,9 +68,12 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
> {
> + struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> +
> /*
> * The memory barrier here is to ensure coherency of DSB vs MMIO,
> * both for weak ordering archs and discrete cards.
> */
> - xe_device_wmb(dsb_buf->vma->bo->tile->xe);
> + xe_device_wmb(xe);
> + xe_device_l2_flush(xe);
> }
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place
2025-06-06 10:45 [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place Matthew Auld
2025-06-06 10:45 ` [PATCH 2/2] drm/xe: move DPT " Matthew Auld
2025-06-06 15:19 ` [PATCH 1/2] drm/xe: Move DSB " Matthew Auld
@ 2025-06-17 16:26 ` Ville Syrjälä
2025-06-18 19:06 ` Lucas De Marchi
3 siblings, 0 replies; 8+ messages in thread
From: Ville Syrjälä @ 2025-06-17 16:26 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst, stable
On Fri, Jun 06, 2025 at 11:45:47AM +0100, Matthew Auld wrote:
> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
> Flushing l2 is only needed after all data has been written.
>
> Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: <stable@vger.kernel.org> # v6.12+
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Looks reasonable.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> index f95375451e2f..9f941fc2e36b 100644
> --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
> @@ -17,10 +17,7 @@ u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
> {
> - struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> -
> iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
> - xe_device_l2_flush(xe);
> }
>
> u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
> @@ -30,12 +27,9 @@ u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>
> void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
> {
> - struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> -
> WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
>
> iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
> - xe_device_l2_flush(xe);
> }
>
> bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
> @@ -74,9 +68,12 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
> {
> + struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
> +
> /*
> * The memory barrier here is to ensure coherency of DSB vs MMIO,
> * both for weak ordering archs and discrete cards.
> */
> - xe_device_wmb(dsb_buf->vma->bo->tile->xe);
> + xe_device_wmb(xe);
> + xe_device_l2_flush(xe);
> }
> --
> 2.49.0
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place
2025-06-06 10:45 [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place Matthew Auld
` (2 preceding siblings ...)
2025-06-17 16:26 ` Ville Syrjälä
@ 2025-06-18 19:06 ` Lucas De Marchi
2025-06-24 17:47 ` Lucas De Marchi
3 siblings, 1 reply; 8+ messages in thread
From: Lucas De Marchi @ 2025-06-18 19:06 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst, stable
On Fri, Jun 06, 2025 at 11:45:47AM +0100, Matthew Auld wrote:
>From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>
>Flushing l2 is only needed after all data has been written.
>
>Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>Cc: Matthew Auld <matthew.auld@intel.com>
>Cc: <stable@vger.kernel.org> # v6.12+
>Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>---
> drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 11 ++++-------
> 1 file changed, 4 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>index f95375451e2f..9f941fc2e36b 100644
>--- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>+++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>@@ -17,10 +17,7 @@ u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
> {
>- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
>-
> iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
>- xe_device_l2_flush(xe);
> }
>
> u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>@@ -30,12 +27,9 @@ u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>
> void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
> {
>- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
>-
> WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
>
> iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
>- xe_device_l2_flush(xe);
> }
>
> bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
>@@ -74,9 +68,12 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
>
> void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
assuming the calls to this function are already in the right place,
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
... but it seems quite fragile as we are exposing the other the
functions writing to it. Not something introduced here though.
Lucas De Marchi
> {
>+ struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
>+
> /*
> * The memory barrier here is to ensure coherency of DSB vs MMIO,
> * both for weak ordering archs and discrete cards.
> */
>- xe_device_wmb(dsb_buf->vma->bo->tile->xe);
>+ xe_device_wmb(xe);
>+ xe_device_l2_flush(xe);
> }
>--
>2.49.0
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] drm/xe: Move DSB l2 flush to a more sensible place
2025-06-18 19:06 ` Lucas De Marchi
@ 2025-06-24 17:47 ` Lucas De Marchi
0 siblings, 0 replies; 8+ messages in thread
From: Lucas De Marchi @ 2025-06-24 17:47 UTC (permalink / raw)
To: Matthew Auld; +Cc: intel-xe, Maarten Lankhorst, stable
On Wed, Jun 18, 2025 at 02:06:39PM -0500, Lucas De Marchi wrote:
>On Fri, Jun 06, 2025 at 11:45:47AM +0100, Matthew Auld wrote:
>>From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>
>>Flushing l2 is only needed after all data has been written.
>>
>>Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
>>Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
>>Cc: Matthew Auld <matthew.auld@intel.com>
>>Cc: <stable@vger.kernel.org> # v6.12+
>>Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>>Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>>---
>>drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 11 ++++-------
>>1 file changed, 4 insertions(+), 7 deletions(-)
>>
>>diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>>index f95375451e2f..9f941fc2e36b 100644
>>--- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>>+++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c
>>@@ -17,10 +17,7 @@ u32 intel_dsb_buffer_ggtt_offset(struct intel_dsb_buffer *dsb_buf)
>>
>>void intel_dsb_buffer_write(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val)
>>{
>>- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
>>-
>> iosys_map_wr(&dsb_buf->vma->bo->vmap, idx * 4, u32, val);
>>- xe_device_l2_flush(xe);
>>}
>>
>>u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>>@@ -30,12 +27,9 @@ u32 intel_dsb_buffer_read(struct intel_dsb_buffer *dsb_buf, u32 idx)
>>
>>void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, size_t size)
>>{
>>- struct xe_device *xe = dsb_buf->vma->bo->tile->xe;
>>-
>> WARN_ON(idx > (dsb_buf->buf_size - size) / sizeof(*dsb_buf->cmd_buf));
>>
>> iosys_map_memset(&dsb_buf->vma->bo->vmap, idx * 4, val, size);
>>- xe_device_l2_flush(xe);
>>}
>>
>>bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size)
>>@@ -74,9 +68,12 @@ void intel_dsb_buffer_cleanup(struct intel_dsb_buffer *dsb_buf)
>>
>>void intel_dsb_buffer_flush_map(struct intel_dsb_buffer *dsb_buf)
>
>assuming the calls to this function are already in the right place,
>
>Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
>
>... but it seems quite fragile as we are exposing the other the
>functions writing to it. Not something introduced here though.
applied both patches to drm-xe-next. Thanks.
Lucas De Marchi
^ permalink raw reply [flat|nested] 8+ messages in thread