* [U-Boot] [PATCH 2/2] 85xx: Fix how we map DDR memory
2009-02-06 15:56 [U-Boot] [PATCH 1/2] fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller Kumar Gala
@ 2009-02-06 15:56 ` Kumar Gala
0 siblings, 0 replies; 2+ messages in thread
From: Kumar Gala @ 2009-02-06 15:56 UTC (permalink / raw)
To: u-boot
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
This depends on the following two patches:
* Add an architecture specific config.h for common defines
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.h
cpu/mpc85xx/tlb.c | 74 +++++++++++++++---------------------------
include/asm-ppc/config.h | 5 ++-
include/asm-ppc/processor.h | 2 +
include/configs/MPC8572DS.h | 1 +
4 files changed, 33 insertions(+), 49 deletions(-)
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 25fa9ee..c73bf05 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -132,61 +132,41 @@ void init_addr_map(void)
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;
- unsigned int ram_tlb_index;
- unsigned int ram_tlb_address;
+ unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
+ unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
+ u64 size, memsize = (u64)memsize_in_meg << 20;
- /*
- * Determine size of each TLB1 entry.
- */
- switch (memsize_in_meg) {
- case 16:
- case 32:
- tlb_size = BOOKE_PAGESZ_16M;
- break;
- case 64:
- case 128:
- tlb_size = BOOKE_PAGESZ_64M;
- break;
- case 256:
- case 512:
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- case 1024:
- case 2048:
- if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
- tlb_size = BOOKE_PAGESZ_1G;
- else
- tlb_size = BOOKE_PAGESZ_256M;
- break;
- default:
- puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
- " and 2G are supported.\n");
-
- /*
- * The memory was not able to be mapped.
- * Default to a small size.
- */
- tlb_size = BOOKE_PAGESZ_64M;
- memsize_in_meg = 64;
- break;
- }
+ size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+
+ /* Convert (4^max) kB to (2^max) bytes */
+ max_cam = max_cam * 2 + 10;
+
+ for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+ u32 camsize = __ilog2_u64(size) & ~1U;
+ u32 align = __ilog2(ram_tlb_address) & ~1U;
+
+ if (align == -2) align = max_cam;
+ if (camsize > align)
+ camsize = align;
+
+ if (camsize > max_cam)
+ camsize = max_cam;
+
+ tlb_size = (camsize - 10) / 2;
- /*
- * Configure DDR TLB1 entries.
- * Starting at TLB1 8, use no more than 8 TLB1 entries.
- */
- ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
- ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
- while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
- && ram_tlb_index < 16) {
set_tlb(1, ram_tlb_address, ram_tlb_address,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, ram_tlb_index, tlb_size, 1);
- ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
- ram_tlb_index++;
+ size -= 1ULL << camsize;
+ memsize -= 1ULL << camsize;
+ ram_tlb_address += 1UL << camsize;
}
+ if (memsize)
+ printf("%lldM left unmapped\n", memsize >> 20);
+
/*
* Confirm that the requested amount of memory was mapped.
*/
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 6d27cb1..5640b39 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -22,8 +22,9 @@
#define _ASM_CONFIG_H_
#ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) && defined(CONFIG_SPD_EEPROM)
-#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
+#if (defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) && defined(CONFIG_SPD_EEPROM)) || \
+ defined(CONFIG_E500)
+#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2u << 30)
#else
#define CONFIG_MAX_MEM_MAPPED (256 << 20)
#endif
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index e07e5d3..4203ada 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -451,6 +451,8 @@
#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
+#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
+#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index ac0a464..a2360d8 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -103,6 +103,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
/* DDR Setup */
#define CONFIG_SYS_DDR_TLB_START 9
+#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
--
1.5.6.6
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