From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 03/15] arm: socfpga: Move Stratix10 and Agilex reset manager common code
Date: Thu, 30 May 2019 17:03:32 +0800 [thread overview]
Message-ID: <1559207024-22181-4-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1559207024-22181-1-git-send-email-ley.foon.tan@intel.com>
Move Stratix10 and Agilex reset manager common code to reset_manager.h.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
.../mach-socfpga/include/mach/reset_manager.h | 26 ++++++
.../include/mach/reset_manager_s10.h | 79 -------------------
2 files changed, 26 insertions(+), 79 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 42beaecdd6..e2dce4b4fb 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -36,6 +36,32 @@ void socfpga_per_reset_all(void);
/* Create a human-readable reference to SoCFPGA reset. */
#define SOCFPGA_RESET(_name) RSTMGR_##_name
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+
+void reset_deassert_peripherals_handoff(void);
+int cpu_has_been_warmreset(void);
+void socfpga_bridges_reset(int enable);
+
+#define RSTMGR_MPUMODRST_CORE0 0
+#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
+#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
+#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
+
+/* Watchdogs and MPU warm reset mask */
+#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
+
+/*
+ * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ */
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
+#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
+#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#endif
+
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..2d78c804c6 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -7,14 +7,6 @@
#ifndef _RESET_MANAGER_S10_
#define _RESET_MANAGER_S10_
-void reset_cpu(ulong addr);
-int cpu_has_been_warmreset(void);
-
-void socfpga_bridges_reset(int enable);
-
-void socfpga_per_reset(u32 reset, int set);
-void socfpga_per_reset_all(void);
-
struct socfpga_reset_manager {
u32 status;
u32 mpu_rst_stat;
@@ -44,75 +36,4 @@ struct socfpga_reset_manager {
u32 dbghdsktimeout;
};
-#define RSTMGR_MPUMODRST_CORE0 0
-#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
-#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040
-#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
-
-/* Watchdogs and MPU warm reset mask */
-#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
-
-/*
- * Define a reset identifier, from which a permodrst bank ID
- * and reset ID can be extracted using the subsequent macros
- * RSTMGR_RESET() and RSTMGR_BANK().
- */
-#define RSTMGR_BANK_OFFSET 8
-#define RSTMGR_BANK_MASK 0x7
-#define RSTMGR_RESET_OFFSET 0
-#define RSTMGR_RESET_MASK 0x1f
-#define RSTMGR_DEFINE(_bank, _offset) \
- ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
-
-/* Extract reset ID from the reset identifier. */
-#define RSTMGR_RESET(_reset) \
- (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
-
-/* Extract bank ID from the reset identifier. */
-#define RSTMGR_BANK(_reset) \
- (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
-
-/*
- * SocFPGA Stratix10 reset IDs, bank mapping is as follows:
- * 0 ... mpumodrst
- * 1 ... per0modrst
- * 2 ... per1modrst
- * 3 ... brgmodrst
- */
-#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
-#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
-#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
-#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3)
-#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4)
-#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
-#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
-#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8)
-#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9)
-#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10)
-#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11)
-#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12)
-#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13)
-#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15)
-#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
-#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
-#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
-#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
-#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
-#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2)
-#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3)
-#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4)
-#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8)
-#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9)
-#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10)
-#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11)
-#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12)
-#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
-#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
-#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24)
-#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25)
-#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
-
-/* Create a human-readable reference to SoCFPGA reset. */
-#define SOCFPGA_RESET(_name) RSTMGR_##_name
-
#endif /* _RESET_MANAGER_S10_ */
--
2.19.0
next prev parent reply other threads:[~2019-05-30 9:03 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-30 9:03 [U-Boot] [PATCH 00/15] Add Intel Agilex SoC support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 01/15] arm: socfpga: agilex: Add base address for Intel Agilex SoC Ley Foon Tan
2019-06-24 20:00 ` Simon Goldschmidt
2019-06-25 1:16 ` Ley Foon Tan
2019-06-25 14:03 ` Dinh Nguyen
2019-07-04 8:14 ` Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 02/15] arm: socfpga: Move firewall code to firewall file Ley Foon Tan
2019-05-30 9:03 ` Ley Foon Tan [this message]
2019-05-30 9:03 ` [U-Boot] [PATCH 04/15] arm: socfpga: agilex: Add reset manager support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 05/15] arm: socfpga: Move Stratix10 and Agilex system manager common code Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 06/15] arm: socfpga: agilex: Add system manager support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 07/15] clk: agilex: Add clock driver for Agilex Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 08/15] arm: socfpga: agilex: Add clock manager support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 09/15] arm: socfpga: agilex: Add CCU support for Agilex Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 10/15] ddr: altera: Restructure Stratix 10 SDRAM driver Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 11/15] ddr: altera: agilex: Add SDRAM driver for Agilex Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 12/15] board: intel: agilex: Add socdk board support for Intel Agilex SoC Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 13/15] arm: socfpga: agilex: Add SPL for " Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 14/15] arm: dts: agilex: Add base dtsi and devkit dts Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 15/15] arm: socfpga: agilex: Enable Agilex SoC build Ley Foon Tan
2019-06-10 6:31 ` [U-Boot] [PATCH 00/15] Add Intel Agilex SoC support Ley Foon Tan
2019-06-11 13:47 ` Marek Vasut
2019-06-11 14:03 ` Simon Goldschmidt
2019-06-24 19:53 ` Simon Goldschmidt
2019-06-25 1:01 ` Ley Foon Tan
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