From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 08/15] arm: socfpga: agilex: Add clock manager support
Date: Thu, 30 May 2019 17:03:37 +0800 [thread overview]
Message-ID: <1559207024-22181-9-git-send-email-ley.foon.tan@intel.com> (raw)
In-Reply-To: <1559207024-22181-1-git-send-email-ley.foon.tan@intel.com>
Add clock manager support for Agilex.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/Makefile | 4 +
arch/arm/mach-socfpga/clock_manager_agilex.c | 87 +++++++++++++++++++
.../include/mach/clock_manager_agilex.h | 2 +
3 files changed, 93 insertions(+)
create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 11370cf4c4..5bb36d07df 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -40,6 +40,10 @@ obj-y += wrap_pinmux_config_s10.o
obj-y += wrap_pll_config_s10.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+obj-y += clock_manager_agilex.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c
new file mode 100644
index 0000000000..5159415fbf
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/stratix10-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(socfpga_agilex_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(STRATIX10_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(STRATIX10_L4_SYS_FREE_CLK);
+}
+
+u32 cm_get_qspi_controller_clk_hz(void)
+{
+ return readl(&sysmgr_regs->boot_scratch_cold0);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(STRATIX10_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index bf5e7c8775..c4d27bad72 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -25,6 +25,8 @@ const unsigned int cm_get_osc_clk_hz(void);
const unsigned int cm_get_intosc_clk_hz(void);
const unsigned int cm_get_fpga_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
#define CLKMGR_EOSC1_HZ 25000000
#define CLKMGR_INTOSC_HZ 400000000
#define CLKMGR_FPGA_CLK_HZ 50000000
--
2.19.0
next prev parent reply other threads:[~2019-05-30 9:03 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-30 9:03 [U-Boot] [PATCH 00/15] Add Intel Agilex SoC support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 01/15] arm: socfpga: agilex: Add base address for Intel Agilex SoC Ley Foon Tan
2019-06-24 20:00 ` Simon Goldschmidt
2019-06-25 1:16 ` Ley Foon Tan
2019-06-25 14:03 ` Dinh Nguyen
2019-07-04 8:14 ` Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 02/15] arm: socfpga: Move firewall code to firewall file Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 03/15] arm: socfpga: Move Stratix10 and Agilex reset manager common code Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 04/15] arm: socfpga: agilex: Add reset manager support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 05/15] arm: socfpga: Move Stratix10 and Agilex system manager common code Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 06/15] arm: socfpga: agilex: Add system manager support Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 07/15] clk: agilex: Add clock driver for Agilex Ley Foon Tan
2019-05-30 9:03 ` Ley Foon Tan [this message]
2019-05-30 9:03 ` [U-Boot] [PATCH 09/15] arm: socfpga: agilex: Add CCU support " Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 10/15] ddr: altera: Restructure Stratix 10 SDRAM driver Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 11/15] ddr: altera: agilex: Add SDRAM driver for Agilex Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 12/15] board: intel: agilex: Add socdk board support for Intel Agilex SoC Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 13/15] arm: socfpga: agilex: Add SPL for " Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 14/15] arm: dts: agilex: Add base dtsi and devkit dts Ley Foon Tan
2019-05-30 9:03 ` [U-Boot] [PATCH 15/15] arm: socfpga: agilex: Enable Agilex SoC build Ley Foon Tan
2019-06-10 6:31 ` [U-Boot] [PATCH 00/15] Add Intel Agilex SoC support Ley Foon Tan
2019-06-11 13:47 ` Marek Vasut
2019-06-11 14:03 ` Simon Goldschmidt
2019-06-24 19:53 ` Simon Goldschmidt
2019-06-25 1:01 ` Ley Foon Tan
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