* [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
2019-09-10 8:37 [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines Ley Foon Tan
@ 2019-09-10 8:38 ` Ley Foon Tan
2019-09-16 14:09 ` Dinh Nguyen
2019-10-02 9:18 ` Simon Goldschmidt
2019-09-10 8:38 ` [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines Ley Foon Tan
` (3 subsequent siblings)
4 siblings, 2 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-10 8:38 UTC (permalink / raw)
To: u-boot
Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
In preparation to get base address from DT.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/dts/socfpga-common-u-boot.dtsi | 8 ++++++++
arch/arm/dts/socfpga.dtsi | 2 +-
arch/arm/dts/socfpga_arria10.dtsi | 2 +-
arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 ++++++++
arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 ++++++++
6 files changed, 27 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
index 322c858c4b..d55460755f 100644
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -10,6 +10,10 @@
};
};
+&clkmgr {
+ u-boot,dm-pre-reloc;
+};
+
&rst {
u-boot,dm-pre-reloc;
};
@@ -17,3 +21,7 @@
&sdr {
u-boot,dm-pre-reloc;
};
+
+&sysmgr {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 51a6a51b53..eda558f2fe 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -114,7 +114,7 @@
status = "disabled";
};
- clkmgr at ffd04000 {
+ clkmgr: clkmgr at ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
index c11a5c0cc1..cc529bcd11 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -96,7 +96,7 @@
fpga-mgr = <&fpga_mgr>;
};
- clkmgr at ffd04000 {
+ clkmgr: clkmgr at ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
index 6e5578d7bd..ef10708ee8 100644
--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
@@ -180,3 +180,11 @@
&l4_sp_clk {
u-boot,dm-pre-reloc;
};
+
+&clkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
index bd68a78a37..91f4e27ef5 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -82,7 +82,7 @@
ranges = <0 0 0 0xffffffff>;
u-boot,dm-pre-reloc;
- clkmgr at ffd1000 {
+ clkmgr: clkmgr at ffd1000 {
compatible = "altr,clk-mgr";
reg = <0xffd10000 0x1000>;
};
diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
index e1cfb522bf..38855aecd7 100755
--- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
@@ -11,6 +11,10 @@
};
};
+&clkmgr {
+ u-boot,dm-pre-reloc;
+};
+
&qspi {
status = "okay";
u-boot,dm-pre-reloc;
@@ -23,3 +27,7 @@
spi-rx-bus-width = <4>;
u-boot,dm-pre-reloc;
};
+
+&sysmgr {
+ u-boot,dm-pre-reloc;
+};
--
2.19.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
2019-09-10 8:38 ` [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes Ley Foon Tan
@ 2019-09-16 14:09 ` Dinh Nguyen
2019-09-18 2:32 ` Ley Foon Tan
2019-10-02 9:18 ` Simon Goldschmidt
1 sibling, 1 reply; 21+ messages in thread
From: Dinh Nguyen @ 2019-09-16 14:09 UTC (permalink / raw)
To: u-boot
On 9/10/19 3:38 AM, Ley Foon Tan wrote:
> Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
> In preparation to get base address from DT.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/dts/socfpga-common-u-boot.dtsi | 8 ++++++++
> arch/arm/dts/socfpga.dtsi | 2 +-
> arch/arm/dts/socfpga_arria10.dtsi | 2 +-
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 ++++++++
> arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 ++++++++
> 6 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
> index 322c858c4b..d55460755f 100644
> --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> @@ -10,6 +10,10 @@
> };
> };
>
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> &rst {
> u-boot,dm-pre-reloc;
> };
> @@ -17,3 +21,7 @@
> &sdr {
> u-boot,dm-pre-reloc;
> };
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 51a6a51b53..eda558f2fe 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -114,7 +114,7 @@
> status = "disabled";
> };
>
> - clkmgr at ffd04000 {
> + clkmgr: clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
>
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> index c11a5c0cc1..cc529bcd11 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -96,7 +96,7 @@
> fpga-mgr = <&fpga_mgr>;
> };
>
> - clkmgr at ffd04000 {
> + clkmgr: clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index 6e5578d7bd..ef10708ee8 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -180,3 +180,11 @@
> &l4_sp_clk {
> u-boot,dm-pre-reloc;
> };
> +
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
> index bd68a78a37..91f4e27ef5 100755
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -82,7 +82,7 @@
> ranges = <0 0 0 0xffffffff>;
> u-boot,dm-pre-reloc;
>
> - clkmgr at ffd1000 {
> + clkmgr: clkmgr at ffd1000 {
Missing another zero in the address.
Dinh
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
2019-09-16 14:09 ` Dinh Nguyen
@ 2019-09-18 2:32 ` Ley Foon Tan
0 siblings, 0 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-18 2:32 UTC (permalink / raw)
To: u-boot
On Mon, Sep 16, 2019 at 10:12 PM Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
>
> On 9/10/19 3:38 AM, Ley Foon Tan wrote:
> > Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
> > In preparation to get base address from DT.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> > ---
> > arch/arm/dts/socfpga-common-u-boot.dtsi | 8 ++++++++
> > arch/arm/dts/socfpga.dtsi | 2 +-
> > arch/arm/dts/socfpga_arria10.dtsi | 2 +-
> > arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 ++++++++
> > arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
> > arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 ++++++++
> > 6 files changed, 27 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
> > index 322c858c4b..d55460755f 100644
> > --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> > +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> > @@ -10,6 +10,10 @@
> > };
> > };
> >
> > +&clkmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > &rst {
> > u-boot,dm-pre-reloc;
> > };
> > @@ -17,3 +21,7 @@
> > &sdr {
> > u-boot,dm-pre-reloc;
> > };
> > +
> > +&sysmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> > index 51a6a51b53..eda558f2fe 100644
> > --- a/arch/arm/dts/socfpga.dtsi
> > +++ b/arch/arm/dts/socfpga.dtsi
> > @@ -114,7 +114,7 @@
> > status = "disabled";
> > };
> >
> > - clkmgr at ffd04000 {
> > + clkmgr: clkmgr at ffd04000 {
> > compatible = "altr,clk-mgr";
> > reg = <0xffd04000 0x1000>;
> >
> > diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> > index c11a5c0cc1..cc529bcd11 100644
> > --- a/arch/arm/dts/socfpga_arria10.dtsi
> > +++ b/arch/arm/dts/socfpga_arria10.dtsi
> > @@ -96,7 +96,7 @@
> > fpga-mgr = <&fpga_mgr>;
> > };
> >
> > - clkmgr at ffd04000 {
> > + clkmgr: clkmgr at ffd04000 {
> > compatible = "altr,clk-mgr";
> > reg = <0xffd04000 0x1000>;
> > u-boot,dm-pre-reloc;
> > diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> > index 6e5578d7bd..ef10708ee8 100644
> > --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> > +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> > @@ -180,3 +180,11 @@
> > &l4_sp_clk {
> > u-boot,dm-pre-reloc;
> > };
> > +
> > +&clkmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sysmgr {
> > + u-boot,dm-pre-reloc;
> > +};
> > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
> > index bd68a78a37..91f4e27ef5 100755
> > --- a/arch/arm/dts/socfpga_stratix10.dtsi
> > +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> > @@ -82,7 +82,7 @@
> > ranges = <0 0 0 0xffffffff>;
> > u-boot,dm-pre-reloc;
> >
> > - clkmgr at ffd1000 {
> > + clkmgr: clkmgr at ffd1000 {
>
> Missing another zero in the address.
Noted.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes
2019-09-10 8:38 ` [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes Ley Foon Tan
2019-09-16 14:09 ` Dinh Nguyen
@ 2019-10-02 9:18 ` Simon Goldschmidt
1 sibling, 0 replies; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-02 9:18 UTC (permalink / raw)
To: u-boot
On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Add u-boot,dm-pre-reloc for sysmgr and clkmgr nodes to use it in SPL.
> In preparation to get base address from DT.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
I'm OK with this change as long as it doesn't blow SPL size limits because of
the additional DT nodes.
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> ---
> arch/arm/dts/socfpga-common-u-boot.dtsi | 8 ++++++++
> arch/arm/dts/socfpga.dtsi | 2 +-
> arch/arm/dts/socfpga_arria10.dtsi | 2 +-
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 8 ++++++++
> arch/arm/dts/socfpga_stratix10.dtsi | 2 +-
> arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 8 ++++++++
> 6 files changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi
> index 322c858c4b..d55460755f 100644
> --- a/arch/arm/dts/socfpga-common-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
> @@ -10,6 +10,10 @@
> };
> };
>
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> &rst {
> u-boot,dm-pre-reloc;
> };
> @@ -17,3 +21,7 @@
> &sdr {
> u-boot,dm-pre-reloc;
> };
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
> index 51a6a51b53..eda558f2fe 100644
> --- a/arch/arm/dts/socfpga.dtsi
> +++ b/arch/arm/dts/socfpga.dtsi
> @@ -114,7 +114,7 @@
> status = "disabled";
> };
>
> - clkmgr at ffd04000 {
> + clkmgr: clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
>
> diff --git a/arch/arm/dts/socfpga_arria10.dtsi b/arch/arm/dts/socfpga_arria10.dtsi
> index c11a5c0cc1..cc529bcd11 100644
> --- a/arch/arm/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/dts/socfpga_arria10.dtsi
> @@ -96,7 +96,7 @@
> fpga-mgr = <&fpga_mgr>;
> };
>
> - clkmgr at ffd04000 {
> + clkmgr: clkmgr at ffd04000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd04000 0x1000>;
> u-boot,dm-pre-reloc;
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index 6e5578d7bd..ef10708ee8 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -180,3 +180,11 @@
> &l4_sp_clk {
> u-boot,dm-pre-reloc;
> };
> +
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi
> index bd68a78a37..91f4e27ef5 100755
> --- a/arch/arm/dts/socfpga_stratix10.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10.dtsi
> @@ -82,7 +82,7 @@
> ranges = <0 0 0 0xffffffff>;
> u-boot,dm-pre-reloc;
>
> - clkmgr at ffd1000 {
> + clkmgr: clkmgr at ffd1000 {
> compatible = "altr,clk-mgr";
> reg = <0xffd10000 0x1000>;
> };
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> index e1cfb522bf..38855aecd7 100755
> --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi
> @@ -11,6 +11,10 @@
> };
> };
>
> +&clkmgr {
> + u-boot,dm-pre-reloc;
> +};
> +
> &qspi {
> status = "okay";
> u-boot,dm-pre-reloc;
> @@ -23,3 +27,7 @@
> spi-rx-bus-width = <4>;
> u-boot,dm-pre-reloc;
> };
> +
> +&sysmgr {
> + u-boot,dm-pre-reloc;
> +};
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines
2019-09-10 8:37 [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines Ley Foon Tan
2019-09-10 8:38 ` [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes Ley Foon Tan
@ 2019-09-10 8:38 ` Ley Foon Tan
2019-10-02 9:20 ` Simon Goldschmidt
2019-09-10 8:38 ` [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system " Ley Foon Tan
` (2 subsequent siblings)
4 siblings, 1 reply; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-10 8:38 UTC (permalink / raw)
To: u-boot
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
No functional change.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
v2:
- Get base address from DT
- Change to use writel(), readl(), setbits_le32() and clrbits_le32().
- Add prefix to defines.
---
arch/arm/mach-socfpga/include/mach/misc.h | 1 +
.../mach-socfpga/include/mach/reset_manager.h | 2 +
.../include/mach/reset_manager_arria10.h | 43 ++++-------------
.../include/mach/reset_manager_gen5.h | 22 ++++-----
.../include/mach/reset_manager_s10.h | 33 ++-----------
arch/arm/mach-socfpga/misc.c | 32 +++++++++++++
arch/arm/mach-socfpga/misc_gen5.c | 7 ++-
arch/arm/mach-socfpga/reset_manager_arria10.c | 47 ++++++++++---------
arch/arm/mach-socfpga/reset_manager_gen5.c | 28 +++++------
arch/arm/mach-socfpga/reset_manager_s10.c | 34 +++++++-------
arch/arm/mach-socfpga/spl_a10.c | 7 ++-
arch/arm/mach-socfpga/spl_gen5.c | 12 ++---
arch/arm/mach-socfpga/spl_s10.c | 12 +++--
drivers/sysreset/sysreset_socfpga.c | 6 +--
14 files changed, 137 insertions(+), 149 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 27d0b6a370..a29b049742 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
+void socfpga_get_manager_addr(void);
#endif /* _MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 6ad037e325..a5b6931350 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -6,6 +6,8 @@
#ifndef _RESET_MANAGER_H_
#define _RESET_MANAGER_H_
+extern phys_addr_t socfpga_rstmgr_base;
+
void reset_cpu(ulong addr);
void socfpga_per_reset(u32 reset, int set);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 6623ebee65..41169aa677 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
void socfpga_reset_deassert_osc1wd0(void);
int socfpga_bridges_reset(void);
-struct socfpga_reset_manager {
- u32 stat;
- u32 ramstat;
- u32 miscstat;
- u32 ctrl;
- u32 hdsken;
- u32 hdskreq;
- u32 hdskack;
- u32 counts;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
- u32 sysmodrst;
- u32 coldmodrst;
- u32 nrstmodrst;
- u32 dbgmodrst;
- u32 mpuwarmmask;
- u32 per0warmmask;
- u32 per1warmmask;
- u32 brgwarmmask;
- u32 syswarmmask;
- u32 nrstwarmmask;
- u32 l3warmmask;
- u32 tststa;
- u32 tstscratch;
- u32 hdsktimeout;
- u32 hmcintr;
- u32 hmcintren;
- u32 hmcintrens;
- u32 hmcintrenr;
- u32 hmcgpout;
- u32 hmcgpin;
-};
+#define RSTMGR_A10_STATUS 0
+#define RSTMGR_A10_CTRL 0xc
+#define RSTMGR_A10_MPUMODRST 0x20
+#define RSTMGR_A10_PER0MODRST 0x24
+#define RSTMGR_A10_PER1MODRST 0x28
+#define RSTMGR_A10_BRGMODRST 0x2c
+#define RSTMGR_A10_SYSMODRST 0x30
+
+#define RSTMGR_CTRL RSTMGR_A10_CTRL
/*
* SocFPGA Arria10 reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
index f4dcb14623..e51ebfd08f 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -11,19 +11,15 @@
void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
void socfpga_bridges_reset(int enable);
-struct socfpga_reset_manager {
- u32 status;
- u32 ctrl;
- u32 counts;
- u32 padding1;
- u32 mpu_mod_reset;
- u32 per_mod_reset;
- u32 per2_mod_reset;
- u32 brg_mod_reset;
- u32 misc_mod_reset;
- u32 padding2[12];
- u32 tstscratch;
-};
+#define RSTMGR_GEN5_STATUS 0
+#define RSTMGR_GEN5_CTRL 4
+#define RSTMGR_GEN5_MPUMODRST 0x10
+#define RSTMGR_GEN5_PERMODRST 0x14
+#define RSTMGR_GEN5_PER2MODRST 0x18
+#define RSTMGR_GEN5_BRGMODRST 0x1c
+#define RSTMGR_GEN5_MISCMODRST 0x20
+
+#define RSTMGR_CTRL RSTMGR_GEN5_CTRL
/*
* SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
index 452147b017..b602129656 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
@@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
-struct socfpga_reset_manager {
- u32 status;
- u32 mpu_rst_stat;
- u32 misc_stat;
- u32 padding1;
- u32 hdsk_en;
- u32 hdsk_req;
- u32 hdsk_ack;
- u32 hdsk_stall;
- u32 mpumodrst;
- u32 per0modrst;
- u32 per1modrst;
- u32 brgmodrst;
- u32 padding2;
- u32 cold_mod_reset;
- u32 padding3;
- u32 dbg_mod_reset;
- u32 tap_mod_reset;
- u32 padding4;
- u32 padding5;
- u32 brg_warm_mask;
- u32 padding6[3];
- u32 tst_stat;
- u32 padding7;
- u32 hdsk_timeout;
- u32 mpul2flushtimeout;
- u32 dbghdsktimeout;
-};
+#define RSTMGR_S10_STATUS 0
+#define RSTMGR_S10_MPUMODRST 0x20
+#define RSTMGR_S10_PER0MODRST 0x24
+#define RSTMGR_S10_PER1MODRST 0x28
+#define RSTMGR_S10_BRGMODRST 0x2c
#define RSTMGR_MPUMODRST_CORE0 0
#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 49dadd4c3d..901c432f82 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -22,6 +22,8 @@
DECLARE_GLOBAL_DATA_PTR;
+phys_addr_t socfpga_rstmgr_base __section(".data");
+
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -145,6 +147,8 @@ void socfpga_fpga_add(void *fpga_desc)
int arch_cpu_init(void)
{
+ socfpga_get_manager_addr();
+
#ifdef CONFIG_HW_WATCHDOG
/*
* In case the watchdog is enabled, make sure to (re-)configure it
@@ -202,3 +206,31 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
);
#endif
+
+static phys_addr_t socfpga_get_base_addr(const char *compat)
+{
+ const void *blob = gd->fdt_blob;
+ struct fdt_resource r;
+ int node;
+ int ret;
+
+ node = fdt_node_offset_by_compatible(blob, -1, compat);
+ if (node < 0)
+ return 0;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ return 0;
+
+ ret = fdt_get_resource(blob, node, "reg", 0, &r);
+ if (ret)
+ return 0;
+
+ return (phys_addr_t)r.start;
+}
+
+void socfpga_get_manager_addr(void)
+{
+ socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
+ if (!socfpga_rstmgr_base)
+ hang();
+}
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 31681b799d..b39a66562d 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -206,8 +206,6 @@ int arch_early_init_r(void)
}
#ifndef CONFIG_SPL_BUILD
-static struct socfpga_reset_manager *reset_manager_base =
- (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
@@ -226,12 +224,13 @@ void do_bridge_reset(int enable, unsigned int mask)
writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
- writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
+ writel(iswgrp_handoff[0],
+ socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
} else {
writel(0, &sysmgr_regs->fpgaintfgrp_module);
writel(0, &sdr_ctrl->fpgaport_rst);
- writel(0, &reset_manager_base->brg_mod_reset);
+ writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
}
}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 471a3045af..4553653992 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,8 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
@@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
void socfpga_watchdog_disable(void)
{
/* assert reset for watchdog */
- setbits_le32(&reset_manager_base->per1modrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
/* Release NOC ddr scheduler from reset */
void socfpga_reset_deassert_noc_ddr_scheduler(void)
{
- clrbits_le32(&reset_manager_base->brgmodrst,
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
}
@@ -103,7 +101,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
/* Release bridges from reset state per handoff value */
- clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
@@ -113,7 +111,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
void socfpga_reset_deassert_osc1wd0(void)
{
- clrbits_le32(&reset_manager_base->per1modrst,
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
}
@@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
*/
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);
switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_A10_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_A10_PER0MODRST;
break;
case 2:
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_A10_PER1MODRST;
break;
case 3:
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_A10_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->sysmodrst;
+ reg = RSTMGR_A10_SYSMODRST;
break;
default:
@@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
}
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -174,11 +174,12 @@ void socfpga_per_reset_all(void)
ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
- writel(~l4wd0, &reset_manager_base->per1modrst);
- setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST);
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST,
+ ~mask_ecc_ocp);
/* Finally disable the ECC_OCP */
- setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST, mask_ecc_ocp);
}
int socfpga_bridges_reset(void)
@@ -224,13 +225,13 @@ int socfpga_bridges_reset(void)
return ret;
/* Put all bridges (except NOR DDR scheduler) into reset state */
- setbits_le32(&reset_manager_base->brgmodrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
- ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
+ ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
+ ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
/* Disable NOC timeout */
writel(0, &sysmgr_regs->noc_timeout);
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index 9a32f5abfe..ad31214711 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,32 +10,30 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const u32 *reg;
+ unsigned long reg;
u32 rstmgr_bank = RSTMGR_BANK(reset);
switch (rstmgr_bank) {
case 0:
- reg = &reset_manager_base->mpu_mod_reset;
+ reg = RSTMGR_GEN5_MPUMODRST;
break;
case 1:
- reg = &reset_manager_base->per_mod_reset;
+ reg = RSTMGR_GEN5_PERMODRST;
break;
case 2:
- reg = &reset_manager_base->per2_mod_reset;
+ reg = RSTMGR_GEN5_PER2MODRST;
break;
case 3:
- reg = &reset_manager_base->brg_mod_reset;
+ reg = RSTMGR_GEN5_BRGMODRST;
break;
case 4:
- reg = &reset_manager_base->misc_mod_reset;
+ reg = RSTMGR_GEN5_MISCMODRST;
break;
default:
@@ -43,9 +41,11 @@ void socfpga_per_reset(u32 reset, int set)
}
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -57,8 +57,8 @@ void socfpga_per_reset_all(void)
{
const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
- writel(~l4wd0, &reset_manager_base->per_mod_reset);
- writel(0xffffffff, &reset_manager_base->per2_mod_reset);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_GEN5_PERMODRST);
+ writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_GEN5_PER2MODRST);
}
#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
@@ -95,7 +95,7 @@ void socfpga_bridges_reset(int enable)
if (enable) {
/* brdmodrst */
- writel(0x7, &reset_manager_base->brg_mod_reset);
+ writel(0x7, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
} else {
socfpga_bridges_set_handoff_regs(false, false, false);
@@ -109,7 +109,7 @@ void socfpga_bridges_reset(int enable)
}
/* brdmodrst */
- writel(0, &reset_manager_base->brg_mod_reset);
+ writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
/* Remap the bridges into memory map */
writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index 499a84aff5..b196d58d3d 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,31 +12,31 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_reset_manager *reset_manager_base =
- (void *)SOCFPGA_RSTMGR_ADDRESS;
static const struct socfpga_system_manager *system_manager_base =
(void *)SOCFPGA_SYSMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
- const void *reg;
+ unsigned long reg;
if (RSTMGR_BANK(reset) == 0)
- reg = &reset_manager_base->mpumodrst;
+ reg = RSTMGR_S10_MPUMODRST;
else if (RSTMGR_BANK(reset) == 1)
- reg = &reset_manager_base->per0modrst;
+ reg = RSTMGR_S10_PER0MODRST;
else if (RSTMGR_BANK(reset) == 2)
- reg = &reset_manager_base->per1modrst;
+ reg = RSTMGR_S10_PER1MODRST;
else if (RSTMGR_BANK(reset) == 3)
- reg = &reset_manager_base->brgmodrst;
+ reg = RSTMGR_S10_BRGMODRST;
else /* Invalid reset register, do nothing */
return;
if (set)
- setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ setbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
else
- clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+ clrbits_le32(socfpga_rstmgr_base + reg,
+ 1 << RSTMGR_RESET(reset));
}
/*
@@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
/* disable all except OCP and l4wd0. OCP disable later */
writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
- &reset_manager_base->per0modrst);
- writel(~l4wd0, &reset_manager_base->per0modrst);
- writel(0xffffffff, &reset_manager_base->per1modrst);
+ socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+ writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
+ writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
}
void socfpga_bridges_reset(int enable)
@@ -62,7 +62,7 @@ void socfpga_bridges_reset(int enable)
setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
/* Release all bridges from reset state */
- clrbits_le32(&reset_manager_base->brgmodrst, ~0);
+ clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
/* Poll until all idleack to 0 */
while (readl(&system_manager_base->noc_idleack))
@@ -85,9 +85,9 @@ void socfpga_bridges_reset(int enable)
;
/* Reset all bridges (except NOR DDR scheduler & F2S) */
- setbits_le32(&reset_manager_base->brgmodrst,
+ setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
~(RSTMGR_BRGMODRST_DDRSCH_MASK |
- RSTMGR_BRGMODRST_FPGA2SOC_MASK));
+ RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
writel(0, &system_manager_base->noc_timeout);
@@ -99,6 +99,6 @@ void socfpga_bridges_reset(int enable)
*/
int cpu_has_been_warmreset(void)
{
- return readl(&reset_manager_base->status) &
- RSTMGR_L4WD_MPU_WARMRESET_MASK;
+ return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
+ RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index b820cb0673..a0d80fd47e 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -106,6 +106,11 @@ void spl_board_init(void)
void board_init_f(ulong dummy)
{
+ if (spl_early_init())
+ hang();
+
+ socfpga_get_manager_addr();
+
dcache_disable();
socfpga_init_security_policies();
@@ -116,8 +121,6 @@ void board_init_f(ulong dummy)
socfpga_per_reset_all();
socfpga_watchdog_disable();
- spl_early_init();
-
/* Configure the clock based on handoff */
cm_basic_init(gd->fdt_blob);
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 47e63709ad..9ee053da3a 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -67,6 +67,12 @@ void board_init_f(ulong dummy)
int ret;
struct udevice *dev;
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_manager_addr();
+
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
@@ -128,12 +134,6 @@ void board_init_f(ulong dummy)
debug_uart_init();
#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
-
ret = uclass_get_device(UCLASS_RESET, 0, &dev);
if (ret)
debug("Reset init failed: %d\n", ret);
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index ec65e1ce64..9a97a84e1e 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -14,6 +14,7 @@
#include <asm/arch/clock_manager.h>
#include <asm/arch/firewall_s10.h>
#include <asm/arch/mailbox_s10.h>
+#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
#include <watchdog.h>
@@ -120,6 +121,12 @@ void board_init_f(ulong dummy)
const struct cm_config *cm_default_cfg = cm_get_default_config();
int ret;
+ ret = spl_early_init();
+ if (ret)
+ hang();
+
+ socfpga_get_manager_addr();
+
#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
@@ -145,11 +152,6 @@ void board_init_f(ulong dummy)
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
debug_uart_init();
#endif
- ret = spl_early_init();
- if (ret) {
- debug("spl_early_init() failed: %d\n", ret);
- hang();
- }
preloader_console_init();
cm_print_clock_quick_summary();
diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
index d6c26a5b23..3390b7bdc2 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -12,7 +12,7 @@
#include <asm/arch/reset_manager.h>
struct socfpga_sysreset_data {
- struct socfpga_reset_manager *rstmgr_base;
+ void __iomem *rstmgr_base;
};
static int socfpga_sysreset_request(struct udevice *dev,
@@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
switch (type) {
case SYSRESET_WARM:
writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
- &data->rstmgr_base->ctrl);
+ data->rstmgr_base + RSTMGR_CTRL);
break;
case SYSRESET_COLD:
writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
- &data->rstmgr_base->ctrl);
+ data->rstmgr_base + RSTMGR_CTRL);
break;
default:
return -EPROTONOSUPPORT;
--
2.19.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines
2019-09-10 8:38 ` [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines Ley Foon Tan
@ 2019-10-02 9:20 ` Simon Goldschmidt
2019-10-04 3:03 ` Ley Foon Tan
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-02 9:20 UTC (permalink / raw)
To: u-boot
On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
> No functional change.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> ---
> v2:
> - Get base address from DT
Wait, "no functional change", yet you now read the base address from DT?
I think that's a good idea, but could you do it in a separate patch?
Regards,
Simon
> - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> - Add prefix to defines.
> ---
> arch/arm/mach-socfpga/include/mach/misc.h | 1 +
> .../mach-socfpga/include/mach/reset_manager.h | 2 +
> .../include/mach/reset_manager_arria10.h | 43 ++++-------------
> .../include/mach/reset_manager_gen5.h | 22 ++++-----
> .../include/mach/reset_manager_s10.h | 33 ++-----------
> arch/arm/mach-socfpga/misc.c | 32 +++++++++++++
> arch/arm/mach-socfpga/misc_gen5.c | 7 ++-
> arch/arm/mach-socfpga/reset_manager_arria10.c | 47 ++++++++++---------
> arch/arm/mach-socfpga/reset_manager_gen5.c | 28 +++++------
> arch/arm/mach-socfpga/reset_manager_s10.c | 34 +++++++-------
> arch/arm/mach-socfpga/spl_a10.c | 7 ++-
> arch/arm/mach-socfpga/spl_gen5.c | 12 ++---
> arch/arm/mach-socfpga/spl_s10.c | 12 +++--
> drivers/sysreset/sysreset_socfpga.c | 6 +--
> 14 files changed, 137 insertions(+), 149 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
> index 27d0b6a370..a29b049742 100644
> --- a/arch/arm/mach-socfpga/include/mach/misc.h
> +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> @@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
>
> void do_bridge_reset(int enable, unsigned int mask);
> void socfpga_pl310_clear(void);
> +void socfpga_get_manager_addr(void);
>
> #endif /* _MISC_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 6ad037e325..a5b6931350 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -6,6 +6,8 @@
> #ifndef _RESET_MANAGER_H_
> #define _RESET_MANAGER_H_
>
> +extern phys_addr_t socfpga_rstmgr_base;
> +
> void reset_cpu(ulong addr);
>
> void socfpga_per_reset(u32 reset, int set);
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> index 6623ebee65..41169aa677 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
> void socfpga_reset_deassert_osc1wd0(void);
> int socfpga_bridges_reset(void);
>
> -struct socfpga_reset_manager {
> - u32 stat;
> - u32 ramstat;
> - u32 miscstat;
> - u32 ctrl;
> - u32 hdsken;
> - u32 hdskreq;
> - u32 hdskack;
> - u32 counts;
> - u32 mpumodrst;
> - u32 per0modrst;
> - u32 per1modrst;
> - u32 brgmodrst;
> - u32 sysmodrst;
> - u32 coldmodrst;
> - u32 nrstmodrst;
> - u32 dbgmodrst;
> - u32 mpuwarmmask;
> - u32 per0warmmask;
> - u32 per1warmmask;
> - u32 brgwarmmask;
> - u32 syswarmmask;
> - u32 nrstwarmmask;
> - u32 l3warmmask;
> - u32 tststa;
> - u32 tstscratch;
> - u32 hdsktimeout;
> - u32 hmcintr;
> - u32 hmcintren;
> - u32 hmcintrens;
> - u32 hmcintrenr;
> - u32 hmcgpout;
> - u32 hmcgpin;
> -};
> +#define RSTMGR_A10_STATUS 0
> +#define RSTMGR_A10_CTRL 0xc
> +#define RSTMGR_A10_MPUMODRST 0x20
> +#define RSTMGR_A10_PER0MODRST 0x24
> +#define RSTMGR_A10_PER1MODRST 0x28
> +#define RSTMGR_A10_BRGMODRST 0x2c
> +#define RSTMGR_A10_SYSMODRST 0x30
> +
> +#define RSTMGR_CTRL RSTMGR_A10_CTRL
>
> /*
> * SocFPGA Arria10 reset IDs, bank mapping is as follows:
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> index f4dcb14623..e51ebfd08f 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> @@ -11,19 +11,15 @@
> void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
> void socfpga_bridges_reset(int enable);
>
> -struct socfpga_reset_manager {
> - u32 status;
> - u32 ctrl;
> - u32 counts;
> - u32 padding1;
> - u32 mpu_mod_reset;
> - u32 per_mod_reset;
> - u32 per2_mod_reset;
> - u32 brg_mod_reset;
> - u32 misc_mod_reset;
> - u32 padding2[12];
> - u32 tstscratch;
> -};
> +#define RSTMGR_GEN5_STATUS 0
> +#define RSTMGR_GEN5_CTRL 4
> +#define RSTMGR_GEN5_MPUMODRST 0x10
> +#define RSTMGR_GEN5_PERMODRST 0x14
> +#define RSTMGR_GEN5_PER2MODRST 0x18
> +#define RSTMGR_GEN5_BRGMODRST 0x1c
> +#define RSTMGR_GEN5_MISCMODRST 0x20
> +
> +#define RSTMGR_CTRL RSTMGR_GEN5_CTRL
>
> /*
> * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> index 452147b017..b602129656 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> @@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
> void socfpga_per_reset(u32 reset, int set);
> void socfpga_per_reset_all(void);
>
> -struct socfpga_reset_manager {
> - u32 status;
> - u32 mpu_rst_stat;
> - u32 misc_stat;
> - u32 padding1;
> - u32 hdsk_en;
> - u32 hdsk_req;
> - u32 hdsk_ack;
> - u32 hdsk_stall;
> - u32 mpumodrst;
> - u32 per0modrst;
> - u32 per1modrst;
> - u32 brgmodrst;
> - u32 padding2;
> - u32 cold_mod_reset;
> - u32 padding3;
> - u32 dbg_mod_reset;
> - u32 tap_mod_reset;
> - u32 padding4;
> - u32 padding5;
> - u32 brg_warm_mask;
> - u32 padding6[3];
> - u32 tst_stat;
> - u32 padding7;
> - u32 hdsk_timeout;
> - u32 mpul2flushtimeout;
> - u32 dbghdsktimeout;
> -};
> +#define RSTMGR_S10_STATUS 0
> +#define RSTMGR_S10_MPUMODRST 0x20
> +#define RSTMGR_S10_PER0MODRST 0x24
> +#define RSTMGR_S10_PER1MODRST 0x28
> +#define RSTMGR_S10_BRGMODRST 0x2c
>
> #define RSTMGR_MPUMODRST_CORE0 0
> #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 49dadd4c3d..901c432f82 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -22,6 +22,8 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +phys_addr_t socfpga_rstmgr_base __section(".data");
> +
> #ifdef CONFIG_SYS_L2_PL310
> static const struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> @@ -145,6 +147,8 @@ void socfpga_fpga_add(void *fpga_desc)
>
> int arch_cpu_init(void)
> {
> + socfpga_get_manager_addr();
> +
> #ifdef CONFIG_HW_WATCHDOG
> /*
> * In case the watchdog is enabled, make sure to (re-)configure it
> @@ -202,3 +206,31 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
> );
>
> #endif
> +
> +static phys_addr_t socfpga_get_base_addr(const char *compat)
> +{
> + const void *blob = gd->fdt_blob;
> + struct fdt_resource r;
> + int node;
> + int ret;
> +
> + node = fdt_node_offset_by_compatible(blob, -1, compat);
> + if (node < 0)
> + return 0;
> +
> + if (!fdtdec_get_is_enabled(blob, node))
> + return 0;
> +
> + ret = fdt_get_resource(blob, node, "reg", 0, &r);
> + if (ret)
> + return 0;
> +
> + return (phys_addr_t)r.start;
> +}
> +
> +void socfpga_get_manager_addr(void)
> +{
> + socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
> + if (!socfpga_rstmgr_base)
> + hang();
> +}
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index 31681b799d..b39a66562d 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -206,8 +206,6 @@ int arch_early_init_r(void)
> }
>
> #ifndef CONFIG_SPL_BUILD
> -static struct socfpga_reset_manager *reset_manager_base =
> - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> static struct socfpga_sdr_ctrl *sdr_ctrl =
> (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
>
> @@ -226,12 +224,13 @@ void do_bridge_reset(int enable, unsigned int mask)
>
> writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
> + writel(iswgrp_handoff[0],
> + socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> writel(iswgrp_handoff[1], &nic301_regs->remap);
> } else {
> writel(0, &sysmgr_regs->fpgaintfgrp_module);
> writel(0, &sdr_ctrl->fpgaport_rst);
> - writel(0, &reset_manager_base->brg_mod_reset);
> + writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> writel(1, &nic301_regs->remap);
> }
> }
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> index 471a3045af..4553653992 100644
> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -15,8 +15,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_reset_manager *reset_manager_base =
> - (void *)SOCFPGA_RSTMGR_ADDRESS;
> static const struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> @@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
> void socfpga_watchdog_disable(void)
> {
> /* assert reset for watchdog */
> - setbits_le32(&reset_manager_base->per1modrst,
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
> ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> }
>
> /* Release NOC ddr scheduler from reset */
> void socfpga_reset_deassert_noc_ddr_scheduler(void)
> {
> - clrbits_le32(&reset_manager_base->brgmodrst,
> + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
> ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
> }
>
> @@ -103,7 +101,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
> setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
>
> /* Release bridges from reset state per handoff value */
> - clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
> + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
>
> /* Poll until all idleack to 0, timeout at 1000ms */
> return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
> @@ -113,7 +111,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
> /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> void socfpga_reset_deassert_osc1wd0(void)
> {
> - clrbits_le32(&reset_manager_base->per1modrst,
> + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
> ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> }
>
> @@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
> */
> void socfpga_per_reset(u32 reset, int set)
> {
> - const u32 *reg;
> + unsigned long reg;
> u32 rstmgr_bank = RSTMGR_BANK(reset);
>
> switch (rstmgr_bank) {
> case 0:
> - reg = &reset_manager_base->mpumodrst;
> + reg = RSTMGR_A10_MPUMODRST;
> break;
> case 1:
> - reg = &reset_manager_base->per0modrst;
> + reg = RSTMGR_A10_PER0MODRST;
> break;
> case 2:
> - reg = &reset_manager_base->per1modrst;
> + reg = RSTMGR_A10_PER1MODRST;
> break;
> case 3:
> - reg = &reset_manager_base->brgmodrst;
> + reg = RSTMGR_A10_BRGMODRST;
> break;
> case 4:
> - reg = &reset_manager_base->sysmodrst;
> + reg = RSTMGR_A10_SYSMODRST;
> break;
>
> default:
> @@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
> }
>
> if (set)
> - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + setbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> else
> - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + clrbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> }
>
> /*
> @@ -174,11 +174,12 @@ void socfpga_per_reset_all(void)
> ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
>
> /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> - writel(~l4wd0, &reset_manager_base->per1modrst);
> - setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
> + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST);
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST,
> + ~mask_ecc_ocp);
>
> /* Finally disable the ECC_OCP */
> - setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST, mask_ecc_ocp);
> }
>
> int socfpga_bridges_reset(void)
> @@ -224,13 +225,13 @@ int socfpga_bridges_reset(void)
> return ret;
>
> /* Put all bridges (except NOR DDR scheduler) into reset state */
> - setbits_le32(&reset_manager_base->brgmodrst,
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
> (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
> - ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
> - ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
> - ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
> - ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
> - ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
> + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
>
> /* Disable NOC timeout */
> writel(0, &sysmgr_regs->noc_timeout);
> diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
> index 9a32f5abfe..ad31214711 100644
> --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> @@ -10,32 +10,30 @@
> #include <asm/arch/reset_manager.h>
> #include <asm/arch/system_manager.h>
>
> -static const struct socfpga_reset_manager *reset_manager_base =
> - (void *)SOCFPGA_RSTMGR_ADDRESS;
> static const struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> /* Assert or de-assert SoCFPGA reset manager reset. */
> void socfpga_per_reset(u32 reset, int set)
> {
> - const u32 *reg;
> + unsigned long reg;
> u32 rstmgr_bank = RSTMGR_BANK(reset);
>
> switch (rstmgr_bank) {
> case 0:
> - reg = &reset_manager_base->mpu_mod_reset;
> + reg = RSTMGR_GEN5_MPUMODRST;
> break;
> case 1:
> - reg = &reset_manager_base->per_mod_reset;
> + reg = RSTMGR_GEN5_PERMODRST;
> break;
> case 2:
> - reg = &reset_manager_base->per2_mod_reset;
> + reg = RSTMGR_GEN5_PER2MODRST;
> break;
> case 3:
> - reg = &reset_manager_base->brg_mod_reset;
> + reg = RSTMGR_GEN5_BRGMODRST;
> break;
> case 4:
> - reg = &reset_manager_base->misc_mod_reset;
> + reg = RSTMGR_GEN5_MISCMODRST;
> break;
>
> default:
> @@ -43,9 +41,11 @@ void socfpga_per_reset(u32 reset, int set)
> }
>
> if (set)
> - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + setbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> else
> - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + clrbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> }
>
> /*
> @@ -57,8 +57,8 @@ void socfpga_per_reset_all(void)
> {
> const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
>
> - writel(~l4wd0, &reset_manager_base->per_mod_reset);
> - writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_GEN5_PERMODRST);
> + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_GEN5_PER2MODRST);
> }
>
> #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
> @@ -95,7 +95,7 @@ void socfpga_bridges_reset(int enable)
>
> if (enable) {
> /* brdmodrst */
> - writel(0x7, &reset_manager_base->brg_mod_reset);
> + writel(0x7, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
> } else {
> socfpga_bridges_set_handoff_regs(false, false, false);
> @@ -109,7 +109,7 @@ void socfpga_bridges_reset(int enable)
> }
>
> /* brdmodrst */
> - writel(0, &reset_manager_base->brg_mod_reset);
> + writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
>
> /* Remap the bridges into memory map */
> writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> index 499a84aff5..b196d58d3d 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -12,31 +12,31 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_reset_manager *reset_manager_base =
> - (void *)SOCFPGA_RSTMGR_ADDRESS;
> static const struct socfpga_system_manager *system_manager_base =
> (void *)SOCFPGA_SYSMGR_ADDRESS;
>
> /* Assert or de-assert SoCFPGA reset manager reset. */
> void socfpga_per_reset(u32 reset, int set)
> {
> - const void *reg;
> + unsigned long reg;
>
> if (RSTMGR_BANK(reset) == 0)
> - reg = &reset_manager_base->mpumodrst;
> + reg = RSTMGR_S10_MPUMODRST;
> else if (RSTMGR_BANK(reset) == 1)
> - reg = &reset_manager_base->per0modrst;
> + reg = RSTMGR_S10_PER0MODRST;
> else if (RSTMGR_BANK(reset) == 2)
> - reg = &reset_manager_base->per1modrst;
> + reg = RSTMGR_S10_PER1MODRST;
> else if (RSTMGR_BANK(reset) == 3)
> - reg = &reset_manager_base->brgmodrst;
> + reg = RSTMGR_S10_BRGMODRST;
> else /* Invalid reset register, do nothing */
> return;
>
> if (set)
> - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + setbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> else
> - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> + clrbits_le32(socfpga_rstmgr_base + reg,
> + 1 << RSTMGR_RESET(reset));
> }
>
> /*
> @@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
>
> /* disable all except OCP and l4wd0. OCP disable later */
> writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
> - &reset_manager_base->per0modrst);
> - writel(~l4wd0, &reset_manager_base->per0modrst);
> - writel(0xffffffff, &reset_manager_base->per1modrst);
> + socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
> }
>
> void socfpga_bridges_reset(int enable)
> @@ -62,7 +62,7 @@ void socfpga_bridges_reset(int enable)
> setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
>
> /* Release all bridges from reset state */
> - clrbits_le32(&reset_manager_base->brgmodrst, ~0);
> + clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
>
> /* Poll until all idleack to 0 */
> while (readl(&system_manager_base->noc_idleack))
> @@ -85,9 +85,9 @@ void socfpga_bridges_reset(int enable)
> ;
>
> /* Reset all bridges (except NOR DDR scheduler & F2S) */
> - setbits_le32(&reset_manager_base->brgmodrst,
> + setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
> ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
> - RSTMGR_BRGMODRST_FPGA2SOC_MASK));
> + RSTMGR_BRGMODRST_FPGA2SOC_MASK));
>
> /* Disable NOC timeout */
> writel(0, &system_manager_base->noc_timeout);
> @@ -99,6 +99,6 @@ void socfpga_bridges_reset(int enable)
> */
> int cpu_has_been_warmreset(void)
> {
> - return readl(&reset_manager_base->status) &
> - RSTMGR_L4WD_MPU_WARMRESET_MASK;
> + return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
> + RSTMGR_L4WD_MPU_WARMRESET_MASK;
> }
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
> index b820cb0673..a0d80fd47e 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -106,6 +106,11 @@ void spl_board_init(void)
>
> void board_init_f(ulong dummy)
> {
> + if (spl_early_init())
> + hang();
> +
> + socfpga_get_manager_addr();
> +
> dcache_disable();
>
> socfpga_init_security_policies();
> @@ -116,8 +121,6 @@ void board_init_f(ulong dummy)
> socfpga_per_reset_all();
> socfpga_watchdog_disable();
>
> - spl_early_init();
> -
> /* Configure the clock based on handoff */
> cm_basic_init(gd->fdt_blob);
>
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index 47e63709ad..9ee053da3a 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -67,6 +67,12 @@ void board_init_f(ulong dummy)
> int ret;
> struct udevice *dev;
>
> + ret = spl_early_init();
> + if (ret)
> + hang();
> +
> + socfpga_get_manager_addr();
> +
> /*
> * First C code to run. Clear fake OCRAM ECC first as SBE
> * and DBE might triggered during power on
> @@ -128,12 +134,6 @@ void board_init_f(ulong dummy)
> debug_uart_init();
> #endif
>
> - ret = spl_early_init();
> - if (ret) {
> - debug("spl_early_init() failed: %d\n", ret);
> - hang();
> - }
> -
> ret = uclass_get_device(UCLASS_RESET, 0, &dev);
> if (ret)
> debug("Reset init failed: %d\n", ret);
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index ec65e1ce64..9a97a84e1e 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -14,6 +14,7 @@
> #include <asm/arch/clock_manager.h>
> #include <asm/arch/firewall_s10.h>
> #include <asm/arch/mailbox_s10.h>
> +#include <asm/arch/misc.h>
> #include <asm/arch/reset_manager.h>
> #include <asm/arch/system_manager.h>
> #include <watchdog.h>
> @@ -120,6 +121,12 @@ void board_init_f(ulong dummy)
> const struct cm_config *cm_default_cfg = cm_get_default_config();
> int ret;
>
> + ret = spl_early_init();
> + if (ret)
> + hang();
> +
> + socfpga_get_manager_addr();
> +
> #ifdef CONFIG_HW_WATCHDOG
> /* Ensure watchdog is paused when debugging is happening */
> writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> @@ -145,11 +152,6 @@ void board_init_f(ulong dummy)
> socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> debug_uart_init();
> #endif
> - ret = spl_early_init();
> - if (ret) {
> - debug("spl_early_init() failed: %d\n", ret);
> - hang();
> - }
>
> preloader_console_init();
> cm_print_clock_quick_summary();
> diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
> index d6c26a5b23..3390b7bdc2 100644
> --- a/drivers/sysreset/sysreset_socfpga.c
> +++ b/drivers/sysreset/sysreset_socfpga.c
> @@ -12,7 +12,7 @@
> #include <asm/arch/reset_manager.h>
>
> struct socfpga_sysreset_data {
> - struct socfpga_reset_manager *rstmgr_base;
> + void __iomem *rstmgr_base;
> };
>
> static int socfpga_sysreset_request(struct udevice *dev,
> @@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
> switch (type) {
> case SYSRESET_WARM:
> writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
> - &data->rstmgr_base->ctrl);
> + data->rstmgr_base + RSTMGR_CTRL);
> break;
> case SYSRESET_COLD:
> writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
> - &data->rstmgr_base->ctrl);
> + data->rstmgr_base + RSTMGR_CTRL);
> break;
> default:
> return -EPROTONOSUPPORT;
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines
2019-10-02 9:20 ` Simon Goldschmidt
@ 2019-10-04 3:03 ` Ley Foon Tan
0 siblings, 0 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-10-04 3:03 UTC (permalink / raw)
To: u-boot
On Wed, Oct 2, 2019 at 5:20 PM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> >
> > Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
> > to defines.
> > No functional change.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> >
> > ---
> > v2:
> > - Get base address from DT
>
> Wait, "no functional change", yet you now read the base address from DT?
> I think that's a good idea, but could you do it in a separate patch?
>
Will remove "No functional change" in commit message. To convert from
struct to defines, we need use DT address.
Regards
Ley Foon
>
> > - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> > - Add prefix to defines.
> > ---
> > arch/arm/mach-socfpga/include/mach/misc.h | 1 +
> > .../mach-socfpga/include/mach/reset_manager.h | 2 +
> > .../include/mach/reset_manager_arria10.h | 43 ++++-------------
> > .../include/mach/reset_manager_gen5.h | 22 ++++-----
> > .../include/mach/reset_manager_s10.h | 33 ++-----------
> > arch/arm/mach-socfpga/misc.c | 32 +++++++++++++
> > arch/arm/mach-socfpga/misc_gen5.c | 7 ++-
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 47 ++++++++++---------
> > arch/arm/mach-socfpga/reset_manager_gen5.c | 28 +++++------
> > arch/arm/mach-socfpga/reset_manager_s10.c | 34 +++++++-------
> > arch/arm/mach-socfpga/spl_a10.c | 7 ++-
> > arch/arm/mach-socfpga/spl_gen5.c | 12 ++---
> > arch/arm/mach-socfpga/spl_s10.c | 12 +++--
> > drivers/sysreset/sysreset_socfpga.c | 6 +--
> > 14 files changed, 137 insertions(+), 149 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
> > index 27d0b6a370..a29b049742 100644
> > --- a/arch/arm/mach-socfpga/include/mach/misc.h
> > +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> > @@ -41,5 +41,6 @@ void socfpga_sdram_remap_zero(void);
> >
> > void do_bridge_reset(int enable, unsigned int mask);
> > void socfpga_pl310_clear(void);
> > +void socfpga_get_manager_addr(void);
> >
> > #endif /* _MISC_H_ */
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 6ad037e325..a5b6931350 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -6,6 +6,8 @@
> > #ifndef _RESET_MANAGER_H_
> > #define _RESET_MANAGER_H_
> >
> > +extern phys_addr_t socfpga_rstmgr_base;
> > +
> > void reset_cpu(ulong addr);
> >
> > void socfpga_per_reset(u32 reset, int set);
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > index 6623ebee65..41169aa677 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > @@ -14,40 +14,15 @@ int socfpga_reset_deassert_bridges_handoff(void);
> > void socfpga_reset_deassert_osc1wd0(void);
> > int socfpga_bridges_reset(void);
> >
> > -struct socfpga_reset_manager {
> > - u32 stat;
> > - u32 ramstat;
> > - u32 miscstat;
> > - u32 ctrl;
> > - u32 hdsken;
> > - u32 hdskreq;
> > - u32 hdskack;
> > - u32 counts;
> > - u32 mpumodrst;
> > - u32 per0modrst;
> > - u32 per1modrst;
> > - u32 brgmodrst;
> > - u32 sysmodrst;
> > - u32 coldmodrst;
> > - u32 nrstmodrst;
> > - u32 dbgmodrst;
> > - u32 mpuwarmmask;
> > - u32 per0warmmask;
> > - u32 per1warmmask;
> > - u32 brgwarmmask;
> > - u32 syswarmmask;
> > - u32 nrstwarmmask;
> > - u32 l3warmmask;
> > - u32 tststa;
> > - u32 tstscratch;
> > - u32 hdsktimeout;
> > - u32 hmcintr;
> > - u32 hmcintren;
> > - u32 hmcintrens;
> > - u32 hmcintrenr;
> > - u32 hmcgpout;
> > - u32 hmcgpin;
> > -};
> > +#define RSTMGR_A10_STATUS 0
> > +#define RSTMGR_A10_CTRL 0xc
> > +#define RSTMGR_A10_MPUMODRST 0x20
> > +#define RSTMGR_A10_PER0MODRST 0x24
> > +#define RSTMGR_A10_PER1MODRST 0x28
> > +#define RSTMGR_A10_BRGMODRST 0x2c
> > +#define RSTMGR_A10_SYSMODRST 0x30
> > +
> > +#define RSTMGR_CTRL RSTMGR_A10_CTRL
> >
> > /*
> > * SocFPGA Arria10 reset IDs, bank mapping is as follows:
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > index f4dcb14623..e51ebfd08f 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > @@ -11,19 +11,15 @@
> > void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h);
> > void socfpga_bridges_reset(int enable);
> >
> > -struct socfpga_reset_manager {
> > - u32 status;
> > - u32 ctrl;
> > - u32 counts;
> > - u32 padding1;
> > - u32 mpu_mod_reset;
> > - u32 per_mod_reset;
> > - u32 per2_mod_reset;
> > - u32 brg_mod_reset;
> > - u32 misc_mod_reset;
> > - u32 padding2[12];
> > - u32 tstscratch;
> > -};
> > +#define RSTMGR_GEN5_STATUS 0
> > +#define RSTMGR_GEN5_CTRL 4
> > +#define RSTMGR_GEN5_MPUMODRST 0x10
> > +#define RSTMGR_GEN5_PERMODRST 0x14
> > +#define RSTMGR_GEN5_PER2MODRST 0x18
> > +#define RSTMGR_GEN5_BRGMODRST 0x1c
> > +#define RSTMGR_GEN5_MISCMODRST 0x20
> > +
> > +#define RSTMGR_CTRL RSTMGR_GEN5_CTRL
> >
> > /*
> > * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> > index 452147b017..b602129656 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h
> > @@ -15,34 +15,11 @@ void socfpga_bridges_reset(int enable);
> > void socfpga_per_reset(u32 reset, int set);
> > void socfpga_per_reset_all(void);
> >
> > -struct socfpga_reset_manager {
> > - u32 status;
> > - u32 mpu_rst_stat;
> > - u32 misc_stat;
> > - u32 padding1;
> > - u32 hdsk_en;
> > - u32 hdsk_req;
> > - u32 hdsk_ack;
> > - u32 hdsk_stall;
> > - u32 mpumodrst;
> > - u32 per0modrst;
> > - u32 per1modrst;
> > - u32 brgmodrst;
> > - u32 padding2;
> > - u32 cold_mod_reset;
> > - u32 padding3;
> > - u32 dbg_mod_reset;
> > - u32 tap_mod_reset;
> > - u32 padding4;
> > - u32 padding5;
> > - u32 brg_warm_mask;
> > - u32 padding6[3];
> > - u32 tst_stat;
> > - u32 padding7;
> > - u32 hdsk_timeout;
> > - u32 mpul2flushtimeout;
> > - u32 dbghdsktimeout;
> > -};
> > +#define RSTMGR_S10_STATUS 0
> > +#define RSTMGR_S10_MPUMODRST 0x20
> > +#define RSTMGR_S10_PER0MODRST 0x24
> > +#define RSTMGR_S10_PER1MODRST 0x28
> > +#define RSTMGR_S10_BRGMODRST 0x2c
> >
> > #define RSTMGR_MPUMODRST_CORE0 0
> > #define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > index 49dadd4c3d..901c432f82 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -22,6 +22,8 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +phys_addr_t socfpga_rstmgr_base __section(".data");
> > +
> > #ifdef CONFIG_SYS_L2_PL310
> > static const struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > @@ -145,6 +147,8 @@ void socfpga_fpga_add(void *fpga_desc)
> >
> > int arch_cpu_init(void)
> > {
> > + socfpga_get_manager_addr();
> > +
> > #ifdef CONFIG_HW_WATCHDOG
> > /*
> > * In case the watchdog is enabled, make sure to (re-)configure it
> > @@ -202,3 +206,31 @@ U_BOOT_CMD(bridge, 3, 1, do_bridge,
> > );
> >
> > #endif
> > +
> > +static phys_addr_t socfpga_get_base_addr(const char *compat)
> > +{
> > + const void *blob = gd->fdt_blob;
> > + struct fdt_resource r;
> > + int node;
> > + int ret;
> > +
> > + node = fdt_node_offset_by_compatible(blob, -1, compat);
> > + if (node < 0)
> > + return 0;
> > +
> > + if (!fdtdec_get_is_enabled(blob, node))
> > + return 0;
> > +
> > + ret = fdt_get_resource(blob, node, "reg", 0, &r);
> > + if (ret)
> > + return 0;
> > +
> > + return (phys_addr_t)r.start;
> > +}
> > +
> > +void socfpga_get_manager_addr(void)
> > +{
> > + socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
> > + if (!socfpga_rstmgr_base)
> > + hang();
> > +}
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> > index 31681b799d..b39a66562d 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -206,8 +206,6 @@ int arch_early_init_r(void)
> > }
> >
> > #ifndef CONFIG_SPL_BUILD
> > -static struct socfpga_reset_manager *reset_manager_base =
> > - (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
> > static struct socfpga_sdr_ctrl *sdr_ctrl =
> > (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
> >
> > @@ -226,12 +224,13 @@ void do_bridge_reset(int enable, unsigned int mask)
> >
> > writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
> > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> > - writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
> > + writel(iswgrp_handoff[0],
> > + socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(iswgrp_handoff[1], &nic301_regs->remap);
> > } else {
> > writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > writel(0, &sdr_ctrl->fpgaport_rst);
> > - writel(0, &reset_manager_base->brg_mod_reset);
> > + writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(1, &nic301_regs->remap);
> > }
> > }
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 471a3045af..4553653992 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -15,8 +15,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_reset_manager *reset_manager_base =
> > - (void *)SOCFPGA_RSTMGR_ADDRESS;
> > static const struct socfpga_system_manager *sysmgr_regs =
> > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > @@ -63,14 +61,14 @@ static const struct bridge_cfg bridge_cfg_tbl[] = {
> > void socfpga_watchdog_disable(void)
> > {
> > /* assert reset for watchdog */
> > - setbits_le32(&reset_manager_base->per1modrst,
> > + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
> > ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> > }
> >
> > /* Release NOC ddr scheduler from reset */
> > void socfpga_reset_deassert_noc_ddr_scheduler(void)
> > {
> > - clrbits_le32(&reset_manager_base->brgmodrst,
> > + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
> > ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
> > }
> >
> > @@ -103,7 +101,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
> > setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
> >
> > /* Release bridges from reset state per handoff value */
> > - clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
> > + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
> >
> > /* Poll until all idleack to 0, timeout at 1000ms */
> > return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
> > @@ -113,7 +111,7 @@ int socfpga_reset_deassert_bridges_handoff(void)
> > /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> > void socfpga_reset_deassert_osc1wd0(void)
> > {
> > - clrbits_le32(&reset_manager_base->per1modrst,
> > + clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST,
> > ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
> > }
> >
> > @@ -122,24 +120,24 @@ void socfpga_reset_deassert_osc1wd0(void)
> > */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > - const u32 *reg;
> > + unsigned long reg;
> > u32 rstmgr_bank = RSTMGR_BANK(reset);
> >
> > switch (rstmgr_bank) {
> > case 0:
> > - reg = &reset_manager_base->mpumodrst;
> > + reg = RSTMGR_A10_MPUMODRST;
> > break;
> > case 1:
> > - reg = &reset_manager_base->per0modrst;
> > + reg = RSTMGR_A10_PER0MODRST;
> > break;
> > case 2:
> > - reg = &reset_manager_base->per1modrst;
> > + reg = RSTMGR_A10_PER1MODRST;
> > break;
> > case 3:
> > - reg = &reset_manager_base->brgmodrst;
> > + reg = RSTMGR_A10_BRGMODRST;
> > break;
> > case 4:
> > - reg = &reset_manager_base->sysmodrst;
> > + reg = RSTMGR_A10_SYSMODRST;
> > break;
> >
> > default:
> > @@ -147,9 +145,11 @@ void socfpga_per_reset(u32 reset, int set)
> > }
> >
> > if (set)
> > - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + setbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > else
> > - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + clrbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > }
> >
> > /*
> > @@ -174,11 +174,12 @@ void socfpga_per_reset_all(void)
> > ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> >
> > /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
> > - writel(~l4wd0, &reset_manager_base->per1modrst);
> > - setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
> > + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_A10_PER1MODRST);
> > + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST,
> > + ~mask_ecc_ocp);
> >
> > /* Finally disable the ECC_OCP */
> > - setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
> > + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_PER0MODRST, mask_ecc_ocp);
> > }
> >
> > int socfpga_bridges_reset(void)
> > @@ -224,13 +225,13 @@ int socfpga_bridges_reset(void)
> > return ret;
> >
> > /* Put all bridges (except NOR DDR scheduler) into reset state */
> > - setbits_le32(&reset_manager_base->brgmodrst,
> > + setbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST,
> > (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
> > - ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
> > - ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
> > - ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
> > - ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
> > - ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> > + ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
> > + ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
> > + ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
> > + ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
> > + ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> >
> > /* Disable NOC timeout */
> > writel(0, &sysmgr_regs->noc_timeout);
> > diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > index 9a32f5abfe..ad31214711 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > @@ -10,32 +10,30 @@
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > -static const struct socfpga_reset_manager *reset_manager_base =
> > - (void *)SOCFPGA_RSTMGR_ADDRESS;
> > static const struct socfpga_system_manager *sysmgr_regs =
> > (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > - const u32 *reg;
> > + unsigned long reg;
> > u32 rstmgr_bank = RSTMGR_BANK(reset);
> >
> > switch (rstmgr_bank) {
> > case 0:
> > - reg = &reset_manager_base->mpu_mod_reset;
> > + reg = RSTMGR_GEN5_MPUMODRST;
> > break;
> > case 1:
> > - reg = &reset_manager_base->per_mod_reset;
> > + reg = RSTMGR_GEN5_PERMODRST;
> > break;
> > case 2:
> > - reg = &reset_manager_base->per2_mod_reset;
> > + reg = RSTMGR_GEN5_PER2MODRST;
> > break;
> > case 3:
> > - reg = &reset_manager_base->brg_mod_reset;
> > + reg = RSTMGR_GEN5_BRGMODRST;
> > break;
> > case 4:
> > - reg = &reset_manager_base->misc_mod_reset;
> > + reg = RSTMGR_GEN5_MISCMODRST;
> > break;
> >
> > default:
> > @@ -43,9 +41,11 @@ void socfpga_per_reset(u32 reset, int set)
> > }
> >
> > if (set)
> > - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + setbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > else
> > - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + clrbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > }
> >
> > /*
> > @@ -57,8 +57,8 @@ void socfpga_per_reset_all(void)
> > {
> > const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
> >
> > - writel(~l4wd0, &reset_manager_base->per_mod_reset);
> > - writel(0xffffffff, &reset_manager_base->per2_mod_reset);
> > + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_GEN5_PERMODRST);
> > + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_GEN5_PER2MODRST);
> > }
> >
> > #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
> > @@ -95,7 +95,7 @@ void socfpga_bridges_reset(int enable)
> >
> > if (enable) {
> > /* brdmodrst */
> > - writel(0x7, &reset_manager_base->brg_mod_reset);
> > + writel(0x7, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
> > } else {
> > socfpga_bridges_set_handoff_regs(false, false, false);
> > @@ -109,7 +109,7 @@ void socfpga_bridges_reset(int enable)
> > }
> >
> > /* brdmodrst */
> > - writel(0, &reset_manager_base->brg_mod_reset);
> > + writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> >
> > /* Remap the bridges into memory map */
> > writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
> > diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> > index 499a84aff5..b196d58d3d 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> > @@ -12,31 +12,31 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_reset_manager *reset_manager_base =
> > - (void *)SOCFPGA_RSTMGR_ADDRESS;
> > static const struct socfpga_system_manager *system_manager_base =
> > (void *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > - const void *reg;
> > + unsigned long reg;
> >
> > if (RSTMGR_BANK(reset) == 0)
> > - reg = &reset_manager_base->mpumodrst;
> > + reg = RSTMGR_S10_MPUMODRST;
> > else if (RSTMGR_BANK(reset) == 1)
> > - reg = &reset_manager_base->per0modrst;
> > + reg = RSTMGR_S10_PER0MODRST;
> > else if (RSTMGR_BANK(reset) == 2)
> > - reg = &reset_manager_base->per1modrst;
> > + reg = RSTMGR_S10_PER1MODRST;
> > else if (RSTMGR_BANK(reset) == 3)
> > - reg = &reset_manager_base->brgmodrst;
> > + reg = RSTMGR_S10_BRGMODRST;
> > else /* Invalid reset register, do nothing */
> > return;
> >
> > if (set)
> > - setbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + setbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > else
> > - clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
> > + clrbits_le32(socfpga_rstmgr_base + reg,
> > + 1 << RSTMGR_RESET(reset));
> > }
> >
> > /*
> > @@ -50,9 +50,9 @@ void socfpga_per_reset_all(void)
> >
> > /* disable all except OCP and l4wd0. OCP disable later */
> > writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
> > - &reset_manager_base->per0modrst);
> > - writel(~l4wd0, &reset_manager_base->per0modrst);
> > - writel(0xffffffff, &reset_manager_base->per1modrst);
> > + socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> > + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);
> > + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
> > }
> >
> > void socfpga_bridges_reset(int enable)
> > @@ -62,7 +62,7 @@ void socfpga_bridges_reset(int enable)
> > setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
> >
> > /* Release all bridges from reset state */
> > - clrbits_le32(&reset_manager_base->brgmodrst, ~0);
> > + clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
> >
> > /* Poll until all idleack to 0 */
> > while (readl(&system_manager_base->noc_idleack))
> > @@ -85,9 +85,9 @@ void socfpga_bridges_reset(int enable)
> > ;
> >
> > /* Reset all bridges (except NOR DDR scheduler & F2S) */
> > - setbits_le32(&reset_manager_base->brgmodrst,
> > + setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
> > ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
> > - RSTMGR_BRGMODRST_FPGA2SOC_MASK));
> > + RSTMGR_BRGMODRST_FPGA2SOC_MASK));
> >
> > /* Disable NOC timeout */
> > writel(0, &system_manager_base->noc_timeout);
> > @@ -99,6 +99,6 @@ void socfpga_bridges_reset(int enable)
> > */
> > int cpu_has_been_warmreset(void)
> > {
> > - return readl(&reset_manager_base->status) &
> > - RSTMGR_L4WD_MPU_WARMRESET_MASK;
> > + return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
> > + RSTMGR_L4WD_MPU_WARMRESET_MASK;
> > }
> > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
> > index b820cb0673..a0d80fd47e 100644
> > --- a/arch/arm/mach-socfpga/spl_a10.c
> > +++ b/arch/arm/mach-socfpga/spl_a10.c
> > @@ -106,6 +106,11 @@ void spl_board_init(void)
> >
> > void board_init_f(ulong dummy)
> > {
> > + if (spl_early_init())
> > + hang();
> > +
> > + socfpga_get_manager_addr();
> > +
> > dcache_disable();
> >
> > socfpga_init_security_policies();
> > @@ -116,8 +121,6 @@ void board_init_f(ulong dummy)
> > socfpga_per_reset_all();
> > socfpga_watchdog_disable();
> >
> > - spl_early_init();
> > -
> > /* Configure the clock based on handoff */
> > cm_basic_init(gd->fdt_blob);
> >
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> > index 47e63709ad..9ee053da3a 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -67,6 +67,12 @@ void board_init_f(ulong dummy)
> > int ret;
> > struct udevice *dev;
> >
> > + ret = spl_early_init();
> > + if (ret)
> > + hang();
> > +
> > + socfpga_get_manager_addr();
> > +
> > /*
> > * First C code to run. Clear fake OCRAM ECC first as SBE
> > * and DBE might triggered during power on
> > @@ -128,12 +134,6 @@ void board_init_f(ulong dummy)
> > debug_uart_init();
> > #endif
> >
> > - ret = spl_early_init();
> > - if (ret) {
> > - debug("spl_early_init() failed: %d\n", ret);
> > - hang();
> > - }
> > -
> > ret = uclass_get_device(UCLASS_RESET, 0, &dev);
> > if (ret)
> > debug("Reset init failed: %d\n", ret);
> > diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> > index ec65e1ce64..9a97a84e1e 100644
> > --- a/arch/arm/mach-socfpga/spl_s10.c
> > +++ b/arch/arm/mach-socfpga/spl_s10.c
> > @@ -14,6 +14,7 @@
> > #include <asm/arch/clock_manager.h>
> > #include <asm/arch/firewall_s10.h>
> > #include <asm/arch/mailbox_s10.h>
> > +#include <asm/arch/misc.h>
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> > #include <watchdog.h>
> > @@ -120,6 +121,12 @@ void board_init_f(ulong dummy)
> > const struct cm_config *cm_default_cfg = cm_get_default_config();
> > int ret;
> >
> > + ret = spl_early_init();
> > + if (ret)
> > + hang();
> > +
> > + socfpga_get_manager_addr();
> > +
> > #ifdef CONFIG_HW_WATCHDOG
> > /* Ensure watchdog is paused when debugging is happening */
> > writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> > @@ -145,11 +152,6 @@ void board_init_f(ulong dummy)
> > socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > debug_uart_init();
> > #endif
> > - ret = spl_early_init();
> > - if (ret) {
> > - debug("spl_early_init() failed: %d\n", ret);
> > - hang();
> > - }
> >
> > preloader_console_init();
> > cm_print_clock_quick_summary();
> > diff --git a/drivers/sysreset/sysreset_socfpga.c b/drivers/sysreset/sysreset_socfpga.c
> > index d6c26a5b23..3390b7bdc2 100644
> > --- a/drivers/sysreset/sysreset_socfpga.c
> > +++ b/drivers/sysreset/sysreset_socfpga.c
> > @@ -12,7 +12,7 @@
> > #include <asm/arch/reset_manager.h>
> >
> > struct socfpga_sysreset_data {
> > - struct socfpga_reset_manager *rstmgr_base;
> > + void __iomem *rstmgr_base;
> > };
> >
> > static int socfpga_sysreset_request(struct udevice *dev,
> > @@ -23,11 +23,11 @@ static int socfpga_sysreset_request(struct udevice *dev,
> > switch (type) {
> > case SYSRESET_WARM:
> > writel(BIT(RSTMGR_CTRL_SWWARMRSTREQ_LSB),
> > - &data->rstmgr_base->ctrl);
> > + data->rstmgr_base + RSTMGR_CTRL);
> > break;
> > case SYSRESET_COLD:
> > writel(BIT(RSTMGR_CTRL_SWCOLDRSTREQ_LSB),
> > - &data->rstmgr_base->ctrl);
> > + data->rstmgr_base + RSTMGR_CTRL);
> > break;
> > default:
> > return -EPROTONOSUPPORT;
> > --
> > 2.19.0
> >
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system manager from struct to defines
2019-09-10 8:37 [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines Ley Foon Tan
2019-09-10 8:38 ` [U-Boot] [PATCH v2 1/4] arm: dts: socfpga: Add u-boot, dm-pre-reloc for sysmgr and clkmgr nodes Ley Foon Tan
2019-09-10 8:38 ` [U-Boot] [PATCH v2 2/4] arm: socfpga: Convert reset manager from struct to defines Ley Foon Tan
@ 2019-09-10 8:38 ` Ley Foon Tan
2019-10-02 9:20 ` Simon Goldschmidt
2019-09-10 8:38 ` [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock " Ley Foon Tan
2019-09-17 22:33 ` [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers " Dinh Nguyen
4 siblings, 1 reply; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-10 8:38 UTC (permalink / raw)
To: u-boot
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
No functional change.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
v2:
- Change to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socfpga/clock_manager_s10.c | 4 +-
.../include/mach/system_manager.h | 2 +
.../include/mach/system_manager_arria10.h | 94 +++------
.../include/mach/system_manager_gen5.h | 123 +++---------
.../include/mach/system_manager_s10.h | 184 +++++++-----------
arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
arch/arm/mach-socfpga/misc.c | 5 +
arch/arm/mach-socfpga/misc_arria10.c | 9 +-
arch/arm/mach-socfpga/misc_gen5.c | 22 ++-
arch/arm/mach-socfpga/misc_s10.c | 9 +-
arch/arm/mach-socfpga/reset_manager_arria10.c | 24 +--
arch/arm/mach-socfpga/reset_manager_gen5.c | 7 +-
arch/arm/mach-socfpga/reset_manager_s10.c | 18 +-
arch/arm/mach-socfpga/scan_manager.c | 6 +-
arch/arm/mach-socfpga/spl_a10.c | 5 +-
arch/arm/mach-socfpga/spl_gen5.c | 11 +-
arch/arm/mach-socfpga/spl_s10.c | 12 +-
arch/arm/mach-socfpga/system_manager_gen5.c | 38 ++--
arch/arm/mach-socfpga/system_manager_s10.c | 39 ++--
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 11 +-
drivers/ddr/altera/sdram_gen5.c | 10 +-
drivers/ddr/altera/sdram_s10.c | 6 +-
drivers/fpga/socfpga_arria10.c | 7 +-
drivers/fpga/socfpga_gen5.c | 4 +-
drivers/mmc/socfpga_dw_mmc.c | 6 +-
25 files changed, 240 insertions(+), 422 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 3ba2a00c02..6cbf07ac6f 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/*
* function to write the bypass register which requires a poll of the
@@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
unsigned int cm_get_qspi_controller_clk_hz(void)
{
- return readl(&sysmgr_regs->boot_scratch_cold0);
+ return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
}
unsigned int cm_get_spi_controller_clk_hz(void)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
index 7e76df74b7..803305eb35 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
@@ -6,6 +6,8 @@
#ifndef _SYSTEM_MANAGER_H_
#define _SYSTEM_MANAGER_H_
+extern phys_addr_t socfpga_sysmgr_base;
+
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include <asm/arch/system_manager_s10.h>
#else
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 14052b957c..1a45c0f134 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -6,73 +6,33 @@
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
#define _SYSTEM_MANAGER_ARRIA10_H_
-struct socfpga_system_manager {
- u32 siliconid1;
- u32 siliconid2;
- u32 wddbg;
- u32 bootinfo;
- u32 mpu_ctrl_l2_ecc;
- u32 _pad_0x14_0x1f[3];
- u32 dma;
- u32 dma_periph;
- u32 sdmmcgrp_ctrl;
- u32 sdmmc_l3master;
- u32 nand_bootstrap;
- u32 nand_l3master;
- u32 usb0_l3master;
- u32 usb1_l3master;
- u32 emac_global;
- u32 emac[3];
- u32 _pad_0x50_0x5f[4];
- u32 fpgaintf_en_global;
- u32 fpgaintf_en_0;
- u32 fpgaintf_en_1;
- u32 fpgaintf_en_2;
- u32 fpgaintf_en_3;
- u32 _pad_0x74_0x7f[3];
- u32 noc_addr_remap_value;
- u32 noc_addr_remap_set;
- u32 noc_addr_remap_clear;
- u32 _pad_0x8c_0x8f;
- u32 ecc_intmask_value;
- u32 ecc_intmask_set;
- u32 ecc_intmask_clr;
- u32 ecc_intstatus_serr;
- u32 ecc_intstatus_derr;
- u32 mpu_status_l2_ecc;
- u32 mpu_clear_l2_ecc;
- u32 mpu_status_l1_parity;
- u32 mpu_clear_l1_parity;
- u32 mpu_set_l1_parity;
- u32 _pad_0xb8_0xbf[2];
- u32 noc_timeout;
- u32 noc_idlereq_set;
- u32 noc_idlereq_clr;
- u32 noc_idlereq_value;
- u32 noc_idleack;
- u32 noc_idlestatus;
- u32 fpga2soc_ctrl;
- u32 _pad_0xdc_0xff[9];
- u32 tsmc_tsel_0;
- u32 tsmc_tsel_1;
- u32 tsmc_tsel_2;
- u32 tsmc_tsel_3;
- u32 _pad_0x110_0x200[60];
- u32 romhw_ctrl;
- u32 romcode_ctrl;
- u32 romcode_cpu1startaddr;
- u32 romcode_initswstate;
- u32 romcode_initswlastld;
- u32 _pad_0x214_0x217;
- u32 warmram_enable;
- u32 warmram_datastart;
- u32 warmram_length;
- u32 warmram_execution;
- u32 warmram_crc;
- u32 _pad_0x22c_0x22f;
- u32 isw_handoff[8];
- u32 romcode_bootromswstate[8];
-};
+#define SYSMGR_A10_WDDBG 0x8
+#define SYSMGR_A10_BOOTINFO 0xc
+#define SYSMGR_A10_DMA 0x20
+#define SYSMGR_A10_DMA_PERIPH 0x24
+#define SYSMGR_A10_SDMMC 0x28
+#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
+#define SYSMGR_A10_EMAC_GLOBAL 0x40
+#define SYSMGR_A10_EMAC0 0x44
+#define SYSMGR_A10_EMAC1 0x48
+#define SYSMGR_A10_EMAC2 0x4c
+#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
+#define SYSMGR_A10_FPGAINTF_EN0 0x64
+#define SYSMGR_A10_FPGAINTF_EN1 0x68
+#define SYSMGR_A10_FPGAINTF_EN2 0x6c
+#define SYSMGR_A10_FPGAINTF_EN3 0x70
+#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
+#define SYSMGR_A10_ECC_INTMASK_SET 0x94
+#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
+#define SYSMGR_A10_NOC_TIMEOUT 0xc0
+#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
+#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
+#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
+#define SYSMGR_A10_NOC_IDLEACK 0xd0
+#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
+#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
+
+#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
index 52e59df513..90cb465d13 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
@@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable);
void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
-struct socfpga_system_manager {
- /* System Manager Module */
- u32 siliconid1; /* 0x00 */
- u32 siliconid2;
- u32 _pad_0x8_0xf[2];
- u32 wddbg; /* 0x10 */
- u32 bootinfo;
- u32 hpsinfo;
- u32 parityinj;
- /* FPGA Interface Group */
- u32 fpgaintfgrp_gbl; /* 0x20 */
- u32 fpgaintfgrp_indiv;
- u32 fpgaintfgrp_module;
- u32 _pad_0x2c_0x2f;
- /* Scan Manager Group */
- u32 scanmgrgrp_ctrl; /* 0x30 */
- u32 _pad_0x34_0x3f[3];
- /* Freeze Control Group */
- u32 frzctrl_vioctrl; /* 0x40 */
- u32 _pad_0x44_0x4f[3];
- u32 frzctrl_hioctrl; /* 0x50 */
- u32 frzctrl_src;
- u32 frzctrl_hwctrl;
- u32 _pad_0x5c_0x5f;
- /* EMAC Group */
- u32 emacgrp_ctrl; /* 0x60 */
- u32 emacgrp_l3master;
- u32 _pad_0x68_0x6f[2];
- /* DMA Controller Group */
- u32 dmagrp_ctrl; /* 0x70 */
- u32 dmagrp_persecurity;
- u32 _pad_0x78_0x7f[2];
- /* Preloader (initial software) Group */
- u32 iswgrp_handoff[8]; /* 0x80 */
- u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
- /* Boot ROM Code Register Group */
- u32 romcodegrp_ctrl; /* 0xc0 */
- u32 romcodegrp_cpu1startaddr;
- u32 romcodegrp_initswstate;
- u32 romcodegrp_initswlastld;
- u32 romcodegrp_bootromswstate; /* 0xd0 */
- u32 __pad_0xd4_0xdf[3];
- /* Warm Boot from On-Chip RAM Group */
- u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
- u32 romcodegrp_warmramgrp_datastart;
- u32 romcodegrp_warmramgrp_length;
- u32 romcodegrp_warmramgrp_execution;
- u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
- u32 __pad_0xf4_0xff[3];
- /* Boot ROM Hardware Register Group */
- u32 romhwgrp_ctrl; /* 0x100 */
- u32 _pad_0x104_0x107;
- /* SDMMC Controller Group */
- u32 sdmmcgrp_ctrl;
- u32 sdmmcgrp_l3master;
- /* NAND Flash Controller Register Group */
- u32 nandgrp_bootstrap; /* 0x110 */
- u32 nandgrp_l3master;
- /* USB Controller Group */
- u32 usbgrp_l3master;
- u32 _pad_0x11c_0x13f[9];
- /* ECC Management Register Group */
- u32 eccgrp_l2; /* 0x140 */
- u32 eccgrp_ocram;
- u32 eccgrp_usb0;
- u32 eccgrp_usb1;
- u32 eccgrp_emac0; /* 0x150 */
- u32 eccgrp_emac1;
- u32 eccgrp_dma;
- u32 eccgrp_can0;
- u32 eccgrp_can1; /* 0x160 */
- u32 eccgrp_nand;
- u32 eccgrp_qspi;
- u32 eccgrp_sdmmc;
- u32 _pad_0x170_0x3ff[164];
- /* Pin Mux Control Group */
- u32 emacio[20]; /* 0x400 */
- u32 flashio[12]; /* 0x450 */
- u32 generalio[28]; /* 0x480 */
- u32 _pad_0x4f0_0x4ff[4];
- u32 mixed1io[22]; /* 0x500 */
- u32 mixed2io[8]; /* 0x558 */
- u32 gplinmux[23]; /* 0x578 */
- u32 gplmux[71]; /* 0x5d4 */
- u32 nandusefpga; /* 0x6f0 */
- u32 _pad_0x6f4;
- u32 rgmii1usefpga; /* 0x6f8 */
- u32 _pad_0x6fc_0x700[2];
- u32 i2c0usefpga; /* 0x704 */
- u32 sdmmcusefpga; /* 0x708 */
- u32 _pad_0x70c_0x710[2];
- u32 rgmii0usefpga; /* 0x714 */
- u32 _pad_0x718_0x720[3];
- u32 i2c3usefpga; /* 0x724 */
- u32 i2c2usefpga; /* 0x728 */
- u32 i2c1usefpga; /* 0x72c */
- u32 spim1usefpga; /* 0x730 */
- u32 _pad_0x734;
- u32 spim0usefpga; /* 0x738 */
-};
+#define SYSMGR_GEN5_WDDBG 0x10
+#define SYSMGR_GEN5_BOOTINFO 0x14
+#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
+#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
+#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
+#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
+#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
+#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
+#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
+#define SYSMGR_GEN5_SDMMC 0x108
+#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
+#define SYSMGR_GEN5_EMACIO 0x400
+#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
+#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8
+#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
+#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704
+#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
+#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
+
+#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
+
+#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
+ SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
#endif
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
index 297f9e1999..e68a8e730e 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -15,125 +15,73 @@ void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-struct socfpga_system_manager {
- /* System Manager Module */
- u32 siliconid1; /* 0x00 */
- u32 siliconid2;
- u32 wddbg;
- u32 _pad_0xc;
- u32 mpu_status; /* 0x10 */
- u32 mpu_ace;
- u32 _pad_0x18_0x1c[2];
- u32 dma; /* 0x20 */
- u32 dma_periph;
- /* SDMMC Controller Group */
- u32 sdmmcgrp_ctrl;
- u32 sdmmcgrp_l3master;
- /* NAND Flash Controller Register Group */
- u32 nandgrp_bootstrap; /* 0x30 */
- u32 nandgrp_l3master;
- /* USB Controller Group */
- u32 usb0_l3master;
- u32 usb1_l3master;
- /* EMAC Group */
- u32 emac_gbl; /* 0x40 */
- u32 emac0;
- u32 emac1;
- u32 emac2;
- u32 emac0_ace; /* 0x50 */
- u32 emac1_ace;
- u32 emac2_ace;
- u32 nand_axuser;
- u32 _pad_0x60_0x64[2]; /* 0x60 */
- /* FPGA interface Group */
- u32 fpgaintf_en_1;
- u32 fpgaintf_en_2;
- u32 fpgaintf_en_3; /* 0x70 */
- u32 dma_l3master;
- u32 etr_l3master;
- u32 _pad_0x7c;
- u32 sec_ctrl_slt; /* 0x80 */
- u32 osc_trim;
- u32 _pad_0x88_0x8c[2];
- /* ECC Group */
- u32 ecc_intmask_value; /* 0x90 */
- u32 ecc_intmask_set;
- u32 ecc_intmask_clr;
- u32 ecc_intstatus_serr;
- u32 ecc_intstatus_derr; /* 0xa0 */
- u32 _pad_0xa4_0xac[3];
- u32 noc_addr_remap; /* 0xb0 */
- u32 hmc_clk;
- u32 io_pa_ctrl;
- u32 _pad_0xbc;
- /* NOC Group */
- u32 noc_timeout; /* 0xc0 */
- u32 noc_idlereq_set;
- u32 noc_idlereq_clr;
- u32 noc_idlereq_value;
- u32 noc_idleack; /* 0xd0 */
- u32 noc_idlestatus;
- u32 fpga2soc_ctrl;
- u32 fpga_config;
- u32 iocsrclk_gate; /* 0xe0 */
- u32 gpo;
- u32 gpi;
- u32 _pad_0xec;
- u32 mpu; /* 0xf0 */
- u32 sdm_hps_spare;
- u32 hps_sdm_spare;
- u32 _pad_0xfc_0x1fc[65];
- /* Boot scratch register group */
- u32 boot_scratch_cold0; /* 0x200 */
- u32 boot_scratch_cold1;
- u32 boot_scratch_cold2;
- u32 boot_scratch_cold3;
- u32 boot_scratch_cold4; /* 0x210 */
- u32 boot_scratch_cold5;
- u32 boot_scratch_cold6;
- u32 boot_scratch_cold7;
- u32 boot_scratch_cold8; /* 0x220 */
- u32 boot_scratch_cold9;
- u32 _pad_0x228_0xffc[886];
- /* Pin select and pin control group */
- u32 pinsel0[40]; /* 0x1000 */
- u32 _pad_0x10a0_0x10fc[24];
- u32 pinsel40[8];
- u32 _pad_0x1120_0x112c[4];
- u32 ioctrl0[28];
- u32 _pad_0x11a0_0x11fc[24];
- u32 ioctrl28[20];
- u32 _pad_0x1250_0x12fc[44];
- /* Use FPGA mux */
- u32 rgmii0usefpga; /* 0x1300 */
- u32 rgmii1usefpga;
- u32 rgmii2usefpga;
- u32 i2c0usefpga;
- u32 i2c1usefpga;
- u32 i2c_emac0_usefpga;
- u32 i2c_emac1_usefpga;
- u32 i2c_emac2_usefpga;
- u32 nandusefpga;
- u32 _pad_0x1324;
- u32 spim0usefpga;
- u32 spim1usefpga;
- u32 spis0usefpga;
- u32 spis1usefpga;
- u32 uart0usefpga;
- u32 uart1usefpga;
- u32 mdio0usefpga;
- u32 mdio1usefpga;
- u32 mdio2usefpga;
- u32 _pad_0x134c;
- u32 jtagusefpga;
- u32 sdmmcusefpga;
- u32 hps_osc_clk;
- u32 _pad_0x135c_0x13fc[41];
- u32 iodelay0[40];
- u32 _pad_0x14a0_0x14fc[24];
- u32 iodelay40[8];
+#define SYSMGR_S10_WDDBG 0x8
+#define SYSMGR_S10_DMA 0x20
+#define SYSMGR_S10_DMA_PERIPH 0x24
+#define SYSMGR_S10_SDMMC 0x28
+#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
+#define SYSMGR_S10_EMAC_GLOBAL 0x40
+#define SYSMGR_S10_EMAC0 0x44
+#define SYSMGR_S10_EMAC1 0x48
+#define SYSMGR_S10_EMAC2 0x4c
+#define SYSMGR_S10_EMAC0_ACE 0x50
+#define SYSMGR_S10_EMAC1_ACE 0x54
+#define SYSMGR_S10_EMAC2_ACE 0x58
+#define SYSMGR_S10_NAND_AXUSER 0x5c
+#define SYSMGR_S10_FPGAINTF_EN1 0x68
+#define SYSMGR_S10_FPGAINTF_EN2 0x6c
+#define SYSMGR_S10_FPGAINTF_EN3 0x70
+#define SYSMGR_S10_DMA_L3MASTER 0x74
+#define SYSMGR_S10_HMC_CLK 0xb4
+#define SYSMGR_S10_IO_PA_CTRL 0xb8
+#define SYSMGR_S10_NOC_TIMEOUT 0xc0
+#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
+#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
+#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
+#define SYSMGR_S10_NOC_IDLEACK 0xd0
+#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
+#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
+#define SYSMGR_S10_FPGA_CONFIG 0xdc
+#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
+#define SYSMGR_S10_GPO 0xe4
+#define SYSMGR_S10_GPI 0xe8
+#define SYSMGR_S10_MPU 0xf0
+#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
+#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
+#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
+#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
+#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
+#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
+#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
+#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
+#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
+#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
+#define SYSMGR_S10_PINSEL0 0x1000
+#define SYSMGR_S10_IOCTRL0 0x1130
+#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
+#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
+#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
+#define SYSMGR_S10_I2C0_USEFPGA 0x130c
+#define SYSMGR_S10_I2C1_USEFPGA 0x1310
+#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
+#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
+#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
+#define SYSMGR_S10_NAND_USEFPGA 0x1320
+#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
+#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
+#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
+#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
+#define SYSMGR_S10_UART0_USEFPGA 0x1338
+#define SYSMGR_S10_UART1_USEFPGA 0x133c
+#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
+#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
+#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
+#define SYSMGR_S10_JTAG_USEFPGA 0x1350
+#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
+#define SYSMGR_S10_HPS_OSC_CLK 0x1358
+#define SYSMGR_S10_IODELAY0 0x1400
-};
+#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 4498ab55df..11b57361c7 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -287,9 +287,6 @@ int mbox_qspi_close(void)
int mbox_qspi_open(void)
{
- static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
int ret;
u32 resp_buf[1];
u32 resp_buf_len;
@@ -318,7 +315,8 @@ int mbox_qspi_open(void)
/* We are getting QSPI ref clock and set into sysmgr boot register */
printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
- writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
+ writel(resp_buf[0],
+ socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
return 0;
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 901c432f82..fcc53b6fbc 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -23,6 +23,7 @@
DECLARE_GLOBAL_DATA_PTR;
phys_addr_t socfpga_rstmgr_base __section(".data");
+phys_addr_t socfpga_sysmgr_base __section(".data");
#ifdef CONFIG_SYS_L2_PL310
static const struct pl310_regs *const pl310 =
@@ -233,4 +234,8 @@ void socfpga_get_manager_addr(void)
socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
if (!socfpga_rstmgr_base)
hang();
+
+ socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
+ if (!socfpga_sysmgr_base)
+ hang();
}
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index 2e2a40b65d..ff6ab83441 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -28,9 +28,6 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
/*
* FPGA programming support for SoC FPGA Arria 10
*/
@@ -81,7 +78,7 @@ void socfpga_init_security_policies(void)
writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
- writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
+ writel(0x0007FFFF, socfpga_sysmgr_base + SYSMGR_A10_ECC_INTMASK_SET);
}
void socfpga_sdram_remap_zero(void)
@@ -105,8 +102,8 @@ int arch_early_init_r(void)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- const u32 bsel =
- SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
+ u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
+ const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
puts("CPU: Altera SoCFPGA Arria 10\n");
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index b39a66562d..7735958e9c 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct nic301_registers *nic301_regs =
(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
static struct scu_registers *scu_regs =
@@ -118,8 +116,8 @@ static int socfpga_fpga_id(const bool print_id)
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
- const u32 bsel =
- SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
+ u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
+ const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
puts("CPU: Altera SoCFPGA Platform\n");
socfpga_fpga_id(1);
@@ -132,7 +130,8 @@ int print_cpuinfo(void)
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
- const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
+ const u32 bsel = readl(socfpga_sysmgr_base +
+ SYSMGR_GEN5_BOOTINFO) & 0x7;
const int fpga_id = socfpga_fpga_id(0);
env_set("bootmode", bsel_str[bsel].mode);
if (fpga_id >= 0)
@@ -190,10 +189,11 @@ int arch_early_init_r(void)
* to support that old code, we write it here instead of in the
* reset_cpu() function just before resetting the CPU.
*/
- writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
+ writel(0xae9efebc, socfpga_sysmgr_base + SYSMGR_GEN5_WARMRAMGRP_EN);
for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
- iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
+ iswgrp_handoff[i] = readl(socfpga_sysmgr_base +
+ SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
socfpga_bridges_reset(1);
@@ -219,16 +219,18 @@ void do_bridge_reset(int enable, unsigned int mask)
!(mask & BIT(2)));
for (i = 0; i < 2; i++) { /* Reload SW setting cache */
iswgrp_handoff[i] =
- readl(&sysmgr_regs->iswgrp_handoff[i]);
+ readl(socfpga_sysmgr_base +
+ SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
}
- writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
+ writel(iswgrp_handoff[2],
+ socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
writel(iswgrp_handoff[0],
socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(iswgrp_handoff[1], &nic301_regs->remap);
} else {
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
+ writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
writel(0, &sdr_ctrl->fpgaport_rst);
writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
writel(1, &nic301_regs->remap);
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index 0a5fab11c0..16fbf71599 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -23,9 +23,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
/*
* FPGA programming support for SoC FPGA Stratix 10
*/
@@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
else
return -EINVAL;
- clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
- SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
- modereg);
+ clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 +
+ gmac_index),
+ SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
return 0;
}
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 4553653992..5611e784e6 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -15,9 +15,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
struct bridge_cfg {
int compat_id;
u32 mask_noc;
@@ -98,14 +95,16 @@ int socfpga_reset_deassert_bridges_handoff(void)
}
/* clear idle request to all bridges */
- setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
+ setbits_le32(socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_CLR,
+ mask_noc);
/* Release bridges from reset state per handoff value */
clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
/* Poll until all idleack to 0, timeout at 1000ms */
- return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
- false, 1000, false);
+ return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
+ SYSMGR_A10_NOC_IDLEACK),
+ mask_noc, false, 1000, false);
}
/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
@@ -195,13 +194,15 @@ int socfpga_bridges_reset(void)
ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
- &sysmgr_regs->noc_idlereq_set);
+ socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_SET);
/* Enable the NOC timeout */
- writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
+ writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
+ socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
+ ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
+ SYSMGR_A10_NOC_IDLEACK),
ALT_SYSMGR_NOC_H2F_SET_MSK |
ALT_SYSMGR_NOC_LWH2F_SET_MSK |
ALT_SYSMGR_NOC_F2H_SET_MSK |
@@ -213,7 +214,8 @@ int socfpga_bridges_reset(void)
return ret;
/* Poll until all idlestatus to 1 */
- ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
+ ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
+ SYSMGR_A10_NOC_IDLESTATUS),
ALT_SYSMGR_NOC_H2F_SET_MSK |
ALT_SYSMGR_NOC_LWH2F_SET_MSK |
ALT_SYSMGR_NOC_F2H_SET_MSK |
@@ -234,7 +236,7 @@ int socfpga_bridges_reset(void)
ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
/* Disable NOC timeout */
- writel(0, &sysmgr_regs->noc_timeout);
+ writel(0, socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
return 0;
}
diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
index ad31214711..6b617fd016 100644
--- a/arch/arm/mach-socfpga/reset_manager_gen5.c
+++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
@@ -10,9 +10,6 @@
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
@@ -83,8 +80,8 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
if (f2h)
brgmask |= BIT(2);
- writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
- writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
+ writel(brgmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
+ writel(l3rmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
}
void socfpga_bridges_reset(int enable)
diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
index b196d58d3d..50a2d80930 100644
--- a/arch/arm/mach-socfpga/reset_manager_s10.c
+++ b/arch/arm/mach-socfpga/reset_manager_s10.c
@@ -12,9 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *system_manager_base =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
-
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
@@ -59,28 +56,29 @@ void socfpga_bridges_reset(int enable)
{
if (enable) {
/* clear idle request to all bridges */
- setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
+ setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR,
+ ~0);
/* Release all bridges from reset state */
clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
/* Poll until all idleack to 0 */
- while (readl(&system_manager_base->noc_idleack))
+ while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
;
} else {
/* set idle request to all bridges */
- writel(~0, &system_manager_base->noc_idlereq_set);
+ writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET);
/* Enable the NOC timeout */
- writel(1, &system_manager_base->noc_timeout);
+ writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
- while ((readl(&system_manager_base->noc_idleack) ^
+ while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
/* Poll until all idlestatus to 1 */
- while ((readl(&system_manager_base->noc_idlestatus) ^
+ while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^
(SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
;
@@ -90,7 +88,7 @@ void socfpga_bridges_reset(int enable)
RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
- writel(0, &system_manager_base->noc_timeout);
+ writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
}
}
diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
index 52175af48b..f1d5f69caa 100644
--- a/arch/arm/mach-socfpga/scan_manager.c
+++ b/arch/arm/mach-socfpga/scan_manager.c
@@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base =
(void *)(SOCFPGA_SCANMGR_ADDRESS);
static const struct socfpga_freeze_controller *freeze_controller_base =
(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
-static struct socfpga_system_manager *sys_mgr_base =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/**
* scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
@@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
int ret;
/* Enable HPS to talk to JTAG in the FPGA through the System Manager */
- writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
+ writel(0x1, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
/* Enable port 7 */
writel(0x80, &scan_manager_base->en);
@@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
/* Disable all port */
writel(0, &scan_manager_base->en);
- writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
+ writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
return id;
}
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index a0d80fd47e..ee811e4ee9 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -31,12 +31,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
u32 spl_boot_device(void)
{
- const u32 bsel = readl(&sysmgr_regs->bootinfo);
+ const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1: /* FPGA (HPS2FPGA Bridge) */
diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index 9ee053da3a..82d9fe0824 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -24,12 +24,9 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
u32 spl_boot_device(void)
{
- const u32 bsel = readl(&sysmgr_regs->bootinfo);
+ const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
case 0x1: /* FPGA (HPS2FPGA Bridge) */
@@ -77,13 +74,13 @@ void board_init_f(ulong dummy)
* First C code to run. Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
*/
- reg = readl(&sysmgr_regs->eccgrp_ocram);
+ reg = readl(socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
if (reg & SYSMGR_ECC_OCRAM_SERR)
writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
- &sysmgr_regs->eccgrp_ocram);
+ socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
if (reg & SYSMGR_ECC_OCRAM_DERR)
writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
- &sysmgr_regs->eccgrp_ocram);
+ socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
socfpga_sdram_remap_zero();
socfpga_pl310_clear();
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index 9a97a84e1e..16f19f901d 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -22,9 +22,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
u32 spl_boot_device(void)
{
/* TODO: Get from SDM or handoff */
@@ -129,7 +126,8 @@ void board_init_f(ulong dummy)
#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */
- writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
+ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
+ socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
/* Enable watchdog before initializing the HW */
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
@@ -157,8 +155,10 @@ void board_init_f(ulong dummy)
cm_print_clock_quick_summary();
/* enable non-secure interface to DMA330 DMA and peripherals */
- writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
- writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
+ writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
+ socfpga_sysmgr_base + SYSMGR_S10_DMA);
+ writel(SYSMGR_DMAPERIPH_ALL_NS,
+ socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
spl_disable_firewall_l4_per();
diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
index 9d04aea2a8..1053a47201 100644
--- a/arch/arm/mach-socfpga/system_manager_gen5.c
+++ b/arch/arm/mach-socfpga/system_manager_gen5.c
@@ -8,9 +8,6 @@
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
/*
* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
@@ -21,30 +18,39 @@ static void populate_sysmgr_fpgaintf_module(void)
u32 handoff_val = 0;
/* ISWGRP_HANDOFF_FPGAINTF */
- writel(0, &sysmgr_regs->iswgrp_handoff[2]);
+ writel(0, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
/* Enable the signal for those HPS peripherals that use FPGA. */
- if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_NAND_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_NAND;
- if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII1_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC1;
- if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SDMMC_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SDMMC;
- if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII0_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC0;
- if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM0_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM0;
- if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM1_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM1;
/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
based on pinmux setting */
- setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
+ setbits_le32(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
+ handoff_val);
- handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
+ handoff_val = readl(socfpga_sysmgr_base +
+ SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
if (fpgamgr_test_fpga_ready()) {
/* Enable the required signals only */
- writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
+ writel(handoff_val,
+ socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
}
}
@@ -53,7 +59,7 @@ static void populate_sysmgr_fpgaintf_module(void)
*/
void sysmgr_pinmux_init(void)
{
- u32 regs = (u32)&sysmgr_regs->emacio[0];
+ u32 regs = (u32)socfpga_sysmgr_base + SYSMGR_GEN5_EMACIO;
const u8 *sys_mgr_init_table;
unsigned int len;
int i;
@@ -74,9 +80,9 @@ void sysmgr_pinmux_init(void)
void sysmgr_config_warmrstcfgio(int enable)
{
if (enable)
- setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+ setbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
else
- clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+ clrbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
}
diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
index 122828c9ce..c046bb17c9 100644
--- a/arch/arm/mach-socfpga/system_manager_s10.c
+++ b/arch/arm/mach-socfpga/system_manager_s10.c
@@ -10,9 +10,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
/*
* Configure all the pin muxes
*/
@@ -32,24 +29,31 @@ void populate_sysmgr_fpgaintf_module(void)
u32 handoff_val = 0;
/* Enable the signal for those HPS peripherals that use FPGA. */
- if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_NAND;
- if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SDMMC;
- if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM0;
- if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_SPIM1;
- writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
+ writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
handoff_val = 0;
- if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC0;
- if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC1;
- if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
+ if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
+ SYSMGR_FPGAINTF_USEFPGA)
handoff_val |= SYSMGR_FPGAINTF_EMAC2;
- writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
+ writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
}
/*
@@ -64,14 +68,16 @@ void populate_sysmgr_pinmux(void)
sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
+ sys_mgr_table_u32[i] +
+ (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
}
/* setup the pin ctrl */
sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
+ sys_mgr_table_u32[i] +
+ (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
}
/* setup the fpga use */
@@ -79,13 +85,14 @@ void populate_sysmgr_pinmux(void)
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
sys_mgr_table_u32[i] +
- (u8 *)&sysmgr_regs->rgmii0usefpga);
+ (u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA);
}
/* setup the IO delay */
sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
for (i = 0; i < len; i = i + 2) {
writel(sys_mgr_table_u32[i + 1],
- sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
+ sys_mgr_table_u32[i] +
+ (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
}
}
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
index 7cafc7dcfc..c9570fea38 100644
--- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
+++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
@@ -10,9 +10,6 @@
#include <asm/arch/handoff_s10.h>
#include <asm/arch/system_manager.h>
-static const struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
const struct cm_config * const cm_get_default_config(void)
{
struct cm_config *cm_handoff_cfg = (struct cm_config *)
@@ -38,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void)
#ifdef CONFIG_SPL_BUILD
u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
- writel(clock, &sysmgr_regs->boot_scratch_cold1);
+ writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
#endif
- return readl(&sysmgr_regs->boot_scratch_cold1);
+ return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
}
const unsigned int cm_get_intosc_clk_hz(void)
@@ -53,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void)
#ifdef CONFIG_SPL_BUILD
u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
- writel(clock, &sysmgr_regs->boot_scratch_cold2);
+ writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
#endif
- return readl(&sysmgr_regs->boot_scratch_cold2);
+ return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
}
diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
index fcd89b619d..46a5c466a7 100644
--- a/drivers/ddr/altera/sdram_gen5.c
+++ b/drivers/ddr/altera/sdram_gen5.c
@@ -40,9 +40,6 @@ struct sdram_prot_rule {
u32 hi_prot_id;
};
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
/**
@@ -455,12 +452,13 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
int ret;
- writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+ writel(rows, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
sdr_load_regs(sdr_ctrl, cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
- writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
+ writel(cfg->fpgaport_rst,
+ socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
/* only enable if the FPGA is programmed */
if (fpgamgr_test_fpga_ready()) {
@@ -516,7 +514,7 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
* since the FB specifies we modify ROWBITs to work around SDRAM
* controller issue.
*/
- row = readl(&sysmgr_regs->iswgrp_handoff[4]);
+ row = readl(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
if (row == 0)
row = rowbits;
/*
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 56cbbac9fe..d5812f2fd7 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -32,9 +32,6 @@ struct altera_sdram_platdata {
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_system_manager *sysmgr_regs =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
-
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
#define PGTABLE_OFF 0x4000
@@ -150,7 +147,8 @@ static int emif_reset(struct altera_sdram_platdata *plat)
static int poll_hmc_clock_status(void)
{
- return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
+ return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
+ SYSMGR_S10_HMC_CLK),
SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
}
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5fb9d6a191..743326cdb3 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_fpga_manager *fpga_manager_base =
(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
-
static void fpgamgr_set_cd_ratio(unsigned long ratio);
static uint32_t fpgamgr_get_msel(void)
@@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
}
/* Disable all signals from HPS peripheral controller to FPGA */
- writel(0, &system_manager_base->fpgaintf_en_global);
+ writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
/* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
@@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
memset(&rbfinfo, 0, sizeof(rbfinfo));
/* Disable all signals from hps peripheral controller to fpga */
- writel(0, &system_manager_base->fpgaintf_en_global);
+ writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
/* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
socfpga_bridges_reset();
diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
index 6d16e0b37f..2b98572742 100644
--- a/drivers/fpga/socfpga_gen5.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -15,8 +15,6 @@
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
/* Set CD ratio */
static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
/* Prior programming the FPGA, all bridges need to be shut off */
/* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
+ writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
/* Disable all signals from FPGA to HPS SDRAM */
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 739c1629a2..bdcd568d60 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
struct socfpga_dwmci_plat {
struct mmc_config cfg;
@@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+ writel(sdmmc_mask, socfpga_sysmgr_base + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
- readl(&system_manager_base->sdmmcgrp_ctrl));
+ readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
/* Enable SDMMC clock */
setbits_le32(&clock_manager_base->per_pll.en,
--
2.19.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system manager from struct to defines
2019-09-10 8:38 ` [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system " Ley Foon Tan
@ 2019-10-02 9:20 ` Simon Goldschmidt
2019-10-04 3:05 ` Ley Foon Tan
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-02 9:20 UTC (permalink / raw)
To: u-boot
On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
> No functional change.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> ---
> v2:
> - Change to use writel(), readl() and etc.
> - Get base address from DT.
Same as 2/4: separate patch please.
Regards,
Simon
> - Add prefix to defines.
> ---
> arch/arm/mach-socfpga/clock_manager_s10.c | 4 +-
> .../include/mach/system_manager.h | 2 +
> .../include/mach/system_manager_arria10.h | 94 +++------
> .../include/mach/system_manager_gen5.h | 123 +++---------
> .../include/mach/system_manager_s10.h | 184 +++++++-----------
> arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
> arch/arm/mach-socfpga/misc.c | 5 +
> arch/arm/mach-socfpga/misc_arria10.c | 9 +-
> arch/arm/mach-socfpga/misc_gen5.c | 22 ++-
> arch/arm/mach-socfpga/misc_s10.c | 9 +-
> arch/arm/mach-socfpga/reset_manager_arria10.c | 24 +--
> arch/arm/mach-socfpga/reset_manager_gen5.c | 7 +-
> arch/arm/mach-socfpga/reset_manager_s10.c | 18 +-
> arch/arm/mach-socfpga/scan_manager.c | 6 +-
> arch/arm/mach-socfpga/spl_a10.c | 5 +-
> arch/arm/mach-socfpga/spl_gen5.c | 11 +-
> arch/arm/mach-socfpga/spl_s10.c | 12 +-
> arch/arm/mach-socfpga/system_manager_gen5.c | 38 ++--
> arch/arm/mach-socfpga/system_manager_s10.c | 39 ++--
> arch/arm/mach-socfpga/wrap_pll_config_s10.c | 11 +-
> drivers/ddr/altera/sdram_gen5.c | 10 +-
> drivers/ddr/altera/sdram_s10.c | 6 +-
> drivers/fpga/socfpga_arria10.c | 7 +-
> drivers/fpga/socfpga_gen5.c | 4 +-
> drivers/mmc/socfpga_dw_mmc.c | 6 +-
> 25 files changed, 240 insertions(+), 422 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> index 3ba2a00c02..6cbf07ac6f 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_clock_manager *clock_manager_base =
> (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> /*
> * function to write the bypass register which requires a poll of the
> @@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
>
> unsigned int cm_get_qspi_controller_clk_hz(void)
> {
> - return readl(&sysmgr_regs->boot_scratch_cold0);
> + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> }
>
> unsigned int cm_get_spi_controller_clk_hz(void)
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
> index 7e76df74b7..803305eb35 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> @@ -6,6 +6,8 @@
> #ifndef _SYSTEM_MANAGER_H_
> #define _SYSTEM_MANAGER_H_
>
> +extern phys_addr_t socfpga_sysmgr_base;
> +
> #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> #include <asm/arch/system_manager_s10.h>
> #else
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> index 14052b957c..1a45c0f134 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> @@ -6,73 +6,33 @@
> #ifndef _SYSTEM_MANAGER_ARRIA10_H_
> #define _SYSTEM_MANAGER_ARRIA10_H_
>
> -struct socfpga_system_manager {
> - u32 siliconid1;
> - u32 siliconid2;
> - u32 wddbg;
> - u32 bootinfo;
> - u32 mpu_ctrl_l2_ecc;
> - u32 _pad_0x14_0x1f[3];
> - u32 dma;
> - u32 dma_periph;
> - u32 sdmmcgrp_ctrl;
> - u32 sdmmc_l3master;
> - u32 nand_bootstrap;
> - u32 nand_l3master;
> - u32 usb0_l3master;
> - u32 usb1_l3master;
> - u32 emac_global;
> - u32 emac[3];
> - u32 _pad_0x50_0x5f[4];
> - u32 fpgaintf_en_global;
> - u32 fpgaintf_en_0;
> - u32 fpgaintf_en_1;
> - u32 fpgaintf_en_2;
> - u32 fpgaintf_en_3;
> - u32 _pad_0x74_0x7f[3];
> - u32 noc_addr_remap_value;
> - u32 noc_addr_remap_set;
> - u32 noc_addr_remap_clear;
> - u32 _pad_0x8c_0x8f;
> - u32 ecc_intmask_value;
> - u32 ecc_intmask_set;
> - u32 ecc_intmask_clr;
> - u32 ecc_intstatus_serr;
> - u32 ecc_intstatus_derr;
> - u32 mpu_status_l2_ecc;
> - u32 mpu_clear_l2_ecc;
> - u32 mpu_status_l1_parity;
> - u32 mpu_clear_l1_parity;
> - u32 mpu_set_l1_parity;
> - u32 _pad_0xb8_0xbf[2];
> - u32 noc_timeout;
> - u32 noc_idlereq_set;
> - u32 noc_idlereq_clr;
> - u32 noc_idlereq_value;
> - u32 noc_idleack;
> - u32 noc_idlestatus;
> - u32 fpga2soc_ctrl;
> - u32 _pad_0xdc_0xff[9];
> - u32 tsmc_tsel_0;
> - u32 tsmc_tsel_1;
> - u32 tsmc_tsel_2;
> - u32 tsmc_tsel_3;
> - u32 _pad_0x110_0x200[60];
> - u32 romhw_ctrl;
> - u32 romcode_ctrl;
> - u32 romcode_cpu1startaddr;
> - u32 romcode_initswstate;
> - u32 romcode_initswlastld;
> - u32 _pad_0x214_0x217;
> - u32 warmram_enable;
> - u32 warmram_datastart;
> - u32 warmram_length;
> - u32 warmram_execution;
> - u32 warmram_crc;
> - u32 _pad_0x22c_0x22f;
> - u32 isw_handoff[8];
> - u32 romcode_bootromswstate[8];
> -};
> +#define SYSMGR_A10_WDDBG 0x8
> +#define SYSMGR_A10_BOOTINFO 0xc
> +#define SYSMGR_A10_DMA 0x20
> +#define SYSMGR_A10_DMA_PERIPH 0x24
> +#define SYSMGR_A10_SDMMC 0x28
> +#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
> +#define SYSMGR_A10_EMAC_GLOBAL 0x40
> +#define SYSMGR_A10_EMAC0 0x44
> +#define SYSMGR_A10_EMAC1 0x48
> +#define SYSMGR_A10_EMAC2 0x4c
> +#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
> +#define SYSMGR_A10_FPGAINTF_EN0 0x64
> +#define SYSMGR_A10_FPGAINTF_EN1 0x68
> +#define SYSMGR_A10_FPGAINTF_EN2 0x6c
> +#define SYSMGR_A10_FPGAINTF_EN3 0x70
> +#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
> +#define SYSMGR_A10_ECC_INTMASK_SET 0x94
> +#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
> +#define SYSMGR_A10_NOC_TIMEOUT 0xc0
> +#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
> +#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
> +#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
> +#define SYSMGR_A10_NOC_IDLEACK 0xd0
> +#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
> +#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
> +
> +#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
>
> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
> #define SYSMGR_BOOTINFO_BSEL_SHIFT 12
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> index 52e59df513..90cb465d13 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> @@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable);
>
> void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
>
> -struct socfpga_system_manager {
> - /* System Manager Module */
> - u32 siliconid1; /* 0x00 */
> - u32 siliconid2;
> - u32 _pad_0x8_0xf[2];
> - u32 wddbg; /* 0x10 */
> - u32 bootinfo;
> - u32 hpsinfo;
> - u32 parityinj;
> - /* FPGA Interface Group */
> - u32 fpgaintfgrp_gbl; /* 0x20 */
> - u32 fpgaintfgrp_indiv;
> - u32 fpgaintfgrp_module;
> - u32 _pad_0x2c_0x2f;
> - /* Scan Manager Group */
> - u32 scanmgrgrp_ctrl; /* 0x30 */
> - u32 _pad_0x34_0x3f[3];
> - /* Freeze Control Group */
> - u32 frzctrl_vioctrl; /* 0x40 */
> - u32 _pad_0x44_0x4f[3];
> - u32 frzctrl_hioctrl; /* 0x50 */
> - u32 frzctrl_src;
> - u32 frzctrl_hwctrl;
> - u32 _pad_0x5c_0x5f;
> - /* EMAC Group */
> - u32 emacgrp_ctrl; /* 0x60 */
> - u32 emacgrp_l3master;
> - u32 _pad_0x68_0x6f[2];
> - /* DMA Controller Group */
> - u32 dmagrp_ctrl; /* 0x70 */
> - u32 dmagrp_persecurity;
> - u32 _pad_0x78_0x7f[2];
> - /* Preloader (initial software) Group */
> - u32 iswgrp_handoff[8]; /* 0x80 */
> - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
> - /* Boot ROM Code Register Group */
> - u32 romcodegrp_ctrl; /* 0xc0 */
> - u32 romcodegrp_cpu1startaddr;
> - u32 romcodegrp_initswstate;
> - u32 romcodegrp_initswlastld;
> - u32 romcodegrp_bootromswstate; /* 0xd0 */
> - u32 __pad_0xd4_0xdf[3];
> - /* Warm Boot from On-Chip RAM Group */
> - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
> - u32 romcodegrp_warmramgrp_datastart;
> - u32 romcodegrp_warmramgrp_length;
> - u32 romcodegrp_warmramgrp_execution;
> - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
> - u32 __pad_0xf4_0xff[3];
> - /* Boot ROM Hardware Register Group */
> - u32 romhwgrp_ctrl; /* 0x100 */
> - u32 _pad_0x104_0x107;
> - /* SDMMC Controller Group */
> - u32 sdmmcgrp_ctrl;
> - u32 sdmmcgrp_l3master;
> - /* NAND Flash Controller Register Group */
> - u32 nandgrp_bootstrap; /* 0x110 */
> - u32 nandgrp_l3master;
> - /* USB Controller Group */
> - u32 usbgrp_l3master;
> - u32 _pad_0x11c_0x13f[9];
> - /* ECC Management Register Group */
> - u32 eccgrp_l2; /* 0x140 */
> - u32 eccgrp_ocram;
> - u32 eccgrp_usb0;
> - u32 eccgrp_usb1;
> - u32 eccgrp_emac0; /* 0x150 */
> - u32 eccgrp_emac1;
> - u32 eccgrp_dma;
> - u32 eccgrp_can0;
> - u32 eccgrp_can1; /* 0x160 */
> - u32 eccgrp_nand;
> - u32 eccgrp_qspi;
> - u32 eccgrp_sdmmc;
> - u32 _pad_0x170_0x3ff[164];
> - /* Pin Mux Control Group */
> - u32 emacio[20]; /* 0x400 */
> - u32 flashio[12]; /* 0x450 */
> - u32 generalio[28]; /* 0x480 */
> - u32 _pad_0x4f0_0x4ff[4];
> - u32 mixed1io[22]; /* 0x500 */
> - u32 mixed2io[8]; /* 0x558 */
> - u32 gplinmux[23]; /* 0x578 */
> - u32 gplmux[71]; /* 0x5d4 */
> - u32 nandusefpga; /* 0x6f0 */
> - u32 _pad_0x6f4;
> - u32 rgmii1usefpga; /* 0x6f8 */
> - u32 _pad_0x6fc_0x700[2];
> - u32 i2c0usefpga; /* 0x704 */
> - u32 sdmmcusefpga; /* 0x708 */
> - u32 _pad_0x70c_0x710[2];
> - u32 rgmii0usefpga; /* 0x714 */
> - u32 _pad_0x718_0x720[3];
> - u32 i2c3usefpga; /* 0x724 */
> - u32 i2c2usefpga; /* 0x728 */
> - u32 i2c1usefpga; /* 0x72c */
> - u32 spim1usefpga; /* 0x730 */
> - u32 _pad_0x734;
> - u32 spim0usefpga; /* 0x738 */
> -};
> +#define SYSMGR_GEN5_WDDBG 0x10
> +#define SYSMGR_GEN5_BOOTINFO 0x14
> +#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
> +#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
> +#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
> +#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
> +#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
> +#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
> +#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
> +#define SYSMGR_GEN5_SDMMC 0x108
> +#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
> +#define SYSMGR_GEN5_EMACIO 0x400
> +#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
> +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8
> +#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
> +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704
> +#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
> +#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
> +
> +#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
> +
> +#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
> + SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
> #endif
>
> #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
> diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> index 297f9e1999..e68a8e730e 100644
> --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> @@ -15,125 +15,73 @@ void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
> void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
> void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
>
> -struct socfpga_system_manager {
> - /* System Manager Module */
> - u32 siliconid1; /* 0x00 */
> - u32 siliconid2;
> - u32 wddbg;
> - u32 _pad_0xc;
> - u32 mpu_status; /* 0x10 */
> - u32 mpu_ace;
> - u32 _pad_0x18_0x1c[2];
> - u32 dma; /* 0x20 */
> - u32 dma_periph;
> - /* SDMMC Controller Group */
> - u32 sdmmcgrp_ctrl;
> - u32 sdmmcgrp_l3master;
> - /* NAND Flash Controller Register Group */
> - u32 nandgrp_bootstrap; /* 0x30 */
> - u32 nandgrp_l3master;
> - /* USB Controller Group */
> - u32 usb0_l3master;
> - u32 usb1_l3master;
> - /* EMAC Group */
> - u32 emac_gbl; /* 0x40 */
> - u32 emac0;
> - u32 emac1;
> - u32 emac2;
> - u32 emac0_ace; /* 0x50 */
> - u32 emac1_ace;
> - u32 emac2_ace;
> - u32 nand_axuser;
> - u32 _pad_0x60_0x64[2]; /* 0x60 */
> - /* FPGA interface Group */
> - u32 fpgaintf_en_1;
> - u32 fpgaintf_en_2;
> - u32 fpgaintf_en_3; /* 0x70 */
> - u32 dma_l3master;
> - u32 etr_l3master;
> - u32 _pad_0x7c;
> - u32 sec_ctrl_slt; /* 0x80 */
> - u32 osc_trim;
> - u32 _pad_0x88_0x8c[2];
> - /* ECC Group */
> - u32 ecc_intmask_value; /* 0x90 */
> - u32 ecc_intmask_set;
> - u32 ecc_intmask_clr;
> - u32 ecc_intstatus_serr;
> - u32 ecc_intstatus_derr; /* 0xa0 */
> - u32 _pad_0xa4_0xac[3];
> - u32 noc_addr_remap; /* 0xb0 */
> - u32 hmc_clk;
> - u32 io_pa_ctrl;
> - u32 _pad_0xbc;
> - /* NOC Group */
> - u32 noc_timeout; /* 0xc0 */
> - u32 noc_idlereq_set;
> - u32 noc_idlereq_clr;
> - u32 noc_idlereq_value;
> - u32 noc_idleack; /* 0xd0 */
> - u32 noc_idlestatus;
> - u32 fpga2soc_ctrl;
> - u32 fpga_config;
> - u32 iocsrclk_gate; /* 0xe0 */
> - u32 gpo;
> - u32 gpi;
> - u32 _pad_0xec;
> - u32 mpu; /* 0xf0 */
> - u32 sdm_hps_spare;
> - u32 hps_sdm_spare;
> - u32 _pad_0xfc_0x1fc[65];
> - /* Boot scratch register group */
> - u32 boot_scratch_cold0; /* 0x200 */
> - u32 boot_scratch_cold1;
> - u32 boot_scratch_cold2;
> - u32 boot_scratch_cold3;
> - u32 boot_scratch_cold4; /* 0x210 */
> - u32 boot_scratch_cold5;
> - u32 boot_scratch_cold6;
> - u32 boot_scratch_cold7;
> - u32 boot_scratch_cold8; /* 0x220 */
> - u32 boot_scratch_cold9;
> - u32 _pad_0x228_0xffc[886];
> - /* Pin select and pin control group */
> - u32 pinsel0[40]; /* 0x1000 */
> - u32 _pad_0x10a0_0x10fc[24];
> - u32 pinsel40[8];
> - u32 _pad_0x1120_0x112c[4];
> - u32 ioctrl0[28];
> - u32 _pad_0x11a0_0x11fc[24];
> - u32 ioctrl28[20];
> - u32 _pad_0x1250_0x12fc[44];
> - /* Use FPGA mux */
> - u32 rgmii0usefpga; /* 0x1300 */
> - u32 rgmii1usefpga;
> - u32 rgmii2usefpga;
> - u32 i2c0usefpga;
> - u32 i2c1usefpga;
> - u32 i2c_emac0_usefpga;
> - u32 i2c_emac1_usefpga;
> - u32 i2c_emac2_usefpga;
> - u32 nandusefpga;
> - u32 _pad_0x1324;
> - u32 spim0usefpga;
> - u32 spim1usefpga;
> - u32 spis0usefpga;
> - u32 spis1usefpga;
> - u32 uart0usefpga;
> - u32 uart1usefpga;
> - u32 mdio0usefpga;
> - u32 mdio1usefpga;
> - u32 mdio2usefpga;
> - u32 _pad_0x134c;
> - u32 jtagusefpga;
> - u32 sdmmcusefpga;
> - u32 hps_osc_clk;
> - u32 _pad_0x135c_0x13fc[41];
> - u32 iodelay0[40];
> - u32 _pad_0x14a0_0x14fc[24];
> - u32 iodelay40[8];
> +#define SYSMGR_S10_WDDBG 0x8
> +#define SYSMGR_S10_DMA 0x20
> +#define SYSMGR_S10_DMA_PERIPH 0x24
> +#define SYSMGR_S10_SDMMC 0x28
> +#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
> +#define SYSMGR_S10_EMAC_GLOBAL 0x40
> +#define SYSMGR_S10_EMAC0 0x44
> +#define SYSMGR_S10_EMAC1 0x48
> +#define SYSMGR_S10_EMAC2 0x4c
> +#define SYSMGR_S10_EMAC0_ACE 0x50
> +#define SYSMGR_S10_EMAC1_ACE 0x54
> +#define SYSMGR_S10_EMAC2_ACE 0x58
> +#define SYSMGR_S10_NAND_AXUSER 0x5c
> +#define SYSMGR_S10_FPGAINTF_EN1 0x68
> +#define SYSMGR_S10_FPGAINTF_EN2 0x6c
> +#define SYSMGR_S10_FPGAINTF_EN3 0x70
> +#define SYSMGR_S10_DMA_L3MASTER 0x74
> +#define SYSMGR_S10_HMC_CLK 0xb4
> +#define SYSMGR_S10_IO_PA_CTRL 0xb8
> +#define SYSMGR_S10_NOC_TIMEOUT 0xc0
> +#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
> +#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
> +#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
> +#define SYSMGR_S10_NOC_IDLEACK 0xd0
> +#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
> +#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
> +#define SYSMGR_S10_FPGA_CONFIG 0xdc
> +#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
> +#define SYSMGR_S10_GPO 0xe4
> +#define SYSMGR_S10_GPI 0xe8
> +#define SYSMGR_S10_MPU 0xf0
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
> +#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
> +#define SYSMGR_S10_PINSEL0 0x1000
> +#define SYSMGR_S10_IOCTRL0 0x1130
> +#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
> +#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
> +#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
> +#define SYSMGR_S10_I2C0_USEFPGA 0x130c
> +#define SYSMGR_S10_I2C1_USEFPGA 0x1310
> +#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
> +#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
> +#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
> +#define SYSMGR_S10_NAND_USEFPGA 0x1320
> +#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
> +#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
> +#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
> +#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
> +#define SYSMGR_S10_UART0_USEFPGA 0x1338
> +#define SYSMGR_S10_UART1_USEFPGA 0x133c
> +#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
> +#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
> +#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
> +#define SYSMGR_S10_JTAG_USEFPGA 0x1350
> +#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
> +#define SYSMGR_S10_HPS_OSC_CLK 0x1358
> +#define SYSMGR_S10_IODELAY0 0x1400
>
> -};
> +#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
>
> #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
> diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> index 4498ab55df..11b57361c7 100644
> --- a/arch/arm/mach-socfpga/mailbox_s10.c
> +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> @@ -287,9 +287,6 @@ int mbox_qspi_close(void)
>
> int mbox_qspi_open(void)
> {
> - static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> int ret;
> u32 resp_buf[1];
> u32 resp_buf_len;
> @@ -318,7 +315,8 @@ int mbox_qspi_open(void)
>
> /* We are getting QSPI ref clock and set into sysmgr boot register */
> printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
> - writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
> + writel(resp_buf[0],
> + socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
>
> return 0;
>
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index 901c432f82..fcc53b6fbc 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -23,6 +23,7 @@
> DECLARE_GLOBAL_DATA_PTR;
>
> phys_addr_t socfpga_rstmgr_base __section(".data");
> +phys_addr_t socfpga_sysmgr_base __section(".data");
>
> #ifdef CONFIG_SYS_L2_PL310
> static const struct pl310_regs *const pl310 =
> @@ -233,4 +234,8 @@ void socfpga_get_manager_addr(void)
> socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
> if (!socfpga_rstmgr_base)
> hang();
> +
> + socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
> + if (!socfpga_sysmgr_base)
> + hang();
> }
> diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
> index 2e2a40b65d..ff6ab83441 100644
> --- a/arch/arm/mach-socfpga/misc_arria10.c
> +++ b/arch/arm/mach-socfpga/misc_arria10.c
> @@ -28,9 +28,6 @@
> #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
> #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /*
> * FPGA programming support for SoC FPGA Arria 10
> */
> @@ -81,7 +78,7 @@ void socfpga_init_security_policies(void)
> writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
> writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
>
> - writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
> + writel(0x0007FFFF, socfpga_sysmgr_base + SYSMGR_A10_ECC_INTMASK_SET);
> }
>
> void socfpga_sdram_remap_zero(void)
> @@ -105,8 +102,8 @@ int arch_early_init_r(void)
> #if defined(CONFIG_DISPLAY_CPUINFO)
> int print_cpuinfo(void)
> {
> - const u32 bsel =
> - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
> + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
>
> puts("CPU: Altera SoCFPGA Arria 10\n");
>
> diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> index b39a66562d..7735958e9c 100644
> --- a/arch/arm/mach-socfpga/misc_gen5.c
> +++ b/arch/arm/mach-socfpga/misc_gen5.c
> @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static struct pl310_regs *const pl310 =
> (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> static struct nic301_registers *nic301_regs =
> (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> static struct scu_registers *scu_regs =
> @@ -118,8 +116,8 @@ static int socfpga_fpga_id(const bool print_id)
> #if defined(CONFIG_DISPLAY_CPUINFO)
> int print_cpuinfo(void)
> {
> - const u32 bsel =
> - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
> + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
>
> puts("CPU: Altera SoCFPGA Platform\n");
> socfpga_fpga_id(1);
> @@ -132,7 +130,8 @@ int print_cpuinfo(void)
> #ifdef CONFIG_ARCH_MISC_INIT
> int arch_misc_init(void)
> {
> - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> + const u32 bsel = readl(socfpga_sysmgr_base +
> + SYSMGR_GEN5_BOOTINFO) & 0x7;
> const int fpga_id = socfpga_fpga_id(0);
> env_set("bootmode", bsel_str[bsel].mode);
> if (fpga_id >= 0)
> @@ -190,10 +189,11 @@ int arch_early_init_r(void)
> * to support that old code, we write it here instead of in the
> * reset_cpu() function just before resetting the CPU.
> */
> - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
> + writel(0xae9efebc, socfpga_sysmgr_base + SYSMGR_GEN5_WARMRAMGRP_EN);
>
> for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
> + iswgrp_handoff[i] = readl(socfpga_sysmgr_base +
> + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
>
> socfpga_bridges_reset(1);
>
> @@ -219,16 +219,18 @@ void do_bridge_reset(int enable, unsigned int mask)
> !(mask & BIT(2)));
> for (i = 0; i < 2; i++) { /* Reload SW setting cache */
> iswgrp_handoff[i] =
> - readl(&sysmgr_regs->iswgrp_handoff[i]);
> + readl(socfpga_sysmgr_base +
> + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
> }
>
> - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
> + writel(iswgrp_handoff[2],
> + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> writel(iswgrp_handoff[0],
> socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> writel(iswgrp_handoff[1], &nic301_regs->remap);
> } else {
> - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> writel(0, &sdr_ctrl->fpgaport_rst);
> writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> writel(1, &nic301_regs->remap);
> diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> index 0a5fab11c0..16fbf71599 100644
> --- a/arch/arm/mach-socfpga/misc_s10.c
> +++ b/arch/arm/mach-socfpga/misc_s10.c
> @@ -23,9 +23,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /*
> * FPGA programming support for SoC FPGA Stratix 10
> */
> @@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
> else
> return -EINVAL;
>
> - clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
> - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> - modereg);
> + clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 +
> + gmac_index),
> + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
>
> return 0;
> }
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> index 4553653992..5611e784e6 100644
> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -15,9 +15,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> struct bridge_cfg {
> int compat_id;
> u32 mask_noc;
> @@ -98,14 +95,16 @@ int socfpga_reset_deassert_bridges_handoff(void)
> }
>
> /* clear idle request to all bridges */
> - setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
> + setbits_le32(socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_CLR,
> + mask_noc);
>
> /* Release bridges from reset state per handoff value */
> clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
>
> /* Poll until all idleack to 0, timeout at 1000ms */
> - return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
> - false, 1000, false);
> + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> + SYSMGR_A10_NOC_IDLEACK),
> + mask_noc, false, 1000, false);
> }
>
> /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> @@ -195,13 +194,15 @@ int socfpga_bridges_reset(void)
> ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
> - &sysmgr_regs->noc_idlereq_set);
> + socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_SET);
>
> /* Enable the NOC timeout */
> - writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
> + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
> + socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
>
> /* Poll until all idleack to 1 */
> - ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
> + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> + SYSMGR_A10_NOC_IDLEACK),
> ALT_SYSMGR_NOC_H2F_SET_MSK |
> ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> ALT_SYSMGR_NOC_F2H_SET_MSK |
> @@ -213,7 +214,8 @@ int socfpga_bridges_reset(void)
> return ret;
>
> /* Poll until all idlestatus to 1 */
> - ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
> + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> + SYSMGR_A10_NOC_IDLESTATUS),
> ALT_SYSMGR_NOC_H2F_SET_MSK |
> ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> ALT_SYSMGR_NOC_F2H_SET_MSK |
> @@ -234,7 +236,7 @@ int socfpga_bridges_reset(void)
> ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
>
> /* Disable NOC timeout */
> - writel(0, &sysmgr_regs->noc_timeout);
> + writel(0, socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
>
> return 0;
> }
> diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
> index ad31214711..6b617fd016 100644
> --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> @@ -10,9 +10,6 @@
> #include <asm/arch/reset_manager.h>
> #include <asm/arch/system_manager.h>
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /* Assert or de-assert SoCFPGA reset manager reset. */
> void socfpga_per_reset(u32 reset, int set)
> {
> @@ -83,8 +80,8 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
> if (f2h)
> brgmask |= BIT(2);
>
> - writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
> - writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
> + writel(brgmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
> + writel(l3rmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
> }
>
> void socfpga_bridges_reset(int enable)
> diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> index b196d58d3d..50a2d80930 100644
> --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> @@ -12,9 +12,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_system_manager *system_manager_base =
> - (void *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /* Assert or de-assert SoCFPGA reset manager reset. */
> void socfpga_per_reset(u32 reset, int set)
> {
> @@ -59,28 +56,29 @@ void socfpga_bridges_reset(int enable)
> {
> if (enable) {
> /* clear idle request to all bridges */
> - setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
> + setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR,
> + ~0);
>
> /* Release all bridges from reset state */
> clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
>
> /* Poll until all idleack to 0 */
> - while (readl(&system_manager_base->noc_idleack))
> + while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
> ;
> } else {
> /* set idle request to all bridges */
> - writel(~0, &system_manager_base->noc_idlereq_set);
> + writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET);
>
> /* Enable the NOC timeout */
> - writel(1, &system_manager_base->noc_timeout);
> + writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
>
> /* Poll until all idleack to 1 */
> - while ((readl(&system_manager_base->noc_idleack) ^
> + while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^
> (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> ;
>
> /* Poll until all idlestatus to 1 */
> - while ((readl(&system_manager_base->noc_idlestatus) ^
> + while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^
> (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> ;
>
> @@ -90,7 +88,7 @@ void socfpga_bridges_reset(int enable)
> RSTMGR_BRGMODRST_FPGA2SOC_MASK));
>
> /* Disable NOC timeout */
> - writel(0, &system_manager_base->noc_timeout);
> + writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> }
> }
>
> diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
> index 52175af48b..f1d5f69caa 100644
> --- a/arch/arm/mach-socfpga/scan_manager.c
> +++ b/arch/arm/mach-socfpga/scan_manager.c
> @@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base =
> (void *)(SOCFPGA_SCANMGR_ADDRESS);
> static const struct socfpga_freeze_controller *freeze_controller_base =
> (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
> -static struct socfpga_system_manager *sys_mgr_base =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> /**
> * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
> @@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
> int ret;
>
> /* Enable HPS to talk to JTAG in the FPGA through the System Manager */
> - writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
> + writel(0x1, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
>
> /* Enable port 7 */
> writel(0x80, &scan_manager_base->en);
> @@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
>
> /* Disable all port */
> writel(0, &scan_manager_base->en);
> - writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
> + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
>
> return id;
> }
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
> index a0d80fd47e..ee811e4ee9 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -31,12 +31,9 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> u32 spl_boot_device(void)
> {
> - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
>
> switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> case 0x1: /* FPGA (HPS2FPGA Bridge) */
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> index 9ee053da3a..82d9fe0824 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -24,12 +24,9 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> u32 spl_boot_device(void)
> {
> - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
>
> switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> case 0x1: /* FPGA (HPS2FPGA Bridge) */
> @@ -77,13 +74,13 @@ void board_init_f(ulong dummy)
> * First C code to run. Clear fake OCRAM ECC first as SBE
> * and DBE might triggered during power on
> */
> - reg = readl(&sysmgr_regs->eccgrp_ocram);
> + reg = readl(socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> if (reg & SYSMGR_ECC_OCRAM_SERR)
> writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
> - &sysmgr_regs->eccgrp_ocram);
> + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> if (reg & SYSMGR_ECC_OCRAM_DERR)
> writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
> - &sysmgr_regs->eccgrp_ocram);
> + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
>
> socfpga_sdram_remap_zero();
> socfpga_pl310_clear();
> diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> index 9a97a84e1e..16f19f901d 100644
> --- a/arch/arm/mach-socfpga/spl_s10.c
> +++ b/arch/arm/mach-socfpga/spl_s10.c
> @@ -22,9 +22,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> u32 spl_boot_device(void)
> {
> /* TODO: Get from SDM or handoff */
> @@ -129,7 +126,8 @@ void board_init_f(ulong dummy)
>
> #ifdef CONFIG_HW_WATCHDOG
> /* Ensure watchdog is paused when debugging is happening */
> - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
> + socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
>
> /* Enable watchdog before initializing the HW */
> socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> @@ -157,8 +155,10 @@ void board_init_f(ulong dummy)
> cm_print_clock_quick_summary();
>
> /* enable non-secure interface to DMA330 DMA and peripherals */
> - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
> - writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
> + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
> + socfpga_sysmgr_base + SYSMGR_S10_DMA);
> + writel(SYSMGR_DMAPERIPH_ALL_NS,
> + socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
>
> spl_disable_firewall_l4_per();
>
> diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
> index 9d04aea2a8..1053a47201 100644
> --- a/arch/arm/mach-socfpga/system_manager_gen5.c
> +++ b/arch/arm/mach-socfpga/system_manager_gen5.c
> @@ -8,9 +8,6 @@
> #include <asm/arch/system_manager.h>
> #include <asm/arch/fpga_manager.h>
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /*
> * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
> * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
> @@ -21,30 +18,39 @@ static void populate_sysmgr_fpgaintf_module(void)
> u32 handoff_val = 0;
>
> /* ISWGRP_HANDOFF_FPGAINTF */
> - writel(0, &sysmgr_regs->iswgrp_handoff[2]);
> + writel(0, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
>
> /* Enable the signal for those HPS peripherals that use FPGA. */
> - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_NAND_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_NAND;
> - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII1_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SDMMC_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII0_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM0_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM1_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SPIM1;
>
> /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
> based on pinmux setting */
> - setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
> + setbits_le32(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
> + handoff_val);
>
> - handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
> + handoff_val = readl(socfpga_sysmgr_base +
> + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
> if (fpgamgr_test_fpga_ready()) {
> /* Enable the required signals only */
> - writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
> + writel(handoff_val,
> + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> }
> }
>
> @@ -53,7 +59,7 @@ static void populate_sysmgr_fpgaintf_module(void)
> */
> void sysmgr_pinmux_init(void)
> {
> - u32 regs = (u32)&sysmgr_regs->emacio[0];
> + u32 regs = (u32)socfpga_sysmgr_base + SYSMGR_GEN5_EMACIO;
> const u8 *sys_mgr_init_table;
> unsigned int len;
> int i;
> @@ -74,9 +80,9 @@ void sysmgr_pinmux_init(void)
> void sysmgr_config_warmrstcfgio(int enable)
> {
> if (enable)
> - setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> + setbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
> SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> else
> - clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> + clrbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
> SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> }
> diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
> index 122828c9ce..c046bb17c9 100644
> --- a/arch/arm/mach-socfpga/system_manager_s10.c
> +++ b/arch/arm/mach-socfpga/system_manager_s10.c
> @@ -10,9 +10,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> /*
> * Configure all the pin muxes
> */
> @@ -32,24 +29,31 @@ void populate_sysmgr_fpgaintf_module(void)
> u32 handoff_val = 0;
>
> /* Enable the signal for those HPS peripherals that use FPGA. */
> - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_NAND;
> - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> - writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
> + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
>
> handoff_val = 0;
> - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> - if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
> + SYSMGR_FPGAINTF_USEFPGA)
> handoff_val |= SYSMGR_FPGAINTF_EMAC2;
> - writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
> + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
> }
>
> /*
> @@ -64,14 +68,16 @@ void populate_sysmgr_pinmux(void)
> sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
> for (i = 0; i < len; i = i + 2) {
> writel(sys_mgr_table_u32[i + 1],
> - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
> + sys_mgr_table_u32[i] +
> + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
> }
>
> /* setup the pin ctrl */
> sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
> for (i = 0; i < len; i = i + 2) {
> writel(sys_mgr_table_u32[i + 1],
> - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
> + sys_mgr_table_u32[i] +
> + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
> }
>
> /* setup the fpga use */
> @@ -79,13 +85,14 @@ void populate_sysmgr_pinmux(void)
> for (i = 0; i < len; i = i + 2) {
> writel(sys_mgr_table_u32[i + 1],
> sys_mgr_table_u32[i] +
> - (u8 *)&sysmgr_regs->rgmii0usefpga);
> + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA);
> }
>
> /* setup the IO delay */
> sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
> for (i = 0; i < len; i = i + 2) {
> writel(sys_mgr_table_u32[i + 1],
> - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
> + sys_mgr_table_u32[i] +
> + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
> }
> }
> diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> index 7cafc7dcfc..c9570fea38 100644
> --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> @@ -10,9 +10,6 @@
> #include <asm/arch/handoff_s10.h>
> #include <asm/arch/system_manager.h>
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> const struct cm_config * const cm_get_default_config(void)
> {
> struct cm_config *cm_handoff_cfg = (struct cm_config *)
> @@ -38,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void)
> #ifdef CONFIG_SPL_BUILD
> u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
>
> - writel(clock, &sysmgr_regs->boot_scratch_cold1);
> + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> #endif
> - return readl(&sysmgr_regs->boot_scratch_cold1);
> + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> }
>
> const unsigned int cm_get_intosc_clk_hz(void)
> @@ -53,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void)
> #ifdef CONFIG_SPL_BUILD
> u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
>
> - writel(clock, &sysmgr_regs->boot_scratch_cold2);
> + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> #endif
> - return readl(&sysmgr_regs->boot_scratch_cold2);
> + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> }
> diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
> index fcd89b619d..46a5c466a7 100644
> --- a/drivers/ddr/altera/sdram_gen5.c
> +++ b/drivers/ddr/altera/sdram_gen5.c
> @@ -40,9 +40,6 @@ struct sdram_prot_rule {
> u32 hi_prot_id;
> };
>
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> -
> static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
>
> /**
> @@ -455,12 +452,13 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
> SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
> int ret;
>
> - writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
> + writel(rows, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
>
> sdr_load_regs(sdr_ctrl, cfg);
>
> /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
> - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
> + writel(cfg->fpgaport_rst,
> + socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
>
> /* only enable if the FPGA is programmed */
> if (fpgamgr_test_fpga_ready()) {
> @@ -516,7 +514,7 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
> * since the FB specifies we modify ROWBITs to work around SDRAM
> * controller issue.
> */
> - row = readl(&sysmgr_regs->iswgrp_handoff[4]);
> + row = readl(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
> if (row == 0)
> row = rowbits;
> /*
> diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> index 56cbbac9fe..d5812f2fd7 100644
> --- a/drivers/ddr/altera/sdram_s10.c
> +++ b/drivers/ddr/altera/sdram_s10.c
> @@ -32,9 +32,6 @@ struct altera_sdram_platdata {
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_system_manager *sysmgr_regs =
> - (void *)SOCFPGA_SYSMGR_ADDRESS;
> -
> #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
>
> #define PGTABLE_OFF 0x4000
> @@ -150,7 +147,8 @@ static int emif_reset(struct altera_sdram_platdata *plat)
>
> static int poll_hmc_clock_status(void)
> {
> - return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
> + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> + SYSMGR_S10_HMC_CLK),
> SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
> }
>
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 5fb9d6a191..743326cdb3 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> static const struct socfpga_fpga_manager *fpga_manager_base =
> (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
>
> -static const struct socfpga_system_manager *system_manager_base =
> - (void *)SOCFPGA_SYSMGR_ADDRESS;
> -
> static void fpgamgr_set_cd_ratio(unsigned long ratio);
>
> static uint32_t fpgamgr_get_msel(void)
> @@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
> }
>
> /* Disable all signals from HPS peripheral controller to FPGA */
> - writel(0, &system_manager_base->fpgaintf_en_global);
> + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
>
> /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
> socfpga_bridges_reset();
> @@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> memset(&rbfinfo, 0, sizeof(rbfinfo));
>
> /* Disable all signals from hps peripheral controller to fpga */
> - writel(0, &system_manager_base->fpgaintf_en_global);
> + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
>
> /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> socfpga_bridges_reset();
> diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
> index 6d16e0b37f..2b98572742 100644
> --- a/drivers/fpga/socfpga_gen5.c
> +++ b/drivers/fpga/socfpga_gen5.c
> @@ -15,8 +15,6 @@
>
> static struct socfpga_fpga_manager *fpgamgr_regs =
> (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> -static struct socfpga_system_manager *sysmgr_regs =
> - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> /* Set CD ratio */
> static void fpgamgr_set_cd_ratio(unsigned long ratio)
> @@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> /* Prior programming the FPGA, all bridges need to be shut off */
>
> /* Disable all signals from hps peripheral controller to fpga */
> - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
>
> /* Disable all signals from FPGA to HPS SDRAM */
> #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index 739c1629a2..bdcd568d60 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
>
> static const struct socfpga_clock_manager *clock_manager_base =
> (void *)SOCFPGA_CLKMGR_ADDRESS;
> -static const struct socfpga_system_manager *system_manager_base =
> - (void *)SOCFPGA_SYSMGR_ADDRESS;
>
> struct socfpga_dwmci_plat {
> struct mmc_config cfg;
> @@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
>
> debug("%s: drvsel %d smplsel %d\n", __func__,
> priv->drvsel, priv->smplsel);
> - writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
> + writel(sdmmc_mask, socfpga_sysmgr_base + SYSMGR_SDMMC);
>
> debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
> - readl(&system_manager_base->sdmmcgrp_ctrl));
> + readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
>
> /* Enable SDMMC clock */
> setbits_le32(&clock_manager_base->per_pll.en,
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system manager from struct to defines
2019-10-02 9:20 ` Simon Goldschmidt
@ 2019-10-04 3:05 ` Ley Foon Tan
0 siblings, 0 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-10-04 3:05 UTC (permalink / raw)
To: u-boot
On Wed, Oct 2, 2019 at 5:20 PM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> >
> > Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
> > to defines.
> > No functional change.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> >
> > ---
> > v2:
> > - Change to use writel(), readl() and etc.
> > - Get base address from DT.
>
> Same as 2/4: separate patch please.
Same for this, will remove "no functional change" in commit message.
Thanks
Ley Foon
>
> > - Add prefix to defines.
> > ---
> > arch/arm/mach-socfpga/clock_manager_s10.c | 4 +-
> > .../include/mach/system_manager.h | 2 +
> > .../include/mach/system_manager_arria10.h | 94 +++------
> > .../include/mach/system_manager_gen5.h | 123 +++---------
> > .../include/mach/system_manager_s10.h | 184 +++++++-----------
> > arch/arm/mach-socfpga/mailbox_s10.c | 6 +-
> > arch/arm/mach-socfpga/misc.c | 5 +
> > arch/arm/mach-socfpga/misc_arria10.c | 9 +-
> > arch/arm/mach-socfpga/misc_gen5.c | 22 ++-
> > arch/arm/mach-socfpga/misc_s10.c | 9 +-
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 24 +--
> > arch/arm/mach-socfpga/reset_manager_gen5.c | 7 +-
> > arch/arm/mach-socfpga/reset_manager_s10.c | 18 +-
> > arch/arm/mach-socfpga/scan_manager.c | 6 +-
> > arch/arm/mach-socfpga/spl_a10.c | 5 +-
> > arch/arm/mach-socfpga/spl_gen5.c | 11 +-
> > arch/arm/mach-socfpga/spl_s10.c | 12 +-
> > arch/arm/mach-socfpga/system_manager_gen5.c | 38 ++--
> > arch/arm/mach-socfpga/system_manager_s10.c | 39 ++--
> > arch/arm/mach-socfpga/wrap_pll_config_s10.c | 11 +-
> > drivers/ddr/altera/sdram_gen5.c | 10 +-
> > drivers/ddr/altera/sdram_s10.c | 6 +-
> > drivers/fpga/socfpga_arria10.c | 7 +-
> > drivers/fpga/socfpga_gen5.c | 4 +-
> > drivers/mmc/socfpga_dw_mmc.c | 6 +-
> > 25 files changed, 240 insertions(+), 422 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> > index 3ba2a00c02..6cbf07ac6f 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -14,8 +14,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static const struct socfpga_clock_manager *clock_manager_base =
> > (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /*
> > * function to write the bypass register which requires a poll of the
> > @@ -351,7 +349,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >
> > unsigned int cm_get_qspi_controller_clk_hz(void)
> > {
> > - return readl(&sysmgr_regs->boot_scratch_cold0);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> > }
> >
> > unsigned int cm_get_spi_controller_clk_hz(void)
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > index 7e76df74b7..803305eb35 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > @@ -6,6 +6,8 @@
> > #ifndef _SYSTEM_MANAGER_H_
> > #define _SYSTEM_MANAGER_H_
> >
> > +extern phys_addr_t socfpga_sysmgr_base;
> > +
> > #if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > #include <asm/arch/system_manager_s10.h>
> > #else
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > index 14052b957c..1a45c0f134 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
> > @@ -6,73 +6,33 @@
> > #ifndef _SYSTEM_MANAGER_ARRIA10_H_
> > #define _SYSTEM_MANAGER_ARRIA10_H_
> >
> > -struct socfpga_system_manager {
> > - u32 siliconid1;
> > - u32 siliconid2;
> > - u32 wddbg;
> > - u32 bootinfo;
> > - u32 mpu_ctrl_l2_ecc;
> > - u32 _pad_0x14_0x1f[3];
> > - u32 dma;
> > - u32 dma_periph;
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmc_l3master;
> > - u32 nand_bootstrap;
> > - u32 nand_l3master;
> > - u32 usb0_l3master;
> > - u32 usb1_l3master;
> > - u32 emac_global;
> > - u32 emac[3];
> > - u32 _pad_0x50_0x5f[4];
> > - u32 fpgaintf_en_global;
> > - u32 fpgaintf_en_0;
> > - u32 fpgaintf_en_1;
> > - u32 fpgaintf_en_2;
> > - u32 fpgaintf_en_3;
> > - u32 _pad_0x74_0x7f[3];
> > - u32 noc_addr_remap_value;
> > - u32 noc_addr_remap_set;
> > - u32 noc_addr_remap_clear;
> > - u32 _pad_0x8c_0x8f;
> > - u32 ecc_intmask_value;
> > - u32 ecc_intmask_set;
> > - u32 ecc_intmask_clr;
> > - u32 ecc_intstatus_serr;
> > - u32 ecc_intstatus_derr;
> > - u32 mpu_status_l2_ecc;
> > - u32 mpu_clear_l2_ecc;
> > - u32 mpu_status_l1_parity;
> > - u32 mpu_clear_l1_parity;
> > - u32 mpu_set_l1_parity;
> > - u32 _pad_0xb8_0xbf[2];
> > - u32 noc_timeout;
> > - u32 noc_idlereq_set;
> > - u32 noc_idlereq_clr;
> > - u32 noc_idlereq_value;
> > - u32 noc_idleack;
> > - u32 noc_idlestatus;
> > - u32 fpga2soc_ctrl;
> > - u32 _pad_0xdc_0xff[9];
> > - u32 tsmc_tsel_0;
> > - u32 tsmc_tsel_1;
> > - u32 tsmc_tsel_2;
> > - u32 tsmc_tsel_3;
> > - u32 _pad_0x110_0x200[60];
> > - u32 romhw_ctrl;
> > - u32 romcode_ctrl;
> > - u32 romcode_cpu1startaddr;
> > - u32 romcode_initswstate;
> > - u32 romcode_initswlastld;
> > - u32 _pad_0x214_0x217;
> > - u32 warmram_enable;
> > - u32 warmram_datastart;
> > - u32 warmram_length;
> > - u32 warmram_execution;
> > - u32 warmram_crc;
> > - u32 _pad_0x22c_0x22f;
> > - u32 isw_handoff[8];
> > - u32 romcode_bootromswstate[8];
> > -};
> > +#define SYSMGR_A10_WDDBG 0x8
> > +#define SYSMGR_A10_BOOTINFO 0xc
> > +#define SYSMGR_A10_DMA 0x20
> > +#define SYSMGR_A10_DMA_PERIPH 0x24
> > +#define SYSMGR_A10_SDMMC 0x28
> > +#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
> > +#define SYSMGR_A10_EMAC_GLOBAL 0x40
> > +#define SYSMGR_A10_EMAC0 0x44
> > +#define SYSMGR_A10_EMAC1 0x48
> > +#define SYSMGR_A10_EMAC2 0x4c
> > +#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
> > +#define SYSMGR_A10_FPGAINTF_EN0 0x64
> > +#define SYSMGR_A10_FPGAINTF_EN1 0x68
> > +#define SYSMGR_A10_FPGAINTF_EN2 0x6c
> > +#define SYSMGR_A10_FPGAINTF_EN3 0x70
> > +#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
> > +#define SYSMGR_A10_ECC_INTMASK_SET 0x94
> > +#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
> > +#define SYSMGR_A10_NOC_TIMEOUT 0xc0
> > +#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
> > +#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
> > +#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
> > +#define SYSMGR_A10_NOC_IDLEACK 0xd0
> > +#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
> > +#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
> > +
> > +#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
> >
> > #define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
> > #define SYSMGR_BOOTINFO_BSEL_SHIFT 12
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > index 52e59df513..90cb465d13 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
> > @@ -13,106 +13,29 @@ void sysmgr_config_warmrstcfgio(int enable);
> >
> > void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
> >
> > -struct socfpga_system_manager {
> > - /* System Manager Module */
> > - u32 siliconid1; /* 0x00 */
> > - u32 siliconid2;
> > - u32 _pad_0x8_0xf[2];
> > - u32 wddbg; /* 0x10 */
> > - u32 bootinfo;
> > - u32 hpsinfo;
> > - u32 parityinj;
> > - /* FPGA Interface Group */
> > - u32 fpgaintfgrp_gbl; /* 0x20 */
> > - u32 fpgaintfgrp_indiv;
> > - u32 fpgaintfgrp_module;
> > - u32 _pad_0x2c_0x2f;
> > - /* Scan Manager Group */
> > - u32 scanmgrgrp_ctrl; /* 0x30 */
> > - u32 _pad_0x34_0x3f[3];
> > - /* Freeze Control Group */
> > - u32 frzctrl_vioctrl; /* 0x40 */
> > - u32 _pad_0x44_0x4f[3];
> > - u32 frzctrl_hioctrl; /* 0x50 */
> > - u32 frzctrl_src;
> > - u32 frzctrl_hwctrl;
> > - u32 _pad_0x5c_0x5f;
> > - /* EMAC Group */
> > - u32 emacgrp_ctrl; /* 0x60 */
> > - u32 emacgrp_l3master;
> > - u32 _pad_0x68_0x6f[2];
> > - /* DMA Controller Group */
> > - u32 dmagrp_ctrl; /* 0x70 */
> > - u32 dmagrp_persecurity;
> > - u32 _pad_0x78_0x7f[2];
> > - /* Preloader (initial software) Group */
> > - u32 iswgrp_handoff[8]; /* 0x80 */
> > - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */
> > - /* Boot ROM Code Register Group */
> > - u32 romcodegrp_ctrl; /* 0xc0 */
> > - u32 romcodegrp_cpu1startaddr;
> > - u32 romcodegrp_initswstate;
> > - u32 romcodegrp_initswlastld;
> > - u32 romcodegrp_bootromswstate; /* 0xd0 */
> > - u32 __pad_0xd4_0xdf[3];
> > - /* Warm Boot from On-Chip RAM Group */
> > - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */
> > - u32 romcodegrp_warmramgrp_datastart;
> > - u32 romcodegrp_warmramgrp_length;
> > - u32 romcodegrp_warmramgrp_execution;
> > - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */
> > - u32 __pad_0xf4_0xff[3];
> > - /* Boot ROM Hardware Register Group */
> > - u32 romhwgrp_ctrl; /* 0x100 */
> > - u32 _pad_0x104_0x107;
> > - /* SDMMC Controller Group */
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmcgrp_l3master;
> > - /* NAND Flash Controller Register Group */
> > - u32 nandgrp_bootstrap; /* 0x110 */
> > - u32 nandgrp_l3master;
> > - /* USB Controller Group */
> > - u32 usbgrp_l3master;
> > - u32 _pad_0x11c_0x13f[9];
> > - /* ECC Management Register Group */
> > - u32 eccgrp_l2; /* 0x140 */
> > - u32 eccgrp_ocram;
> > - u32 eccgrp_usb0;
> > - u32 eccgrp_usb1;
> > - u32 eccgrp_emac0; /* 0x150 */
> > - u32 eccgrp_emac1;
> > - u32 eccgrp_dma;
> > - u32 eccgrp_can0;
> > - u32 eccgrp_can1; /* 0x160 */
> > - u32 eccgrp_nand;
> > - u32 eccgrp_qspi;
> > - u32 eccgrp_sdmmc;
> > - u32 _pad_0x170_0x3ff[164];
> > - /* Pin Mux Control Group */
> > - u32 emacio[20]; /* 0x400 */
> > - u32 flashio[12]; /* 0x450 */
> > - u32 generalio[28]; /* 0x480 */
> > - u32 _pad_0x4f0_0x4ff[4];
> > - u32 mixed1io[22]; /* 0x500 */
> > - u32 mixed2io[8]; /* 0x558 */
> > - u32 gplinmux[23]; /* 0x578 */
> > - u32 gplmux[71]; /* 0x5d4 */
> > - u32 nandusefpga; /* 0x6f0 */
> > - u32 _pad_0x6f4;
> > - u32 rgmii1usefpga; /* 0x6f8 */
> > - u32 _pad_0x6fc_0x700[2];
> > - u32 i2c0usefpga; /* 0x704 */
> > - u32 sdmmcusefpga; /* 0x708 */
> > - u32 _pad_0x70c_0x710[2];
> > - u32 rgmii0usefpga; /* 0x714 */
> > - u32 _pad_0x718_0x720[3];
> > - u32 i2c3usefpga; /* 0x724 */
> > - u32 i2c2usefpga; /* 0x728 */
> > - u32 i2c1usefpga; /* 0x72c */
> > - u32 spim1usefpga; /* 0x730 */
> > - u32 _pad_0x734;
> > - u32 spim0usefpga; /* 0x738 */
> > -};
> > +#define SYSMGR_GEN5_WDDBG 0x10
> > +#define SYSMGR_GEN5_BOOTINFO 0x14
> > +#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
> > +#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
> > +#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
> > +#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
> > +#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
> > +#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
> > +#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
> > +#define SYSMGR_GEN5_SDMMC 0x108
> > +#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
> > +#define SYSMGR_GEN5_EMACIO 0x400
> > +#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
> > +#define SYSMGR_GEN5_RGMII0_USEFPGA 0x6f8
> > +#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
> > +#define SYSMGR_GEN5_RGMII1_USEFPGA 0x704
> > +#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
> > +#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
> > +
> > +#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
> > +
> > +#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
> > + SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
> > #endif
> >
> > #define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > index 297f9e1999..e68a8e730e 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
> > @@ -15,125 +15,73 @@ void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
> > void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
> > void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
> >
> > -struct socfpga_system_manager {
> > - /* System Manager Module */
> > - u32 siliconid1; /* 0x00 */
> > - u32 siliconid2;
> > - u32 wddbg;
> > - u32 _pad_0xc;
> > - u32 mpu_status; /* 0x10 */
> > - u32 mpu_ace;
> > - u32 _pad_0x18_0x1c[2];
> > - u32 dma; /* 0x20 */
> > - u32 dma_periph;
> > - /* SDMMC Controller Group */
> > - u32 sdmmcgrp_ctrl;
> > - u32 sdmmcgrp_l3master;
> > - /* NAND Flash Controller Register Group */
> > - u32 nandgrp_bootstrap; /* 0x30 */
> > - u32 nandgrp_l3master;
> > - /* USB Controller Group */
> > - u32 usb0_l3master;
> > - u32 usb1_l3master;
> > - /* EMAC Group */
> > - u32 emac_gbl; /* 0x40 */
> > - u32 emac0;
> > - u32 emac1;
> > - u32 emac2;
> > - u32 emac0_ace; /* 0x50 */
> > - u32 emac1_ace;
> > - u32 emac2_ace;
> > - u32 nand_axuser;
> > - u32 _pad_0x60_0x64[2]; /* 0x60 */
> > - /* FPGA interface Group */
> > - u32 fpgaintf_en_1;
> > - u32 fpgaintf_en_2;
> > - u32 fpgaintf_en_3; /* 0x70 */
> > - u32 dma_l3master;
> > - u32 etr_l3master;
> > - u32 _pad_0x7c;
> > - u32 sec_ctrl_slt; /* 0x80 */
> > - u32 osc_trim;
> > - u32 _pad_0x88_0x8c[2];
> > - /* ECC Group */
> > - u32 ecc_intmask_value; /* 0x90 */
> > - u32 ecc_intmask_set;
> > - u32 ecc_intmask_clr;
> > - u32 ecc_intstatus_serr;
> > - u32 ecc_intstatus_derr; /* 0xa0 */
> > - u32 _pad_0xa4_0xac[3];
> > - u32 noc_addr_remap; /* 0xb0 */
> > - u32 hmc_clk;
> > - u32 io_pa_ctrl;
> > - u32 _pad_0xbc;
> > - /* NOC Group */
> > - u32 noc_timeout; /* 0xc0 */
> > - u32 noc_idlereq_set;
> > - u32 noc_idlereq_clr;
> > - u32 noc_idlereq_value;
> > - u32 noc_idleack; /* 0xd0 */
> > - u32 noc_idlestatus;
> > - u32 fpga2soc_ctrl;
> > - u32 fpga_config;
> > - u32 iocsrclk_gate; /* 0xe0 */
> > - u32 gpo;
> > - u32 gpi;
> > - u32 _pad_0xec;
> > - u32 mpu; /* 0xf0 */
> > - u32 sdm_hps_spare;
> > - u32 hps_sdm_spare;
> > - u32 _pad_0xfc_0x1fc[65];
> > - /* Boot scratch register group */
> > - u32 boot_scratch_cold0; /* 0x200 */
> > - u32 boot_scratch_cold1;
> > - u32 boot_scratch_cold2;
> > - u32 boot_scratch_cold3;
> > - u32 boot_scratch_cold4; /* 0x210 */
> > - u32 boot_scratch_cold5;
> > - u32 boot_scratch_cold6;
> > - u32 boot_scratch_cold7;
> > - u32 boot_scratch_cold8; /* 0x220 */
> > - u32 boot_scratch_cold9;
> > - u32 _pad_0x228_0xffc[886];
> > - /* Pin select and pin control group */
> > - u32 pinsel0[40]; /* 0x1000 */
> > - u32 _pad_0x10a0_0x10fc[24];
> > - u32 pinsel40[8];
> > - u32 _pad_0x1120_0x112c[4];
> > - u32 ioctrl0[28];
> > - u32 _pad_0x11a0_0x11fc[24];
> > - u32 ioctrl28[20];
> > - u32 _pad_0x1250_0x12fc[44];
> > - /* Use FPGA mux */
> > - u32 rgmii0usefpga; /* 0x1300 */
> > - u32 rgmii1usefpga;
> > - u32 rgmii2usefpga;
> > - u32 i2c0usefpga;
> > - u32 i2c1usefpga;
> > - u32 i2c_emac0_usefpga;
> > - u32 i2c_emac1_usefpga;
> > - u32 i2c_emac2_usefpga;
> > - u32 nandusefpga;
> > - u32 _pad_0x1324;
> > - u32 spim0usefpga;
> > - u32 spim1usefpga;
> > - u32 spis0usefpga;
> > - u32 spis1usefpga;
> > - u32 uart0usefpga;
> > - u32 uart1usefpga;
> > - u32 mdio0usefpga;
> > - u32 mdio1usefpga;
> > - u32 mdio2usefpga;
> > - u32 _pad_0x134c;
> > - u32 jtagusefpga;
> > - u32 sdmmcusefpga;
> > - u32 hps_osc_clk;
> > - u32 _pad_0x135c_0x13fc[41];
> > - u32 iodelay0[40];
> > - u32 _pad_0x14a0_0x14fc[24];
> > - u32 iodelay40[8];
> > +#define SYSMGR_S10_WDDBG 0x8
> > +#define SYSMGR_S10_DMA 0x20
> > +#define SYSMGR_S10_DMA_PERIPH 0x24
> > +#define SYSMGR_S10_SDMMC 0x28
> > +#define SYSMGR_S10_SDMMC_L3MASTER 0x2c
> > +#define SYSMGR_S10_EMAC_GLOBAL 0x40
> > +#define SYSMGR_S10_EMAC0 0x44
> > +#define SYSMGR_S10_EMAC1 0x48
> > +#define SYSMGR_S10_EMAC2 0x4c
> > +#define SYSMGR_S10_EMAC0_ACE 0x50
> > +#define SYSMGR_S10_EMAC1_ACE 0x54
> > +#define SYSMGR_S10_EMAC2_ACE 0x58
> > +#define SYSMGR_S10_NAND_AXUSER 0x5c
> > +#define SYSMGR_S10_FPGAINTF_EN1 0x68
> > +#define SYSMGR_S10_FPGAINTF_EN2 0x6c
> > +#define SYSMGR_S10_FPGAINTF_EN3 0x70
> > +#define SYSMGR_S10_DMA_L3MASTER 0x74
> > +#define SYSMGR_S10_HMC_CLK 0xb4
> > +#define SYSMGR_S10_IO_PA_CTRL 0xb8
> > +#define SYSMGR_S10_NOC_TIMEOUT 0xc0
> > +#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4
> > +#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8
> > +#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc
> > +#define SYSMGR_S10_NOC_IDLEACK 0xd0
> > +#define SYSMGR_S10_NOC_IDLESTATUS 0xd4
> > +#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8
> > +#define SYSMGR_S10_FPGA_CONFIG 0xdc
> > +#define SYSMGR_S10_IOCSRCLK_GATE 0xe0
> > +#define SYSMGR_S10_GPO 0xe4
> > +#define SYSMGR_S10_GPI 0xe8
> > +#define SYSMGR_S10_MPU 0xf0
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220
> > +#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224
> > +#define SYSMGR_S10_PINSEL0 0x1000
> > +#define SYSMGR_S10_IOCTRL0 0x1130
> > +#define SYSMGR_S10_EMAC0_USEFPGA 0x1300
> > +#define SYSMGR_S10_EMAC1_USEFPGA 0x1304
> > +#define SYSMGR_S10_EMAC2_USEFPGA 0x1308
> > +#define SYSMGR_S10_I2C0_USEFPGA 0x130c
> > +#define SYSMGR_S10_I2C1_USEFPGA 0x1310
> > +#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314
> > +#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318
> > +#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c
> > +#define SYSMGR_S10_NAND_USEFPGA 0x1320
> > +#define SYSMGR_S10_SPIM0_USEFPGA 0x1328
> > +#define SYSMGR_S10_SPIM1_USEFPGA 0x132c
> > +#define SYSMGR_S10_SPIS0_USEFPGA 0x1330
> > +#define SYSMGR_S10_SPIS1_USEFPGA 0x1334
> > +#define SYSMGR_S10_UART0_USEFPGA 0x1338
> > +#define SYSMGR_S10_UART1_USEFPGA 0x133c
> > +#define SYSMGR_S10_MDIO0_USEFPGA 0x1340
> > +#define SYSMGR_S10_MDIO1_USEFPGA 0x1344
> > +#define SYSMGR_S10_MDIO2_USEFPGA 0x1348
> > +#define SYSMGR_S10_JTAG_USEFPGA 0x1350
> > +#define SYSMGR_S10_SDMMC_USEFPGA 0x1354
> > +#define SYSMGR_S10_HPS_OSC_CLK 0x1358
> > +#define SYSMGR_S10_IODELAY0 0x1400
> >
> > -};
> > +#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
> >
> > #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
> > #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
> > diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
> > index 4498ab55df..11b57361c7 100644
> > --- a/arch/arm/mach-socfpga/mailbox_s10.c
> > +++ b/arch/arm/mach-socfpga/mailbox_s10.c
> > @@ -287,9 +287,6 @@ int mbox_qspi_close(void)
> >
> > int mbox_qspi_open(void)
> > {
> > - static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > int ret;
> > u32 resp_buf[1];
> > u32 resp_buf_len;
> > @@ -318,7 +315,8 @@ int mbox_qspi_open(void)
> >
> > /* We are getting QSPI ref clock and set into sysmgr boot register */
> > printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]);
> > - writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0);
> > + writel(resp_buf[0],
> > + socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
> >
> > return 0;
> >
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > index 901c432f82..fcc53b6fbc 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -23,6 +23,7 @@
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > phys_addr_t socfpga_rstmgr_base __section(".data");
> > +phys_addr_t socfpga_sysmgr_base __section(".data");
> >
> > #ifdef CONFIG_SYS_L2_PL310
> > static const struct pl310_regs *const pl310 =
> > @@ -233,4 +234,8 @@ void socfpga_get_manager_addr(void)
> > socfpga_rstmgr_base = socfpga_get_base_addr("altr,rst-mgr");
> > if (!socfpga_rstmgr_base)
> > hang();
> > +
> > + socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
> > + if (!socfpga_sysmgr_base)
> > + hang();
> > }
> > diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
> > index 2e2a40b65d..ff6ab83441 100644
> > --- a/arch/arm/mach-socfpga/misc_arria10.c
> > +++ b/arch/arm/mach-socfpga/misc_arria10.c
> > @@ -28,9 +28,6 @@
> > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
> > #define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * FPGA programming support for SoC FPGA Arria 10
> > */
> > @@ -81,7 +78,7 @@ void socfpga_init_security_policies(void)
> > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
> > writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
> >
> > - writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
> > + writel(0x0007FFFF, socfpga_sysmgr_base + SYSMGR_A10_ECC_INTMASK_SET);
> > }
> >
> > void socfpga_sdram_remap_zero(void)
> > @@ -105,8 +102,8 @@ int arch_early_init_r(void)
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > int print_cpuinfo(void)
> > {
> > - const u32 bsel =
> > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
> > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
> >
> > puts("CPU: Altera SoCFPGA Arria 10\n");
> >
> > diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
> > index b39a66562d..7735958e9c 100644
> > --- a/arch/arm/mach-socfpga/misc_gen5.c
> > +++ b/arch/arm/mach-socfpga/misc_gen5.c
> > @@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > static struct nic301_registers *nic301_regs =
> > (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > static struct scu_registers *scu_regs =
> > @@ -118,8 +116,8 @@ static int socfpga_fpga_id(const bool print_id)
> > #if defined(CONFIG_DISPLAY_CPUINFO)
> > int print_cpuinfo(void)
> > {
> > - const u32 bsel =
> > - SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
> > + u32 bootinfo = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
> > + const u32 bsel = SYSMGR_GET_BOOTINFO_BSEL(bootinfo);
> >
> > puts("CPU: Altera SoCFPGA Platform\n");
> > socfpga_fpga_id(1);
> > @@ -132,7 +130,8 @@ int print_cpuinfo(void)
> > #ifdef CONFIG_ARCH_MISC_INIT
> > int arch_misc_init(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
> > + const u32 bsel = readl(socfpga_sysmgr_base +
> > + SYSMGR_GEN5_BOOTINFO) & 0x7;
> > const int fpga_id = socfpga_fpga_id(0);
> > env_set("bootmode", bsel_str[bsel].mode);
> > if (fpga_id >= 0)
> > @@ -190,10 +189,11 @@ int arch_early_init_r(void)
> > * to support that old code, we write it here instead of in the
> > * reset_cpu() function just before resetting the CPU.
> > */
> > - writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
> > + writel(0xae9efebc, socfpga_sysmgr_base + SYSMGR_GEN5_WARMRAMGRP_EN);
> >
> > for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> > - iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
> > + iswgrp_handoff[i] = readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
> >
> > socfpga_bridges_reset(1);
> >
> > @@ -219,16 +219,18 @@ void do_bridge_reset(int enable, unsigned int mask)
> > !(mask & BIT(2)));
> > for (i = 0; i < 2; i++) { /* Reload SW setting cache */
> > iswgrp_handoff[i] =
> > - readl(&sysmgr_regs->iswgrp_handoff[i]);
> > + readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(i));
> > }
> >
> > - writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
> > + writel(iswgrp_handoff[2],
> > + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
> > writel(iswgrp_handoff[0],
> > socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(iswgrp_handoff[1], &nic301_regs->remap);
> > } else {
> > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > writel(0, &sdr_ctrl->fpgaport_rst);
> > writel(0, socfpga_rstmgr_base + RSTMGR_GEN5_BRGMODRST);
> > writel(1, &nic301_regs->remap);
> > diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
> > index 0a5fab11c0..16fbf71599 100644
> > --- a/arch/arm/mach-socfpga/misc_s10.c
> > +++ b/arch/arm/mach-socfpga/misc_s10.c
> > @@ -23,9 +23,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * FPGA programming support for SoC FPGA Stratix 10
> > */
> > @@ -68,9 +65,9 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
> > else
> > return -EINVAL;
> >
> > - clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
> > - SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
> > - modereg);
> > + clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 +
> > + gmac_index),
> > + SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
> >
> > return 0;
> > }
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 4553653992..5611e784e6 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -15,9 +15,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > struct bridge_cfg {
> > int compat_id;
> > u32 mask_noc;
> > @@ -98,14 +95,16 @@ int socfpga_reset_deassert_bridges_handoff(void)
> > }
> >
> > /* clear idle request to all bridges */
> > - setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_CLR,
> > + mask_noc);
> >
> > /* Release bridges from reset state per handoff value */
> > clrbits_le32(socfpga_rstmgr_base + RSTMGR_A10_BRGMODRST, mask_rstmgr);
> >
> > /* Poll until all idleack to 0, timeout at 1000ms */
> > - return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
> > - false, 1000, false);
> > + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLEACK),
> > + mask_noc, false, 1000, false);
> > }
> >
> > /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
> > @@ -195,13 +194,15 @@ int socfpga_bridges_reset(void)
> > ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
> > ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
> > ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
> > - &sysmgr_regs->noc_idlereq_set);
> > + socfpga_sysmgr_base + SYSMGR_A10_NOC_IDLEREQ_SET);
> >
> > /* Enable the NOC timeout */
> > - writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
> > + writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
> > + socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
> >
> > /* Poll until all idleack to 1 */
> > - ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
> > + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLEACK),
> > ALT_SYSMGR_NOC_H2F_SET_MSK |
> > ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> > ALT_SYSMGR_NOC_F2H_SET_MSK |
> > @@ -213,7 +214,8 @@ int socfpga_bridges_reset(void)
> > return ret;
> >
> > /* Poll until all idlestatus to 1 */
> > - ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
> > + ret = wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_A10_NOC_IDLESTATUS),
> > ALT_SYSMGR_NOC_H2F_SET_MSK |
> > ALT_SYSMGR_NOC_LWH2F_SET_MSK |
> > ALT_SYSMGR_NOC_F2H_SET_MSK |
> > @@ -234,7 +236,7 @@ int socfpga_bridges_reset(void)
> > ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
> >
> > /* Disable NOC timeout */
> > - writel(0, &sysmgr_regs->noc_timeout);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_NOC_TIMEOUT);
> >
> > return 0;
> > }
> > diff --git a/arch/arm/mach-socfpga/reset_manager_gen5.c b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > index ad31214711..6b617fd016 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_gen5.c
> > @@ -10,9 +10,6 @@
> > #include <asm/arch/reset_manager.h>
> > #include <asm/arch/system_manager.h>
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > @@ -83,8 +80,8 @@ void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
> > if (f2h)
> > brgmask |= BIT(2);
> >
> > - writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
> > - writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
> > + writel(brgmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(0));
> > + writel(l3rmask, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(1));
> > }
> >
> > void socfpga_bridges_reset(int enable)
> > diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c
> > index b196d58d3d..50a2d80930 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_s10.c
> > @@ -12,9 +12,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /* Assert or de-assert SoCFPGA reset manager reset. */
> > void socfpga_per_reset(u32 reset, int set)
> > {
> > @@ -59,28 +56,29 @@ void socfpga_bridges_reset(int enable)
> > {
> > if (enable) {
> > /* clear idle request to all bridges */
> > - setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR,
> > + ~0);
> >
> > /* Release all bridges from reset state */
> > clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
> >
> > /* Poll until all idleack to 0 */
> > - while (readl(&system_manager_base->noc_idleack))
> > + while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
> > ;
> > } else {
> > /* set idle request to all bridges */
> > - writel(~0, &system_manager_base->noc_idlereq_set);
> > + writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET);
> >
> > /* Enable the NOC timeout */
> > - writel(1, &system_manager_base->noc_timeout);
> > + writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> >
> > /* Poll until all idleack to 1 */
> > - while ((readl(&system_manager_base->noc_idleack) ^
> > + while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^
> > (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> > ;
> >
> > /* Poll until all idlestatus to 1 */
> > - while ((readl(&system_manager_base->noc_idlestatus) ^
> > + while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^
> > (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
> > ;
> >
> > @@ -90,7 +88,7 @@ void socfpga_bridges_reset(int enable)
> > RSTMGR_BRGMODRST_FPGA2SOC_MASK));
> >
> > /* Disable NOC timeout */
> > - writel(0, &system_manager_base->noc_timeout);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
> > }
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/scan_manager.c b/arch/arm/mach-socfpga/scan_manager.c
> > index 52175af48b..f1d5f69caa 100644
> > --- a/arch/arm/mach-socfpga/scan_manager.c
> > +++ b/arch/arm/mach-socfpga/scan_manager.c
> > @@ -31,8 +31,6 @@ static const struct socfpga_scan_manager *scan_manager_base =
> > (void *)(SOCFPGA_SCANMGR_ADDRESS);
> > static const struct socfpga_freeze_controller *freeze_controller_base =
> > (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
> > -static struct socfpga_system_manager *sys_mgr_base =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /**
> > * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
> > @@ -218,7 +216,7 @@ u32 scan_mgr_get_fpga_id(void)
> > int ret;
> >
> > /* Enable HPS to talk to JTAG in the FPGA through the System Manager */
> > - writel(0x1, &sys_mgr_base->scanmgrgrp_ctrl);
> > + writel(0x1, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
> >
> > /* Enable port 7 */
> > writel(0x80, &scan_manager_base->en);
> > @@ -253,7 +251,7 @@ u32 scan_mgr_get_fpga_id(void)
> >
> > /* Disable all port */
> > writel(0, &scan_manager_base->en);
> > - writel(0, &sys_mgr_base->scanmgrgrp_ctrl);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_SCANMGRGRP_CTRL);
> >
> > return id;
> > }
> > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
> > index a0d80fd47e..ee811e4ee9 100644
> > --- a/arch/arm/mach-socfpga/spl_a10.c
> > +++ b/arch/arm/mach-socfpga/spl_a10.c
> > @@ -31,12 +31,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_A10_BOOTINFO);
> >
> > switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
> > index 9ee053da3a..82d9fe0824 100644
> > --- a/arch/arm/mach-socfpga/spl_gen5.c
> > +++ b/arch/arm/mach-socfpga/spl_gen5.c
> > @@ -24,12 +24,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > - const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > + const u32 bsel = readl(socfpga_sysmgr_base + SYSMGR_GEN5_BOOTINFO);
> >
> > switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > case 0x1: /* FPGA (HPS2FPGA Bridge) */
> > @@ -77,13 +74,13 @@ void board_init_f(ulong dummy)
> > * First C code to run. Clear fake OCRAM ECC first as SBE
> > * and DBE might triggered during power on
> > */
> > - reg = readl(&sysmgr_regs->eccgrp_ocram);
> > + reg = readl(socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> > if (reg & SYSMGR_ECC_OCRAM_SERR)
> > writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
> > - &sysmgr_regs->eccgrp_ocram);
> > + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> > if (reg & SYSMGR_ECC_OCRAM_DERR)
> > writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
> > - &sysmgr_regs->eccgrp_ocram);
> > + socfpga_sysmgr_base + SYSMGR_GEN5_ECCGRP_OCRAM);
> >
> > socfpga_sdram_remap_zero();
> > socfpga_pl310_clear();
> > diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
> > index 9a97a84e1e..16f19f901d 100644
> > --- a/arch/arm/mach-socfpga/spl_s10.c
> > +++ b/arch/arm/mach-socfpga/spl_s10.c
> > @@ -22,9 +22,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > u32 spl_boot_device(void)
> > {
> > /* TODO: Get from SDM or handoff */
> > @@ -129,7 +126,8 @@ void board_init_f(ulong dummy)
> >
> > #ifdef CONFIG_HW_WATCHDOG
> > /* Ensure watchdog is paused when debugging is happening */
> > - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
> > + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
> > + socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
> >
> > /* Enable watchdog before initializing the HW */
> > socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
> > @@ -157,8 +155,10 @@ void board_init_f(ulong dummy)
> > cm_print_clock_quick_summary();
> >
> > /* enable non-secure interface to DMA330 DMA and peripherals */
> > - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
> > - writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
> > + writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
> > + socfpga_sysmgr_base + SYSMGR_S10_DMA);
> > + writel(SYSMGR_DMAPERIPH_ALL_NS,
> > + socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
> >
> > spl_disable_firewall_l4_per();
> >
> > diff --git a/arch/arm/mach-socfpga/system_manager_gen5.c b/arch/arm/mach-socfpga/system_manager_gen5.c
> > index 9d04aea2a8..1053a47201 100644
> > --- a/arch/arm/mach-socfpga/system_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/system_manager_gen5.c
> > @@ -8,9 +8,6 @@
> > #include <asm/arch/system_manager.h>
> > #include <asm/arch/fpga_manager.h>
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
> > * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
> > @@ -21,30 +18,39 @@ static void populate_sysmgr_fpgaintf_module(void)
> > u32 handoff_val = 0;
> >
> > /* ISWGRP_HANDOFF_FPGAINTF */
> > - writel(0, &sysmgr_regs->iswgrp_handoff[2]);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
> >
> > /* Enable the signal for those HPS peripherals that use FPGA. */
> > - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_NAND_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_NAND;
> > - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> > - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SDMMC_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> > - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_RGMII0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> > - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> > - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_GEN5_SPIM1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> >
> > /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
> > based on pinmux setting */
> > - setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
> > + handoff_val);
> >
> > - handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
> > + handoff_val = readl(socfpga_sysmgr_base +
> > + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
> > if (fpgamgr_test_fpga_ready()) {
> > /* Enable the required signals only */
> > - writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(handoff_val,
> > + socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> > }
> > }
> >
> > @@ -53,7 +59,7 @@ static void populate_sysmgr_fpgaintf_module(void)
> > */
> > void sysmgr_pinmux_init(void)
> > {
> > - u32 regs = (u32)&sysmgr_regs->emacio[0];
> > + u32 regs = (u32)socfpga_sysmgr_base + SYSMGR_GEN5_EMACIO;
> > const u8 *sys_mgr_init_table;
> > unsigned int len;
> > int i;
> > @@ -74,9 +80,9 @@ void sysmgr_pinmux_init(void)
> > void sysmgr_config_warmrstcfgio(int enable)
> > {
> > if (enable)
> > - setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> > + setbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
> > SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> > else
> > - clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
> > + clrbits_le32(socfpga_sysmgr_base + SYSMGR_GEN5_ROMCODEGRP_CTRL,
> > SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
> > }
> > diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c
> > index 122828c9ce..c046bb17c9 100644
> > --- a/arch/arm/mach-socfpga/system_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/system_manager_s10.c
> > @@ -10,9 +10,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > /*
> > * Configure all the pin muxes
> > */
> > @@ -32,24 +29,31 @@ void populate_sysmgr_fpgaintf_module(void)
> > u32 handoff_val = 0;
> >
> > /* Enable the signal for those HPS peripherals that use FPGA. */
> > - if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_NAND;
> > - if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SDMMC;
> > - if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM0;
> > - if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_SPIM1;
> > - writel(handoff_val, &sysmgr_regs->fpgaintf_en_2);
> > + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
> >
> > handoff_val = 0;
> > - if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC0;
> > - if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC1;
> > - if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA)
> > + if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
> > + SYSMGR_FPGAINTF_USEFPGA)
> > handoff_val |= SYSMGR_FPGAINTF_EMAC2;
> > - writel(handoff_val, &sysmgr_regs->fpgaintf_en_3);
> > + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
> > }
> >
> > /*
> > @@ -64,14 +68,16 @@ void populate_sysmgr_pinmux(void)
> > sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->pinsel0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
> > }
> >
> > /* setup the pin ctrl */
> > sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->ioctrl0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
> > }
> >
> > /* setup the fpga use */
> > @@ -79,13 +85,14 @@ void populate_sysmgr_pinmux(void)
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > sys_mgr_table_u32[i] +
> > - (u8 *)&sysmgr_regs->rgmii0usefpga);
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA);
> > }
> >
> > /* setup the IO delay */
> > sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
> > for (i = 0; i < len; i = i + 2) {
> > writel(sys_mgr_table_u32[i + 1],
> > - sys_mgr_table_u32[i] + (u8 *)&sysmgr_regs->iodelay0[0]);
> > + sys_mgr_table_u32[i] +
> > + (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
> > }
> > }
> > diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > index 7cafc7dcfc..c9570fea38 100644
> > --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c
> > @@ -10,9 +10,6 @@
> > #include <asm/arch/handoff_s10.h>
> > #include <asm/arch/system_manager.h>
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > const struct cm_config * const cm_get_default_config(void)
> > {
> > struct cm_config *cm_handoff_cfg = (struct cm_config *)
> > @@ -38,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void)
> > #ifdef CONFIG_SPL_BUILD
> > u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
> >
> > - writel(clock, &sysmgr_regs->boot_scratch_cold1);
> > + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> > #endif
> > - return readl(&sysmgr_regs->boot_scratch_cold1);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
> > }
> >
> > const unsigned int cm_get_intosc_clk_hz(void)
> > @@ -53,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void)
> > #ifdef CONFIG_SPL_BUILD
> > u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
> >
> > - writel(clock, &sysmgr_regs->boot_scratch_cold2);
> > + writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> > #endif
> > - return readl(&sysmgr_regs->boot_scratch_cold2);
> > + return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
> > }
> > diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c
> > index fcd89b619d..46a5c466a7 100644
> > --- a/drivers/ddr/altera/sdram_gen5.c
> > +++ b/drivers/ddr/altera/sdram_gen5.c
> > @@ -40,9 +40,6 @@ struct sdram_prot_rule {
> > u32 hi_prot_id;
> > };
> >
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
> >
> > /**
> > @@ -455,12 +452,13 @@ int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
> > SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
> > int ret;
> >
> > - writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
> > + writel(rows, socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
> >
> > sdr_load_regs(sdr_ctrl, cfg);
> >
> > /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
> > - writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
> > + writel(cfg->fpgaport_rst,
> > + socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(3));
> >
> > /* only enable if the FPGA is programmed */
> > if (fpgamgr_test_fpga_ready()) {
> > @@ -516,7 +514,7 @@ static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
> > * since the FB specifies we modify ROWBITs to work around SDRAM
> > * controller issue.
> > */
> > - row = readl(&sysmgr_regs->iswgrp_handoff[4]);
> > + row = readl(socfpga_sysmgr_base + SYSMGR_ISWGRP_HANDOFF_OFFSET(4));
> > if (row == 0)
> > row = rowbits;
> > /*
> > diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
> > index 56cbbac9fe..d5812f2fd7 100644
> > --- a/drivers/ddr/altera/sdram_s10.c
> > +++ b/drivers/ddr/altera/sdram_s10.c
> > @@ -32,9 +32,6 @@ struct altera_sdram_platdata {
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_system_manager *sysmgr_regs =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
> >
> > #define PGTABLE_OFF 0x4000
> > @@ -150,7 +147,8 @@ static int emif_reset(struct altera_sdram_platdata *plat)
> >
> > static int poll_hmc_clock_status(void)
> > {
> > - return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
> > + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
> > + SYSMGR_S10_HMC_CLK),
> > SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
> > }
> >
> > diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> > index 5fb9d6a191..743326cdb3 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
> > static const struct socfpga_fpga_manager *fpga_manager_base =
> > (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> >
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> > -
> > static void fpgamgr_set_cd_ratio(unsigned long ratio);
> >
> > static uint32_t fpgamgr_get_msel(void)
> > @@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
> > }
> >
> > /* Disable all signals from HPS peripheral controller to FPGA */
> > - writel(0, &system_manager_base->fpgaintf_en_global);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
> >
> > /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */
> > socfpga_bridges_reset();
> > @@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> > memset(&rbfinfo, 0, sizeof(rbfinfo));
> >
> > /* Disable all signals from hps peripheral controller to fpga */
> > - writel(0, &system_manager_base->fpgaintf_en_global);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_A10_FPGAINTF_EN_GLOBAL);
> >
> > /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
> > socfpga_bridges_reset();
> > diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c
> > index 6d16e0b37f..2b98572742 100644
> > --- a/drivers/fpga/socfpga_gen5.c
> > +++ b/drivers/fpga/socfpga_gen5.c
> > @@ -15,8 +15,6 @@
> >
> > static struct socfpga_fpga_manager *fpgamgr_regs =
> > (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> > -static struct socfpga_system_manager *sysmgr_regs =
> > - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > /* Set CD ratio */
> > static void fpgamgr_set_cd_ratio(unsigned long ratio)
> > @@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
> > /* Prior programming the FPGA, all bridges need to be shut off */
> >
> > /* Disable all signals from hps peripheral controller to fpga */
> > - writel(0, &sysmgr_regs->fpgaintfgrp_module);
> > + writel(0, socfpga_sysmgr_base + SYSMGR_GEN5_FPGAINFGRP_MODULE);
> >
> > /* Disable all signals from FPGA to HPS SDRAM */
> > #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
> > diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> > index 739c1629a2..bdcd568d60 100644
> > --- a/drivers/mmc/socfpga_dw_mmc.c
> > +++ b/drivers/mmc/socfpga_dw_mmc.c
> > @@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
> >
> > static const struct socfpga_clock_manager *clock_manager_base =
> > (void *)SOCFPGA_CLKMGR_ADDRESS;
> > -static const struct socfpga_system_manager *system_manager_base =
> > - (void *)SOCFPGA_SYSMGR_ADDRESS;
> >
> > struct socfpga_dwmci_plat {
> > struct mmc_config cfg;
> > @@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> >
> > debug("%s: drvsel %d smplsel %d\n", __func__,
> > priv->drvsel, priv->smplsel);
> > - writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
> > + writel(sdmmc_mask, socfpga_sysmgr_base + SYSMGR_SDMMC);
> >
> > debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
> > - readl(&system_manager_base->sdmmcgrp_ctrl));
> > + readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
> >
> > /* Enable SDMMC clock */
> > setbits_le32(&clock_manager_base->per_pll.en,
> > --
> > 2.19.0
> >
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock manager from struct to defines
2019-09-10 8:37 [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines Ley Foon Tan
` (2 preceding siblings ...)
2019-09-10 8:38 ` [U-Boot] [PATCH v2 3/4] arm: socfpga: Convert system " Ley Foon Tan
@ 2019-09-10 8:38 ` Ley Foon Tan
2019-10-02 9:22 ` Simon Goldschmidt
2019-09-17 22:33 ` [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers " Dinh Nguyen
4 siblings, 1 reply; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-10 8:38 UTC (permalink / raw)
To: u-boot
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
No functional change.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
v2:
- Change to use writel(), readl() and etc.
- Get base address from DT.
- Add prefix to defines.
---
arch/arm/mach-socfpga/clock_manager.c | 12 +-
arch/arm/mach-socfpga/clock_manager_arria10.c | 156 +++++++------
arch/arm/mach-socfpga/clock_manager_gen5.c | 199 +++++++++--------
arch/arm/mach-socfpga/clock_manager_s10.c | 206 ++++++++++--------
.../mach-socfpga/include/mach/clock_manager.h | 2 +
.../include/mach/clock_manager_arria10.h | 133 +++++------
.../include/mach/clock_manager_gen5.h | 112 ++++------
.../include/mach/clock_manager_s10.h | 115 ++++------
arch/arm/mach-socfpga/misc.c | 5 +
drivers/mmc/socfpga_dw_mmc.c | 11 +-
10 files changed, 476 insertions(+), 475 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 9f3c643df8..09857dc37b 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -10,18 +10,15 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
void cm_wait_for_lock(u32 mask)
{
u32 inter_val;
u32 retry = 0;
do {
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- inter_val = readl(&clock_manager_base->inter) & mask;
+ inter_val = readl(socfpga_clkmgr_base + CLKMGR_INTER) & mask;
#else
- inter_val = readl(&clock_manager_base->stat) & mask;
+ inter_val = readl(socfpga_clkmgr_base + CLKMGR_STAT) & mask;
#endif
/* Wait for stable lock */
if (inter_val == mask)
@@ -36,8 +33,9 @@ void cm_wait_for_lock(u32 mask)
/* function to poll in the fsm busy bit */
int cm_wait_for_fsm(void)
{
- return wait_for_bit_le32(&clock_manager_base->stat,
- CLKMGR_STAT_BUSY, false, 20000, false);
+ return wait_for_bit_le32((const void *)(socfpga_clkmgr_base +
+ CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
+ false);
}
int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 334a79fd9c..33aebd4f47 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
return 0;
}
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
/* calculate the intended main VCO frequency based on handoff */
static unsigned int cm_calc_handoff_main_vco_clk_hz
(struct mainpll_cfg *main_cfg)
@@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
writel((main_cfg->vco1_denom <<
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
- &clock_manager_base->main_pll.vco1);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
- main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
+ main_cfg->vco1_numer,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
@@ -579,14 +577,17 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
/* execute the ramping here */
for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
- writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
- cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
- &clock_manager_base->per_pll.vco1);
+ writel((per_cfg->vco1_denom <<
+ CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
+ clk_hz),
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
- per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
+ per_cfg->vco1_numer,
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
mdelay(1);
cm_wait_for_lock(LOCKED_MASK);
}
@@ -638,16 +639,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
/* gate off all mainpll clock excpet HW managed clock */
writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
- &clock_manager_base->main_pll.enr);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENR);
/* now we can gate off the rest of the peripheral clocks */
- writel(0, &clock_manager_base->per_pll.en);
+ writel(0, socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EN);
/* Put all plls in external bypass */
writel(CLKMGR_MAINPLL_BYPASS_RESET,
- &clock_manager_base->main_pll.bypasss);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSS);
writel(CLKMGR_PERPLL_BYPASS_RESET,
- &clock_manager_base->per_pll.bypasss);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSS);
/*
* Put all plls VCO registers back to reset value.
@@ -657,15 +658,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
writel(CLKMGR_MAINPLL_VCO0_RESET |
CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
(main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
- &clock_manager_base->main_pll.vco0);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
writel(CLKMGR_PERPLL_VCO0_RESET |
CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
(per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
- &clock_manager_base->per_pll.vco0);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
- writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
- writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
+ writel(CLKMGR_MAINPLL_VCO1_RESET,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
+ writel(CLKMGR_PERPLL_VCO1_RESET,
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
/* clear the interrupt register status register */
writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
@@ -676,7 +679,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
- &clock_manager_base->intr);
+ socfpga_clkmgr_base + CLKMGR_A10_INTR);
/* Program VCO Numerator and Denominator for main PLL */
ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
@@ -687,14 +690,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
else if (ramp_required == 2)
pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
- writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ writel((main_cfg->vco1_denom <<
+ CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
pll_ramp_main_hz),
- &clock_manager_base->main_pll.vco1);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
} else
- writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
- main_cfg->vco1_numer,
- &clock_manager_base->main_pll.vco1);
+ writel((main_cfg->vco1_denom <<
+ CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
+ main_cfg->vco1_numer,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
/* Program VCO Numerator and Denominator for periph PLL */
ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
@@ -707,23 +712,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
pll_ramp_periph_hz =
CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
- writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ writel((per_cfg->vco1_denom <<
+ CLKMGR_PERPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
pll_ramp_periph_hz),
- &clock_manager_base->per_pll.vco1);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
} else
- writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
+ writel((per_cfg->vco1_denom <<
+ CLKMGR_PERPLL_VCO1_DENOM_LSB) |
per_cfg->vco1_numer,
- &clock_manager_base->per_pll.vco1);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
/* Wait for at least 5 us */
udelay(5);
/* Now deassert BGPWRDN and PWRDN */
- clrbits_le32(&clock_manager_base->main_pll.vco0,
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
- clrbits_le32(&clock_manager_base->per_pll.vco0,
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
@@ -731,84 +738,90 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
udelay(7);
/* enable the VCO and disable the external regulator to PLL */
- writel((readl(&clock_manager_base->main_pll.vco0) &
+ writel((readl(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0) &
~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
- &clock_manager_base->main_pll.vco0);
- writel((readl(&clock_manager_base->per_pll.vco0) &
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
+ writel((readl(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0) &
~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
CLKMGR_PERPLL_VCO0_EN_SET_MSK,
- &clock_manager_base->per_pll.vco0);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
/* setup all the main PLL counter and clock source */
- writel(main_cfg->nocclk,
- SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
- writel(main_cfg->mpuclk,
- SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
+ writel(main_cfg->nocclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_NOCCLK);
+ writel(main_cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_MPUCLK);
/* main_emaca_clk divider */
- writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
+ writel(main_cfg->cntr2clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR2CLK);
/* main_emacb_clk divider */
- writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
+ writel(main_cfg->cntr3clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR3CLK);
/* main_emac_ptp_clk divider */
- writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
+ writel(main_cfg->cntr4clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR4CLK);
/* main_gpio_db_clk divider */
- writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
+ writel(main_cfg->cntr5clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR5CLK);
/* main_sdmmc_clk divider */
- writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
+ writel(main_cfg->cntr6clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR6CLK);
/* main_s2f_user0_clk divider */
writel(main_cfg->cntr7clk_cnt |
(main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
- &clock_manager_base->main_pll.cntr7clk);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR7CLK);
/* main_s2f_user1_clk divider */
- writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
+ writel(main_cfg->cntr8clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR8CLK);
/* main_hmc_pll_clk divider */
writel(main_cfg->cntr9clk_cnt |
(main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
- &clock_manager_base->main_pll.cntr9clk);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR9CLK);
/* main_periph_ref_clk divider */
writel(main_cfg->cntr15clk_cnt,
- &clock_manager_base->main_pll.cntr15clk);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR15CLK);
/* setup all the peripheral PLL counter and clock source */
/* peri_emaca_clk divider */
writel(per_cfg->cntr2clk_cnt |
(per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr2clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR2CLK);
/* peri_emacb_clk divider */
writel(per_cfg->cntr3clk_cnt |
(per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr3clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR3CLK);
/* peri_emac_ptp_clk divider */
writel(per_cfg->cntr4clk_cnt |
(per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr4clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR4CLK);
/* peri_gpio_db_clk divider */
writel(per_cfg->cntr5clk_cnt |
(per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr5clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR5CLK);
/* peri_sdmmc_clk divider */
writel(per_cfg->cntr6clk_cnt |
(per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr6clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR6CLK);
/* peri_s2f_user0_clk divider */
- writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
+ writel(per_cfg->cntr7clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR7CLK);
/* peri_s2f_user1_clk divider */
writel(per_cfg->cntr8clk_cnt |
(per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
- &clock_manager_base->per_pll.cntr8clk);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR8CLK);
/* peri_hmc_pll_clk divider */
- writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
+ writel(per_cfg->cntr9clk_cnt,
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR9CLK);
/* setup all the external PLL counter */
/* mpu wrapper / external divider */
writel(main_cfg->mpuclk_cnt |
(main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
- &clock_manager_base->main_pll.mpuclk);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_MPUCLK);
/* NOC wrapper / external divider */
writel(main_cfg->nocclk_cnt |
(main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
- &clock_manager_base->main_pll.nocclk);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCCLK);
/* NOC subclock divider such as l4 */
writel(main_cfg->nocdiv_l4mainclk |
(main_cfg->nocdiv_l4mpclk <<
@@ -821,10 +834,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
(main_cfg->nocdiv_cspdbclk <<
CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
- &clock_manager_base->main_pll.nocdiv);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCDIV);
/* gpio_db external divider */
writel(per_cfg->gpiodiv_gpiodbclk,
- &clock_manager_base->per_pll.gpiodiv);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_GPIOFIV);
/* setup the EMAC clock mux select */
writel((per_cfg->emacctl_emac0sel <<
@@ -833,7 +846,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
(per_cfg->emacctl_emac2sel <<
CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
- &clock_manager_base->per_pll.emacctl);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EMACCTL);
/* at this stage, check for PLL lock status */
cm_wait_for_lock(LOCKED_MASK);
@@ -843,33 +856,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
* assert/deassert outresetall
*/
/* assert mainpll outresetall */
- setbits_le32(&clock_manager_base->main_pll.vco0,
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
/* assert perpll outresetall */
- setbits_le32(&clock_manager_base->per_pll.vco0,
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
/* de-assert mainpll outresetall */
- clrbits_le32(&clock_manager_base->main_pll.vco0,
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
/* de-assert perpll outresetall */
- clrbits_le32(&clock_manager_base->per_pll.vco0,
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
/* Take all PLLs out of bypass when boot mode is cleared. */
/* release mainpll from bypass */
writel(CLKMGR_MAINPLL_BYPASS_RESET,
- &clock_manager_base->main_pll.bypassr);
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSR);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
/* release perpll from bypass */
writel(CLKMGR_PERPLL_BYPASS_RESET,
- &clock_manager_base->per_pll.bypassr);
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSR);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
/* clear boot mode */
- clrbits_le32(&clock_manager_base->ctrl,
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
/* wait till Clock Manager is not busy */
cm_wait_for_fsm();
@@ -882,9 +895,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
/* Now ungate non-hw-managed clocks */
writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
- CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
- &clock_manager_base->main_pll.ens);
- writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
+ CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
+ socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENS);
+ writel(CLKMGR_PERPLL_EN_RESET,
+ socfpga_clkmgr_base + CLKMGR_A10_PERPLL_ENS);
/* Clear the loss lock and slip bits as they might set during
clock reconfiguration */
@@ -894,14 +908,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
- &clock_manager_base->intr);
+ socfpga_clkmgr_base + CLKMGR_A10_INTR);
return 0;
}
static void cm_use_intosc(void)
{
- setbits_le32(&clock_manager_base->ctrl,
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
}
diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
index 3a64600861..c9990af46f 100644
--- a/arch/arm/mach-socfpga/clock_manager_gen5.c
+++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
@@ -9,23 +9,20 @@
#include <asm/arch/clock_manager.h>
#include <wait_bit.h>
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
/*
* function to write the bypass register which requires a poll of the
* busy bit
*/
static void cm_write_bypass(u32 val)
{
- writel(val, &clock_manager_base->bypass);
+ writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_BYPASS);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
static void cm_write_ctrl(u32 val)
{
- writel(val, &clock_manager_base->ctrl);
+ writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_CTRL);
cm_wait_for_fsm();
}
@@ -79,8 +76,8 @@ int cm_basic_init(const struct cm_config * const cfg)
* gatting off the rest of the periperal clocks.
*/
writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
- readl(&clock_manager_base->per_pll.en),
- &clock_manager_base->per_pll.en);
+ readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN),
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
/* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
@@ -89,12 +86,12 @@ int cm_basic_init(const struct cm_config * const cfg)
CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
- &clock_manager_base->main_pll.en);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
- writel(0, &clock_manager_base->sdr_pll.en);
+ writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
/* now we can gate off the rest of the peripheral clocks */
- writel(0, &clock_manager_base->per_pll.en);
+ writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
/* Put all plls in bypass */
cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
@@ -103,13 +100,13 @@ int cm_basic_init(const struct cm_config * const cfg)
/* Put all plls VCO registers back to reset value. */
writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->main_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->per_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
- &clock_manager_base->sdr_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/*
* The clocks to the flash devices and the L4_MAIN clocks can
@@ -119,23 +116,26 @@ int cm_basic_init(const struct cm_config * const cfg)
* after exiting safe mode but before ungating the clocks.
*/
writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
- &clock_manager_base->per_pll.src);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
- &clock_manager_base->main_pll.l4src);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
/* read back for the required 5 us delay. */
- readl(&clock_manager_base->main_pll.vco);
- readl(&clock_manager_base->per_pll.vco);
- readl(&clock_manager_base->sdr_pll.vco);
+ readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
+ readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
+ readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/*
* We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
* with numerator and denominator.
*/
- writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
- writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
- writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
+ writel(cfg->main_vco_base,
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
+ writel(cfg->peri_vco_base,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
+ writel(cfg->sdram_vco_base,
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/*
* Time starts here. Must wait 7 us from
@@ -144,44 +144,53 @@ int cm_basic_init(const struct cm_config * const cfg)
end = timer_get_us() + 7;
/* main mpu */
- writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+ writel(cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
/* altera group mpuclk */
- writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
+ writel(cfg->altera_grp_mpuclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
/* main main clock */
- writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
+ writel(cfg->mainclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
/* main for dbg */
- writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
+ writel(cfg->dbgatclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGATCLK);
/* main for cfgs2fuser0clk */
writel(cfg->cfg2fuser0clk,
- &clock_manager_base->main_pll.cfgs2fuser0clk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
/* Peri emac0 50 MHz default to RMII */
- writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
+ writel(cfg->emac0clk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC0CLK);
/* Peri emac1 50 MHz default to RMII */
- writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
+ writel(cfg->emac1clk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC1CLK);
/* Peri QSPI */
- writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
+ writel(cfg->mainqspiclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
- writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
+ writel(cfg->perqspiclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERQSPICLK);
/* Peri pernandsdmmcclk */
writel(cfg->mainnandsdmmcclk,
- &clock_manager_base->main_pll.mainnandsdmmcclk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
writel(cfg->pernandsdmmcclk,
- &clock_manager_base->per_pll.pernandsdmmcclk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
/* Peri perbaseclk */
- writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
+ writel(cfg->perbaseclk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
/* Peri s2fuser1clk */
- writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
+ writel(cfg->s2fuser1clk,
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
/* 7 us must have elapsed before we can enable the VCO */
while (timer_get_us() < end)
@@ -190,101 +199,106 @@ int cm_basic_init(const struct cm_config * const cfg)
/* Enable vco */
/* main pll vco */
writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->main_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
/* periferal pll */
writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->per_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
/* sdram pll vco */
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->sdr_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/* L3 MP and L3 SP */
- writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
+ writel(cfg->maindiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
- writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
+ writel(cfg->dbgdiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGDIV);
- writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
+ writel(cfg->tracediv,
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_TRACEDIV);
/* L4 MP, L4 SP, can0, and can1 */
- writel(cfg->perdiv, &clock_manager_base->per_pll.div);
+ writel(cfg->perdiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_DIV);
- writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+ writel(cfg->gpiodiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_GPIODIV);
cm_wait_for_lock(LOCKED_MASK);
/* write the sdram clock counters before toggling outreset all */
writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddrdqsclk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddr2xdqsclk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
- &clock_manager_base->sdr_pll.ddrdqclk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
- &clock_manager_base->sdr_pll.s2fuser2clk);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
/*
* after locking, but before taking out of bypass
* assert/deassert outresetall
*/
- u32 mainvco = readl(&clock_manager_base->main_pll.vco);
+ u32 mainvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
/* assert main outresetall */
writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
- u32 periphvco = readl(&clock_manager_base->per_pll.vco);
+ u32 periphvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
/* assert pheriph outresetall */
writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
/* assert sdram outresetall */
- writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
- CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
- &clock_manager_base->sdr_pll.vco);
+ writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
+ CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/* deassert main outresetall */
writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->main_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
/* deassert pheriph outresetall */
writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
- &clock_manager_base->per_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
/* deassert sdram outresetall */
writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
- &clock_manager_base->sdr_pll.vco);
+ socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
/*
* now that we've toggled outreset all, all the clocks
* are aligned nicely; so we can change any phase.
*/
ret = cm_write_with_phase(cfg->ddrdqsclk,
- &clock_manager_base->sdr_pll.ddrdqsclk,
+ (const void *)(socfpga_clkmgr_base +
+ CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
if (ret)
return ret;
/* SDRAM DDR2XDQSCLK */
ret = cm_write_with_phase(cfg->ddr2xdqsclk,
- &clock_manager_base->sdr_pll.ddr2xdqsclk,
+ (const void *)(socfpga_clkmgr_base +
+ CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
if (ret)
return ret;
ret = cm_write_with_phase(cfg->ddrdqclk,
- &clock_manager_base->sdr_pll.ddrdqclk,
+ (const void *)(socfpga_clkmgr_base +
+ CLKMGR_GEN5_SDRPLL_DDRDQCLK),
CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
if (ret)
return ret;
ret = cm_write_with_phase(cfg->s2fuser2clk,
- &clock_manager_base->sdr_pll.s2fuser2clk,
+ (const void *)(socfpga_clkmgr_base +
+ CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
if (ret)
return ret;
@@ -293,24 +307,26 @@ int cm_basic_init(const struct cm_config * const cfg)
cm_write_bypass(0);
/* clear safe mode */
- cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
+ cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_GEN5_CTRL) |
+ CLKMGR_CTRL_SAFEMODE);
/*
* now that safe mode is clear with clocks gated
* it safe to change the source mux for the flashes the the L4_MAIN
*/
- writel(cfg->persrc, &clock_manager_base->per_pll.src);
- writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
+ writel(cfg->persrc, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
+ writel(cfg->l4src, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
/* Now ungate non-hw-managed clocks */
- writel(~0, &clock_manager_base->main_pll.en);
- writel(~0, &clock_manager_base->per_pll.en);
- writel(~0, &clock_manager_base->sdr_pll.en);
+ writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
+ writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
+ writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
/* Clear the loss of lock bits (write 1 to clear) */
- writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
- CLKMGR_INTER_MAINPLLLOST_MASK,
- &clock_manager_base->inter);
+ writel(CLKMGR_INTER_SDRPLLLOST_MASK |
+ CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK,
+ socfpga_clkmgr_base + CLKMGR_GEN5_INTER);
return 0;
}
@@ -320,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
u32 reg, clock;
/* get the main VCO clock */
- reg = readl(&clock_manager_base->main_pll.vco);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
clock = cm_get_osc_clk_hz(1);
clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
@@ -335,7 +351,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
u32 reg, clock = 0;
/* identify PER PLL clock source */
- reg = readl(&clock_manager_base->per_pll.vco);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -346,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
clock = cm_get_f2s_per_ref_clk_hz();
/* get the PER VCO clock */
- reg = readl(&clock_manager_base->per_pll.vco);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
@@ -362,9 +378,9 @@ unsigned long cm_get_mpu_clk_hz(void)
clock = cm_get_main_vco_clk_hz();
/* get the MPU clock */
- reg = readl(&clock_manager_base->altera.mpuclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
clock /= (reg + 1);
- reg = readl(&clock_manager_base->main_pll.mpuclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
clock /= (reg + 1);
return clock;
}
@@ -374,7 +390,7 @@ unsigned long cm_get_sdram_clk_hz(void)
u32 reg, clock = 0;
/* identify SDRAM PLL clock source */
- reg = readl(&clock_manager_base->sdr_pll.vco);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
if (reg == CLKMGR_VCO_SSRC_EOSC1)
@@ -385,14 +401,14 @@ unsigned long cm_get_sdram_clk_hz(void)
clock = cm_get_f2s_sdr_ref_clk_hz();
/* get the SDRAM VCO clock */
- reg = readl(&clock_manager_base->sdr_pll.vco);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
/* get the SDRAM (DDR_DQS) clock */
- reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
clock /= (reg + 1);
@@ -405,7 +421,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
u32 reg, clock = 0;
/* identify the source of L4 SP clock */
- reg = readl(&clock_manager_base->main_pll.l4src);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
@@ -413,20 +429,21 @@ unsigned int cm_get_l4_sp_clk_hz(void)
clock = cm_get_main_vco_clk_hz();
/* get the clock prior L4 SP divider (main clk) */
- reg = readl(&clock_manager_base->altera.mainclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MAINCLK);
clock /= (reg + 1);
- reg = readl(&clock_manager_base->main_pll.mainclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
clock /= (reg + 1);
} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
clock = cm_get_per_vco_clk_hz();
/* get the clock prior L4 SP divider (periph_base_clk) */
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
+ reg = readl(socfpga_clkmgr_base +
+ CLKMGR_GEN5_PERPLL_PERBASECLK);
clock /= (reg + 1);
}
/* get the L4 SP clock which supplied to UART */
- reg = readl(&clock_manager_base->main_pll.maindiv);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
clock = clock / (1 << reg);
@@ -439,7 +456,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
u32 reg, clock = 0;
/* identify the source of MMC clock */
- reg = readl(&clock_manager_base->per_pll.src);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
@@ -449,13 +466,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
clock = cm_get_main_vco_clk_hz();
/* get the SDMMC clock */
- reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
+ reg = readl(socfpga_clkmgr_base +
+ CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
clock /= (reg + 1);
} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
clock = cm_get_per_vco_clk_hz();
/* get the SDMMC clock */
- reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
+ reg = readl(socfpga_clkmgr_base +
+ CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
clock /= (reg + 1);
}
@@ -469,7 +488,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
u32 reg, clock = 0;
/* identify the source of QSPI clock */
- reg = readl(&clock_manager_base->per_pll.src);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
@@ -479,13 +498,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
clock = cm_get_main_vco_clk_hz();
/* get the qspi clock */
- reg = readl(&clock_manager_base->main_pll.mainqspiclk);
+ reg = readl(socfpga_clkmgr_base +
+ CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
clock /= (reg + 1);
} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
clock = cm_get_per_vco_clk_hz();
/* get the qspi clock */
- reg = readl(&clock_manager_base->per_pll.perqspiclk);
+ reg = readl(socfpga_clkmgr_base +
+ CLKMGR_GEN5_PERPLL_PERQSPICLK);
clock /= (reg + 1);
}
@@ -499,7 +520,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
clock = cm_get_per_vco_clk_hz();
/* get the clock prior L4 SP divider (periph_base_clk) */
- reg = readl(&clock_manager_base->per_pll.perbaseclk);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
clock /= (reg + 1);
return clock;
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 6cbf07ac6f..c6269701f0 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -12,29 +12,26 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_clock_manager *clock_manager_base =
- (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
-
/*
* function to write the bypass register which requires a poll of the
* busy bit
*/
static void cm_write_bypass_mainpll(u32 val)
{
- writel(val, &clock_manager_base->main_pll.bypass);
+ writel(val, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_BYPASS);
cm_wait_for_fsm();
}
static void cm_write_bypass_perpll(u32 val)
{
- writel(val, &clock_manager_base->per_pll.bypass);
+ writel(val, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_BYPASS);
cm_wait_for_fsm();
}
/* function to write the ctrl register which requires a poll of the busy bit */
static void cm_write_ctrl(u32 val)
{
- writel(val, &clock_manager_base->ctrl);
+ writel(val, socfpga_clkmgr_base + CLKMGR_S10_CTRL);
cm_wait_for_fsm();
}
@@ -66,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg)
writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
~CLKMGR_PLLGLOB_RST_MASK),
- &clock_manager_base->main_pll.pllglob);
- writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
- writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
- writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
- writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
- writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
+ writel(cfg->main_pll_fdbck,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
+ writel(vcocalib,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_VCOCALIB);
+ writel(cfg->main_pll_pllc0,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC0);
+ writel(cfg->main_pll_pllc1,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC1);
+ writel(cfg->main_pll_nocdiv,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCDIV);
/* setup peripheral PLL dividers */
/* calculate the vcocalib value */
@@ -88,18 +90,23 @@ void cm_basic_init(const struct cm_config * const cfg)
writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
~CLKMGR_PLLGLOB_RST_MASK),
- &clock_manager_base->per_pll.pllglob);
- writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
- writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
- writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
- writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
- writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
- writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
+ writel(cfg->per_pll_fdbck,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
+ writel(vcocalib, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_VCOCALIB);
+ writel(cfg->per_pll_pllc0,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC0);
+ writel(cfg->per_pll_pllc1,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1);
+ writel(cfg->per_pll_emacctl,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EMACCTL);
+ writel(cfg->per_pll_gpiodiv,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_GPIODIV);
/* Take both PLL out of reset and power up */
- setbits_le32(&clock_manager_base->main_pll.pllglob,
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB,
CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
- setbits_le32(&clock_manager_base->per_pll.pllglob,
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB,
CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
#define LOCKED_MASK \
@@ -113,66 +120,85 @@ void cm_basic_init(const struct cm_config * const cfg)
* only take effect upon value change, we shall set a maximum value as
* default value.
*/
- writel(0xff, &clock_manager_base->main_pll.mpuclk);
- writel(0xff, &clock_manager_base->main_pll.nocclk);
- writel(0xff, &clock_manager_base->main_pll.cntr2clk);
- writel(0xff, &clock_manager_base->main_pll.cntr3clk);
- writel(0xff, &clock_manager_base->main_pll.cntr4clk);
- writel(0xff, &clock_manager_base->main_pll.cntr5clk);
- writel(0xff, &clock_manager_base->main_pll.cntr6clk);
- writel(0xff, &clock_manager_base->main_pll.cntr7clk);
- writel(0xff, &clock_manager_base->main_pll.cntr8clk);
- writel(0xff, &clock_manager_base->main_pll.cntr9clk);
- writel(0xff, &clock_manager_base->per_pll.cntr2clk);
- writel(0xff, &clock_manager_base->per_pll.cntr3clk);
- writel(0xff, &clock_manager_base->per_pll.cntr4clk);
- writel(0xff, &clock_manager_base->per_pll.cntr5clk);
- writel(0xff, &clock_manager_base->per_pll.cntr6clk);
- writel(0xff, &clock_manager_base->per_pll.cntr7clk);
- writel(0xff, &clock_manager_base->per_pll.cntr8clk);
- writel(0xff, &clock_manager_base->per_pll.cntr9clk);
-
- writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
- writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
- writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
- writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
- writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
- writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
- writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
- writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
- writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
- writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
- writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
- writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
- writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
- writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
- writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
- writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
- writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
- writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
+ writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
+
+ writel(cfg->main_pll_mpuclk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
+ writel(cfg->main_pll_nocclk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
+ writel(cfg->main_pll_cntr2clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
+ writel(cfg->main_pll_cntr3clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
+ writel(cfg->main_pll_cntr4clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
+ writel(cfg->main_pll_cntr5clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
+ writel(cfg->main_pll_cntr6clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
+ writel(cfg->main_pll_cntr7clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
+ writel(cfg->main_pll_cntr8clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
+ writel(cfg->main_pll_cntr9clk,
+ socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
+ writel(cfg->per_pll_cntr2clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
+ writel(cfg->per_pll_cntr3clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
+ writel(cfg->per_pll_cntr4clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
+ writel(cfg->per_pll_cntr5clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
+ writel(cfg->per_pll_cntr6clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
+ writel(cfg->per_pll_cntr7clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
+ writel(cfg->per_pll_cntr8clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
+ writel(cfg->per_pll_cntr9clk,
+ socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
/* Take all PLLs out of bypass */
cm_write_bypass_mainpll(0);
cm_write_bypass_perpll(0);
/* clear safe mode / out of boot mode */
- cm_write_ctrl(readl(&clock_manager_base->ctrl)
- & ~(CLKMGR_CTRL_SAFEMODE));
+ cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_S10_CTRL) &
+ ~(CLKMGR_CTRL_SAFEMODE));
/* Now ungate non-hw-managed clocks */
- writel(~0, &clock_manager_base->main_pll.en);
- writel(~0, &clock_manager_base->per_pll.en);
+ writel(~0, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_EN);
+ writel(~0, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EN);
/* Clear the loss of lock bits (write 1 to clear) */
- writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
- &clock_manager_base->intrclr);
+ writel(CLKMGR_INTER_PERPLLLOST_MASK |
+ CLKMGR_INTER_MAINPLLLOST_MASK,
+ socfpga_clkmgr_base + CLKMGR_S10_INTRCLR);
}
static unsigned long cm_get_main_vco_clk_hz(void)
{
unsigned long fref, refdiv, mdiv, reg, vco;
- reg = readl(&clock_manager_base->main_pll.pllglob);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -191,7 +217,7 @@ static unsigned long cm_get_main_vco_clk_hz(void)
refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
CLKMGR_PLLGLOB_REFCLKDIV_MASK;
- reg = readl(&clock_manager_base->main_pll.fdbck);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
vco = fref / refdiv;
@@ -203,7 +229,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
{
unsigned long fref, refdiv, mdiv, reg, vco;
- reg = readl(&clock_manager_base->per_pll.pllglob);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
CLKMGR_PLLGLOB_VCO_PSRC_MASK;
@@ -222,7 +248,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
CLKMGR_PLLGLOB_REFCLKDIV_MASK;
- reg = readl(&clock_manager_base->per_pll.fdbck);
+ reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
vco = fref / refdiv;
@@ -232,20 +258,23 @@ static unsigned long cm_get_per_vco_clk_hz(void)
unsigned long cm_get_mpu_clk_hz(void)
{
- unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+ unsigned long clock = readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_MPUCLK);
clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
switch (clock) {
case CLKMGR_CLKSRC_MAIN:
clock = cm_get_main_vco_clk_hz();
- clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+ clock /= (readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_PLLC0) &
CLKMGR_PLLC0_DIV_MASK);
break;
case CLKMGR_CLKSRC_PER:
clock = cm_get_per_vco_clk_hz();
- clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+ clock /= (readl(socfpga_clkmgr_base +
+ CLKMGR_S10_PERPLL_PLLC0) &
CLKMGR_CLKCNT_MSK);
break;
@@ -262,27 +291,28 @@ unsigned long cm_get_mpu_clk_hz(void)
break;
}
- clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
- CLKMGR_CLKCNT_MSK);
+ clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK) &
+ CLKMGR_CLKCNT_MSK);
return clock;
}
unsigned int cm_get_l3_main_clk_hz(void)
{
- u32 clock = readl(&clock_manager_base->main_pll.nocclk);
+ u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
switch (clock) {
case CLKMGR_CLKSRC_MAIN:
clock = cm_get_main_vco_clk_hz();
- clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+ clock /= (readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_PLLC1) &
CLKMGR_PLLC0_DIV_MASK);
break;
case CLKMGR_CLKSRC_PER:
clock = cm_get_per_vco_clk_hz();
- clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+ clock /= (readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1) &
CLKMGR_CLKCNT_MSK);
break;
@@ -299,28 +329,30 @@ unsigned int cm_get_l3_main_clk_hz(void)
break;
}
- clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+ clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK) &
CLKMGR_CLKCNT_MSK);
return clock;
}
unsigned int cm_get_mmc_controller_clk_hz(void)
{
- u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
+ u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
switch (clock) {
case CLKMGR_CLKSRC_MAIN:
clock = cm_get_l3_main_clk_hz();
- clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
- CLKMGR_CLKCNT_MSK);
+ clock /= 1 + (readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_CNTR6CLK) &
+ CLKMGR_CLKCNT_MSK);
break;
case CLKMGR_CLKSRC_PER:
clock = cm_get_l3_main_clk_hz();
- clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
- CLKMGR_CLKCNT_MSK);
+ clock /= 1 + (readl(socfpga_clkmgr_base +
+ CLKMGR_S10_PERPLL_CNTR6CLK) &
+ CLKMGR_CLKCNT_MSK);
break;
case CLKMGR_CLKSRC_OSC1:
@@ -342,8 +374,9 @@ unsigned int cm_get_l4_sp_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();
- clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
- CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+ clock /= (1 << ((readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
return clock;
}
@@ -356,8 +389,9 @@ unsigned int cm_get_spi_controller_clk_hz(void)
{
u32 clock = cm_get_l3_main_clk_hz();
- clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
- CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
+ clock /= (1 << ((readl(socfpga_clkmgr_base +
+ CLKMGR_S10_MAINPLL_NOCDIV) >>
+ CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
return clock;
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index dd80e3a767..4f9d10dd78 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -6,6 +6,8 @@
#ifndef _CLOCK_MANAGER_H_
#define _CLOCK_MANAGER_H_
+extern phys_addr_t socfpga_clkmgr_base;
+
#ifndef __ASSEMBLER__
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index de8c22540f..52b579e6e1 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -8,86 +8,57 @@
#ifndef __ASSEMBLER__
-struct socfpga_clock_manager_main_pll {
- u32 vco0;
- u32 vco1;
- u32 en;
- u32 ens;
- u32 enr;
- u32 bypass;
- u32 bypasss;
- u32 bypassr;
- u32 mpuclk;
- u32 nocclk;
- u32 cntr2clk;
- u32 cntr3clk;
- u32 cntr4clk;
- u32 cntr5clk;
- u32 cntr6clk;
- u32 cntr7clk;
- u32 cntr8clk;
- u32 cntr9clk;
- u32 pad_0x48_0x5b[5];
- u32 cntr15clk;
- u32 outrst;
- u32 outrststat;
- u32 nocdiv;
- u32 pad_0x6c_0x80[5];
-};
-
-struct socfpga_clock_manager_per_pll {
- u32 vco0;
- u32 vco1;
- u32 en;
- u32 ens;
- u32 enr;
- u32 bypass;
- u32 bypasss;
- u32 bypassr;
- u32 pad_0x20_0x27[2];
- u32 cntr2clk;
- u32 cntr3clk;
- u32 cntr4clk;
- u32 cntr5clk;
- u32 cntr6clk;
- u32 cntr7clk;
- u32 cntr8clk;
- u32 cntr9clk;
- u32 pad_0x48_0x5f[6];
- u32 outrst;
- u32 outrststat;
- u32 emacctl;
- u32 gpiodiv;
- u32 pad_0x70_0x80[4];
-};
-
-struct socfpga_clock_manager_altera {
- u32 mpuclk;
- u32 nocclk;
- u32 mainmisc0;
- u32 mainmisc1;
- u32 perimisc0;
- u32 perimisc1;
-};
-
-struct socfpga_clock_manager {
- /* clkmgr */
- u32 ctrl;
- u32 intr;
- u32 intrs;
- u32 intrr;
- u32 intren;
- u32 intrens;
- u32 intrenr;
- u32 stat;
- u32 testioctrl;
- u32 _pad_0x24_0x40[7];
- /* mainpllgrp */
- struct socfpga_clock_manager_main_pll main_pll;
- /* perpllgrp */
- struct socfpga_clock_manager_per_pll per_pll;
- struct socfpga_clock_manager_altera altera;
-};
+/* Clock manager group */
+#define CLKMGR_A10_CTRL 0
+#define CLKMGR_A10_INTR 4
+#define CLKMGR_A10_STAT 0x1c
+/* MainPLL group */
+#define CLKMGR_A10_MAINPLL_VCO0 0x40
+#define CLKMGR_A10_MAINPLL_VCO1 0x44
+#define CLKMGR_A10_MAINPLL_EN 0x48
+#define CLKMGR_A10_MAINPLL_ENS 0x4c
+#define CLKMGR_A10_MAINPLL_ENR 0x50
+#define CLKMGR_A10_MAINPLL_BYPASS 0x54
+#define CLKMGR_A10_MAINPLL_BYPASSS 0x58
+#define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
+#define CLKMGR_A10_MAINPLL_MPUCLK 0x60
+#define CLKMGR_A10_MAINPLL_NOCCLK 0x64
+#define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
+#define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
+#define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
+#define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
+#define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
+#define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
+#define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
+#define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
+#define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
+#define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
+/* Peripheral PLL group */
+#define CLKMGR_A10_PERPLL_VCO0 0xc0
+#define CLKMGR_A10_PERPLL_VCO1 0xc4
+#define CLKMGR_A10_PERPLL_EN 0xc8
+#define CLKMGR_A10_PERPLL_ENS 0xcc
+#define CLKMGR_A10_PERPLL_ENR 0xd0
+#define CLKMGR_A10_PERPLL_BYPASS 0xd4
+#define CLKMGR_A10_PERPLL_BYPASSS 0xd8
+#define CLKMGR_A10_PERPLL_BYPASSR 0xdc
+#define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
+#define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
+#define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
+#define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
+#define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
+#define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
+#define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
+#define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
+#define CLKMGR_A10_PERPLL_EMACCTL 0x128
+#define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
+/* Altera group */
+#define CLKMGR_A10_ALTR_MPUCLK 0x140
+#define CLKMGR_A10_ALTR_NOCCLK 0x144
+
+#define CLKMGR_STAT CLKMGR_A10_STAT
+#define CLKMGR_INTER CLKMGR_A10_INTER
+#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
#ifdef CONFIG_SPL_BUILD
int cm_basic_init(const void *blob);
@@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#endif /* __ASSEMBLER__ */
-#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
-#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 5bedf28cf1..caa1231c69 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -45,71 +45,53 @@ struct cm_config {
u32 altera_grp_mpuclk;
};
-struct socfpga_clock_manager_main_pll {
- u32 vco;
- u32 misc;
- u32 mpuclk;
- u32 mainclk;
- u32 dbgatclk;
- u32 mainqspiclk;
- u32 mainnandsdmmcclk;
- u32 cfgs2fuser0clk;
- u32 en;
- u32 maindiv;
- u32 dbgdiv;
- u32 tracediv;
- u32 l4src;
- u32 stat;
- u32 _pad_0x38_0x40[2];
-};
-
-struct socfpga_clock_manager_per_pll {
- u32 vco;
- u32 misc;
- u32 emac0clk;
- u32 emac1clk;
- u32 perqspiclk;
- u32 pernandsdmmcclk;
- u32 perbaseclk;
- u32 s2fuser1clk;
- u32 en;
- u32 div;
- u32 gpiodiv;
- u32 src;
- u32 stat;
- u32 _pad_0x34_0x40[3];
-};
-
-struct socfpga_clock_manager_sdr_pll {
- u32 vco;
- u32 ctrl;
- u32 ddrdqsclk;
- u32 ddr2xdqsclk;
- u32 ddrdqclk;
- u32 s2fuser2clk;
- u32 en;
- u32 stat;
-};
-
-struct socfpga_clock_manager_altera {
- u32 mpuclk;
- u32 mainclk;
-};
-
-struct socfpga_clock_manager {
- u32 ctrl;
- u32 bypass;
- u32 inter;
- u32 intren;
- u32 dbctrl;
- u32 stat;
- u32 _pad_0x18_0x3f[10];
- struct socfpga_clock_manager_main_pll main_pll;
- struct socfpga_clock_manager_per_pll per_pll;
- struct socfpga_clock_manager_sdr_pll sdr_pll;
- struct socfpga_clock_manager_altera altera;
- u32 _pad_0xe8_0x200[70];
-};
+/* Clock manager group */
+#define CLKMGR_GEN5_CTRL 0
+#define CLKMGR_GEN5_BYPASS 4
+#define CLKMGR_GEN5_INTER 8
+#define CLKMGR_GEN5_STAT 0x14
+/* MainPLL group */
+#define CLKMGR_GEN5_MAINPLL_VCO 0x40
+#define CLKMGR_GEN5_MAINPLL_MISC 0x44
+#define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48
+#define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c
+#define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50
+#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54
+#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58
+#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c
+#define CLKMGR_GEN5_MAINPLL_EN 0x60
+#define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64
+#define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68
+#define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c
+#define CLKMGR_GEN5_MAINPLL_L4SRC 0x70
+/* Peripheral PLL group */
+#define CLKMGR_GEN5_PERPLL_VCO 0x80
+#define CLKMGR_GEN5_PERPLL_MISC 0x84
+#define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88
+#define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c
+#define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90
+#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94
+#define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98
+#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c
+#define CLKMGR_GEN5_PERPLL_EN 0xa0
+#define CLKMGR_GEN5_PERPLL_DIV 0xa4
+#define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8
+#define CLKMGR_GEN5_PERPLL_SRC 0xac
+/* SDRAM PLL group */
+#define CLKMGR_GEN5_SDRPLL_VCO 0xc0
+#define CLKMGR_GEN5_SDRPLL_CTRL 0xc4
+#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8
+#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc
+#define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0
+#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4
+#define CLKMGR_GEN5_SDRPLL_EN 0xd8
+/* Altera group */
+#define CLKMGR_GEN5_ALTR_MPUCLK 0xe0
+#define CLKMGR_GEN5_ALTR_MAINCLK 0xe4
+
+#define CLKMGR_STAT CLKMGR_GEN5_STAT
+#define CLKMGR_INTER CLKMGR_GEN5_INTER
+#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
unsigned long cm_get_mpu_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 24b20de011..fa0ba26f09 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -69,75 +69,54 @@ struct cm_config {
void cm_basic_init(const struct cm_config * const cfg);
-struct socfpga_clock_manager_main_pll {
- u32 en;
- u32 ens;
- u32 enr;
- u32 bypass;
- u32 bypasss;
- u32 bypassr;
- u32 mpuclk;
- u32 nocclk;
- u32 cntr2clk;
- u32 cntr3clk;
- u32 cntr4clk;
- u32 cntr5clk;
- u32 cntr6clk;
- u32 cntr7clk;
- u32 cntr8clk;
- u32 cntr9clk;
- u32 nocdiv;
- u32 pllglob;
- u32 fdbck;
- u32 mem;
- u32 memstat;
- u32 pllc0;
- u32 pllc1;
- u32 vcocalib;
- u32 _pad_0x90_0xA0[5];
-};
-
-struct socfpga_clock_manager_per_pll {
- u32 en;
- u32 ens;
- u32 enr;
- u32 bypass;
- u32 bypasss;
- u32 bypassr;
- u32 cntr2clk;
- u32 cntr3clk;
- u32 cntr4clk;
- u32 cntr5clk;
- u32 cntr6clk;
- u32 cntr7clk;
- u32 cntr8clk;
- u32 cntr9clk;
- u32 emacctl;
- u32 gpiodiv;
- u32 pllglob;
- u32 fdbck;
- u32 mem;
- u32 memstat;
- u32 pllc0;
- u32 pllc1;
- u32 vcocalib;
- u32 _pad_0x100_0x124[10];
-};
+/* Control status */
+#define CLKMGR_S10_CTRL 0
+#define CLKMGR_S10_STAT 4
+#define CLKMGR_S10_INTRCLR 0x14
+/* Mainpll group */
+#define CLKMGR_S10_MAINPLL_EN 0x30
+#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
+#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
+#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
+#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
+#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
+#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
+#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
+#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
+#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
+#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
+#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
+#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
+#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
+#define CLKMGR_S10_MAINPLL_FDBCK 0x78
+#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
+#define CLKMGR_S10_MAINPLL_PLLC0 0x84
+#define CLKMGR_S10_MAINPLL_PLLC1 0x88
+#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
+/* Periphpll group */
+#define CLKMGR_S10_PERPLL_EN 0xa4
+#define CLKMGR_S10_PERPLL_BYPASS 0xac
+#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
+#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
+#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
+#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
+#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
+#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
+#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
+#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
+#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
+#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
+#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
+#define CLKMGR_S10_PERPLL_FDBCK 0xe8
+#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
+#define CLKMGR_S10_PERPLL_PLLC0 0xf4
+#define CLKMGR_S10_PERPLL_PLLC1 0xf8
+#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
+
+#define CLKMGR_STAT CLKMGR_S10_STAT
+#define CLKMGR_INTER CLKMGR_S10_INTER
+#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
-struct socfpga_clock_manager {
- u32 ctrl;
- u32 stat;
- u32 testioctrl;
- u32 intrgen;
- u32 intrmsk;
- u32 intrclr;
- u32 intrsts;
- u32 intrstk;
- u32 intrraw;
- u32 _pad_0x24_0x2c[3];
- struct socfpga_clock_manager_main_pll main_pll;
- struct socfpga_clock_manager_per_pll per_pll;
-};
#define CLKMGR_CTRL_SAFEMODE BIT(0)
#define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index fcc53b6fbc..dffd1b2e41 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -22,6 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
+phys_addr_t socfpga_clkmgr_base __section(".data");
phys_addr_t socfpga_rstmgr_base __section(".data");
phys_addr_t socfpga_sysmgr_base __section(".data");
@@ -238,4 +239,8 @@ void socfpga_get_manager_addr(void)
socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
if (!socfpga_sysmgr_base)
hang();
+
+ socfpga_clkmgr_base = socfpga_get_base_addr("altr,clk-mgr");
+ if (!socfpga_clkmgr_base)
+ hang();
}
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index bdcd568d60..aefcae8fb6 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -18,9 +18,6 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct socfpga_clock_manager *clock_manager_base =
- (void *)SOCFPGA_CLKMGR_ADDRESS;
-
struct socfpga_dwmci_plat {
struct mmc_config cfg;
struct mmc mmc;
@@ -54,8 +51,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
/* Disable SDMMC clock. */
- clrbits_le32(&clock_manager_base->per_pll.en,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ clrbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
+ CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
@@ -65,8 +62,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
/* Enable SDMMC clock */
- setbits_le32(&clock_manager_base->per_pll.en,
- CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
+ setbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
+ CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
}
static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
--
2.19.0
^ permalink raw reply related [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock manager from struct to defines
2019-09-10 8:38 ` [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock " Ley Foon Tan
@ 2019-10-02 9:22 ` Simon Goldschmidt
2019-10-04 2:57 ` Ley Foon Tan
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-02 9:22 UTC (permalink / raw)
To: u-boot
On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
>
> Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
> to defines.
> No functional change.
>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>
> ---
> v2:
> - Change to use writel(), readl() and etc.
> - Get base address from DT.
And again: separate patch please. You're mixing "no functional change"
restructuring with actual changes that could possibly break
(non-upstreamed) boards.
Regards,
Simon
> - Add prefix to defines.
> ---
> arch/arm/mach-socfpga/clock_manager.c | 12 +-
> arch/arm/mach-socfpga/clock_manager_arria10.c | 156 +++++++------
> arch/arm/mach-socfpga/clock_manager_gen5.c | 199 +++++++++--------
> arch/arm/mach-socfpga/clock_manager_s10.c | 206 ++++++++++--------
> .../mach-socfpga/include/mach/clock_manager.h | 2 +
> .../include/mach/clock_manager_arria10.h | 133 +++++------
> .../include/mach/clock_manager_gen5.h | 112 ++++------
> .../include/mach/clock_manager_s10.h | 115 ++++------
> arch/arm/mach-socfpga/misc.c | 5 +
> drivers/mmc/socfpga_dw_mmc.c | 11 +-
> 10 files changed, 476 insertions(+), 475 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> index 9f3c643df8..09857dc37b 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -10,18 +10,15 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> -
> void cm_wait_for_lock(u32 mask)
> {
> u32 inter_val;
> u32 retry = 0;
> do {
> #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> - inter_val = readl(&clock_manager_base->inter) & mask;
> + inter_val = readl(socfpga_clkmgr_base + CLKMGR_INTER) & mask;
> #else
> - inter_val = readl(&clock_manager_base->stat) & mask;
> + inter_val = readl(socfpga_clkmgr_base + CLKMGR_STAT) & mask;
> #endif
> /* Wait for stable lock */
> if (inter_val == mask)
> @@ -36,8 +33,9 @@ void cm_wait_for_lock(u32 mask)
> /* function to poll in the fsm busy bit */
> int cm_wait_for_fsm(void)
> {
> - return wait_for_bit_le32(&clock_manager_base->stat,
> - CLKMGR_STAT_BUSY, false, 20000, false);
> + return wait_for_bit_le32((const void *)(socfpga_clkmgr_base +
> + CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
> + false);
> }
>
> int set_cpu_clk_info(void)
> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
> index 334a79fd9c..33aebd4f47 100644
> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> @@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
> return 0;
> }
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> -
> /* calculate the intended main VCO frequency based on handoff */
> static unsigned int cm_calc_handoff_main_vco_clk_hz
> (struct mainpll_cfg *main_cfg)
> @@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
> writel((main_cfg->vco1_denom <<
> CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
> - &clock_manager_base->main_pll.vco1);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> mdelay(1);
> cm_wait_for_lock(LOCKED_MASK);
> }
> writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> - main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
> + main_cfg->vco1_numer,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> mdelay(1);
> cm_wait_for_lock(LOCKED_MASK);
> }
> @@ -579,14 +577,17 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
> /* execute the ramping here */
> for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
> clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
> - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> - cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
> - &clock_manager_base->per_pll.vco1);
> + writel((per_cfg->vco1_denom <<
> + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> + cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
> + clk_hz),
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> mdelay(1);
> cm_wait_for_lock(LOCKED_MASK);
> }
> writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> - per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
> + per_cfg->vco1_numer,
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> mdelay(1);
> cm_wait_for_lock(LOCKED_MASK);
> }
> @@ -638,16 +639,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> /* gate off all mainpll clock excpet HW managed clock */
> writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
> CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> - &clock_manager_base->main_pll.enr);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENR);
>
> /* now we can gate off the rest of the peripheral clocks */
> - writel(0, &clock_manager_base->per_pll.en);
> + writel(0, socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EN);
>
> /* Put all plls in external bypass */
> writel(CLKMGR_MAINPLL_BYPASS_RESET,
> - &clock_manager_base->main_pll.bypasss);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSS);
> writel(CLKMGR_PERPLL_BYPASS_RESET,
> - &clock_manager_base->per_pll.bypasss);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSS);
>
> /*
> * Put all plls VCO registers back to reset value.
> @@ -657,15 +658,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> writel(CLKMGR_MAINPLL_VCO0_RESET |
> CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
> (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
> - &clock_manager_base->main_pll.vco0);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
>
> writel(CLKMGR_PERPLL_VCO0_RESET |
> CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
> (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
> - &clock_manager_base->per_pll.vco0);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
>
> - writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
> - writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
> + writel(CLKMGR_MAINPLL_VCO1_RESET,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> + writel(CLKMGR_PERPLL_VCO1_RESET,
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
>
> /* clear the interrupt register status register */
> writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
> @@ -676,7 +679,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
> CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
> CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
> - &clock_manager_base->intr);
> + socfpga_clkmgr_base + CLKMGR_A10_INTR);
>
> /* Program VCO Numerator and Denominator for main PLL */
> ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
> @@ -687,14 +690,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> else if (ramp_required == 2)
> pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
>
> - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> + writel((main_cfg->vco1_denom <<
> + CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
> pll_ramp_main_hz),
> - &clock_manager_base->main_pll.vco1);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> } else
> - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> - main_cfg->vco1_numer,
> - &clock_manager_base->main_pll.vco1);
> + writel((main_cfg->vco1_denom <<
> + CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> + main_cfg->vco1_numer,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
>
> /* Program VCO Numerator and Denominator for periph PLL */
> ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
> @@ -707,23 +712,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> pll_ramp_periph_hz =
> CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
>
> - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> + writel((per_cfg->vco1_denom <<
> + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
> pll_ramp_periph_hz),
> - &clock_manager_base->per_pll.vco1);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> } else
> - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> + writel((per_cfg->vco1_denom <<
> + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> per_cfg->vco1_numer,
> - &clock_manager_base->per_pll.vco1);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
>
> /* Wait for at least 5 us */
> udelay(5);
>
> /* Now deassert BGPWRDN and PWRDN */
> - clrbits_le32(&clock_manager_base->main_pll.vco0,
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
> CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
> - clrbits_le32(&clock_manager_base->per_pll.vco0,
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
> CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
>
> @@ -731,84 +738,90 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> udelay(7);
>
> /* enable the VCO and disable the external regulator to PLL */
> - writel((readl(&clock_manager_base->main_pll.vco0) &
> + writel((readl(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0) &
> ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
> CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
> - &clock_manager_base->main_pll.vco0);
> - writel((readl(&clock_manager_base->per_pll.vco0) &
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
> + writel((readl(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0) &
> ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
> CLKMGR_PERPLL_VCO0_EN_SET_MSK,
> - &clock_manager_base->per_pll.vco0);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
>
> /* setup all the main PLL counter and clock source */
> - writel(main_cfg->nocclk,
> - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
> - writel(main_cfg->mpuclk,
> - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
> + writel(main_cfg->nocclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_NOCCLK);
> + writel(main_cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_MPUCLK);
>
> /* main_emaca_clk divider */
> - writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
> + writel(main_cfg->cntr2clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR2CLK);
> /* main_emacb_clk divider */
> - writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
> + writel(main_cfg->cntr3clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR3CLK);
> /* main_emac_ptp_clk divider */
> - writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
> + writel(main_cfg->cntr4clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR4CLK);
> /* main_gpio_db_clk divider */
> - writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
> + writel(main_cfg->cntr5clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR5CLK);
> /* main_sdmmc_clk divider */
> - writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
> + writel(main_cfg->cntr6clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR6CLK);
> /* main_s2f_user0_clk divider */
> writel(main_cfg->cntr7clk_cnt |
> (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
> - &clock_manager_base->main_pll.cntr7clk);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR7CLK);
> /* main_s2f_user1_clk divider */
> - writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
> + writel(main_cfg->cntr8clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR8CLK);
> /* main_hmc_pll_clk divider */
> writel(main_cfg->cntr9clk_cnt |
> (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
> - &clock_manager_base->main_pll.cntr9clk);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR9CLK);
> /* main_periph_ref_clk divider */
> writel(main_cfg->cntr15clk_cnt,
> - &clock_manager_base->main_pll.cntr15clk);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR15CLK);
>
> /* setup all the peripheral PLL counter and clock source */
> /* peri_emaca_clk divider */
> writel(per_cfg->cntr2clk_cnt |
> (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr2clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR2CLK);
> /* peri_emacb_clk divider */
> writel(per_cfg->cntr3clk_cnt |
> (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr3clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR3CLK);
> /* peri_emac_ptp_clk divider */
> writel(per_cfg->cntr4clk_cnt |
> (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr4clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR4CLK);
> /* peri_gpio_db_clk divider */
> writel(per_cfg->cntr5clk_cnt |
> (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr5clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR5CLK);
> /* peri_sdmmc_clk divider */
> writel(per_cfg->cntr6clk_cnt |
> (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr6clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR6CLK);
> /* peri_s2f_user0_clk divider */
> - writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
> + writel(per_cfg->cntr7clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR7CLK);
> /* peri_s2f_user1_clk divider */
> writel(per_cfg->cntr8clk_cnt |
> (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
> - &clock_manager_base->per_pll.cntr8clk);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR8CLK);
> /* peri_hmc_pll_clk divider */
> - writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
> + writel(per_cfg->cntr9clk_cnt,
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR9CLK);
>
> /* setup all the external PLL counter */
> /* mpu wrapper / external divider */
> writel(main_cfg->mpuclk_cnt |
> (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
> - &clock_manager_base->main_pll.mpuclk);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_MPUCLK);
> /* NOC wrapper / external divider */
> writel(main_cfg->nocclk_cnt |
> (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
> - &clock_manager_base->main_pll.nocclk);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCCLK);
> /* NOC subclock divider such as l4 */
> writel(main_cfg->nocdiv_l4mainclk |
> (main_cfg->nocdiv_l4mpclk <<
> @@ -821,10 +834,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
> (main_cfg->nocdiv_cspdbclk <<
> CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
> - &clock_manager_base->main_pll.nocdiv);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCDIV);
> /* gpio_db external divider */
> writel(per_cfg->gpiodiv_gpiodbclk,
> - &clock_manager_base->per_pll.gpiodiv);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_GPIOFIV);
>
> /* setup the EMAC clock mux select */
> writel((per_cfg->emacctl_emac0sel <<
> @@ -833,7 +846,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
> (per_cfg->emacctl_emac2sel <<
> CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
> - &clock_manager_base->per_pll.emacctl);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EMACCTL);
>
> /* at this stage, check for PLL lock status */
> cm_wait_for_lock(LOCKED_MASK);
> @@ -843,33 +856,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> * assert/deassert outresetall
> */
> /* assert mainpll outresetall */
> - setbits_le32(&clock_manager_base->main_pll.vco0,
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
> /* assert perpll outresetall */
> - setbits_le32(&clock_manager_base->per_pll.vco0,
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
> /* de-assert mainpll outresetall */
> - clrbits_le32(&clock_manager_base->main_pll.vco0,
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
> /* de-assert perpll outresetall */
> - clrbits_le32(&clock_manager_base->per_pll.vco0,
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
>
> /* Take all PLLs out of bypass when boot mode is cleared. */
> /* release mainpll from bypass */
> writel(CLKMGR_MAINPLL_BYPASS_RESET,
> - &clock_manager_base->main_pll.bypassr);
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSR);
> /* wait till Clock Manager is not busy */
> cm_wait_for_fsm();
>
> /* release perpll from bypass */
> writel(CLKMGR_PERPLL_BYPASS_RESET,
> - &clock_manager_base->per_pll.bypassr);
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSR);
> /* wait till Clock Manager is not busy */
> cm_wait_for_fsm();
>
> /* clear boot mode */
> - clrbits_le32(&clock_manager_base->ctrl,
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
> CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
> /* wait till Clock Manager is not busy */
> cm_wait_for_fsm();
> @@ -882,9 +895,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
>
> /* Now ungate non-hw-managed clocks */
> writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
> - CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> - &clock_manager_base->main_pll.ens);
> - writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
> + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENS);
> + writel(CLKMGR_PERPLL_EN_RESET,
> + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_ENS);
>
> /* Clear the loss lock and slip bits as they might set during
> clock reconfiguration */
> @@ -894,14 +908,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
> CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
> CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
> - &clock_manager_base->intr);
> + socfpga_clkmgr_base + CLKMGR_A10_INTR);
>
> return 0;
> }
>
> static void cm_use_intosc(void)
> {
> - setbits_le32(&clock_manager_base->ctrl,
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
> CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
> }
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
> index 3a64600861..c9990af46f 100644
> --- a/arch/arm/mach-socfpga/clock_manager_gen5.c
> +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
> @@ -9,23 +9,20 @@
> #include <asm/arch/clock_manager.h>
> #include <wait_bit.h>
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> -
> /*
> * function to write the bypass register which requires a poll of the
> * busy bit
> */
> static void cm_write_bypass(u32 val)
> {
> - writel(val, &clock_manager_base->bypass);
> + writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_BYPASS);
> cm_wait_for_fsm();
> }
>
> /* function to write the ctrl register which requires a poll of the busy bit */
> static void cm_write_ctrl(u32 val)
> {
> - writel(val, &clock_manager_base->ctrl);
> + writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_CTRL);
> cm_wait_for_fsm();
> }
>
> @@ -79,8 +76,8 @@ int cm_basic_init(const struct cm_config * const cfg)
> * gatting off the rest of the periperal clocks.
> */
> writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
> - readl(&clock_manager_base->per_pll.en),
> - &clock_manager_base->per_pll.en);
> + readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN),
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
>
> /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
> writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
> @@ -89,12 +86,12 @@ int cm_basic_init(const struct cm_config * const cfg)
> CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
> CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
> CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
> - &clock_manager_base->main_pll.en);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
>
> - writel(0, &clock_manager_base->sdr_pll.en);
> + writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
>
> /* now we can gate off the rest of the peripheral clocks */
> - writel(0, &clock_manager_base->per_pll.en);
> + writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
>
> /* Put all plls in bypass */
> cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
> @@ -103,13 +100,13 @@ int cm_basic_init(const struct cm_config * const cfg)
> /* Put all plls VCO registers back to reset value. */
> writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
> ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
> - &clock_manager_base->main_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
> ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
> - &clock_manager_base->per_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
> ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
> - &clock_manager_base->sdr_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
> /*
> * The clocks to the flash devices and the L4_MAIN clocks can
> @@ -119,23 +116,26 @@ int cm_basic_init(const struct cm_config * const cfg)
> * after exiting safe mode but before ungating the clocks.
> */
> writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
> - &clock_manager_base->per_pll.src);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
> - &clock_manager_base->main_pll.l4src);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
>
> /* read back for the required 5 us delay. */
> - readl(&clock_manager_base->main_pll.vco);
> - readl(&clock_manager_base->per_pll.vco);
> - readl(&clock_manager_base->sdr_pll.vco);
> + readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> + readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> + readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
>
> /*
> * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
> * with numerator and denominator.
> */
> - writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
> - writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
> - writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
> + writel(cfg->main_vco_base,
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> + writel(cfg->peri_vco_base,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> + writel(cfg->sdram_vco_base,
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
> /*
> * Time starts here. Must wait 7 us from
> @@ -144,44 +144,53 @@ int cm_basic_init(const struct cm_config * const cfg)
> end = timer_get_us() + 7;
>
> /* main mpu */
> - writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
> + writel(cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
>
> /* altera group mpuclk */
> - writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
> + writel(cfg->altera_grp_mpuclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
>
> /* main main clock */
> - writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
> + writel(cfg->mainclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
>
> /* main for dbg */
> - writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
> + writel(cfg->dbgatclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGATCLK);
>
> /* main for cfgs2fuser0clk */
> writel(cfg->cfg2fuser0clk,
> - &clock_manager_base->main_pll.cfgs2fuser0clk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
>
> /* Peri emac0 50 MHz default to RMII */
> - writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
> + writel(cfg->emac0clk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC0CLK);
>
> /* Peri emac1 50 MHz default to RMII */
> - writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
> + writel(cfg->emac1clk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC1CLK);
>
> /* Peri QSPI */
> - writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
> + writel(cfg->mainqspiclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
>
> - writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
> + writel(cfg->perqspiclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERQSPICLK);
>
> /* Peri pernandsdmmcclk */
> writel(cfg->mainnandsdmmcclk,
> - &clock_manager_base->main_pll.mainnandsdmmcclk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
>
> writel(cfg->pernandsdmmcclk,
> - &clock_manager_base->per_pll.pernandsdmmcclk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
>
> /* Peri perbaseclk */
> - writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
> + writel(cfg->perbaseclk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
>
> /* Peri s2fuser1clk */
> - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
> + writel(cfg->s2fuser1clk,
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
>
> /* 7 us must have elapsed before we can enable the VCO */
> while (timer_get_us() < end)
> @@ -190,101 +199,106 @@ int cm_basic_init(const struct cm_config * const cfg)
> /* Enable vco */
> /* main pll vco */
> writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> - &clock_manager_base->main_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
>
> /* periferal pll */
> writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> - &clock_manager_base->per_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
>
> /* sdram pll vco */
> writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> - &clock_manager_base->sdr_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
> /* L3 MP and L3 SP */
> - writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
> + writel(cfg->maindiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
>
> - writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
> + writel(cfg->dbgdiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGDIV);
>
> - writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
> + writel(cfg->tracediv,
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_TRACEDIV);
>
> /* L4 MP, L4 SP, can0, and can1 */
> - writel(cfg->perdiv, &clock_manager_base->per_pll.div);
> + writel(cfg->perdiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_DIV);
>
> - writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
> + writel(cfg->gpiodiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_GPIODIV);
>
> cm_wait_for_lock(LOCKED_MASK);
>
> /* write the sdram clock counters before toggling outreset all */
> writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
> - &clock_manager_base->sdr_pll.ddrdqsclk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
>
> writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
> - &clock_manager_base->sdr_pll.ddr2xdqsclk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
>
> writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
> - &clock_manager_base->sdr_pll.ddrdqclk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
>
> writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
> - &clock_manager_base->sdr_pll.s2fuser2clk);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
>
> /*
> * after locking, but before taking out of bypass
> * assert/deassert outresetall
> */
> - u32 mainvco = readl(&clock_manager_base->main_pll.vco);
> + u32 mainvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
>
> /* assert main outresetall */
> writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
> - &clock_manager_base->main_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
>
> - u32 periphvco = readl(&clock_manager_base->per_pll.vco);
> + u32 periphvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
>
> /* assert pheriph outresetall */
> writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
> - &clock_manager_base->per_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
>
> /* assert sdram outresetall */
> - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
> - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
> - &clock_manager_base->sdr_pll.vco);
> + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
> + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
> /* deassert main outresetall */
> writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
> - &clock_manager_base->main_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
>
> /* deassert pheriph outresetall */
> writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
> - &clock_manager_base->per_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
>
> /* deassert sdram outresetall */
> writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> - &clock_manager_base->sdr_pll.vco);
> + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
>
> /*
> * now that we've toggled outreset all, all the clocks
> * are aligned nicely; so we can change any phase.
> */
> ret = cm_write_with_phase(cfg->ddrdqsclk,
> - &clock_manager_base->sdr_pll.ddrdqsclk,
> + (const void *)(socfpga_clkmgr_base +
> + CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
> CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
> if (ret)
> return ret;
>
> /* SDRAM DDR2XDQSCLK */
> ret = cm_write_with_phase(cfg->ddr2xdqsclk,
> - &clock_manager_base->sdr_pll.ddr2xdqsclk,
> + (const void *)(socfpga_clkmgr_base +
> + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
> CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
> if (ret)
> return ret;
>
> ret = cm_write_with_phase(cfg->ddrdqclk,
> - &clock_manager_base->sdr_pll.ddrdqclk,
> + (const void *)(socfpga_clkmgr_base +
> + CLKMGR_GEN5_SDRPLL_DDRDQCLK),
> CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
> if (ret)
> return ret;
>
> ret = cm_write_with_phase(cfg->s2fuser2clk,
> - &clock_manager_base->sdr_pll.s2fuser2clk,
> + (const void *)(socfpga_clkmgr_base +
> + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
> CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
> if (ret)
> return ret;
> @@ -293,24 +307,26 @@ int cm_basic_init(const struct cm_config * const cfg)
> cm_write_bypass(0);
>
> /* clear safe mode */
> - cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
> + cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_GEN5_CTRL) |
> + CLKMGR_CTRL_SAFEMODE);
>
> /*
> * now that safe mode is clear with clocks gated
> * it safe to change the source mux for the flashes the the L4_MAIN
> */
> - writel(cfg->persrc, &clock_manager_base->per_pll.src);
> - writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
> + writel(cfg->persrc, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> + writel(cfg->l4src, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
>
> /* Now ungate non-hw-managed clocks */
> - writel(~0, &clock_manager_base->main_pll.en);
> - writel(~0, &clock_manager_base->per_pll.en);
> - writel(~0, &clock_manager_base->sdr_pll.en);
> + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
> + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
> + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
>
> /* Clear the loss of lock bits (write 1 to clear) */
> - writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
> - CLKMGR_INTER_MAINPLLLOST_MASK,
> - &clock_manager_base->inter);
> + writel(CLKMGR_INTER_SDRPLLLOST_MASK |
> + CLKMGR_INTER_PERPLLLOST_MASK |
> + CLKMGR_INTER_MAINPLLLOST_MASK,
> + socfpga_clkmgr_base + CLKMGR_GEN5_INTER);
>
> return 0;
> }
> @@ -320,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
> u32 reg, clock;
>
> /* get the main VCO clock */
> - reg = readl(&clock_manager_base->main_pll.vco);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> clock = cm_get_osc_clk_hz(1);
> clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
> CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
> @@ -335,7 +351,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
> u32 reg, clock = 0;
>
> /* identify PER PLL clock source */
> - reg = readl(&clock_manager_base->per_pll.vco);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
> CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
> if (reg == CLKMGR_VCO_SSRC_EOSC1)
> @@ -346,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
> clock = cm_get_f2s_per_ref_clk_hz();
>
> /* get the PER VCO clock */
> - reg = readl(&clock_manager_base->per_pll.vco);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
> CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
> clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
> @@ -362,9 +378,9 @@ unsigned long cm_get_mpu_clk_hz(void)
> clock = cm_get_main_vco_clk_hz();
>
> /* get the MPU clock */
> - reg = readl(&clock_manager_base->altera.mpuclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
> clock /= (reg + 1);
> - reg = readl(&clock_manager_base->main_pll.mpuclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
> clock /= (reg + 1);
> return clock;
> }
> @@ -374,7 +390,7 @@ unsigned long cm_get_sdram_clk_hz(void)
> u32 reg, clock = 0;
>
> /* identify SDRAM PLL clock source */
> - reg = readl(&clock_manager_base->sdr_pll.vco);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
> CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
> if (reg == CLKMGR_VCO_SSRC_EOSC1)
> @@ -385,14 +401,14 @@ unsigned long cm_get_sdram_clk_hz(void)
> clock = cm_get_f2s_sdr_ref_clk_hz();
>
> /* get the SDRAM VCO clock */
> - reg = readl(&clock_manager_base->sdr_pll.vco);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
> CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
> clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
> CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
>
> /* get the SDRAM (DDR_DQS) clock */
> - reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
> reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
> CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
> clock /= (reg + 1);
> @@ -405,7 +421,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> u32 reg, clock = 0;
>
> /* identify the source of L4 SP clock */
> - reg = readl(&clock_manager_base->main_pll.l4src);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
> reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
> CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
>
> @@ -413,20 +429,21 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> clock = cm_get_main_vco_clk_hz();
>
> /* get the clock prior L4 SP divider (main clk) */
> - reg = readl(&clock_manager_base->altera.mainclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MAINCLK);
> clock /= (reg + 1);
> - reg = readl(&clock_manager_base->main_pll.mainclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
> clock /= (reg + 1);
> } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
> clock = cm_get_per_vco_clk_hz();
>
> /* get the clock prior L4 SP divider (periph_base_clk) */
> - reg = readl(&clock_manager_base->per_pll.perbaseclk);
> + reg = readl(socfpga_clkmgr_base +
> + CLKMGR_GEN5_PERPLL_PERBASECLK);
> clock /= (reg + 1);
> }
>
> /* get the L4 SP clock which supplied to UART */
> - reg = readl(&clock_manager_base->main_pll.maindiv);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
> reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
> CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
> clock = clock / (1 << reg);
> @@ -439,7 +456,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
> u32 reg, clock = 0;
>
> /* identify the source of MMC clock */
> - reg = readl(&clock_manager_base->per_pll.src);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
> CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
>
> @@ -449,13 +466,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
> clock = cm_get_main_vco_clk_hz();
>
> /* get the SDMMC clock */
> - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
> + reg = readl(socfpga_clkmgr_base +
> + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
> clock /= (reg + 1);
> } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
> clock = cm_get_per_vco_clk_hz();
>
> /* get the SDMMC clock */
> - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
> + reg = readl(socfpga_clkmgr_base +
> + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
> clock /= (reg + 1);
> }
>
> @@ -469,7 +488,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
> u32 reg, clock = 0;
>
> /* identify the source of QSPI clock */
> - reg = readl(&clock_manager_base->per_pll.src);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
> CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
>
> @@ -479,13 +498,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
> clock = cm_get_main_vco_clk_hz();
>
> /* get the qspi clock */
> - reg = readl(&clock_manager_base->main_pll.mainqspiclk);
> + reg = readl(socfpga_clkmgr_base +
> + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
> clock /= (reg + 1);
> } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
> clock = cm_get_per_vco_clk_hz();
>
> /* get the qspi clock */
> - reg = readl(&clock_manager_base->per_pll.perqspiclk);
> + reg = readl(socfpga_clkmgr_base +
> + CLKMGR_GEN5_PERPLL_PERQSPICLK);
> clock /= (reg + 1);
> }
>
> @@ -499,7 +520,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
> clock = cm_get_per_vco_clk_hz();
>
> /* get the clock prior L4 SP divider (periph_base_clk) */
> - reg = readl(&clock_manager_base->per_pll.perbaseclk);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
> clock /= (reg + 1);
>
> return clock;
> diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> index 6cbf07ac6f..c6269701f0 100644
> --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> @@ -12,29 +12,26 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> -
> /*
> * function to write the bypass register which requires a poll of the
> * busy bit
> */
> static void cm_write_bypass_mainpll(u32 val)
> {
> - writel(val, &clock_manager_base->main_pll.bypass);
> + writel(val, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_BYPASS);
> cm_wait_for_fsm();
> }
>
> static void cm_write_bypass_perpll(u32 val)
> {
> - writel(val, &clock_manager_base->per_pll.bypass);
> + writel(val, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_BYPASS);
> cm_wait_for_fsm();
> }
>
> /* function to write the ctrl register which requires a poll of the busy bit */
> static void cm_write_ctrl(u32 val)
> {
> - writel(val, &clock_manager_base->ctrl);
> + writel(val, socfpga_clkmgr_base + CLKMGR_S10_CTRL);
> cm_wait_for_fsm();
> }
>
> @@ -66,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg)
>
> writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> ~CLKMGR_PLLGLOB_RST_MASK),
> - &clock_manager_base->main_pll.pllglob);
> - writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
> - writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
> - writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
> - writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
> - writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
> + writel(cfg->main_pll_fdbck,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
> + writel(vcocalib,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_VCOCALIB);
> + writel(cfg->main_pll_pllc0,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC0);
> + writel(cfg->main_pll_pllc1,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC1);
> + writel(cfg->main_pll_nocdiv,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCDIV);
>
> /* setup peripheral PLL dividers */
> /* calculate the vcocalib value */
> @@ -88,18 +90,23 @@ void cm_basic_init(const struct cm_config * const cfg)
>
> writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> ~CLKMGR_PLLGLOB_RST_MASK),
> - &clock_manager_base->per_pll.pllglob);
> - writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
> - writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
> - writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
> - writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
> - writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
> - writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
> + writel(cfg->per_pll_fdbck,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
> + writel(vcocalib, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_VCOCALIB);
> + writel(cfg->per_pll_pllc0,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC0);
> + writel(cfg->per_pll_pllc1,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1);
> + writel(cfg->per_pll_emacctl,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EMACCTL);
> + writel(cfg->per_pll_gpiodiv,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_GPIODIV);
>
> /* Take both PLL out of reset and power up */
> - setbits_le32(&clock_manager_base->main_pll.pllglob,
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB,
> CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> - setbits_le32(&clock_manager_base->per_pll.pllglob,
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB,
> CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
>
> #define LOCKED_MASK \
> @@ -113,66 +120,85 @@ void cm_basic_init(const struct cm_config * const cfg)
> * only take effect upon value change, we shall set a maximum value as
> * default value.
> */
> - writel(0xff, &clock_manager_base->main_pll.mpuclk);
> - writel(0xff, &clock_manager_base->main_pll.nocclk);
> - writel(0xff, &clock_manager_base->main_pll.cntr2clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr3clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr4clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr5clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr6clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr7clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr8clk);
> - writel(0xff, &clock_manager_base->main_pll.cntr9clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr2clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr3clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr4clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr5clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr6clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr7clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr8clk);
> - writel(0xff, &clock_manager_base->per_pll.cntr9clk);
> -
> - writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
> - writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
> - writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
> - writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
> - writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
> - writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
> - writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
> - writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
> - writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
> - writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
> - writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
> - writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
> - writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
> - writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
> - writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
> - writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
> - writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
> - writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
> + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
> +
> + writel(cfg->main_pll_mpuclk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
> + writel(cfg->main_pll_nocclk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
> + writel(cfg->main_pll_cntr2clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
> + writel(cfg->main_pll_cntr3clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
> + writel(cfg->main_pll_cntr4clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
> + writel(cfg->main_pll_cntr5clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
> + writel(cfg->main_pll_cntr6clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
> + writel(cfg->main_pll_cntr7clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
> + writel(cfg->main_pll_cntr8clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
> + writel(cfg->main_pll_cntr9clk,
> + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
> + writel(cfg->per_pll_cntr2clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
> + writel(cfg->per_pll_cntr3clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
> + writel(cfg->per_pll_cntr4clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
> + writel(cfg->per_pll_cntr5clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
> + writel(cfg->per_pll_cntr6clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
> + writel(cfg->per_pll_cntr7clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
> + writel(cfg->per_pll_cntr8clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
> + writel(cfg->per_pll_cntr9clk,
> + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
>
> /* Take all PLLs out of bypass */
> cm_write_bypass_mainpll(0);
> cm_write_bypass_perpll(0);
>
> /* clear safe mode / out of boot mode */
> - cm_write_ctrl(readl(&clock_manager_base->ctrl)
> - & ~(CLKMGR_CTRL_SAFEMODE));
> + cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_S10_CTRL) &
> + ~(CLKMGR_CTRL_SAFEMODE));
>
> /* Now ungate non-hw-managed clocks */
> - writel(~0, &clock_manager_base->main_pll.en);
> - writel(~0, &clock_manager_base->per_pll.en);
> + writel(~0, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_EN);
> + writel(~0, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EN);
>
> /* Clear the loss of lock bits (write 1 to clear) */
> - writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
> - &clock_manager_base->intrclr);
> + writel(CLKMGR_INTER_PERPLLLOST_MASK |
> + CLKMGR_INTER_MAINPLLLOST_MASK,
> + socfpga_clkmgr_base + CLKMGR_S10_INTRCLR);
> }
>
> static unsigned long cm_get_main_vco_clk_hz(void)
> {
> unsigned long fref, refdiv, mdiv, reg, vco;
>
> - reg = readl(&clock_manager_base->main_pll.pllglob);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
>
> fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> @@ -191,7 +217,7 @@ static unsigned long cm_get_main_vco_clk_hz(void)
> refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>
> - reg = readl(&clock_manager_base->main_pll.fdbck);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
> mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
>
> vco = fref / refdiv;
> @@ -203,7 +229,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
> {
> unsigned long fref, refdiv, mdiv, reg, vco;
>
> - reg = readl(&clock_manager_base->per_pll.pllglob);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
>
> fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> @@ -222,7 +248,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
> refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> CLKMGR_PLLGLOB_REFCLKDIV_MASK;
>
> - reg = readl(&clock_manager_base->per_pll.fdbck);
> + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
> mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
>
> vco = fref / refdiv;
> @@ -232,20 +258,23 @@ static unsigned long cm_get_per_vco_clk_hz(void)
>
> unsigned long cm_get_mpu_clk_hz(void)
> {
> - unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
> + unsigned long clock = readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_MPUCLK);
>
> clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>
> switch (clock) {
> case CLKMGR_CLKSRC_MAIN:
> clock = cm_get_main_vco_clk_hz();
> - clock /= (readl(&clock_manager_base->main_pll.pllc0) &
> + clock /= (readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_PLLC0) &
> CLKMGR_PLLC0_DIV_MASK);
> break;
>
> case CLKMGR_CLKSRC_PER:
> clock = cm_get_per_vco_clk_hz();
> - clock /= (readl(&clock_manager_base->per_pll.pllc0) &
> + clock /= (readl(socfpga_clkmgr_base +
> + CLKMGR_S10_PERPLL_PLLC0) &
> CLKMGR_CLKCNT_MSK);
> break;
>
> @@ -262,27 +291,28 @@ unsigned long cm_get_mpu_clk_hz(void)
> break;
> }
>
> - clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
> - CLKMGR_CLKCNT_MSK);
> + clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK) &
> + CLKMGR_CLKCNT_MSK);
> return clock;
> }
>
> unsigned int cm_get_l3_main_clk_hz(void)
> {
> - u32 clock = readl(&clock_manager_base->main_pll.nocclk);
> + u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
>
> clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>
> switch (clock) {
> case CLKMGR_CLKSRC_MAIN:
> clock = cm_get_main_vco_clk_hz();
> - clock /= (readl(&clock_manager_base->main_pll.pllc1) &
> + clock /= (readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_PLLC1) &
> CLKMGR_PLLC0_DIV_MASK);
> break;
>
> case CLKMGR_CLKSRC_PER:
> clock = cm_get_per_vco_clk_hz();
> - clock /= (readl(&clock_manager_base->per_pll.pllc1) &
> + clock /= (readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1) &
> CLKMGR_CLKCNT_MSK);
> break;
>
> @@ -299,28 +329,30 @@ unsigned int cm_get_l3_main_clk_hz(void)
> break;
> }
>
> - clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
> + clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK) &
> CLKMGR_CLKCNT_MSK);
> return clock;
> }
>
> unsigned int cm_get_mmc_controller_clk_hz(void)
> {
> - u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
> + u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
>
> clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
>
> switch (clock) {
> case CLKMGR_CLKSRC_MAIN:
> clock = cm_get_l3_main_clk_hz();
> - clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
> - CLKMGR_CLKCNT_MSK);
> + clock /= 1 + (readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_CNTR6CLK) &
> + CLKMGR_CLKCNT_MSK);
> break;
>
> case CLKMGR_CLKSRC_PER:
> clock = cm_get_l3_main_clk_hz();
> - clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
> - CLKMGR_CLKCNT_MSK);
> + clock /= 1 + (readl(socfpga_clkmgr_base +
> + CLKMGR_S10_PERPLL_CNTR6CLK) &
> + CLKMGR_CLKCNT_MSK);
> break;
>
> case CLKMGR_CLKSRC_OSC1:
> @@ -342,8 +374,9 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> {
> u32 clock = cm_get_l3_main_clk_hz();
>
> - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
> - CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> + clock /= (1 << ((readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> return clock;
> }
>
> @@ -356,8 +389,9 @@ unsigned int cm_get_spi_controller_clk_hz(void)
> {
> u32 clock = cm_get_l3_main_clk_hz();
>
> - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
> - CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
> + clock /= (1 << ((readl(socfpga_clkmgr_base +
> + CLKMGR_S10_MAINPLL_NOCDIV) >>
> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
> return clock;
> }
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index dd80e3a767..4f9d10dd78 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -6,6 +6,8 @@
> #ifndef _CLOCK_MANAGER_H_
> #define _CLOCK_MANAGER_H_
>
> +extern phys_addr_t socfpga_clkmgr_base;
> +
> #ifndef __ASSEMBLER__
> void cm_wait_for_lock(u32 mask);
> int cm_wait_for_fsm(void);
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> index de8c22540f..52b579e6e1 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> @@ -8,86 +8,57 @@
>
> #ifndef __ASSEMBLER__
>
> -struct socfpga_clock_manager_main_pll {
> - u32 vco0;
> - u32 vco1;
> - u32 en;
> - u32 ens;
> - u32 enr;
> - u32 bypass;
> - u32 bypasss;
> - u32 bypassr;
> - u32 mpuclk;
> - u32 nocclk;
> - u32 cntr2clk;
> - u32 cntr3clk;
> - u32 cntr4clk;
> - u32 cntr5clk;
> - u32 cntr6clk;
> - u32 cntr7clk;
> - u32 cntr8clk;
> - u32 cntr9clk;
> - u32 pad_0x48_0x5b[5];
> - u32 cntr15clk;
> - u32 outrst;
> - u32 outrststat;
> - u32 nocdiv;
> - u32 pad_0x6c_0x80[5];
> -};
> -
> -struct socfpga_clock_manager_per_pll {
> - u32 vco0;
> - u32 vco1;
> - u32 en;
> - u32 ens;
> - u32 enr;
> - u32 bypass;
> - u32 bypasss;
> - u32 bypassr;
> - u32 pad_0x20_0x27[2];
> - u32 cntr2clk;
> - u32 cntr3clk;
> - u32 cntr4clk;
> - u32 cntr5clk;
> - u32 cntr6clk;
> - u32 cntr7clk;
> - u32 cntr8clk;
> - u32 cntr9clk;
> - u32 pad_0x48_0x5f[6];
> - u32 outrst;
> - u32 outrststat;
> - u32 emacctl;
> - u32 gpiodiv;
> - u32 pad_0x70_0x80[4];
> -};
> -
> -struct socfpga_clock_manager_altera {
> - u32 mpuclk;
> - u32 nocclk;
> - u32 mainmisc0;
> - u32 mainmisc1;
> - u32 perimisc0;
> - u32 perimisc1;
> -};
> -
> -struct socfpga_clock_manager {
> - /* clkmgr */
> - u32 ctrl;
> - u32 intr;
> - u32 intrs;
> - u32 intrr;
> - u32 intren;
> - u32 intrens;
> - u32 intrenr;
> - u32 stat;
> - u32 testioctrl;
> - u32 _pad_0x24_0x40[7];
> - /* mainpllgrp */
> - struct socfpga_clock_manager_main_pll main_pll;
> - /* perpllgrp */
> - struct socfpga_clock_manager_per_pll per_pll;
> - struct socfpga_clock_manager_altera altera;
> -};
> +/* Clock manager group */
> +#define CLKMGR_A10_CTRL 0
> +#define CLKMGR_A10_INTR 4
> +#define CLKMGR_A10_STAT 0x1c
> +/* MainPLL group */
> +#define CLKMGR_A10_MAINPLL_VCO0 0x40
> +#define CLKMGR_A10_MAINPLL_VCO1 0x44
> +#define CLKMGR_A10_MAINPLL_EN 0x48
> +#define CLKMGR_A10_MAINPLL_ENS 0x4c
> +#define CLKMGR_A10_MAINPLL_ENR 0x50
> +#define CLKMGR_A10_MAINPLL_BYPASS 0x54
> +#define CLKMGR_A10_MAINPLL_BYPASSS 0x58
> +#define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
> +#define CLKMGR_A10_MAINPLL_MPUCLK 0x60
> +#define CLKMGR_A10_MAINPLL_NOCCLK 0x64
> +#define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
> +#define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
> +#define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
> +#define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
> +#define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
> +#define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
> +#define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
> +#define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
> +#define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
> +#define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
> +/* Peripheral PLL group */
> +#define CLKMGR_A10_PERPLL_VCO0 0xc0
> +#define CLKMGR_A10_PERPLL_VCO1 0xc4
> +#define CLKMGR_A10_PERPLL_EN 0xc8
> +#define CLKMGR_A10_PERPLL_ENS 0xcc
> +#define CLKMGR_A10_PERPLL_ENR 0xd0
> +#define CLKMGR_A10_PERPLL_BYPASS 0xd4
> +#define CLKMGR_A10_PERPLL_BYPASSS 0xd8
> +#define CLKMGR_A10_PERPLL_BYPASSR 0xdc
> +#define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
> +#define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
> +#define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
> +#define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
> +#define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
> +#define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
> +#define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
> +#define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
> +#define CLKMGR_A10_PERPLL_EMACCTL 0x128
> +#define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
> +/* Altera group */
> +#define CLKMGR_A10_ALTR_MPUCLK 0x140
> +#define CLKMGR_A10_ALTR_NOCCLK 0x144
> +
> +#define CLKMGR_STAT CLKMGR_A10_STAT
> +#define CLKMGR_INTER CLKMGR_A10_INTER
> +#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
>
> #ifdef CONFIG_SPL_BUILD
> int cm_basic_init(const void *blob);
> @@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>
> #endif /* __ASSEMBLER__ */
>
> -#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
> -#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
> #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
> CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> index 5bedf28cf1..caa1231c69 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> @@ -45,71 +45,53 @@ struct cm_config {
> u32 altera_grp_mpuclk;
> };
>
> -struct socfpga_clock_manager_main_pll {
> - u32 vco;
> - u32 misc;
> - u32 mpuclk;
> - u32 mainclk;
> - u32 dbgatclk;
> - u32 mainqspiclk;
> - u32 mainnandsdmmcclk;
> - u32 cfgs2fuser0clk;
> - u32 en;
> - u32 maindiv;
> - u32 dbgdiv;
> - u32 tracediv;
> - u32 l4src;
> - u32 stat;
> - u32 _pad_0x38_0x40[2];
> -};
> -
> -struct socfpga_clock_manager_per_pll {
> - u32 vco;
> - u32 misc;
> - u32 emac0clk;
> - u32 emac1clk;
> - u32 perqspiclk;
> - u32 pernandsdmmcclk;
> - u32 perbaseclk;
> - u32 s2fuser1clk;
> - u32 en;
> - u32 div;
> - u32 gpiodiv;
> - u32 src;
> - u32 stat;
> - u32 _pad_0x34_0x40[3];
> -};
> -
> -struct socfpga_clock_manager_sdr_pll {
> - u32 vco;
> - u32 ctrl;
> - u32 ddrdqsclk;
> - u32 ddr2xdqsclk;
> - u32 ddrdqclk;
> - u32 s2fuser2clk;
> - u32 en;
> - u32 stat;
> -};
> -
> -struct socfpga_clock_manager_altera {
> - u32 mpuclk;
> - u32 mainclk;
> -};
> -
> -struct socfpga_clock_manager {
> - u32 ctrl;
> - u32 bypass;
> - u32 inter;
> - u32 intren;
> - u32 dbctrl;
> - u32 stat;
> - u32 _pad_0x18_0x3f[10];
> - struct socfpga_clock_manager_main_pll main_pll;
> - struct socfpga_clock_manager_per_pll per_pll;
> - struct socfpga_clock_manager_sdr_pll sdr_pll;
> - struct socfpga_clock_manager_altera altera;
> - u32 _pad_0xe8_0x200[70];
> -};
> +/* Clock manager group */
> +#define CLKMGR_GEN5_CTRL 0
> +#define CLKMGR_GEN5_BYPASS 4
> +#define CLKMGR_GEN5_INTER 8
> +#define CLKMGR_GEN5_STAT 0x14
> +/* MainPLL group */
> +#define CLKMGR_GEN5_MAINPLL_VCO 0x40
> +#define CLKMGR_GEN5_MAINPLL_MISC 0x44
> +#define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48
> +#define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c
> +#define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50
> +#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54
> +#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58
> +#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c
> +#define CLKMGR_GEN5_MAINPLL_EN 0x60
> +#define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64
> +#define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68
> +#define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c
> +#define CLKMGR_GEN5_MAINPLL_L4SRC 0x70
> +/* Peripheral PLL group */
> +#define CLKMGR_GEN5_PERPLL_VCO 0x80
> +#define CLKMGR_GEN5_PERPLL_MISC 0x84
> +#define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88
> +#define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c
> +#define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90
> +#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94
> +#define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98
> +#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c
> +#define CLKMGR_GEN5_PERPLL_EN 0xa0
> +#define CLKMGR_GEN5_PERPLL_DIV 0xa4
> +#define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8
> +#define CLKMGR_GEN5_PERPLL_SRC 0xac
> +/* SDRAM PLL group */
> +#define CLKMGR_GEN5_SDRPLL_VCO 0xc0
> +#define CLKMGR_GEN5_SDRPLL_CTRL 0xc4
> +#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8
> +#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc
> +#define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0
> +#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4
> +#define CLKMGR_GEN5_SDRPLL_EN 0xd8
> +/* Altera group */
> +#define CLKMGR_GEN5_ALTR_MPUCLK 0xe0
> +#define CLKMGR_GEN5_ALTR_MAINCLK 0xe4
> +
> +#define CLKMGR_STAT CLKMGR_GEN5_STAT
> +#define CLKMGR_INTER CLKMGR_GEN5_INTER
> +#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
>
> /* Clock speed accessors */
> unsigned long cm_get_mpu_clk_hz(void);
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> index 24b20de011..fa0ba26f09 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> @@ -69,75 +69,54 @@ struct cm_config {
>
> void cm_basic_init(const struct cm_config * const cfg);
>
> -struct socfpga_clock_manager_main_pll {
> - u32 en;
> - u32 ens;
> - u32 enr;
> - u32 bypass;
> - u32 bypasss;
> - u32 bypassr;
> - u32 mpuclk;
> - u32 nocclk;
> - u32 cntr2clk;
> - u32 cntr3clk;
> - u32 cntr4clk;
> - u32 cntr5clk;
> - u32 cntr6clk;
> - u32 cntr7clk;
> - u32 cntr8clk;
> - u32 cntr9clk;
> - u32 nocdiv;
> - u32 pllglob;
> - u32 fdbck;
> - u32 mem;
> - u32 memstat;
> - u32 pllc0;
> - u32 pllc1;
> - u32 vcocalib;
> - u32 _pad_0x90_0xA0[5];
> -};
> -
> -struct socfpga_clock_manager_per_pll {
> - u32 en;
> - u32 ens;
> - u32 enr;
> - u32 bypass;
> - u32 bypasss;
> - u32 bypassr;
> - u32 cntr2clk;
> - u32 cntr3clk;
> - u32 cntr4clk;
> - u32 cntr5clk;
> - u32 cntr6clk;
> - u32 cntr7clk;
> - u32 cntr8clk;
> - u32 cntr9clk;
> - u32 emacctl;
> - u32 gpiodiv;
> - u32 pllglob;
> - u32 fdbck;
> - u32 mem;
> - u32 memstat;
> - u32 pllc0;
> - u32 pllc1;
> - u32 vcocalib;
> - u32 _pad_0x100_0x124[10];
> -};
> +/* Control status */
> +#define CLKMGR_S10_CTRL 0
> +#define CLKMGR_S10_STAT 4
> +#define CLKMGR_S10_INTRCLR 0x14
> +/* Mainpll group */
> +#define CLKMGR_S10_MAINPLL_EN 0x30
> +#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
> +#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
> +#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
> +#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
> +#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
> +#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
> +#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
> +#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
> +#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
> +#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
> +#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
> +#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
> +#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
> +#define CLKMGR_S10_MAINPLL_FDBCK 0x78
> +#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
> +#define CLKMGR_S10_MAINPLL_PLLC0 0x84
> +#define CLKMGR_S10_MAINPLL_PLLC1 0x88
> +#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
> +/* Periphpll group */
> +#define CLKMGR_S10_PERPLL_EN 0xa4
> +#define CLKMGR_S10_PERPLL_BYPASS 0xac
> +#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
> +#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
> +#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
> +#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
> +#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
> +#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
> +#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
> +#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
> +#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
> +#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
> +#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
> +#define CLKMGR_S10_PERPLL_FDBCK 0xe8
> +#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
> +#define CLKMGR_S10_PERPLL_PLLC0 0xf4
> +#define CLKMGR_S10_PERPLL_PLLC1 0xf8
> +#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
> +
> +#define CLKMGR_STAT CLKMGR_S10_STAT
> +#define CLKMGR_INTER CLKMGR_S10_INTER
> +#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
>
> -struct socfpga_clock_manager {
> - u32 ctrl;
> - u32 stat;
> - u32 testioctrl;
> - u32 intrgen;
> - u32 intrmsk;
> - u32 intrclr;
> - u32 intrsts;
> - u32 intrstk;
> - u32 intrraw;
> - u32 _pad_0x24_0x2c[3];
> - struct socfpga_clock_manager_main_pll main_pll;
> - struct socfpga_clock_manager_per_pll per_pll;
> -};
>
> #define CLKMGR_CTRL_SAFEMODE BIT(0)
> #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
> diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> index fcc53b6fbc..dffd1b2e41 100644
> --- a/arch/arm/mach-socfpga/misc.c
> +++ b/arch/arm/mach-socfpga/misc.c
> @@ -22,6 +22,7 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +phys_addr_t socfpga_clkmgr_base __section(".data");
> phys_addr_t socfpga_rstmgr_base __section(".data");
> phys_addr_t socfpga_sysmgr_base __section(".data");
>
> @@ -238,4 +239,8 @@ void socfpga_get_manager_addr(void)
> socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
> if (!socfpga_sysmgr_base)
> hang();
> +
> + socfpga_clkmgr_base = socfpga_get_base_addr("altr,clk-mgr");
> + if (!socfpga_clkmgr_base)
> + hang();
> }
> diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> index bdcd568d60..aefcae8fb6 100644
> --- a/drivers/mmc/socfpga_dw_mmc.c
> +++ b/drivers/mmc/socfpga_dw_mmc.c
> @@ -18,9 +18,6 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static const struct socfpga_clock_manager *clock_manager_base =
> - (void *)SOCFPGA_CLKMGR_ADDRESS;
> -
> struct socfpga_dwmci_plat {
> struct mmc_config cfg;
> struct mmc mmc;
> @@ -54,8 +51,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
>
> /* Disable SDMMC clock. */
> - clrbits_le32(&clock_manager_base->per_pll.en,
> - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> + clrbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
> + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
>
> debug("%s: drvsel %d smplsel %d\n", __func__,
> priv->drvsel, priv->smplsel);
> @@ -65,8 +62,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
>
> /* Enable SDMMC clock */
> - setbits_le32(&clock_manager_base->per_pll.en,
> - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> + setbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
> + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> }
>
> static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
> --
> 2.19.0
>
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock manager from struct to defines
2019-10-02 9:22 ` Simon Goldschmidt
@ 2019-10-04 2:57 ` Ley Foon Tan
0 siblings, 0 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-10-04 2:57 UTC (permalink / raw)
To: u-boot
On Wed, Oct 2, 2019 at 5:22 PM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> On Tue, Sep 10, 2019 at 10:38 AM Ley Foon Tan <ley.foon.tan@intel.com> wrote:
> >
> > Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
> > to defines.
> > No functional change.
> >
> > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> >
> > ---
> > v2:
> > - Change to use writel(), readl() and etc.
> > - Get base address from DT.
>
> And again: separate patch please. You're mixing "no functional change"
> restructuring with actual changes that could possibly break
> (non-upstreamed) boards.
The original code is using write() and readl() and etc. I will change
the history message from "change to" to "revert to" to avoid
misleading.
Regards
Ley Foon
>
> Regards,
> Simon
>
> > - Add prefix to defines.
> > ---
> > arch/arm/mach-socfpga/clock_manager.c | 12 +-
> > arch/arm/mach-socfpga/clock_manager_arria10.c | 156 +++++++------
> > arch/arm/mach-socfpga/clock_manager_gen5.c | 199 +++++++++--------
> > arch/arm/mach-socfpga/clock_manager_s10.c | 206 ++++++++++--------
> > .../mach-socfpga/include/mach/clock_manager.h | 2 +
> > .../include/mach/clock_manager_arria10.h | 133 +++++------
> > .../include/mach/clock_manager_gen5.h | 112 ++++------
> > .../include/mach/clock_manager_s10.h | 115 ++++------
> > arch/arm/mach-socfpga/misc.c | 5 +
> > drivers/mmc/socfpga_dw_mmc.c | 11 +-
> > 10 files changed, 476 insertions(+), 475 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
> > index 9f3c643df8..09857dc37b 100644
> > --- a/arch/arm/mach-socfpga/clock_manager.c
> > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > @@ -10,18 +10,15 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_clock_manager *clock_manager_base =
> > - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -
> > void cm_wait_for_lock(u32 mask)
> > {
> > u32 inter_val;
> > u32 retry = 0;
> > do {
> > #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > - inter_val = readl(&clock_manager_base->inter) & mask;
> > + inter_val = readl(socfpga_clkmgr_base + CLKMGR_INTER) & mask;
> > #else
> > - inter_val = readl(&clock_manager_base->stat) & mask;
> > + inter_val = readl(socfpga_clkmgr_base + CLKMGR_STAT) & mask;
> > #endif
> > /* Wait for stable lock */
> > if (inter_val == mask)
> > @@ -36,8 +33,9 @@ void cm_wait_for_lock(u32 mask)
> > /* function to poll in the fsm busy bit */
> > int cm_wait_for_fsm(void)
> > {
> > - return wait_for_bit_le32(&clock_manager_base->stat,
> > - CLKMGR_STAT_BUSY, false, 20000, false);
> > + return wait_for_bit_le32((const void *)(socfpga_clkmgr_base +
> > + CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
> > + false);
> > }
> >
> > int set_cpu_clk_info(void)
> > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > index 334a79fd9c..33aebd4f47 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > @@ -231,9 +231,6 @@ static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
> > return 0;
> > }
> >
> > -static const struct socfpga_clock_manager *clock_manager_base =
> > - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -
> > /* calculate the intended main VCO frequency based on handoff */
> > static unsigned int cm_calc_handoff_main_vco_clk_hz
> > (struct mainpll_cfg *main_cfg)
> > @@ -551,12 +548,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
> > writel((main_cfg->vco1_denom <<
> > CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
> > - &clock_manager_base->main_pll.vco1);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> > mdelay(1);
> > cm_wait_for_lock(LOCKED_MASK);
> > }
> > writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > - main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
> > + main_cfg->vco1_numer,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> > mdelay(1);
> > cm_wait_for_lock(LOCKED_MASK);
> > }
> > @@ -579,14 +577,17 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
> > /* execute the ramping here */
> > for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
> > clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
> > - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > - cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
> > - &clock_manager_base->per_pll.vco1);
> > + writel((per_cfg->vco1_denom <<
> > + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > + cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
> > + clk_hz),
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> > mdelay(1);
> > cm_wait_for_lock(LOCKED_MASK);
> > }
> > writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > - per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
> > + per_cfg->vco1_numer,
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> > mdelay(1);
> > cm_wait_for_lock(LOCKED_MASK);
> > }
> > @@ -638,16 +639,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > /* gate off all mainpll clock excpet HW managed clock */
> > writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
> > CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> > - &clock_manager_base->main_pll.enr);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENR);
> >
> > /* now we can gate off the rest of the peripheral clocks */
> > - writel(0, &clock_manager_base->per_pll.en);
> > + writel(0, socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EN);
> >
> > /* Put all plls in external bypass */
> > writel(CLKMGR_MAINPLL_BYPASS_RESET,
> > - &clock_manager_base->main_pll.bypasss);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSS);
> > writel(CLKMGR_PERPLL_BYPASS_RESET,
> > - &clock_manager_base->per_pll.bypasss);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSS);
> >
> > /*
> > * Put all plls VCO registers back to reset value.
> > @@ -657,15 +658,17 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > writel(CLKMGR_MAINPLL_VCO0_RESET |
> > CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
> > (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
> > - &clock_manager_base->main_pll.vco0);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
> >
> > writel(CLKMGR_PERPLL_VCO0_RESET |
> > CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
> > (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
> > - &clock_manager_base->per_pll.vco0);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
> >
> > - writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
> > - writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
> > + writel(CLKMGR_MAINPLL_VCO1_RESET,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> > + writel(CLKMGR_PERPLL_VCO1_RESET,
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> >
> > /* clear the interrupt register status register */
> > writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
> > @@ -676,7 +679,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
> > CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
> > CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
> > - &clock_manager_base->intr);
> > + socfpga_clkmgr_base + CLKMGR_A10_INTR);
> >
> > /* Program VCO Numerator and Denominator for main PLL */
> > ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
> > @@ -687,14 +690,16 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > else if (ramp_required == 2)
> > pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
> >
> > - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > + writel((main_cfg->vco1_denom <<
> > + CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
> > pll_ramp_main_hz),
> > - &clock_manager_base->main_pll.vco1);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> > } else
> > - writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > - main_cfg->vco1_numer,
> > - &clock_manager_base->main_pll.vco1);
> > + writel((main_cfg->vco1_denom <<
> > + CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
> > + main_cfg->vco1_numer,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO1);
> >
> > /* Program VCO Numerator and Denominator for periph PLL */
> > ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
> > @@ -707,23 +712,25 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > pll_ramp_periph_hz =
> > CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
> >
> > - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > + writel((per_cfg->vco1_denom <<
> > + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
> > pll_ramp_periph_hz),
> > - &clock_manager_base->per_pll.vco1);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> > } else
> > - writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > + writel((per_cfg->vco1_denom <<
> > + CLKMGR_PERPLL_VCO1_DENOM_LSB) |
> > per_cfg->vco1_numer,
> > - &clock_manager_base->per_pll.vco1);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO1);
> >
> > /* Wait for at least 5 us */
> > udelay(5);
> >
> > /* Now deassert BGPWRDN and PWRDN */
> > - clrbits_le32(&clock_manager_base->main_pll.vco0,
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> > CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
> > CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
> > - clrbits_le32(&clock_manager_base->per_pll.vco0,
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> > CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
> > CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
> >
> > @@ -731,84 +738,90 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > udelay(7);
> >
> > /* enable the VCO and disable the external regulator to PLL */
> > - writel((readl(&clock_manager_base->main_pll.vco0) &
> > + writel((readl(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0) &
> > ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
> > CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
> > - &clock_manager_base->main_pll.vco0);
> > - writel((readl(&clock_manager_base->per_pll.vco0) &
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0);
> > + writel((readl(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0) &
> > ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
> > CLKMGR_PERPLL_VCO0_EN_SET_MSK,
> > - &clock_manager_base->per_pll.vco0);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0);
> >
> > /* setup all the main PLL counter and clock source */
> > - writel(main_cfg->nocclk,
> > - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
> > - writel(main_cfg->mpuclk,
> > - SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
> > + writel(main_cfg->nocclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_NOCCLK);
> > + writel(main_cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_A10_ALTR_MPUCLK);
> >
> > /* main_emaca_clk divider */
> > - writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
> > + writel(main_cfg->cntr2clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR2CLK);
> > /* main_emacb_clk divider */
> > - writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
> > + writel(main_cfg->cntr3clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR3CLK);
> > /* main_emac_ptp_clk divider */
> > - writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
> > + writel(main_cfg->cntr4clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR4CLK);
> > /* main_gpio_db_clk divider */
> > - writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
> > + writel(main_cfg->cntr5clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR5CLK);
> > /* main_sdmmc_clk divider */
> > - writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
> > + writel(main_cfg->cntr6clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR6CLK);
> > /* main_s2f_user0_clk divider */
> > writel(main_cfg->cntr7clk_cnt |
> > (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
> > - &clock_manager_base->main_pll.cntr7clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR7CLK);
> > /* main_s2f_user1_clk divider */
> > - writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
> > + writel(main_cfg->cntr8clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR8CLK);
> > /* main_hmc_pll_clk divider */
> > writel(main_cfg->cntr9clk_cnt |
> > (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
> > - &clock_manager_base->main_pll.cntr9clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR9CLK);
> > /* main_periph_ref_clk divider */
> > writel(main_cfg->cntr15clk_cnt,
> > - &clock_manager_base->main_pll.cntr15clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_CNTR15CLK);
> >
> > /* setup all the peripheral PLL counter and clock source */
> > /* peri_emaca_clk divider */
> > writel(per_cfg->cntr2clk_cnt |
> > (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr2clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR2CLK);
> > /* peri_emacb_clk divider */
> > writel(per_cfg->cntr3clk_cnt |
> > (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr3clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR3CLK);
> > /* peri_emac_ptp_clk divider */
> > writel(per_cfg->cntr4clk_cnt |
> > (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr4clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR4CLK);
> > /* peri_gpio_db_clk divider */
> > writel(per_cfg->cntr5clk_cnt |
> > (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr5clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR5CLK);
> > /* peri_sdmmc_clk divider */
> > writel(per_cfg->cntr6clk_cnt |
> > (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr6clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR6CLK);
> > /* peri_s2f_user0_clk divider */
> > - writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
> > + writel(per_cfg->cntr7clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR7CLK);
> > /* peri_s2f_user1_clk divider */
> > writel(per_cfg->cntr8clk_cnt |
> > (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
> > - &clock_manager_base->per_pll.cntr8clk);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR8CLK);
> > /* peri_hmc_pll_clk divider */
> > - writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
> > + writel(per_cfg->cntr9clk_cnt,
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_CNTR9CLK);
> >
> > /* setup all the external PLL counter */
> > /* mpu wrapper / external divider */
> > writel(main_cfg->mpuclk_cnt |
> > (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
> > - &clock_manager_base->main_pll.mpuclk);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_MPUCLK);
> > /* NOC wrapper / external divider */
> > writel(main_cfg->nocclk_cnt |
> > (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
> > - &clock_manager_base->main_pll.nocclk);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCCLK);
> > /* NOC subclock divider such as l4 */
> > writel(main_cfg->nocdiv_l4mainclk |
> > (main_cfg->nocdiv_l4mpclk <<
> > @@ -821,10 +834,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
> > (main_cfg->nocdiv_cspdbclk <<
> > CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
> > - &clock_manager_base->main_pll.nocdiv);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_NOCDIV);
> > /* gpio_db external divider */
> > writel(per_cfg->gpiodiv_gpiodbclk,
> > - &clock_manager_base->per_pll.gpiodiv);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_GPIOFIV);
> >
> > /* setup the EMAC clock mux select */
> > writel((per_cfg->emacctl_emac0sel <<
> > @@ -833,7 +846,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
> > (per_cfg->emacctl_emac2sel <<
> > CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
> > - &clock_manager_base->per_pll.emacctl);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_EMACCTL);
> >
> > /* at this stage, check for PLL lock status */
> > cm_wait_for_lock(LOCKED_MASK);
> > @@ -843,33 +856,33 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > * assert/deassert outresetall
> > */
> > /* assert mainpll outresetall */
> > - setbits_le32(&clock_manager_base->main_pll.vco0,
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> > CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
> > /* assert perpll outresetall */
> > - setbits_le32(&clock_manager_base->per_pll.vco0,
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> > CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
> > /* de-assert mainpll outresetall */
> > - clrbits_le32(&clock_manager_base->main_pll.vco0,
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_VCO0,
> > CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
> > /* de-assert perpll outresetall */
> > - clrbits_le32(&clock_manager_base->per_pll.vco0,
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_PERPLL_VCO0,
> > CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
> >
> > /* Take all PLLs out of bypass when boot mode is cleared. */
> > /* release mainpll from bypass */
> > writel(CLKMGR_MAINPLL_BYPASS_RESET,
> > - &clock_manager_base->main_pll.bypassr);
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_BYPASSR);
> > /* wait till Clock Manager is not busy */
> > cm_wait_for_fsm();
> >
> > /* release perpll from bypass */
> > writel(CLKMGR_PERPLL_BYPASS_RESET,
> > - &clock_manager_base->per_pll.bypassr);
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_BYPASSR);
> > /* wait till Clock Manager is not busy */
> > cm_wait_for_fsm();
> >
> > /* clear boot mode */
> > - clrbits_le32(&clock_manager_base->ctrl,
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
> > CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
> > /* wait till Clock Manager is not busy */
> > cm_wait_for_fsm();
> > @@ -882,9 +895,10 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> >
> > /* Now ungate non-hw-managed clocks */
> > writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
> > - CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> > - &clock_manager_base->main_pll.ens);
> > - writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
> > + CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
> > + socfpga_clkmgr_base + CLKMGR_A10_MAINPLL_ENS);
> > + writel(CLKMGR_PERPLL_EN_RESET,
> > + socfpga_clkmgr_base + CLKMGR_A10_PERPLL_ENS);
> >
> > /* Clear the loss lock and slip bits as they might set during
> > clock reconfiguration */
> > @@ -894,14 +908,14 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
> > CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
> > CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
> > CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
> > - &clock_manager_base->intr);
> > + socfpga_clkmgr_base + CLKMGR_A10_INTR);
> >
> > return 0;
> > }
> >
> > static void cm_use_intosc(void)
> > {
> > - setbits_le32(&clock_manager_base->ctrl,
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_A10_CTRL,
> > CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_gen5.c b/arch/arm/mach-socfpga/clock_manager_gen5.c
> > index 3a64600861..c9990af46f 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_gen5.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_gen5.c
> > @@ -9,23 +9,20 @@
> > #include <asm/arch/clock_manager.h>
> > #include <wait_bit.h>
> >
> > -static const struct socfpga_clock_manager *clock_manager_base =
> > - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -
> > /*
> > * function to write the bypass register which requires a poll of the
> > * busy bit
> > */
> > static void cm_write_bypass(u32 val)
> > {
> > - writel(val, &clock_manager_base->bypass);
> > + writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_BYPASS);
> > cm_wait_for_fsm();
> > }
> >
> > /* function to write the ctrl register which requires a poll of the busy bit */
> > static void cm_write_ctrl(u32 val)
> > {
> > - writel(val, &clock_manager_base->ctrl);
> > + writel(val, socfpga_clkmgr_base + CLKMGR_GEN5_CTRL);
> > cm_wait_for_fsm();
> > }
> >
> > @@ -79,8 +76,8 @@ int cm_basic_init(const struct cm_config * const cfg)
> > * gatting off the rest of the periperal clocks.
> > */
> > writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
> > - readl(&clock_manager_base->per_pll.en),
> > - &clock_manager_base->per_pll.en);
> > + readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN),
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
> >
> > /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
> > writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
> > @@ -89,12 +86,12 @@ int cm_basic_init(const struct cm_config * const cfg)
> > CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
> > CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
> > CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
> > - &clock_manager_base->main_pll.en);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
> >
> > - writel(0, &clock_manager_base->sdr_pll.en);
> > + writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
> >
> > /* now we can gate off the rest of the peripheral clocks */
> > - writel(0, &clock_manager_base->per_pll.en);
> > + writel(0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
> >
> > /* Put all plls in bypass */
> > cm_write_bypass(CLKMGR_BYPASS_PERPLL | CLKMGR_BYPASS_SDRPLL |
> > @@ -103,13 +100,13 @@ int cm_basic_init(const struct cm_config * const cfg)
> > /* Put all plls VCO registers back to reset value. */
> > writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE &
> > ~CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
> > - &clock_manager_base->main_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> > writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE &
> > ~CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
> > - &clock_manager_base->per_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> > writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE &
> > ~CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
> > - &clock_manager_base->sdr_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> > /*
> > * The clocks to the flash devices and the L4_MAIN clocks can
> > @@ -119,23 +116,26 @@ int cm_basic_init(const struct cm_config * const cfg)
> > * after exiting safe mode but before ungating the clocks.
> > */
> > writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
> > - &clock_manager_base->per_pll.src);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> > writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
> > - &clock_manager_base->main_pll.l4src);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
> >
> > /* read back for the required 5 us delay. */
> > - readl(&clock_manager_base->main_pll.vco);
> > - readl(&clock_manager_base->per_pll.vco);
> > - readl(&clock_manager_base->sdr_pll.vco);
> > + readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> > + readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> > + readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> >
> > /*
> > * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
> > * with numerator and denominator.
> > */
> > - writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);
> > - writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco);
> > - writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco);
> > + writel(cfg->main_vco_base,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> > + writel(cfg->peri_vco_base,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> > + writel(cfg->sdram_vco_base,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> > /*
> > * Time starts here. Must wait 7 us from
> > @@ -144,44 +144,53 @@ int cm_basic_init(const struct cm_config * const cfg)
> > end = timer_get_us() + 7;
> >
> > /* main mpu */
> > - writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
> > + writel(cfg->mpuclk, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
> >
> > /* altera group mpuclk */
> > - writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
> > + writel(cfg->altera_grp_mpuclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
> >
> > /* main main clock */
> > - writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
> > + writel(cfg->mainclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
> >
> > /* main for dbg */
> > - writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
> > + writel(cfg->dbgatclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGATCLK);
> >
> > /* main for cfgs2fuser0clk */
> > writel(cfg->cfg2fuser0clk,
> > - &clock_manager_base->main_pll.cfgs2fuser0clk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK);
> >
> > /* Peri emac0 50 MHz default to RMII */
> > - writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
> > + writel(cfg->emac0clk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC0CLK);
> >
> > /* Peri emac1 50 MHz default to RMII */
> > - writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
> > + writel(cfg->emac1clk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EMAC1CLK);
> >
> > /* Peri QSPI */
> > - writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
> > + writel(cfg->mainqspiclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
> >
> > - writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
> > + writel(cfg->perqspiclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERQSPICLK);
> >
> > /* Peri pernandsdmmcclk */
> > writel(cfg->mainnandsdmmcclk,
> > - &clock_manager_base->main_pll.mainnandsdmmcclk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
> >
> > writel(cfg->pernandsdmmcclk,
> > - &clock_manager_base->per_pll.pernandsdmmcclk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
> >
> > /* Peri perbaseclk */
> > - writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
> > + writel(cfg->perbaseclk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
> >
> > /* Peri s2fuser1clk */
> > - writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
> > + writel(cfg->s2fuser1clk,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_S2FUSER1CLK);
> >
> > /* 7 us must have elapsed before we can enable the VCO */
> > while (timer_get_us() < end)
> > @@ -190,101 +199,106 @@ int cm_basic_init(const struct cm_config * const cfg)
> > /* Enable vco */
> > /* main pll vco */
> > writel(cfg->main_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> > - &clock_manager_base->main_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> >
> > /* periferal pll */
> > writel(cfg->peri_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> > - &clock_manager_base->per_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> >
> > /* sdram pll vco */
> > writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> > - &clock_manager_base->sdr_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> > /* L3 MP and L3 SP */
> > - writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
> > + writel(cfg->maindiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
> >
> > - writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
> > + writel(cfg->dbgdiv, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_DBGDIV);
> >
> > - writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
> > + writel(cfg->tracediv,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_TRACEDIV);
> >
> > /* L4 MP, L4 SP, can0, and can1 */
> > - writel(cfg->perdiv, &clock_manager_base->per_pll.div);
> > + writel(cfg->perdiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_DIV);
> >
> > - writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
> > + writel(cfg->gpiodiv, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_GPIODIV);
> >
> > cm_wait_for_lock(LOCKED_MASK);
> >
> > /* write the sdram clock counters before toggling outreset all */
> > writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
> > - &clock_manager_base->sdr_pll.ddrdqsclk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
> >
> > writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
> > - &clock_manager_base->sdr_pll.ddr2xdqsclk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK);
> >
> > writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
> > - &clock_manager_base->sdr_pll.ddrdqclk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQCLK);
> >
> > writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
> > - &clock_manager_base->sdr_pll.s2fuser2clk);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK);
> >
> > /*
> > * after locking, but before taking out of bypass
> > * assert/deassert outresetall
> > */
> > - u32 mainvco = readl(&clock_manager_base->main_pll.vco);
> > + u32 mainvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> >
> > /* assert main outresetall */
> > writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
> > - &clock_manager_base->main_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> >
> > - u32 periphvco = readl(&clock_manager_base->per_pll.vco);
> > + u32 periphvco = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> >
> > /* assert pheriph outresetall */
> > writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
> > - &clock_manager_base->per_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> >
> > /* assert sdram outresetall */
> > - writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN|
> > - CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
> > - &clock_manager_base->sdr_pll.vco);
> > + writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN |
> > + CLKMGR_SDRPLLGRP_VCO_OUTRESETALL,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> > /* deassert main outresetall */
> > writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
> > - &clock_manager_base->main_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> >
> > /* deassert pheriph outresetall */
> > writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
> > - &clock_manager_base->per_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> >
> > /* deassert sdram outresetall */
> > writel(cfg->sdram_vco_base | CLKMGR_MAINPLLGRP_VCO_EN,
> > - &clock_manager_base->sdr_pll.vco);
> > + socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> >
> > /*
> > * now that we've toggled outreset all, all the clocks
> > * are aligned nicely; so we can change any phase.
> > */
> > ret = cm_write_with_phase(cfg->ddrdqsclk,
> > - &clock_manager_base->sdr_pll.ddrdqsclk,
> > + (const void *)(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_SDRPLL_DDRDQSCLK),
> > CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
> > if (ret)
> > return ret;
> >
> > /* SDRAM DDR2XDQSCLK */
> > ret = cm_write_with_phase(cfg->ddr2xdqsclk,
> > - &clock_manager_base->sdr_pll.ddr2xdqsclk,
> > + (const void *)(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK),
> > CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
> > if (ret)
> > return ret;
> >
> > ret = cm_write_with_phase(cfg->ddrdqclk,
> > - &clock_manager_base->sdr_pll.ddrdqclk,
> > + (const void *)(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_SDRPLL_DDRDQCLK),
> > CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
> > if (ret)
> > return ret;
> >
> > ret = cm_write_with_phase(cfg->s2fuser2clk,
> > - &clock_manager_base->sdr_pll.s2fuser2clk,
> > + (const void *)(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_SDRPLL_S2FUSER2CLK),
> > CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
> > if (ret)
> > return ret;
> > @@ -293,24 +307,26 @@ int cm_basic_init(const struct cm_config * const cfg)
> > cm_write_bypass(0);
> >
> > /* clear safe mode */
> > - cm_write_ctrl(readl(&clock_manager_base->ctrl) | CLKMGR_CTRL_SAFEMODE);
> > + cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_GEN5_CTRL) |
> > + CLKMGR_CTRL_SAFEMODE);
> >
> > /*
> > * now that safe mode is clear with clocks gated
> > * it safe to change the source mux for the flashes the the L4_MAIN
> > */
> > - writel(cfg->persrc, &clock_manager_base->per_pll.src);
> > - writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
> > + writel(cfg->persrc, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> > + writel(cfg->l4src, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
> >
> > /* Now ungate non-hw-managed clocks */
> > - writel(~0, &clock_manager_base->main_pll.en);
> > - writel(~0, &clock_manager_base->per_pll.en);
> > - writel(~0, &clock_manager_base->sdr_pll.en);
> > + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_EN);
> > + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_EN);
> > + writel(~0, socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_EN);
> >
> > /* Clear the loss of lock bits (write 1 to clear) */
> > - writel(CLKMGR_INTER_SDRPLLLOST_MASK | CLKMGR_INTER_PERPLLLOST_MASK |
> > - CLKMGR_INTER_MAINPLLLOST_MASK,
> > - &clock_manager_base->inter);
> > + writel(CLKMGR_INTER_SDRPLLLOST_MASK |
> > + CLKMGR_INTER_PERPLLLOST_MASK |
> > + CLKMGR_INTER_MAINPLLLOST_MASK,
> > + socfpga_clkmgr_base + CLKMGR_GEN5_INTER);
> >
> > return 0;
> > }
> > @@ -320,7 +336,7 @@ static unsigned int cm_get_main_vco_clk_hz(void)
> > u32 reg, clock;
> >
> > /* get the main VCO clock */
> > - reg = readl(&clock_manager_base->main_pll.vco);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_VCO);
> > clock = cm_get_osc_clk_hz(1);
> > clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
> > CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) + 1;
> > @@ -335,7 +351,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
> > u32 reg, clock = 0;
> >
> > /* identify PER PLL clock source */
> > - reg = readl(&clock_manager_base->per_pll.vco);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> > reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
> > CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET;
> > if (reg == CLKMGR_VCO_SSRC_EOSC1)
> > @@ -346,7 +362,7 @@ static unsigned int cm_get_per_vco_clk_hz(void)
> > clock = cm_get_f2s_per_ref_clk_hz();
> >
> > /* get the PER VCO clock */
> > - reg = readl(&clock_manager_base->per_pll.vco);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_VCO);
> > clock /= ((reg & CLKMGR_PERPLLGRP_VCO_DENOM_MASK) >>
> > CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) + 1;
> > clock *= ((reg & CLKMGR_PERPLLGRP_VCO_NUMER_MASK) >>
> > @@ -362,9 +378,9 @@ unsigned long cm_get_mpu_clk_hz(void)
> > clock = cm_get_main_vco_clk_hz();
> >
> > /* get the MPU clock */
> > - reg = readl(&clock_manager_base->altera.mpuclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MPUCLK);
> > clock /= (reg + 1);
> > - reg = readl(&clock_manager_base->main_pll.mpuclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MPUCLK);
> > clock /= (reg + 1);
> > return clock;
> > }
> > @@ -374,7 +390,7 @@ unsigned long cm_get_sdram_clk_hz(void)
> > u32 reg, clock = 0;
> >
> > /* identify SDRAM PLL clock source */
> > - reg = readl(&clock_manager_base->sdr_pll.vco);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> > reg = (reg & CLKMGR_SDRPLLGRP_VCO_SSRC_MASK) >>
> > CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET;
> > if (reg == CLKMGR_VCO_SSRC_EOSC1)
> > @@ -385,14 +401,14 @@ unsigned long cm_get_sdram_clk_hz(void)
> > clock = cm_get_f2s_sdr_ref_clk_hz();
> >
> > /* get the SDRAM VCO clock */
> > - reg = readl(&clock_manager_base->sdr_pll.vco);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_VCO);
> > clock /= ((reg & CLKMGR_SDRPLLGRP_VCO_DENOM_MASK) >>
> > CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) + 1;
> > clock *= ((reg & CLKMGR_SDRPLLGRP_VCO_NUMER_MASK) >>
> > CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) + 1;
> >
> > /* get the SDRAM (DDR_DQS) clock */
> > - reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_SDRPLL_DDRDQSCLK);
> > reg = (reg & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK) >>
> > CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET;
> > clock /= (reg + 1);
> > @@ -405,7 +421,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > u32 reg, clock = 0;
> >
> > /* identify the source of L4 SP clock */
> > - reg = readl(&clock_manager_base->main_pll.l4src);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_L4SRC);
> > reg = (reg & CLKMGR_MAINPLLGRP_L4SRC_L4SP) >>
> > CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET;
> >
> > @@ -413,20 +429,21 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > clock = cm_get_main_vco_clk_hz();
> >
> > /* get the clock prior L4 SP divider (main clk) */
> > - reg = readl(&clock_manager_base->altera.mainclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_ALTR_MAINCLK);
> > clock /= (reg + 1);
> > - reg = readl(&clock_manager_base->main_pll.mainclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINCLK);
> > clock /= (reg + 1);
> > } else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
> > clock = cm_get_per_vco_clk_hz();
> >
> > /* get the clock prior L4 SP divider (periph_base_clk) */
> > - reg = readl(&clock_manager_base->per_pll.perbaseclk);
> > + reg = readl(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_PERPLL_PERBASECLK);
> > clock /= (reg + 1);
> > }
> >
> > /* get the L4 SP clock which supplied to UART */
> > - reg = readl(&clock_manager_base->main_pll.maindiv);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_MAINPLL_MAINDIV);
> > reg = (reg & CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK) >>
> > CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET;
> > clock = clock / (1 << reg);
> > @@ -439,7 +456,7 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
> > u32 reg, clock = 0;
> >
> > /* identify the source of MMC clock */
> > - reg = readl(&clock_manager_base->per_pll.src);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> > reg = (reg & CLKMGR_PERPLLGRP_SRC_SDMMC_MASK) >>
> > CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET;
> >
> > @@ -449,13 +466,15 @@ unsigned int cm_get_mmc_controller_clk_hz(void)
> > clock = cm_get_main_vco_clk_hz();
> >
> > /* get the SDMMC clock */
> > - reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
> > + reg = readl(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK);
> > clock /= (reg + 1);
> > } else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
> > clock = cm_get_per_vco_clk_hz();
> >
> > /* get the SDMMC clock */
> > - reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
> > + reg = readl(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK);
> > clock /= (reg + 1);
> > }
> >
> > @@ -469,7 +488,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
> > u32 reg, clock = 0;
> >
> > /* identify the source of QSPI clock */
> > - reg = readl(&clock_manager_base->per_pll.src);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_SRC);
> > reg = (reg & CLKMGR_PERPLLGRP_SRC_QSPI_MASK) >>
> > CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET;
> >
> > @@ -479,13 +498,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void)
> > clock = cm_get_main_vco_clk_hz();
> >
> > /* get the qspi clock */
> > - reg = readl(&clock_manager_base->main_pll.mainqspiclk);
> > + reg = readl(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_MAINPLL_MAINQSPICLK);
> > clock /= (reg + 1);
> > } else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
> > clock = cm_get_per_vco_clk_hz();
> >
> > /* get the qspi clock */
> > - reg = readl(&clock_manager_base->per_pll.perqspiclk);
> > + reg = readl(socfpga_clkmgr_base +
> > + CLKMGR_GEN5_PERPLL_PERQSPICLK);
> > clock /= (reg + 1);
> > }
> >
> > @@ -499,7 +520,7 @@ unsigned int cm_get_spi_controller_clk_hz(void)
> > clock = cm_get_per_vco_clk_hz();
> >
> > /* get the clock prior L4 SP divider (periph_base_clk) */
> > - reg = readl(&clock_manager_base->per_pll.perbaseclk);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_GEN5_PERPLL_PERBASECLK);
> > clock /= (reg + 1);
> >
> > return clock;
> > diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
> > index 6cbf07ac6f..c6269701f0 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_s10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_s10.c
> > @@ -12,29 +12,26 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_clock_manager *clock_manager_base =
> > - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> > -
> > /*
> > * function to write the bypass register which requires a poll of the
> > * busy bit
> > */
> > static void cm_write_bypass_mainpll(u32 val)
> > {
> > - writel(val, &clock_manager_base->main_pll.bypass);
> > + writel(val, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_BYPASS);
> > cm_wait_for_fsm();
> > }
> >
> > static void cm_write_bypass_perpll(u32 val)
> > {
> > - writel(val, &clock_manager_base->per_pll.bypass);
> > + writel(val, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_BYPASS);
> > cm_wait_for_fsm();
> > }
> >
> > /* function to write the ctrl register which requires a poll of the busy bit */
> > static void cm_write_ctrl(u32 val)
> > {
> > - writel(val, &clock_manager_base->ctrl);
> > + writel(val, socfpga_clkmgr_base + CLKMGR_S10_CTRL);
> > cm_wait_for_fsm();
> > }
> >
> > @@ -66,12 +63,17 @@ void cm_basic_init(const struct cm_config * const cfg)
> >
> > writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> > ~CLKMGR_PLLGLOB_RST_MASK),
> > - &clock_manager_base->main_pll.pllglob);
> > - writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
> > - writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
> > - writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
> > - writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
> > - writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
> > + writel(cfg->main_pll_fdbck,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
> > + writel(vcocalib,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_VCOCALIB);
> > + writel(cfg->main_pll_pllc0,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC0);
> > + writel(cfg->main_pll_pllc1,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLC1);
> > + writel(cfg->main_pll_nocdiv,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCDIV);
> >
> > /* setup peripheral PLL dividers */
> > /* calculate the vcocalib value */
> > @@ -88,18 +90,23 @@ void cm_basic_init(const struct cm_config * const cfg)
> >
> > writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
> > ~CLKMGR_PLLGLOB_RST_MASK),
> > - &clock_manager_base->per_pll.pllglob);
> > - writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
> > - writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
> > - writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
> > - writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
> > - writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
> > - writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
> > + writel(cfg->per_pll_fdbck,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
> > + writel(vcocalib, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_VCOCALIB);
> > + writel(cfg->per_pll_pllc0,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC0);
> > + writel(cfg->per_pll_pllc1,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1);
> > + writel(cfg->per_pll_emacctl,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EMACCTL);
> > + writel(cfg->per_pll_gpiodiv,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_GPIODIV);
> >
> > /* Take both PLL out of reset and power up */
> > - setbits_le32(&clock_manager_base->main_pll.pllglob,
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB,
> > CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> > - setbits_le32(&clock_manager_base->per_pll.pllglob,
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB,
> > CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
> >
> > #define LOCKED_MASK \
> > @@ -113,66 +120,85 @@ void cm_basic_init(const struct cm_config * const cfg)
> > * only take effect upon value change, we shall set a maximum value as
> > * default value.
> > */
> > - writel(0xff, &clock_manager_base->main_pll.mpuclk);
> > - writel(0xff, &clock_manager_base->main_pll.nocclk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr2clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr3clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr4clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr5clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr6clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr7clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr8clk);
> > - writel(0xff, &clock_manager_base->main_pll.cntr9clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr2clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr3clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr4clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr5clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr6clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr7clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr8clk);
> > - writel(0xff, &clock_manager_base->per_pll.cntr9clk);
> > -
> > - writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
> > - writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
> > - writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
> > - writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
> > - writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
> > - writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
> > - writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
> > - writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
> > - writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
> > - writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
> > - writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
> > - writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
> > - writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
> > - writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
> > - writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
> > - writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
> > - writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
> > - writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
> > + writel(0xff, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
> > +
> > + writel(cfg->main_pll_mpuclk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK);
> > + writel(cfg->main_pll_nocclk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
> > + writel(cfg->main_pll_cntr2clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR2CLK);
> > + writel(cfg->main_pll_cntr3clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR3CLK);
> > + writel(cfg->main_pll_cntr4clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR4CLK);
> > + writel(cfg->main_pll_cntr5clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR5CLK);
> > + writel(cfg->main_pll_cntr6clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR6CLK);
> > + writel(cfg->main_pll_cntr7clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR7CLK);
> > + writel(cfg->main_pll_cntr8clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR8CLK);
> > + writel(cfg->main_pll_cntr9clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_CNTR9CLK);
> > + writel(cfg->per_pll_cntr2clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR2CLK);
> > + writel(cfg->per_pll_cntr3clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR3CLK);
> > + writel(cfg->per_pll_cntr4clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR4CLK);
> > + writel(cfg->per_pll_cntr5clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR5CLK);
> > + writel(cfg->per_pll_cntr6clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
> > + writel(cfg->per_pll_cntr7clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR7CLK);
> > + writel(cfg->per_pll_cntr8clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR8CLK);
> > + writel(cfg->per_pll_cntr9clk,
> > + socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR9CLK);
> >
> > /* Take all PLLs out of bypass */
> > cm_write_bypass_mainpll(0);
> > cm_write_bypass_perpll(0);
> >
> > /* clear safe mode / out of boot mode */
> > - cm_write_ctrl(readl(&clock_manager_base->ctrl)
> > - & ~(CLKMGR_CTRL_SAFEMODE));
> > + cm_write_ctrl(readl(socfpga_clkmgr_base + CLKMGR_S10_CTRL) &
> > + ~(CLKMGR_CTRL_SAFEMODE));
> >
> > /* Now ungate non-hw-managed clocks */
> > - writel(~0, &clock_manager_base->main_pll.en);
> > - writel(~0, &clock_manager_base->per_pll.en);
> > + writel(~0, socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_EN);
> > + writel(~0, socfpga_clkmgr_base + CLKMGR_S10_PERPLL_EN);
> >
> > /* Clear the loss of lock bits (write 1 to clear) */
> > - writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,
> > - &clock_manager_base->intrclr);
> > + writel(CLKMGR_INTER_PERPLLLOST_MASK |
> > + CLKMGR_INTER_MAINPLLLOST_MASK,
> > + socfpga_clkmgr_base + CLKMGR_S10_INTRCLR);
> > }
> >
> > static unsigned long cm_get_main_vco_clk_hz(void)
> > {
> > unsigned long fref, refdiv, mdiv, reg, vco;
> >
> > - reg = readl(&clock_manager_base->main_pll.pllglob);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_PLLGLOB);
> >
> > fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> > CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> > @@ -191,7 +217,7 @@ static unsigned long cm_get_main_vco_clk_hz(void)
> > refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> > CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> >
> > - reg = readl(&clock_manager_base->main_pll.fdbck);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_FDBCK);
> > mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> >
> > vco = fref / refdiv;
> > @@ -203,7 +229,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
> > {
> > unsigned long fref, refdiv, mdiv, reg, vco;
> >
> > - reg = readl(&clock_manager_base->per_pll.pllglob);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLGLOB);
> >
> > fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
> > CLKMGR_PLLGLOB_VCO_PSRC_MASK;
> > @@ -222,7 +248,7 @@ static unsigned long cm_get_per_vco_clk_hz(void)
> > refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
> > CLKMGR_PLLGLOB_REFCLKDIV_MASK;
> >
> > - reg = readl(&clock_manager_base->per_pll.fdbck);
> > + reg = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_FDBCK);
> > mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
> >
> > vco = fref / refdiv;
> > @@ -232,20 +258,23 @@ static unsigned long cm_get_per_vco_clk_hz(void)
> >
> > unsigned long cm_get_mpu_clk_hz(void)
> > {
> > - unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
> > + unsigned long clock = readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_MPUCLK);
> >
> > clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> >
> > switch (clock) {
> > case CLKMGR_CLKSRC_MAIN:
> > clock = cm_get_main_vco_clk_hz();
> > - clock /= (readl(&clock_manager_base->main_pll.pllc0) &
> > + clock /= (readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_PLLC0) &
> > CLKMGR_PLLC0_DIV_MASK);
> > break;
> >
> > case CLKMGR_CLKSRC_PER:
> > clock = cm_get_per_vco_clk_hz();
> > - clock /= (readl(&clock_manager_base->per_pll.pllc0) &
> > + clock /= (readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_PERPLL_PLLC0) &
> > CLKMGR_CLKCNT_MSK);
> > break;
> >
> > @@ -262,27 +291,28 @@ unsigned long cm_get_mpu_clk_hz(void)
> > break;
> > }
> >
> > - clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
> > - CLKMGR_CLKCNT_MSK);
> > + clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_MPUCLK) &
> > + CLKMGR_CLKCNT_MSK);
> > return clock;
> > }
> >
> > unsigned int cm_get_l3_main_clk_hz(void)
> > {
> > - u32 clock = readl(&clock_manager_base->main_pll.nocclk);
> > + u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK);
> >
> > clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> >
> > switch (clock) {
> > case CLKMGR_CLKSRC_MAIN:
> > clock = cm_get_main_vco_clk_hz();
> > - clock /= (readl(&clock_manager_base->main_pll.pllc1) &
> > + clock /= (readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_PLLC1) &
> > CLKMGR_PLLC0_DIV_MASK);
> > break;
> >
> > case CLKMGR_CLKSRC_PER:
> > clock = cm_get_per_vco_clk_hz();
> > - clock /= (readl(&clock_manager_base->per_pll.pllc1) &
> > + clock /= (readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_PLLC1) &
> > CLKMGR_CLKCNT_MSK);
> > break;
> >
> > @@ -299,28 +329,30 @@ unsigned int cm_get_l3_main_clk_hz(void)
> > break;
> > }
> >
> > - clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
> > + clock /= 1 + (readl(socfpga_clkmgr_base + CLKMGR_S10_MAINPLL_NOCCLK) &
> > CLKMGR_CLKCNT_MSK);
> > return clock;
> > }
> >
> > unsigned int cm_get_mmc_controller_clk_hz(void)
> > {
> > - u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);
> > + u32 clock = readl(socfpga_clkmgr_base + CLKMGR_S10_PERPLL_CNTR6CLK);
> >
> > clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
> >
> > switch (clock) {
> > case CLKMGR_CLKSRC_MAIN:
> > clock = cm_get_l3_main_clk_hz();
> > - clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
> > - CLKMGR_CLKCNT_MSK);
> > + clock /= 1 + (readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_CNTR6CLK) &
> > + CLKMGR_CLKCNT_MSK);
> > break;
> >
> > case CLKMGR_CLKSRC_PER:
> > clock = cm_get_l3_main_clk_hz();
> > - clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
> > - CLKMGR_CLKCNT_MSK);
> > + clock /= 1 + (readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_PERPLL_CNTR6CLK) &
> > + CLKMGR_CLKCNT_MSK);
> > break;
> >
> > case CLKMGR_CLKSRC_OSC1:
> > @@ -342,8 +374,9 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> > {
> > u32 clock = cm_get_l3_main_clk_hz();
> >
> > - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
> > - CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> > + clock /= (1 << ((readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_NOCDIV) >>
> > + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
> > return clock;
> > }
> >
> > @@ -356,8 +389,9 @@ unsigned int cm_get_spi_controller_clk_hz(void)
> > {
> > u32 clock = cm_get_l3_main_clk_hz();
> >
> > - clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
> > - CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
> > + clock /= (1 << ((readl(socfpga_clkmgr_base +
> > + CLKMGR_S10_MAINPLL_NOCDIV) >>
> > + CLKMGR_NOCDIV_L4MAIN_OFFSET) & CLKMGR_CLKCNT_MSK));
> > return clock;
> > }
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > index dd80e3a767..4f9d10dd78 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> > @@ -6,6 +6,8 @@
> > #ifndef _CLOCK_MANAGER_H_
> > #define _CLOCK_MANAGER_H_
> >
> > +extern phys_addr_t socfpga_clkmgr_base;
> > +
> > #ifndef __ASSEMBLER__
> > void cm_wait_for_lock(u32 mask);
> > int cm_wait_for_fsm(void);
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> > index de8c22540f..52b579e6e1 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
> > @@ -8,86 +8,57 @@
> >
> > #ifndef __ASSEMBLER__
> >
> > -struct socfpga_clock_manager_main_pll {
> > - u32 vco0;
> > - u32 vco1;
> > - u32 en;
> > - u32 ens;
> > - u32 enr;
> > - u32 bypass;
> > - u32 bypasss;
> > - u32 bypassr;
> > - u32 mpuclk;
> > - u32 nocclk;
> > - u32 cntr2clk;
> > - u32 cntr3clk;
> > - u32 cntr4clk;
> > - u32 cntr5clk;
> > - u32 cntr6clk;
> > - u32 cntr7clk;
> > - u32 cntr8clk;
> > - u32 cntr9clk;
> > - u32 pad_0x48_0x5b[5];
> > - u32 cntr15clk;
> > - u32 outrst;
> > - u32 outrststat;
> > - u32 nocdiv;
> > - u32 pad_0x6c_0x80[5];
> > -};
> > -
> > -struct socfpga_clock_manager_per_pll {
> > - u32 vco0;
> > - u32 vco1;
> > - u32 en;
> > - u32 ens;
> > - u32 enr;
> > - u32 bypass;
> > - u32 bypasss;
> > - u32 bypassr;
> > - u32 pad_0x20_0x27[2];
> > - u32 cntr2clk;
> > - u32 cntr3clk;
> > - u32 cntr4clk;
> > - u32 cntr5clk;
> > - u32 cntr6clk;
> > - u32 cntr7clk;
> > - u32 cntr8clk;
> > - u32 cntr9clk;
> > - u32 pad_0x48_0x5f[6];
> > - u32 outrst;
> > - u32 outrststat;
> > - u32 emacctl;
> > - u32 gpiodiv;
> > - u32 pad_0x70_0x80[4];
> > -};
> > -
> > -struct socfpga_clock_manager_altera {
> > - u32 mpuclk;
> > - u32 nocclk;
> > - u32 mainmisc0;
> > - u32 mainmisc1;
> > - u32 perimisc0;
> > - u32 perimisc1;
> > -};
> > -
> > -struct socfpga_clock_manager {
> > - /* clkmgr */
> > - u32 ctrl;
> > - u32 intr;
> > - u32 intrs;
> > - u32 intrr;
> > - u32 intren;
> > - u32 intrens;
> > - u32 intrenr;
> > - u32 stat;
> > - u32 testioctrl;
> > - u32 _pad_0x24_0x40[7];
> > - /* mainpllgrp */
> > - struct socfpga_clock_manager_main_pll main_pll;
> > - /* perpllgrp */
> > - struct socfpga_clock_manager_per_pll per_pll;
> > - struct socfpga_clock_manager_altera altera;
> > -};
> > +/* Clock manager group */
> > +#define CLKMGR_A10_CTRL 0
> > +#define CLKMGR_A10_INTR 4
> > +#define CLKMGR_A10_STAT 0x1c
> > +/* MainPLL group */
> > +#define CLKMGR_A10_MAINPLL_VCO0 0x40
> > +#define CLKMGR_A10_MAINPLL_VCO1 0x44
> > +#define CLKMGR_A10_MAINPLL_EN 0x48
> > +#define CLKMGR_A10_MAINPLL_ENS 0x4c
> > +#define CLKMGR_A10_MAINPLL_ENR 0x50
> > +#define CLKMGR_A10_MAINPLL_BYPASS 0x54
> > +#define CLKMGR_A10_MAINPLL_BYPASSS 0x58
> > +#define CLKMGR_A10_MAINPLL_BYPASSR 0x5c
> > +#define CLKMGR_A10_MAINPLL_MPUCLK 0x60
> > +#define CLKMGR_A10_MAINPLL_NOCCLK 0x64
> > +#define CLKMGR_A10_MAINPLL_CNTR2CLK 0x68
> > +#define CLKMGR_A10_MAINPLL_CNTR3CLK 0x6c
> > +#define CLKMGR_A10_MAINPLL_CNTR4CLK 0x70
> > +#define CLKMGR_A10_MAINPLL_CNTR5CLK 0x74
> > +#define CLKMGR_A10_MAINPLL_CNTR6CLK 0x78
> > +#define CLKMGR_A10_MAINPLL_CNTR7CLK 0x7c
> > +#define CLKMGR_A10_MAINPLL_CNTR8CLK 0x80
> > +#define CLKMGR_A10_MAINPLL_CNTR9CLK 0x84
> > +#define CLKMGR_A10_MAINPLL_CNTR15CLK 0x9c
> > +#define CLKMGR_A10_MAINPLL_NOCDIV 0xa8
> > +/* Peripheral PLL group */
> > +#define CLKMGR_A10_PERPLL_VCO0 0xc0
> > +#define CLKMGR_A10_PERPLL_VCO1 0xc4
> > +#define CLKMGR_A10_PERPLL_EN 0xc8
> > +#define CLKMGR_A10_PERPLL_ENS 0xcc
> > +#define CLKMGR_A10_PERPLL_ENR 0xd0
> > +#define CLKMGR_A10_PERPLL_BYPASS 0xd4
> > +#define CLKMGR_A10_PERPLL_BYPASSS 0xd8
> > +#define CLKMGR_A10_PERPLL_BYPASSR 0xdc
> > +#define CLKMGR_A10_PERPLL_CNTR2CLK 0xe8
> > +#define CLKMGR_A10_PERPLL_CNTR3CLK 0xec
> > +#define CLKMGR_A10_PERPLL_CNTR4CLK 0xf0
> > +#define CLKMGR_A10_PERPLL_CNTR5CLK 0xf4
> > +#define CLKMGR_A10_PERPLL_CNTR6CLK 0xf8
> > +#define CLKMGR_A10_PERPLL_CNTR7CLK 0xfc
> > +#define CLKMGR_A10_PERPLL_CNTR8CLK 0x100
> > +#define CLKMGR_A10_PERPLL_CNTR9CLK 0x104
> > +#define CLKMGR_A10_PERPLL_EMACCTL 0x128
> > +#define CLKMGR_A10_PERPLL_GPIOFIV 0x12c
> > +/* Altera group */
> > +#define CLKMGR_A10_ALTR_MPUCLK 0x140
> > +#define CLKMGR_A10_ALTR_NOCCLK 0x144
> > +
> > +#define CLKMGR_STAT CLKMGR_A10_STAT
> > +#define CLKMGR_INTER CLKMGR_A10_INTER
> > +#define CLKMGR_PERPLL_EN CLKMGR_A10_PERPLL_EN
> >
> > #ifdef CONFIG_SPL_BUILD
> > int cm_basic_init(const void *blob);
> > @@ -100,8 +71,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >
> > #endif /* __ASSEMBLER__ */
> >
> > -#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
> > -#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
> > #define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
> > CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> > index 5bedf28cf1..caa1231c69 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
> > @@ -45,71 +45,53 @@ struct cm_config {
> > u32 altera_grp_mpuclk;
> > };
> >
> > -struct socfpga_clock_manager_main_pll {
> > - u32 vco;
> > - u32 misc;
> > - u32 mpuclk;
> > - u32 mainclk;
> > - u32 dbgatclk;
> > - u32 mainqspiclk;
> > - u32 mainnandsdmmcclk;
> > - u32 cfgs2fuser0clk;
> > - u32 en;
> > - u32 maindiv;
> > - u32 dbgdiv;
> > - u32 tracediv;
> > - u32 l4src;
> > - u32 stat;
> > - u32 _pad_0x38_0x40[2];
> > -};
> > -
> > -struct socfpga_clock_manager_per_pll {
> > - u32 vco;
> > - u32 misc;
> > - u32 emac0clk;
> > - u32 emac1clk;
> > - u32 perqspiclk;
> > - u32 pernandsdmmcclk;
> > - u32 perbaseclk;
> > - u32 s2fuser1clk;
> > - u32 en;
> > - u32 div;
> > - u32 gpiodiv;
> > - u32 src;
> > - u32 stat;
> > - u32 _pad_0x34_0x40[3];
> > -};
> > -
> > -struct socfpga_clock_manager_sdr_pll {
> > - u32 vco;
> > - u32 ctrl;
> > - u32 ddrdqsclk;
> > - u32 ddr2xdqsclk;
> > - u32 ddrdqclk;
> > - u32 s2fuser2clk;
> > - u32 en;
> > - u32 stat;
> > -};
> > -
> > -struct socfpga_clock_manager_altera {
> > - u32 mpuclk;
> > - u32 mainclk;
> > -};
> > -
> > -struct socfpga_clock_manager {
> > - u32 ctrl;
> > - u32 bypass;
> > - u32 inter;
> > - u32 intren;
> > - u32 dbctrl;
> > - u32 stat;
> > - u32 _pad_0x18_0x3f[10];
> > - struct socfpga_clock_manager_main_pll main_pll;
> > - struct socfpga_clock_manager_per_pll per_pll;
> > - struct socfpga_clock_manager_sdr_pll sdr_pll;
> > - struct socfpga_clock_manager_altera altera;
> > - u32 _pad_0xe8_0x200[70];
> > -};
> > +/* Clock manager group */
> > +#define CLKMGR_GEN5_CTRL 0
> > +#define CLKMGR_GEN5_BYPASS 4
> > +#define CLKMGR_GEN5_INTER 8
> > +#define CLKMGR_GEN5_STAT 0x14
> > +/* MainPLL group */
> > +#define CLKMGR_GEN5_MAINPLL_VCO 0x40
> > +#define CLKMGR_GEN5_MAINPLL_MISC 0x44
> > +#define CLKMGR_GEN5_MAINPLL_MPUCLK 0x48
> > +#define CLKMGR_GEN5_MAINPLL_MAINCLK 0x4c
> > +#define CLKMGR_GEN5_MAINPLL_DBGATCLK 0x50
> > +#define CLKMGR_GEN5_MAINPLL_MAINQSPICLK 0x54
> > +#define CLKMGR_GEN5_MAINPLL_MAINNANDSDMMCCLK 0x58
> > +#define CLKMGR_GEN5_MAINPLL_CFGS2FUSER0CLK 0x5c
> > +#define CLKMGR_GEN5_MAINPLL_EN 0x60
> > +#define CLKMGR_GEN5_MAINPLL_MAINDIV 0x64
> > +#define CLKMGR_GEN5_MAINPLL_DBGDIV 0x68
> > +#define CLKMGR_GEN5_MAINPLL_TRACEDIV 0x6c
> > +#define CLKMGR_GEN5_MAINPLL_L4SRC 0x70
> > +/* Peripheral PLL group */
> > +#define CLKMGR_GEN5_PERPLL_VCO 0x80
> > +#define CLKMGR_GEN5_PERPLL_MISC 0x84
> > +#define CLKMGR_GEN5_PERPLL_EMAC0CLK 0x88
> > +#define CLKMGR_GEN5_PERPLL_EMAC1CLK 0x8c
> > +#define CLKMGR_GEN5_PERPLL_PERQSPICLK 0x90
> > +#define CLKMGR_GEN5_PERPLL_PERNANDSDMMCCLK 0x94
> > +#define CLKMGR_GEN5_PERPLL_PERBASECLK 0x98
> > +#define CLKMGR_GEN5_PERPLL_S2FUSER1CLK 0x9c
> > +#define CLKMGR_GEN5_PERPLL_EN 0xa0
> > +#define CLKMGR_GEN5_PERPLL_DIV 0xa4
> > +#define CLKMGR_GEN5_PERPLL_GPIODIV 0xa8
> > +#define CLKMGR_GEN5_PERPLL_SRC 0xac
> > +/* SDRAM PLL group */
> > +#define CLKMGR_GEN5_SDRPLL_VCO 0xc0
> > +#define CLKMGR_GEN5_SDRPLL_CTRL 0xc4
> > +#define CLKMGR_GEN5_SDRPLL_DDRDQSCLK 0xc8
> > +#define CLKMGR_GEN5_SDRPLL_DDR2XDQSCLK 0xcc
> > +#define CLKMGR_GEN5_SDRPLL_DDRDQCLK 0xd0
> > +#define CLKMGR_GEN5_SDRPLL_S2FUSER2CLK 0xd4
> > +#define CLKMGR_GEN5_SDRPLL_EN 0xd8
> > +/* Altera group */
> > +#define CLKMGR_GEN5_ALTR_MPUCLK 0xe0
> > +#define CLKMGR_GEN5_ALTR_MAINCLK 0xe4
> > +
> > +#define CLKMGR_STAT CLKMGR_GEN5_STAT
> > +#define CLKMGR_INTER CLKMGR_GEN5_INTER
> > +#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
> >
> > /* Clock speed accessors */
> > unsigned long cm_get_mpu_clk_hz(void);
> > diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > index 24b20de011..fa0ba26f09 100644
> > --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
> > @@ -69,75 +69,54 @@ struct cm_config {
> >
> > void cm_basic_init(const struct cm_config * const cfg);
> >
> > -struct socfpga_clock_manager_main_pll {
> > - u32 en;
> > - u32 ens;
> > - u32 enr;
> > - u32 bypass;
> > - u32 bypasss;
> > - u32 bypassr;
> > - u32 mpuclk;
> > - u32 nocclk;
> > - u32 cntr2clk;
> > - u32 cntr3clk;
> > - u32 cntr4clk;
> > - u32 cntr5clk;
> > - u32 cntr6clk;
> > - u32 cntr7clk;
> > - u32 cntr8clk;
> > - u32 cntr9clk;
> > - u32 nocdiv;
> > - u32 pllglob;
> > - u32 fdbck;
> > - u32 mem;
> > - u32 memstat;
> > - u32 pllc0;
> > - u32 pllc1;
> > - u32 vcocalib;
> > - u32 _pad_0x90_0xA0[5];
> > -};
> > -
> > -struct socfpga_clock_manager_per_pll {
> > - u32 en;
> > - u32 ens;
> > - u32 enr;
> > - u32 bypass;
> > - u32 bypasss;
> > - u32 bypassr;
> > - u32 cntr2clk;
> > - u32 cntr3clk;
> > - u32 cntr4clk;
> > - u32 cntr5clk;
> > - u32 cntr6clk;
> > - u32 cntr7clk;
> > - u32 cntr8clk;
> > - u32 cntr9clk;
> > - u32 emacctl;
> > - u32 gpiodiv;
> > - u32 pllglob;
> > - u32 fdbck;
> > - u32 mem;
> > - u32 memstat;
> > - u32 pllc0;
> > - u32 pllc1;
> > - u32 vcocalib;
> > - u32 _pad_0x100_0x124[10];
> > -};
> > +/* Control status */
> > +#define CLKMGR_S10_CTRL 0
> > +#define CLKMGR_S10_STAT 4
> > +#define CLKMGR_S10_INTRCLR 0x14
> > +/* Mainpll group */
> > +#define CLKMGR_S10_MAINPLL_EN 0x30
> > +#define CLKMGR_S10_MAINPLL_BYPASS 0x3c
> > +#define CLKMGR_S10_MAINPLL_MPUCLK 0x48
> > +#define CLKMGR_S10_MAINPLL_NOCCLK 0x4c
> > +#define CLKMGR_S10_MAINPLL_CNTR2CLK 0x50
> > +#define CLKMGR_S10_MAINPLL_CNTR3CLK 0x54
> > +#define CLKMGR_S10_MAINPLL_CNTR4CLK 0x58
> > +#define CLKMGR_S10_MAINPLL_CNTR5CLK 0x5c
> > +#define CLKMGR_S10_MAINPLL_CNTR6CLK 0x60
> > +#define CLKMGR_S10_MAINPLL_CNTR7CLK 0x64
> > +#define CLKMGR_S10_MAINPLL_CNTR8CLK 0x68
> > +#define CLKMGR_S10_MAINPLL_CNTR9CLK 0x6c
> > +#define CLKMGR_S10_MAINPLL_NOCDIV 0x70
> > +#define CLKMGR_S10_MAINPLL_PLLGLOB 0x74
> > +#define CLKMGR_S10_MAINPLL_FDBCK 0x78
> > +#define CLKMGR_S10_MAINPLL_MEMSTAT 0x80
> > +#define CLKMGR_S10_MAINPLL_PLLC0 0x84
> > +#define CLKMGR_S10_MAINPLL_PLLC1 0x88
> > +#define CLKMGR_S10_MAINPLL_VCOCALIB 0x8c
> > +/* Periphpll group */
> > +#define CLKMGR_S10_PERPLL_EN 0xa4
> > +#define CLKMGR_S10_PERPLL_BYPASS 0xac
> > +#define CLKMGR_S10_PERPLL_CNTR2CLK 0xbc
> > +#define CLKMGR_S10_PERPLL_CNTR3CLK 0xc0
> > +#define CLKMGR_S10_PERPLL_CNTR4CLK 0xc4
> > +#define CLKMGR_S10_PERPLL_CNTR5CLK 0xc8
> > +#define CLKMGR_S10_PERPLL_CNTR6CLK 0xcc
> > +#define CLKMGR_S10_PERPLL_CNTR7CLK 0xd0
> > +#define CLKMGR_S10_PERPLL_CNTR8CLK 0xd4
> > +#define CLKMGR_S10_PERPLL_CNTR9CLK 0xd8
> > +#define CLKMGR_S10_PERPLL_EMACCTL 0xdc
> > +#define CLKMGR_S10_PERPLL_GPIODIV 0xe0
> > +#define CLKMGR_S10_PERPLL_PLLGLOB 0xe4
> > +#define CLKMGR_S10_PERPLL_FDBCK 0xe8
> > +#define CLKMGR_S10_PERPLL_MEMSTAT 0xf0
> > +#define CLKMGR_S10_PERPLL_PLLC0 0xf4
> > +#define CLKMGR_S10_PERPLL_PLLC1 0xf8
> > +#define CLKMGR_S10_PERPLL_VCOCALIB 0xfc
> > +
> > +#define CLKMGR_STAT CLKMGR_S10_STAT
> > +#define CLKMGR_INTER CLKMGR_S10_INTER
> > +#define CLKMGR_PERPLL_EN CLKMGR_S10_PERPLL_EN
> >
> > -struct socfpga_clock_manager {
> > - u32 ctrl;
> > - u32 stat;
> > - u32 testioctrl;
> > - u32 intrgen;
> > - u32 intrmsk;
> > - u32 intrclr;
> > - u32 intrsts;
> > - u32 intrstk;
> > - u32 intrraw;
> > - u32 _pad_0x24_0x2c[3];
> > - struct socfpga_clock_manager_main_pll main_pll;
> > - struct socfpga_clock_manager_per_pll per_pll;
> > -};
> >
> > #define CLKMGR_CTRL_SAFEMODE BIT(0)
> > #define CLKMGR_BYPASS_MAINPLL_ALL 0x00000007
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > index fcc53b6fbc..dffd1b2e41 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -22,6 +22,7 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +phys_addr_t socfpga_clkmgr_base __section(".data");
> > phys_addr_t socfpga_rstmgr_base __section(".data");
> > phys_addr_t socfpga_sysmgr_base __section(".data");
> >
> > @@ -238,4 +239,8 @@ void socfpga_get_manager_addr(void)
> > socfpga_sysmgr_base = socfpga_get_base_addr("altr,sys-mgr");
> > if (!socfpga_sysmgr_base)
> > hang();
> > +
> > + socfpga_clkmgr_base = socfpga_get_base_addr("altr,clk-mgr");
> > + if (!socfpga_clkmgr_base)
> > + hang();
> > }
> > diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
> > index bdcd568d60..aefcae8fb6 100644
> > --- a/drivers/mmc/socfpga_dw_mmc.c
> > +++ b/drivers/mmc/socfpga_dw_mmc.c
> > @@ -18,9 +18,6 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > -static const struct socfpga_clock_manager *clock_manager_base =
> > - (void *)SOCFPGA_CLKMGR_ADDRESS;
> > -
> > struct socfpga_dwmci_plat {
> > struct mmc_config cfg;
> > struct mmc mmc;
> > @@ -54,8 +51,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> > ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
> >
> > /* Disable SDMMC clock. */
> > - clrbits_le32(&clock_manager_base->per_pll.en,
> > - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> > + clrbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
> > + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> >
> > debug("%s: drvsel %d smplsel %d\n", __func__,
> > priv->drvsel, priv->smplsel);
> > @@ -65,8 +62,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
> > readl(socfpga_sysmgr_base + SYSMGR_SDMMC));
> >
> > /* Enable SDMMC clock */
> > - setbits_le32(&clock_manager_base->per_pll.en,
> > - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> > + setbits_le32(socfpga_clkmgr_base + CLKMGR_PERPLL_EN,
> > + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
> > }
> >
> > static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
> > --
> > 2.19.0
> >
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-09-10 8:37 [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines Ley Foon Tan
` (3 preceding siblings ...)
2019-09-10 8:38 ` [U-Boot] [PATCH v2 4/4] arm: socfpga: Convert clock " Ley Foon Tan
@ 2019-09-17 22:33 ` Dinh Nguyen
2019-09-18 2:32 ` Ley Foon Tan
4 siblings, 1 reply; 21+ messages in thread
From: Dinh Nguyen @ 2019-09-17 22:33 UTC (permalink / raw)
To: u-boot
On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> This is 2nd version of patchset to convert reset, system and clock manager
> drivers to use #define instead of struct.
>
> Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
>
> Patch 1 is new one, patch 2 to 4 have changes.
>
> Main changes in this version are:
> - Get base address from DT
> - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> - Add prefix to defines.
> - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
>
> History:
> v1: https://patchwork.ozlabs.org/cover/1149731/
>
I think you also need to Simon Goldschmidt to this series.
Beside the minor incorrect address missing a zero in patch 1, I've
tested this series on the Sockit.
Tested-by: Dinh Nguyen <dinguyen@kernel.org>
Dinh
^ permalink raw reply [flat|nested] 21+ messages in thread* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-09-17 22:33 ` [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers " Dinh Nguyen
@ 2019-09-18 2:32 ` Ley Foon Tan
2019-09-18 4:22 ` Simon Goldschmidt
0 siblings, 1 reply; 21+ messages in thread
From: Ley Foon Tan @ 2019-09-18 2:32 UTC (permalink / raw)
To: u-boot
On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>
>
>
> On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> > This is 2nd version of patchset to convert reset, system and clock manager
> > drivers to use #define instead of struct.
> >
> > Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
> >
> > Patch 1 is new one, patch 2 to 4 have changes.
> >
> > Main changes in this version are:
> > - Get base address from DT
> > - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> > - Add prefix to defines.
> > - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
> >
> > History:
> > v1: https://patchwork.ozlabs.org/cover/1149731/
> >
>
> I think you also need to Simon Goldschmidt to this series.
Simon is in the CC list in my original email.
>
> Beside the minor incorrect address missing a zero in patch 1, I've
> tested this series on the Sockit.
>
> Tested-by: Dinh Nguyen <dinguyen@kernel.org>
>
Regards
Ley Foon
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-09-18 2:32 ` Ley Foon Tan
@ 2019-09-18 4:22 ` Simon Goldschmidt
2019-10-02 8:13 ` Ley Foon Tan
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-09-18 4:22 UTC (permalink / raw)
To: u-boot
Ley Foon Tan <lftan.linux@gmail.com> schrieb am Mi., 18. Sep. 2019, 04:32:
> On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
> >
> >
> >
> > On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> > > This is 2nd version of patchset to convert reset, system and clock
> manager
> > > drivers to use #define instead of struct.
> > >
> > > Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
> > >
> > > Patch 1 is new one, patch 2 to 4 have changes.
> > >
> > > Main changes in this version are:
> > > - Get base address from DT
> > > - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> > > - Add prefix to defines.
> > > - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
> > >
> > > History:
> > > v1: https://patchwork.ozlabs.org/cover/1149731/
> > >
> >
> > I think you also need to Simon Goldschmidt to this series.
> Simon is in the CC list in my original email.
>
And I'm trying my best to catch up with u-boot mails and patches. I already
read it through but failed to find the time to review and test it. Next
week, hopefully...
Regards,
Simon
>
> > Beside the minor incorrect address missing a zero in patch 1, I've
> > tested this series on the Sockit.
> >
> > Tested-by: Dinh Nguyen <dinguyen@kernel.org>
> >
> Regards
> Ley Foon
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-09-18 4:22 ` Simon Goldschmidt
@ 2019-10-02 8:13 ` Ley Foon Tan
2019-10-02 9:23 ` Simon Goldschmidt
0 siblings, 1 reply; 21+ messages in thread
From: Ley Foon Tan @ 2019-10-02 8:13 UTC (permalink / raw)
To: u-boot
On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
>
>
> Ley Foon Tan <lftan.linux@gmail.com> schrieb am Mi., 18. Sep. 2019, 04:32:
>>
>> On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>> >
>> >
>> >
>> > On 9/10/19 3:37 AM, Ley Foon Tan wrote:
>> > > This is 2nd version of patchset to convert reset, system and clock manager
>> > > drivers to use #define instead of struct.
>> > >
>> > > Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
>> > >
>> > > Patch 1 is new one, patch 2 to 4 have changes.
>> > >
>> > > Main changes in this version are:
>> > > - Get base address from DT
>> > > - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
>> > > - Add prefix to defines.
>> > > - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
>> > >
>> > > History:
>> > > v1: https://patchwork.ozlabs.org/cover/1149731/
>> > >
>> >
>> > I think you also need to Simon Goldschmidt to this series.
>> Simon is in the CC list in my original email.
>
>
> And I'm trying my best to catch up with u-boot mails and patches. I already read it through but failed to find the time to review and test it. Next week, hopefully...
>
> Regards,
> Simon
>
>> >
>> > Beside the minor incorrect address missing a zero in patch 1, I've
>> > tested this series on the Sockit.
>> >
>> > Tested-by: Dinh Nguyen <dinguyen@kernel.org>
Hi Marek and Simon
Any further comment for this series? Otherwise, I will send v3 with
minor change for Dinh's comment.
Thanks.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-10-02 8:13 ` Ley Foon Tan
@ 2019-10-02 9:23 ` Simon Goldschmidt
2019-10-09 18:42 ` Simon Goldschmidt
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-02 9:23 UTC (permalink / raw)
To: u-boot
On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan <lftan.linux@gmail.com> wrote:
>
> On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com> wrote:
> >
> >
> >
> > Ley Foon Tan <lftan.linux@gmail.com> schrieb am Mi., 18. Sep. 2019, 04:32:
> >>
> >> On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
> >> >
> >> >
> >> >
> >> > On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> >> > > This is 2nd version of patchset to convert reset, system and clock manager
> >> > > drivers to use #define instead of struct.
> >> > >
> >> > > Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
> >> > >
> >> > > Patch 1 is new one, patch 2 to 4 have changes.
> >> > >
> >> > > Main changes in this version are:
> >> > > - Get base address from DT
> >> > > - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> >> > > - Add prefix to defines.
> >> > > - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
> >> > >
> >> > > History:
> >> > > v1: https://patchwork.ozlabs.org/cover/1149731/
> >> > >
> >> >
> >> > I think you also need to Simon Goldschmidt to this series.
> >> Simon is in the CC list in my original email.
> >
> >
> > And I'm trying my best to catch up with u-boot mails and patches. I already read it through but failed to find the time to review and test it. Next week, hopefully...
> >
> > Regards,
> > Simon
> >
> >> >
> >> > Beside the minor incorrect address missing a zero in patch 1, I've
> >> > tested this series on the Sockit.
> >> >
> >> > Tested-by: Dinh Nguyen <dinguyen@kernel.org>
>
> Hi Marek and Simon
>
> Any further comment for this series? Otherwise, I will send v3 with
> minor change for Dinh's comment.
I did my best to catch up now. Ping back if there are still patches missing/
uncommented, please.
Regards,
Simon
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-10-02 9:23 ` Simon Goldschmidt
@ 2019-10-09 18:42 ` Simon Goldschmidt
2019-10-10 0:47 ` Ley Foon Tan
0 siblings, 1 reply; 21+ messages in thread
From: Simon Goldschmidt @ 2019-10-09 18:42 UTC (permalink / raw)
To: u-boot
Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
> On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan <lftan.linux@gmail.com> wrote:
>>
>> On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
>> <simon.k.r.goldschmidt@gmail.com> wrote:
>>>
>>>
>>>
>>> Ley Foon Tan <lftan.linux@gmail.com> schrieb am Mi., 18. Sep. 2019, 04:32:
>>>>
>>>> On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>>>>>
>>>>>
>>>>>
>>>>> On 9/10/19 3:37 AM, Ley Foon Tan wrote:
>>>>>> This is 2nd version of patchset to convert reset, system and clock manager
>>>>>> drivers to use #define instead of struct.
>>>>>>
>>>>>> Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
>>>>>>
>>>>>> Patch 1 is new one, patch 2 to 4 have changes.
>>>>>>
>>>>>> Main changes in this version are:
>>>>>> - Get base address from DT
>>>>>> - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
>>>>>> - Add prefix to defines.
>>>>>> - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
>>>>>>
>>>>>> History:
>>>>>> v1: https://patchwork.ozlabs.org/cover/1149731/
>>>>>>
>>>>>
>>>>> I think you also need to Simon Goldschmidt to this series.
>>>> Simon is in the CC list in my original email.
>>>
>>>
>>> And I'm trying my best to catch up with u-boot mails and patches. I already read it through but failed to find the time to review and test it. Next week, hopefully...
>>>
>>> Regards,
>>> Simon
>>>
>>>>>
>>>>> Beside the minor incorrect address missing a zero in patch 1, I've
>>>>> tested this series on the Sockit.
>>>>>
>>>>> Tested-by: Dinh Nguyen <dinguyen@kernel.org>
>>
>> Hi Marek and Simon
>>
>> Any further comment for this series? Otherwise, I will send v3 with
>> minor change for Dinh's comment.
>
> I did my best to catch up now. Ping back if there are still patches missing/
> uncommented, please.
So could we have v3 with those minor changes (and adjusted commit
messages)? I'd like to base my series on these changes to prevent merge
conflicts.
Thanks,
Simon
>
> Regards,
> Simon
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [U-Boot] [PATCH v2 0/4] arm: socfpga: Convert drivers from struct to defines
2019-10-09 18:42 ` Simon Goldschmidt
@ 2019-10-10 0:47 ` Ley Foon Tan
0 siblings, 0 replies; 21+ messages in thread
From: Ley Foon Tan @ 2019-10-10 0:47 UTC (permalink / raw)
To: u-boot
On Thu, Oct 10, 2019 at 2:42 AM Simon Goldschmidt
<simon.k.r.goldschmidt@gmail.com> wrote:
>
> Am 02.10.2019 um 11:23 schrieb Simon Goldschmidt:
> > On Wed, Oct 2, 2019 at 10:13 AM Ley Foon Tan <lftan.linux@gmail.com> wrote:
> >>
> >> On Wed, Sep 18, 2019 at 12:23 PM Simon Goldschmidt
> >> <simon.k.r.goldschmidt@gmail.com> wrote:
> >>>
> >>>
> >>>
> >>> Ley Foon Tan <lftan.linux@gmail.com> schrieb am Mi., 18. Sep. 2019, 04:32:
> >>>>
> >>>> On Wed, Sep 18, 2019 at 6:33 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
> >>>>>
> >>>>>
> >>>>>
> >>>>> On 9/10/19 3:37 AM, Ley Foon Tan wrote:
> >>>>>> This is 2nd version of patchset to convert reset, system and clock manager
> >>>>>> drivers to use #define instead of struct.
> >>>>>>
> >>>>>> Tested on Cyclone 5, Arria 10 and Stratix 10 devices.
> >>>>>>
> >>>>>> Patch 1 is new one, patch 2 to 4 have changes.
> >>>>>>
> >>>>>> Main changes in this version are:
> >>>>>> - Get base address from DT
> >>>>>> - Change to use writel(), readl(), setbits_le32() and clrbits_le32().
> >>>>>> - Add prefix to defines.
> >>>>>> - Add "u-boot,dm-pre-reloc" to clock and system manager nodes.
> >>>>>>
> >>>>>> History:
> >>>>>> v1: https://patchwork.ozlabs.org/cover/1149731/
> >>>>>>
> >>>>>
> >>>>> I think you also need to Simon Goldschmidt to this series.
> >>>> Simon is in the CC list in my original email.
> >>>
> >>>
> >>> And I'm trying my best to catch up with u-boot mails and patches. I already read it through but failed to find the time to review and test it. Next week, hopefully...
> >>>
> >>> Regards,
> >>> Simon
> >>>
> >>>>>
> >>>>> Beside the minor incorrect address missing a zero in patch 1, I've
> >>>>> tested this series on the Sockit.
> >>>>>
> >>>>> Tested-by: Dinh Nguyen <dinguyen@kernel.org>
> >>
> >> Hi Marek and Simon
> >>
> >> Any further comment for this series? Otherwise, I will send v3 with
> >> minor change for Dinh's comment.
> >
> > I did my best to catch up now. Ping back if there are still patches missing/
> > uncommented, please.
>
> So could we have v3 with those minor changes (and adjusted commit
> messages)? I'd like to base my series on these changes to prevent merge
> conflicts.
>
Sure, I have make those updates. Will send out today.
Thanks.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 21+ messages in thread