* [U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values
@ 2016-11-03 10:05 Lokesh Vutla
2016-11-04 11:25 ` Tom Rini
2016-11-13 20:57 ` [U-Boot] " Tom Rini
0 siblings, 2 replies; 3+ messages in thread
From: Lokesh Vutla @ 2016-11-03 10:05 UTC (permalink / raw)
To: u-boot
Only a certain set of PLLM/D values are recommended to configure the DDR
at the required speeds for a given clock input frequency. Updating these
values as specified in Data Sheet[1] Table 5-18
[1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
board/ti/ks2_evm/board_k2g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 8f16845..40edbaa 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -66,7 +66,7 @@ static struct pll_init_data tetris_pll_config[NUM_SPDS] = {
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 133, 1, 16};
struct pll_init_data *get_pll_init_data(int pll)
{
--
2.10.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values
2016-11-03 10:05 [U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values Lokesh Vutla
@ 2016-11-04 11:25 ` Tom Rini
2016-11-13 20:57 ` [U-Boot] " Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Tom Rini @ 2016-11-04 11:25 UTC (permalink / raw)
To: u-boot
On Thu, Nov 03, 2016 at 03:35:02PM +0530, Lokesh Vutla wrote:
> Only a certain set of PLLM/D values are recommended to configure the DDR
> at the required speeds for a given clock input frequency. Updating these
> values as specified in Data Sheet[1] Table 5-18
>
> [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
--
Tom
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* [U-Boot] ARM: k2g: Update PLL Multiplier and divider values
2016-11-03 10:05 [U-Boot] [PATCH] ARM: k2g: Update PLL Multiplier and divider values Lokesh Vutla
2016-11-04 11:25 ` Tom Rini
@ 2016-11-13 20:57 ` Tom Rini
1 sibling, 0 replies; 3+ messages in thread
From: Tom Rini @ 2016-11-13 20:57 UTC (permalink / raw)
To: u-boot
On Thu, Nov 03, 2016 at 03:35:02PM +0530, Lokesh Vutla wrote:
> Only a certain set of PLLM/D values are recommended to configure the DDR
> at the required speeds for a given clock input frequency. Updating these
> values as specified in Data Sheet[1] Table 5-18
>
> [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf
>
> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>
Applied to u-boot/master, thanks!
--
Tom
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