* [U-Boot] [PATCH 2/2] ARM: add SBx81LIFKW board
2018-05-28 9:00 [U-Boot] [PATCH 1/2] ARM: kirkwood: remove automatic I2C config if DM_I2C is enabled Chris Packham
@ 2018-05-28 9:00 ` Chris Packham
2018-05-28 9:16 ` Stefan Roese
0 siblings, 1 reply; 3+ messages in thread
From: Chris Packham @ 2018-05-28 9:00 UTC (permalink / raw)
To: u-boot
This is a series of line cards for Allied Telesis's SBx8100 chassis
switch. The CPU block is common to the SBx81GS24a, SBx81XS6, SBx81XS16
and SBx81GT40 cards collectively referred to as SBx81LIFKW in u-boot.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
This is the board I've been using for testing the device tree support
for kirkwood. The Ethernet arrangement is a bit complicated and doesn't
currently work on u-boot#master but I can test SPI and I2C.
arch/arm/dts/kirkwood-atl-sbx81lifkw.dts | 133 ++++++++++++++
arch/arm/mach-kirkwood/Kconfig | 4 +
board/alliedtelesis/SBx81LIFKW/Kconfig | 12 ++
board/alliedtelesis/SBx81LIFKW/MAINTAINERS | 7 +
board/alliedtelesis/SBx81LIFKW/Makefile | 8 +
board/alliedtelesis/SBx81LIFKW/kwbimage.cfg | 47 +++++
board/alliedtelesis/SBx81LIFKW/platform.S | 108 +++++++++++
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 192 ++++++++++++++++++++
configs/SBx81LIFKW_defconfig | 32 ++++
include/configs/SBx81LIFKW.h | 123 +++++++++++++
10 files changed, 666 insertions(+)
create mode 100644 arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
create mode 100644 board/alliedtelesis/SBx81LIFKW/Kconfig
create mode 100644 board/alliedtelesis/SBx81LIFKW/MAINTAINERS
create mode 100644 board/alliedtelesis/SBx81LIFKW/Makefile
create mode 100644 board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
create mode 100644 board/alliedtelesis/SBx81LIFKW/platform.S
create mode 100644 board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
create mode 100644 configs/SBx81LIFKW_defconfig
create mode 100644 include/configs/SBx81LIFKW.h
diff --git a/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
new file mode 100644
index 000000000000..e5b1efa1415a
--- /dev/null
+++ b/arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "Allied Telesis SBx81LIFKW Board";
+ compatible = "atl,SBx81LIFKW", "marvell,kirkwood-88f6281",
+ "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>; /* 128 MB */
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ ethernet0 = ð0;
+ i2c0 = &i2c0;
+ spi0 = &spi0;
+ };
+
+ dsa {
+ compatible = "marvell,dsa";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ dsa,ethernet = <ð0>;
+ dsa,mii-bus = <&mdio>;
+ status = "okay";
+
+ switch at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1 0>;
+
+ port at 0 {
+ reg = <0>;
+ label = "internal0";
+ };
+ port at 1 {
+ reg = <1>;
+ label = "internal1";
+ };
+ port at 8 {
+ reg = <8>;
+ label = "internal8";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port at 9 {
+ reg = <9>;
+ label = "internal9";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ port at 10 {
+ reg = <10>;
+ label = "cpu";
+ };
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p128", "jedec,spi-nor", "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ mode = <0>;
+
+ partition at u-boot {
+ reg = <0x00000000 0x00c00000>;
+ label = "u-boot";
+ };
+ partition at u-boot-env {
+ reg = <0x00c00000 0x00040000>;
+ label = "u-boot-env";
+ };
+ partition at unused {
+ reg = <0x00100000 0x00f00000>;
+ label = "unused";
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom at 52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+
+ ethernet0-port at 0 {
+ speed = <1000>;
+ duplex = <1>;
+ };
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 2dd107a8b3bf..5a5a63cea719 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -59,6 +59,9 @@ config TARGET_NAS220
config TARGET_NSA310S
bool "Zyxel NSA310S"
+config TARGET_SBx81LIFKW
+ bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16"
+
endchoice
config SYS_SOC
@@ -81,5 +84,6 @@ source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
source "board/Seagate/nas220/Kconfig"
source "board/zyxel/nsa310s/Kconfig"
+source "board/alliedtelesis/SBx81LIFKW/Kconfig"
endif
diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig
new file mode 100644
index 000000000000..5c2609b7f464
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SBx81LIFKW
+
+config SYS_BOARD
+ default "SBx81LIFKW"
+
+config SYS_VENDOR
+ default "alliedtelesis"
+
+config SYS_CONFIG_NAME
+ default "SBx81LIFKW"
+
+endif
diff --git a/board/alliedtelesis/SBx81LIFKW/MAINTAINERS b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
new file mode 100644
index 000000000000..31ccec0e9b7e
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/MAINTAINERS
@@ -0,0 +1,7 @@
+SBx81LIFKW BOARD
+M: Chris Packham <chris.packham@alliedtelesis.co.nz>
+S: Maintained
+F: board/alliedtelesis/SBx81LIFKW/
+F: include/configs/SBx81LIFKW
+F: configs/SBx81LIFKW_defconfig
+F: arch/arm/dts/kirkwood-atl-sbx81lifkw.dts
diff --git a/board/alliedtelesis/SBx81LIFKW/Makefile b/board/alliedtelesis/SBx81LIFKW/Makefile
new file mode 100644
index 000000000000..2a5a33fa0807
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2010, 2018
+# Allied Telesis <www.alliedtelesis.com>
+#
+
+obj-y += sbx81lifkw.o
+obj-y += platform.o
diff --git a/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
new file mode 100644
index 000000000000..9726f15e28b0
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/kwbimage.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2018 Allied Telesis
+#
+# Refer docs/README.kwimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM spi # Boot from SPI flash
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+DATA 0xffd100e0 0x1b1b1b1b
+DATA 0xffd20134 0xffffffff
+DATA 0xffd20138 0x009fffff
+DATA 0xffd20154 0x00000000
+DATA 0xffd2014c 0x00000000
+DATA 0xffd20148 0x00000001
+
+# Dram initalization for 1 x x16
+# DDR II Micron part number MT47H64M16HR-3
+# MClk 333MHz, Size 128MB, ECC disable
+#
+DATA 0xffd01400 0x43000618
+DATA 0xffd01404 0x35143000
+DATA 0xffd01408 0x11012227
+DATA 0xffd0140c 0x00000819
+DATA 0xffd01410 0x0000000d
+DATA 0xffd01414 0x00000000
+DATA 0xffd01418 0x00000000
+DATA 0xffd0141c 0x00000632
+DATA 0xffd01420 0x00000040
+DATA 0xffd01424 0x0000f07f
+DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
+DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
+DATA 0xffd01508 0x10000000
+DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
+DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
+DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
+DATA 0xffd01494 0x00030000
+DATA 0xffd01498 0x00000000
+DATA 0xffd0149c 0x0000e803
+DATA 0xffd01480 0x00000001
+
+# End of Header extension
+DATA 0x0 0x0
diff --git a/board/alliedtelesis/SBx81LIFKW/platform.S b/board/alliedtelesis/SBx81LIFKW/platform.S
new file mode 100644
index 000000000000..44ce603696af
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/platform.S
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2010
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+/* based (loosley) on Marvell's board/mv_feroceon/mv_kw/platform.S */
+
+#include <config.h>
+
+platform_lowlevel_init_data:
+ /* AHB to Mbus Bridge
+ * Change CPU reg base to 0xF1000000
+ * These *MUST* be first, and it hits
+ * both potential address to be safe
+ */
+ .long 0xD0020080, KW_REGS_PHY_BASE
+ .long 0xF1020080, KW_REGS_PHY_BASE
+
+ /* Configure RGMII-0 interface pad voltage to 1.8V */
+ .long KW_REGS_PHY_BASE + 0x100E0, 0x1B1B1B1B
+
+ .long KW_REGS_PHY_BASE + 0x20134, 0xffffffff
+ .long KW_REGS_PHY_BASE + 0x20138, 0x009fffff
+ .long KW_REGS_PHY_BASE + 0x20154, 0x00000000
+ .long KW_REGS_PHY_BASE + 0x2014c, 0x00000000
+ .long KW_REGS_PHY_BASE + 0x20148, 0x00000001
+
+ /* Dram initalization for 1 x x16
+ * DDR II Micron part number MT47H64M16HR-3
+ * MClk 333MHz, Size 128MB, ECC disable
+ */
+ .long KW_REGS_PHY_BASE + 0x01400, 0x43000618 /* DDR Configuration register */
+ .long KW_REGS_PHY_BASE + 0x01404, 0x35143000 /* DDR Controller Control Low */
+ .long KW_REGS_PHY_BASE + 0x01408, 0x11012227 /* DDR Timing (Low) (active cycles value +1) */
+ .long KW_REGS_PHY_BASE + 0x0140C, 0x00000819 /* DDR Timing (High) */
+ .long KW_REGS_PHY_BASE + 0x01410, 0x0000000d /* DDR Address Control */
+ .long KW_REGS_PHY_BASE + 0x01414, 0x00000000 /* DDR Open Pages Control */
+ .long KW_REGS_PHY_BASE + 0x01418, 0x00000000 /* DDR Operation */
+ .long KW_REGS_PHY_BASE + 0x0141C, 0x00000632 /* DDR Mode */
+ .long KW_REGS_PHY_BASE + 0x01420, 0x00000040 /* DDR Extended Mode */
+ .long KW_REGS_PHY_BASE + 0x01424, 0x0000f07f /* DDR Controller Control High */
+ .long KW_REGS_PHY_BASE + 0x01428, 0x00063300 /* DDR2 ODT Read Timing (default values) */
+ .long KW_REGS_PHY_BASE + 0x0147C, 0x00006330 /* DDR2 ODT Write Timing (default values) */
+
+ .long KW_REGS_PHY_BASE + 0x01500, 0x00000000 /* SDRAM CS[0] Base address at 0x00000000 */
+ .long KW_REGS_PHY_BASE + 0x01504, 0x07FFFFF1 /* SDRAM CS[0] Size 128MiB */
+ .long KW_REGS_PHY_BASE + 0x01508, 0x10000000 /* SDRAM CS[1] Base address */
+ .long KW_REGS_PHY_BASE + 0x0150C, 0x00FFFFF4 /* SDRAM CS[1] Size, window disabled */
+ .long KW_REGS_PHY_BASE + 0x01510, 0x20000000 /* SDRAM CS[2] Base address */
+ .long KW_REGS_PHY_BASE + 0x01514, 0x00FFFFF8 /* SDRAM CS[2] Size, window disabled */
+ .long KW_REGS_PHY_BASE + 0x01518, 0x30000000 /* SDRAM CS[3] Base address */
+ .long KW_REGS_PHY_BASE + 0x0151C, 0x00FFFFFC /* SDRAM CS[3] Size, window disabled */
+
+ .long KW_REGS_PHY_BASE + 0x01494, 0x00030000 /* DDR ODT Control (Low) */
+ .long KW_REGS_PHY_BASE + 0x01498, 0x00000000 /* DDR ODT Control (High) */
+ .long KW_REGS_PHY_BASE + 0x0149C, 0x0000e803 /* CPU ODT Control */
+
+ .long KW_REGS_PHY_BASE + 0x01480, 0x00000001 /* DDR Initialization Control */
+
+ /* End of Header extension */
+ .long 0x0, 0x0
+
+.globl lowlevel_init
+
+/************************************************/
+/* lowlevel_init *
+/************************************************/
+
+lowlevel_init:
+ /* change CPU registers according to platform spec */
+ adr r2, platform_lowlevel_init_data
+ b check_next
+
+reg_write:
+ /* TODO: This does not yet cater for BigEndian (BE) systems */
+ str r1, [r0]
+ add r2, #8
+check_next:
+ ldr r0, [r2]
+ ldr r1, [r2, #4]
+ cmp r0, #0x0
+ bne reg_write
+
+ /* Change L2 cache to exist */
+ ldr r1, =(KW_REGS_PHY_BASE + 0x20128)
+ ldr r2, [r1]
+ orr r2, r2, #0x18
+ str r2, [r1]
+
+ /* Read operation to make sure the L2 bit is set */
+ ldr r2, [r1]
+
+ /* invalidate L2 cache */
+ mov r0, #0
+ mcr p15, 1, r0, c15, c11, 0
+
+#if defined(CONFIG_SPI_FLASH)
+ /* configure the Prescale of SPI clk Tclk = 166MHz */
+ ldr r1, =(KW_REGS_PHY_BASE + 0x10604)
+ ldr r3, [r1]
+ and r3, r3, #~0x1f
+ orr r3, r3, #0x15
+ str r3, [r1]
+#endif
+
+done:
+ mov pc, lr
diff --git a/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
new file mode 100644
index 000000000000..c2fd6304151d
--- /dev/null
+++ b/board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2010, 2018
+ * Allied Telesis <www.alliedtelesis.com>
+ */
+
+#include <common.h>
+#include <linux/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/mpp.h>
+#include <asm/arch/gpio.h>
+
+/* Note: GPIO differences between specific boards
+ *
+ * We're trying to avoid having multiple build targets for all the Kirkwood
+ * based boards one area where things tend to differ is GPIO usage. For the
+ * most part the GPIOs driven by the bootloader are similar enough in function
+ * that there is no harm in driving them.
+ *
+ * XZ4 XS6 XS16 GS24A GT40 GP24A GT24A
+ * GPIO39 - INT(<) NC MUX_RST_N(>) NC POE_DIS_N(>) NC
+ */
+
+#define SBX81LIFKW_OE_LOW ~(BIT(31) | BIT(30) | BIT(28) | BIT(27) | \
+ BIT(18) | BIT(17) | BIT(13) | BIT(12) | \
+ BIT(10))
+#define SBX81LIFKW_OE_HIGH ~(BIT(0) | BIT(1) | BIT(7))
+#define SBX81LIFKW_OE_VAL_LOW (BIT(31) | BIT(30) | BIT(28) | BIT(27))
+#define SBX81LIFKW_OE_VAL_HIGH (BIT(0) | BIT(1))
+
+#define MV88E6097_RESET 27
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct led {
+ u32 reg;
+ u32 value;
+ u32 mask;
+};
+
+struct led amber_solid = {
+ MVEBU_GPIO0_BASE,
+ BIT(10),
+ BIT(18) | BIT(10)
+};
+
+struct led green_solid = {
+ MVEBU_GPIO0_BASE,
+ BIT(18) | BIT(10),
+ BIT(18) | BIT(10)
+};
+
+struct led amber_flash = {
+ MVEBU_GPIO0_BASE,
+ 0,
+ BIT(18) | BIT(10)
+};
+
+struct led green_flash = {
+ MVEBU_GPIO0_BASE,
+ BIT(18),
+ BIT(18) | BIT(10)
+};
+
+static void status_led_set(struct led *led)
+{
+ u32 val;
+
+ val = readl(led->reg);
+ val &= ~led->mask;
+ val |= led->value;
+ writel(val, led->reg);
+}
+
+int board_early_init_f(void)
+{
+ /*
+ * default gpio configuration
+ * There are maximum 64 gpios controlled through 2 sets of registers
+ * the below configuration configures mainly initial LED status
+ */
+ mvebu_config_gpio(SBX81LIFKW_OE_VAL_LOW,
+ SBX81LIFKW_OE_VAL_HIGH,
+ SBX81LIFKW_OE_LOW, SBX81LIFKW_OE_HIGH);
+
+ /* Multi-Purpose Pins Functionality configuration */
+ static const u32 kwmpp_config[] = {
+ MPP0_SPI_SCn,
+ MPP1_SPI_MOSI,
+ MPP2_SPI_SCK,
+ MPP3_SPI_MISO,
+ MPP4_UART0_RXD,
+ MPP5_UART0_TXD,
+ MPP6_SYSRST_OUTn,
+ MPP7_PEX_RST_OUTn,
+ MPP8_TW_SDA,
+ MPP9_TW_SCK,
+ MPP10_GPO,
+ MPP11_GPIO,
+ MPP12_GPO,
+ MPP13_GPIO,
+ MPP14_GPIO,
+ MPP15_UART0_RTS,
+ MPP16_UART0_CTS,
+ MPP17_GPIO,
+ MPP18_GPO,
+ MPP19_GPO,
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO,
+ MPP23_GPIO,
+ MPP24_GPIO,
+ MPP25_GPIO,
+ MPP26_GPIO,
+ MPP27_GPIO,
+ MPP28_GPIO,
+ MPP29_GPIO,
+ MPP30_GPIO,
+ MPP31_GPIO,
+ MPP32_GPIO,
+ MPP33_GPIO,
+ MPP34_GPIO,
+ MPP35_GPIO,
+ MPP36_GPIO,
+ MPP37_GPIO,
+ MPP38_GPIO,
+ MPP39_GPIO,
+ MPP40_GPIO,
+ MPP41_GPIO,
+ MPP42_GPIO,
+ MPP43_GPIO,
+ MPP44_GPIO,
+ MPP45_GPIO,
+ MPP46_GPIO,
+ MPP47_GPIO,
+ MPP48_GPIO,
+ MPP49_GPIO,
+ 0
+ };
+
+ kirkwood_mpp_conf(kwmpp_config, NULL);
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Power-down unused subsystems. The required
+ * subsystems are:
+ *
+ * GE0 b0
+ * PEX0 PHY b1
+ * PEX0.0 b2
+ * TSU b5
+ * SDRAM b6
+ * RUNIT b7
+ */
+ writel((BIT(0) | BIT(1) | BIT(2) |
+ BIT(5) | BIT(6) | BIT(7)),
+ KW_CPU_REG_BASE + 0x1c);
+
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ status_led_set(&amber_solid);
+
+ return 0;
+}
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+/* Configure and enable Switch and PHY */
+void reset_phy(void)
+{
+ /* Ensure the 88e6097 gets at least 10ms Reset
+ */
+ kw_gpio_set_value(MV88E6097_RESET, 0);
+ mdelay(20);
+ kw_gpio_set_value(MV88E6097_RESET, 1);
+ mdelay(20);
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+ status_led_set(&green_flash);
+
+ return 0;
+}
+#endif
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
new file mode 100644
index 000000000000..01bbbfcc2231
--- /dev/null
+++ b/configs/SBx81LIFKW_defconfig
@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_SYS_TEXT_BASE=0x00600000
+CONFIG_TARGET_SBx81LIFKW=y
+CONFIG_IDENT_STRING="\nSBx81LIFKW"
+CONFIG_DEFAULT_DEVICE_TREE="kirkwood-atl-sbx81lifkw"
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_BOOTDELAY=3
+CONFIG_SILENT_CONSOLE=y
+CONFIG_SILENT_U_BOOT_ONLY=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+# CONFIG_MMC is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI=y
+CONFIG_KIRKWOOD_SPI=y
diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h
new file mode 100644
index 000000000000..ea85c9ee7716
--- /dev/null
+++ b/include/configs/SBx81LIFKW.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Allied Telesis <www.alliedtelesis.co.nz>
+ */
+
+#ifndef _CONFIG_SBX81LIFKW_H
+#define _CONFIG_SBX81LIFKW_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
+#define CONFIG_KW88F6281 1 /* SOC Name */
+#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
+#define CONFIG_BUILD_TARGET "u-boot.kwb"
+
+/* additions for new ARM relocation support */
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
+#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
+#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */
+#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
+#define CONFIG_KIRKWOOD_GPIO 1
+
+#define CONFIG_MISC_INIT_R /* call misc_init_r */
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)"
+#define MTDPARTS_MTDOOPS "errlog"
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_SPI_BUS 0
+#define CONFIG_ENV_SPI_CS 0
+#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
+#define CONFIG_ENV_SIZE 0x02000
+#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */
+
+/*
+ * U-Boot bootcode configuration
+ */
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */
+#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
+
+/* size in bytes reserved for initial data */
+
+#include <asm/arch/config.h>
+/* There is no PHY directly connected so don't ask it for link status */
+#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_NR_DRAM_BANKS 4
+#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
+#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
+
+/*
+ * Ethernet Driver configuration
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+#define CONFIG_NET_MULTI /* specify more that one ports available */
+#define CONFIG_MII /* expose smi over miiphy interface */
+#define CONFIG_PHYLIB
+#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */
+#define CONFIG_PHY_BASE_ADR 0x01
+#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
+#define CONFIG_RESET_PHY_R /* use reset_phy() to init switch */
+#define CONFIG_MV88E61XX_SWITCH /* Enable MV88E61XX switch driver */
+#define CONFIG_MV88E61XX_PHY_PORTS 0x303 /* Pt0,1,8,9 */
+#define CONFIG_MV88E61XX_CPU_PORT 10 /* 10(CPU) */
+#endif /* CONFIG_CMD_NET */
+
+/*
+ * Time settings
+ */
+#define CONFIG_RTC_MV
+
+#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */
+
+#endif /* _CONFIG_SBX81LIFKW_H */
--
2.17.0
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