* [U-Boot] [PATCH v3 5/7] clk: mediatek: add driver for MT8516
2019-03-24 15:46 [U-Boot] [PATCH v3 0/7] Add support for MT8516 SoC Fabien Parent
` (3 preceding siblings ...)
2019-03-24 15:46 ` [U-Boot] [PATCH v3 4/7] clk: mediatek: add support for SETCLR_INV and NO_SETCLR flags Fabien Parent
@ 2019-03-24 15:46 ` Fabien Parent
2019-04-24 13:30 ` [U-Boot] [U-Boot,v3,5/7] " Tom Rini
2019-03-24 15:46 ` [U-Boot] [PATCH v3 6/7] pinctrl: " Fabien Parent
2019-03-24 15:46 ` [U-Boot] [PATCH v3 7/7] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
6 siblings, 1 reply; 15+ messages in thread
From: Fabien Parent @ 2019-03-24 15:46 UTC (permalink / raw)
To: u-boot
Add clock driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
v3:
* Remove invalid clocks
v2:
* Fix invalid GATE_TOP5 flag
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8516.c | 802 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8516-clk.h | 251 ++++++++
3 files changed, 1054 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8516.c
create mode 100644 include/dt-bindings/clock/mt8516-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0632dc87b6..a47a5bdbc2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 0000000000..e07cc59f7f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX (1502UL * MHZ)
+#define MT8516_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8516_CON0_RST_BAR, \
+ .fmax = MT8516_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+ 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+ 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+ 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+ 31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+ FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+ FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+ FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+ FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_GFMUX_EMI1X_SEL,
+ CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+};
+
+static const int csw_mux_mfg_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int pwm_mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+};
+
+static const int uart1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int spm_52m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB_PHY48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+ CLK_TOP_AHB_INFRA_SEL,
+ CLK_TOP_NFI1X,
+};
+
+static const int mfg_mm_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_MUX_MFG_SEL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D3,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D14
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int axi_mfg_in_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int slow_mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL1_D2_EN,
+ CLK_TOP_RG_APLL1_D4_EN,
+ CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL2_D2_EN,
+ CLK_TOP_RG_APLL2_D4_EN,
+ CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_RG_AUD1,
+ CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_NFI2X_PAD_SEL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+ MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+ MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+ MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+ MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+ MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+ MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+ MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+ /* CLK_MUX_SEL9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+ MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+ MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+ MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xb4,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+ GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
+ GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+ GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+ GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+ GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+ GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+ GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+ GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+ GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+ GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
+ GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
+ GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+ GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+ GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+ GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+ /* TOP4 */
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+ /* TOP5 */
+ GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+ GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+ GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+ GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8516-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8516-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_apmixed_compat,
+ .probe = mt8516_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8516-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_compat,
+ .probe = mt8516_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8516-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_cg_compat,
+ .probe = mt8516_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000000..b62a971c59
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_I2S_INFRA_BCK 1
+#define CLK_TOP_MEMPLL 2
+#define CLK_TOP_DMPLL 3
+#define CLK_TOP_MAINPLL_D2 4
+#define CLK_TOP_MAINPLL_D4 5
+#define CLK_TOP_MAINPLL_D8 6
+#define CLK_TOP_MAINPLL_D16 7
+#define CLK_TOP_MAINPLL_D11 8
+#define CLK_TOP_MAINPLL_D22 9
+#define CLK_TOP_MAINPLL_D3 10
+#define CLK_TOP_MAINPLL_D6 11
+#define CLK_TOP_MAINPLL_D12 12
+#define CLK_TOP_MAINPLL_D5 13
+#define CLK_TOP_MAINPLL_D10 14
+#define CLK_TOP_MAINPLL_D20 15
+#define CLK_TOP_MAINPLL_D40 16
+#define CLK_TOP_MAINPLL_D7 17
+#define CLK_TOP_MAINPLL_D14 18
+#define CLK_TOP_UNIVPLL_D2 19
+#define CLK_TOP_UNIVPLL_D4 20
+#define CLK_TOP_UNIVPLL_D8 21
+#define CLK_TOP_UNIVPLL_D16 22
+#define CLK_TOP_UNIVPLL_D3 23
+#define CLK_TOP_UNIVPLL_D6 24
+#define CLK_TOP_UNIVPLL_D12 25
+#define CLK_TOP_UNIVPLL_D24 26
+#define CLK_TOP_UNIVPLL_D5 27
+#define CLK_TOP_UNIVPLL_D20 28
+#define CLK_TOP_MMPLL380M 29
+#define CLK_TOP_MMPLL_D2 30
+#define CLK_TOP_MMPLL_200M 31
+#define CLK_TOP_USB_PHY48M 32
+#define CLK_TOP_APLL1 33
+#define CLK_TOP_APLL1_D2 34
+#define CLK_TOP_APLL1_D4 35
+#define CLK_TOP_APLL1_D8 36
+#define CLK_TOP_APLL2 37
+#define CLK_TOP_APLL2_D2 38
+#define CLK_TOP_APLL2_D4 39
+#define CLK_TOP_APLL2_D8 40
+#define CLK_TOP_CLK26M 41
+#define CLK_TOP_CLK26M_D2 42
+#define CLK_TOP_AHB_INFRA_D2 43
+#define CLK_TOP_NFI1X 44
+#define CLK_TOP_ETH_D2 45
+#define CLK_TOP_UART0_SEL 46
+#define CLK_TOP_GFMUX_EMI1X_SEL 47
+#define CLK_TOP_EMI_DDRPHY_SEL 48
+#define CLK_TOP_AHB_INFRA_SEL 49
+#define CLK_TOP_CSW_MUX_MFG_SEL 50
+#define CLK_TOP_MSDC0_SEL 51
+#define CLK_TOP_PWM_MM_SEL 52
+#define CLK_TOP_UART1_SEL 53
+#define CLK_TOP_MSDC1_SEL 54
+#define CLK_TOP_SPM_52M_SEL 55
+#define CLK_TOP_PMICSPI_SEL 56
+#define CLK_TOP_QAXI_AUD26M_SEL 57
+#define CLK_TOP_AUD_INTBUS_SEL 58
+#define CLK_TOP_NFI2X_PAD_SEL 59
+#define CLK_TOP_NFI1X_PAD_SEL 60
+#define CLK_TOP_MFG_MM_SEL 61
+#define CLK_TOP_DDRPHYCFG_SEL 62
+#define CLK_TOP_USB_78M_SEL 63
+#define CLK_TOP_SPINOR_SEL 64
+#define CLK_TOP_MSDC2_SEL 65
+#define CLK_TOP_ETH_SEL 66
+#define CLK_TOP_AXI_MFG_IN_SEL 67
+#define CLK_TOP_SLOW_MFG_SEL 68
+#define CLK_TOP_AUD1_SEL 69
+#define CLK_TOP_AUD2_SEL 70
+#define CLK_TOP_AUD_ENGEN1_SEL 71
+#define CLK_TOP_AUD_ENGEN2_SEL 72
+#define CLK_TOP_I2C_SEL 73
+#define CLK_TOP_AUD_I2S0_M_SEL 74
+#define CLK_TOP_AUD_I2S1_M_SEL 75
+#define CLK_TOP_AUD_I2S2_M_SEL 76
+#define CLK_TOP_AUD_I2S3_M_SEL 77
+#define CLK_TOP_AUD_I2S4_M_SEL 78
+#define CLK_TOP_AUD_I2S5_M_SEL 79
+#define CLK_TOP_AUD_SPDIF_B_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_SPI_SEL 82
+#define CLK_TOP_AUD_SPDIFIN_SEL 83
+#define CLK_TOP_UART2_SEL 84
+#define CLK_TOP_BSI_SEL 85
+#define CLK_TOP_DBG_ATCLK_SEL 86
+#define CLK_TOP_CSW_NFIECC_SEL 87
+#define CLK_TOP_NFIECC_SEL 88
+#define CLK_TOP_APLL12_CK_DIV0 89
+#define CLK_TOP_APLL12_CK_DIV1 90
+#define CLK_TOP_APLL12_CK_DIV2 91
+#define CLK_TOP_APLL12_CK_DIV3 92
+#define CLK_TOP_APLL12_CK_DIV4 93
+#define CLK_TOP_APLL12_CK_DIV4B 94
+#define CLK_TOP_APLL12_CK_DIV5 95
+#define CLK_TOP_APLL12_CK_DIV5B 96
+#define CLK_TOP_APLL12_CK_DIV6 97
+#define CLK_TOP_NR_CLK 98
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM 0
+#define CLK_TOP_MFG_MM 1
+#define CLK_TOP_SPM_52M 2
+#define CLK_TOP_THEM 3
+#define CLK_TOP_APDMA 4
+#define CLK_TOP_I2C0 5
+#define CLK_TOP_I2C1 6
+#define CLK_TOP_AUXADC1 7
+#define CLK_TOP_NFI 8
+#define CLK_TOP_NFIECC 9
+#define CLK_TOP_DEBUGSYS 10
+#define CLK_TOP_PWM 11
+#define CLK_TOP_UART0 12
+#define CLK_TOP_UART1 13
+#define CLK_TOP_BTIF 14
+#define CLK_TOP_USB 15
+#define CLK_TOP_FLASHIF_26M 16
+#define CLK_TOP_AUXADC2 17
+#define CLK_TOP_I2C2 18
+#define CLK_TOP_MSDC0 19
+#define CLK_TOP_MSDC1 20
+#define CLK_TOP_NFI2X 21
+#define CLK_TOP_PMICWRAP_AP 22
+#define CLK_TOP_SEJ 23
+#define CLK_TOP_MEMSLP_DLYER 24
+#define CLK_TOP_SPI 25
+#define CLK_TOP_APXGPT 26
+#define CLK_TOP_AUDIO 27
+#define CLK_TOP_PMICWRAP_MD 28
+#define CLK_TOP_PMICWRAP_CONN 29
+#define CLK_TOP_PMICWRAP_26M 30
+#define CLK_TOP_AUX_ADC 31
+#define CLK_TOP_AUX_TP 32
+#define CLK_TOP_MSDC2 33
+#define CLK_TOP_RBIST 34
+#define CLK_TOP_NFI_BUS 35
+#define CLK_TOP_GCE 36
+#define CLK_TOP_TRNG 37
+#define CLK_TOP_SEJ_13M 38
+#define CLK_TOP_AES 39
+#define CLK_TOP_PWM_B 40
+#define CLK_TOP_PWM1_FB 41
+#define CLK_TOP_PWM2_FB 42
+#define CLK_TOP_PWM3_FB 43
+#define CLK_TOP_PWM4_FB 44
+#define CLK_TOP_PWM5_FB 45
+#define CLK_TOP_USB_1P 46
+#define CLK_TOP_FLASHIF_FREERUN 47
+#define CLK_TOP_66M_ETH 48
+#define CLK_TOP_133M_ETH 49
+#define CLK_TOP_FETH_25M 50
+#define CLK_TOP_FETH_50M 51
+#define CLK_TOP_FLASHIF_AXI 52
+#define CLK_TOP_USBIF 53
+#define CLK_TOP_UART2 54
+#define CLK_TOP_BSI 55
+#define CLK_TOP_MSDC0_INFRA 56
+#define CLK_TOP_MSDC1_INFRA 57
+#define CLK_TOP_MSDC2_INFRA 58
+#define CLK_TOP_USB_78M 59
+#define CLK_TOP_RG_SPINOR 60
+#define CLK_TOP_RG_MSDC2 61
+#define CLK_TOP_RG_ETH 62
+#define CLK_TOP_RG_AXI_MFG 63
+#define CLK_TOP_RG_SLOW_MFG 64
+#define CLK_TOP_RG_AUD1 65
+#define CLK_TOP_RG_AUD2 66
+#define CLK_TOP_RG_AUD_ENGEN1 67
+#define CLK_TOP_RG_AUD_ENGEN2 68
+#define CLK_TOP_RG_I2C 69
+#define CLK_TOP_RG_PWM_INFRA 70
+#define CLK_TOP_RG_AUD_SPDIF_IN 71
+#define CLK_TOP_RG_UART2 72
+#define CLK_TOP_RG_BSI 73
+#define CLK_TOP_RG_DBG_ATCLK 74
+#define CLK_TOP_RG_NFIECC 75
+#define CLK_TOP_RG_APLL1_D2_EN 76
+#define CLK_TOP_RG_APLL1_D4_EN 77
+#define CLK_TOP_RG_APLL1_D8_EN 78
+#define CLK_TOP_RG_APLL2_D2_EN 79
+#define CLK_TOP_RG_APLL2_D4_EN 80
+#define CLK_TOP_RG_APLL2_D8_EN 81
+#define CLK_TOP_APLL12_DIV0 82
+#define CLK_TOP_APLL12_DIV1 83
+#define CLK_TOP_APLL12_DIV2 84
+#define CLK_TOP_APLL12_DIV3 85
+#define CLK_TOP_APLL12_DIV4 86
+#define CLK_TOP_APLL12_DIV4B 87
+#define CLK_TOP_APLL12_DIV5 88
+#define CLK_TOP_APLL12_DIV5B 89
+#define CLK_TOP_APLL12_DIV6 90
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL 0
+#define CLK_IFR_ETH_25M_SEL 1
+#define CLK_IFR_I2C0_SEL 2
+#define CLK_IFR_I2C1_SEL 3
+#define CLK_IFR_I2C2_SEL 4
+#define CLK_IFR_NR_CLK 5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_HDMI 7
+#define CLK_AUD_SPDF 8
+#define CLK_AUD_ADC 9
+#define CLK_AUD_DAC 10
+#define CLK_AUD_DAC_PREDIS 11
+#define CLK_AUD_TML 12
+#define CLK_AUD_NR_CLK 13
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI 0
+#define CLK_MFG_BMEM 1
+#define CLK_MFG_BG3D 2
+#define CLK_MFG_B26M 3
+#define CLK_MFG_NR_CLK 4
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8516.c | 802 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8516-clk.h | 251 ++++++++
3 files changed, 1054 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8516.c
create mode 100644 include/dt-bindings/clock/mt8516-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0632dc87b6..a47a5bdbc2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 0000000000..e07cc59f7f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,802 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX (1502UL * MHZ)
+#define MT8516_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8516_CON0_RST_BAR, \
+ .fmax = MT8516_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+ 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+ 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+ 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+ 31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+ FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+ FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+ FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+ FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_GFMUX_EMI1X_SEL,
+ CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+};
+
+static const int csw_mux_mfg_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D3,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int pwm_mm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+};
+
+static const int uart1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int spm_52m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB_PHY48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+ CLK_TOP_AHB_INFRA_SEL,
+ CLK_TOP_NFI1X,
+};
+
+static const int mfg_mm_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_MUX_MFG_SEL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D3,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D14
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int axi_mfg_in_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_MMPLL380M,
+};
+
+static const int slow_mfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL1_D2_EN,
+ CLK_TOP_RG_APLL1_D4_EN,
+ CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL2_D2_EN,
+ CLK_TOP_RG_APLL2_D4_EN,
+ CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_RG_AUD1,
+ CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_NFI2X_PAD_SEL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+ MUX(CLK_TOP_CSW_MUX_MFG_SEL, csw_mux_mfg_parents, 0x000, 8, 3),
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+ MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
+ MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+ MUX(CLK_TOP_SPM_52M_SEL, spm_52m_parents, 0x000, 23, 1),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+ MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+ MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+ MUX(CLK_TOP_MFG_MM_SEL, mfg_mm_parents, 0x004, 8, 6),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AXI_MFG_IN_SEL, axi_mfg_in_parents, 0x040, 18, 2),
+ MUX(CLK_TOP_SLOW_MFG_SEL, slow_mfg_parents, 0x040, 20, 2),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+ /* CLK_MUX_SEL9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+ MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+ MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+ MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top0_cg_regs = {
+ .set_ofs = 0x50,
+ .clr_ofs = 0x80,
+ .sta_ofs = 0x20,
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xb4,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+#define GATE_TOP0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP0 */
+ GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
+ GATE_TOP0(CLK_TOP_MFG_MM, CLK_TOP_MFG_MM_SEL, 2),
+ GATE_TOP0(CLK_TOP_SPM_52M, CLK_TOP_SPM_52M_SEL, 3),
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+ GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+ GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+ GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AHB_INFRA_SEL, 4),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+ GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+ GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+ GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+ GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+ GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP3(CLK_TOP_RG_AXI_MFG, CLK_TOP_AXI_MFG_IN_SEL, 6),
+ GATE_TOP3(CLK_TOP_RG_SLOW_MFG, CLK_TOP_SLOW_MFG_SEL, 7),
+ GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+ GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+ GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+ GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+ /* TOP4 */
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+ /* TOP5 */
+ GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+ GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+ GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+ GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8516-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8516-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_apmixed_compat,
+ .probe = mt8516_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8516-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_compat,
+ .probe = mt8516_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8516-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_cg_compat,
+ .probe = mt8516_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000000..b62a971c59
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_I2S_INFRA_BCK 1
+#define CLK_TOP_MEMPLL 2
+#define CLK_TOP_DMPLL 3
+#define CLK_TOP_MAINPLL_D2 4
+#define CLK_TOP_MAINPLL_D4 5
+#define CLK_TOP_MAINPLL_D8 6
+#define CLK_TOP_MAINPLL_D16 7
+#define CLK_TOP_MAINPLL_D11 8
+#define CLK_TOP_MAINPLL_D22 9
+#define CLK_TOP_MAINPLL_D3 10
+#define CLK_TOP_MAINPLL_D6 11
+#define CLK_TOP_MAINPLL_D12 12
+#define CLK_TOP_MAINPLL_D5 13
+#define CLK_TOP_MAINPLL_D10 14
+#define CLK_TOP_MAINPLL_D20 15
+#define CLK_TOP_MAINPLL_D40 16
+#define CLK_TOP_MAINPLL_D7 17
+#define CLK_TOP_MAINPLL_D14 18
+#define CLK_TOP_UNIVPLL_D2 19
+#define CLK_TOP_UNIVPLL_D4 20
+#define CLK_TOP_UNIVPLL_D8 21
+#define CLK_TOP_UNIVPLL_D16 22
+#define CLK_TOP_UNIVPLL_D3 23
+#define CLK_TOP_UNIVPLL_D6 24
+#define CLK_TOP_UNIVPLL_D12 25
+#define CLK_TOP_UNIVPLL_D24 26
+#define CLK_TOP_UNIVPLL_D5 27
+#define CLK_TOP_UNIVPLL_D20 28
+#define CLK_TOP_MMPLL380M 29
+#define CLK_TOP_MMPLL_D2 30
+#define CLK_TOP_MMPLL_200M 31
+#define CLK_TOP_USB_PHY48M 32
+#define CLK_TOP_APLL1 33
+#define CLK_TOP_APLL1_D2 34
+#define CLK_TOP_APLL1_D4 35
+#define CLK_TOP_APLL1_D8 36
+#define CLK_TOP_APLL2 37
+#define CLK_TOP_APLL2_D2 38
+#define CLK_TOP_APLL2_D4 39
+#define CLK_TOP_APLL2_D8 40
+#define CLK_TOP_CLK26M 41
+#define CLK_TOP_CLK26M_D2 42
+#define CLK_TOP_AHB_INFRA_D2 43
+#define CLK_TOP_NFI1X 44
+#define CLK_TOP_ETH_D2 45
+#define CLK_TOP_UART0_SEL 46
+#define CLK_TOP_GFMUX_EMI1X_SEL 47
+#define CLK_TOP_EMI_DDRPHY_SEL 48
+#define CLK_TOP_AHB_INFRA_SEL 49
+#define CLK_TOP_CSW_MUX_MFG_SEL 50
+#define CLK_TOP_MSDC0_SEL 51
+#define CLK_TOP_PWM_MM_SEL 52
+#define CLK_TOP_UART1_SEL 53
+#define CLK_TOP_MSDC1_SEL 54
+#define CLK_TOP_SPM_52M_SEL 55
+#define CLK_TOP_PMICSPI_SEL 56
+#define CLK_TOP_QAXI_AUD26M_SEL 57
+#define CLK_TOP_AUD_INTBUS_SEL 58
+#define CLK_TOP_NFI2X_PAD_SEL 59
+#define CLK_TOP_NFI1X_PAD_SEL 60
+#define CLK_TOP_MFG_MM_SEL 61
+#define CLK_TOP_DDRPHYCFG_SEL 62
+#define CLK_TOP_USB_78M_SEL 63
+#define CLK_TOP_SPINOR_SEL 64
+#define CLK_TOP_MSDC2_SEL 65
+#define CLK_TOP_ETH_SEL 66
+#define CLK_TOP_AXI_MFG_IN_SEL 67
+#define CLK_TOP_SLOW_MFG_SEL 68
+#define CLK_TOP_AUD1_SEL 69
+#define CLK_TOP_AUD2_SEL 70
+#define CLK_TOP_AUD_ENGEN1_SEL 71
+#define CLK_TOP_AUD_ENGEN2_SEL 72
+#define CLK_TOP_I2C_SEL 73
+#define CLK_TOP_AUD_I2S0_M_SEL 74
+#define CLK_TOP_AUD_I2S1_M_SEL 75
+#define CLK_TOP_AUD_I2S2_M_SEL 76
+#define CLK_TOP_AUD_I2S3_M_SEL 77
+#define CLK_TOP_AUD_I2S4_M_SEL 78
+#define CLK_TOP_AUD_I2S5_M_SEL 79
+#define CLK_TOP_AUD_SPDIF_B_SEL 80
+#define CLK_TOP_PWM_SEL 81
+#define CLK_TOP_SPI_SEL 82
+#define CLK_TOP_AUD_SPDIFIN_SEL 83
+#define CLK_TOP_UART2_SEL 84
+#define CLK_TOP_BSI_SEL 85
+#define CLK_TOP_DBG_ATCLK_SEL 86
+#define CLK_TOP_CSW_NFIECC_SEL 87
+#define CLK_TOP_NFIECC_SEL 88
+#define CLK_TOP_APLL12_CK_DIV0 89
+#define CLK_TOP_APLL12_CK_DIV1 90
+#define CLK_TOP_APLL12_CK_DIV2 91
+#define CLK_TOP_APLL12_CK_DIV3 92
+#define CLK_TOP_APLL12_CK_DIV4 93
+#define CLK_TOP_APLL12_CK_DIV4B 94
+#define CLK_TOP_APLL12_CK_DIV5 95
+#define CLK_TOP_APLL12_CK_DIV5B 96
+#define CLK_TOP_APLL12_CK_DIV6 97
+#define CLK_TOP_NR_CLK 98
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_PWM_MM 0
+#define CLK_TOP_MFG_MM 1
+#define CLK_TOP_SPM_52M 2
+#define CLK_TOP_THEM 3
+#define CLK_TOP_APDMA 4
+#define CLK_TOP_I2C0 5
+#define CLK_TOP_I2C1 6
+#define CLK_TOP_AUXADC1 7
+#define CLK_TOP_NFI 8
+#define CLK_TOP_NFIECC 9
+#define CLK_TOP_DEBUGSYS 10
+#define CLK_TOP_PWM 11
+#define CLK_TOP_UART0 12
+#define CLK_TOP_UART1 13
+#define CLK_TOP_BTIF 14
+#define CLK_TOP_USB 15
+#define CLK_TOP_FLASHIF_26M 16
+#define CLK_TOP_AUXADC2 17
+#define CLK_TOP_I2C2 18
+#define CLK_TOP_MSDC0 19
+#define CLK_TOP_MSDC1 20
+#define CLK_TOP_NFI2X 21
+#define CLK_TOP_PMICWRAP_AP 22
+#define CLK_TOP_SEJ 23
+#define CLK_TOP_MEMSLP_DLYER 24
+#define CLK_TOP_SPI 25
+#define CLK_TOP_APXGPT 26
+#define CLK_TOP_AUDIO 27
+#define CLK_TOP_PMICWRAP_MD 28
+#define CLK_TOP_PMICWRAP_CONN 29
+#define CLK_TOP_PMICWRAP_26M 30
+#define CLK_TOP_AUX_ADC 31
+#define CLK_TOP_AUX_TP 32
+#define CLK_TOP_MSDC2 33
+#define CLK_TOP_RBIST 34
+#define CLK_TOP_NFI_BUS 35
+#define CLK_TOP_GCE 36
+#define CLK_TOP_TRNG 37
+#define CLK_TOP_SEJ_13M 38
+#define CLK_TOP_AES 39
+#define CLK_TOP_PWM_B 40
+#define CLK_TOP_PWM1_FB 41
+#define CLK_TOP_PWM2_FB 42
+#define CLK_TOP_PWM3_FB 43
+#define CLK_TOP_PWM4_FB 44
+#define CLK_TOP_PWM5_FB 45
+#define CLK_TOP_USB_1P 46
+#define CLK_TOP_FLASHIF_FREERUN 47
+#define CLK_TOP_66M_ETH 48
+#define CLK_TOP_133M_ETH 49
+#define CLK_TOP_FETH_25M 50
+#define CLK_TOP_FETH_50M 51
+#define CLK_TOP_FLASHIF_AXI 52
+#define CLK_TOP_USBIF 53
+#define CLK_TOP_UART2 54
+#define CLK_TOP_BSI 55
+#define CLK_TOP_MSDC0_INFRA 56
+#define CLK_TOP_MSDC1_INFRA 57
+#define CLK_TOP_MSDC2_INFRA 58
+#define CLK_TOP_USB_78M 59
+#define CLK_TOP_RG_SPINOR 60
+#define CLK_TOP_RG_MSDC2 61
+#define CLK_TOP_RG_ETH 62
+#define CLK_TOP_RG_AXI_MFG 63
+#define CLK_TOP_RG_SLOW_MFG 64
+#define CLK_TOP_RG_AUD1 65
+#define CLK_TOP_RG_AUD2 66
+#define CLK_TOP_RG_AUD_ENGEN1 67
+#define CLK_TOP_RG_AUD_ENGEN2 68
+#define CLK_TOP_RG_I2C 69
+#define CLK_TOP_RG_PWM_INFRA 70
+#define CLK_TOP_RG_AUD_SPDIF_IN 71
+#define CLK_TOP_RG_UART2 72
+#define CLK_TOP_RG_BSI 73
+#define CLK_TOP_RG_DBG_ATCLK 74
+#define CLK_TOP_RG_NFIECC 75
+#define CLK_TOP_RG_APLL1_D2_EN 76
+#define CLK_TOP_RG_APLL1_D4_EN 77
+#define CLK_TOP_RG_APLL1_D8_EN 78
+#define CLK_TOP_RG_APLL2_D2_EN 79
+#define CLK_TOP_RG_APLL2_D4_EN 80
+#define CLK_TOP_RG_APLL2_D8_EN 81
+#define CLK_TOP_APLL12_DIV0 82
+#define CLK_TOP_APLL12_DIV1 83
+#define CLK_TOP_APLL12_DIV2 84
+#define CLK_TOP_APLL12_DIV3 85
+#define CLK_TOP_APLL12_DIV4 86
+#define CLK_TOP_APLL12_DIV4B 87
+#define CLK_TOP_APLL12_DIV5 88
+#define CLK_TOP_APLL12_DIV5B 89
+#define CLK_TOP_APLL12_DIV6 90
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL 0
+#define CLK_IFR_ETH_25M_SEL 1
+#define CLK_IFR_I2C0_SEL 2
+#define CLK_IFR_I2C1_SEL 3
+#define CLK_IFR_I2C2_SEL 4
+#define CLK_IFR_NR_CLK 5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_HDMI 7
+#define CLK_AUD_SPDF 8
+#define CLK_AUD_ADC 9
+#define CLK_AUD_DAC 10
+#define CLK_AUD_DAC_PREDIS 11
+#define CLK_AUD_TML 12
+#define CLK_AUD_NR_CLK 13
+
+/* MFGCFG */
+
+#define CLK_MFG_BAXI 0
+#define CLK_MFG_BMEM 1
+#define CLK_MFG_BG3D 2
+#define CLK_MFG_B26M 3
+#define CLK_MFG_NR_CLK 4
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8516.c | 701 +++++++++++++++++++++++++
include/dt-bindings/clock/mt8516-clk.h | 230 ++++++++
3 files changed, 932 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8516.c
create mode 100644 include/dt-bindings/clock/mt8516-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 0632dc87b6..a47a5bdbc2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
+obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
new file mode 100644
index 0000000000..1b060258d8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -0,0 +1,701 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8516 SoC
+ *
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt8516-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT8516_PLL_FMAX (1502UL * MHZ)
+#define MT8516_CON0_RST_BAR BIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT8516_CON0_RST_BAR, \
+ .fmax = MT8516_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001, 0,
+ 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001, 0,
+ 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001, 0,
+ 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001, 0,
+ 31, 0x01A0, 1, 0x01A4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
+ FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, CLK_TOP_CLK_NULL, 26000000),
+ FIXED_CLK(CLK_TOP_MEMPLL, CLK_TOP_CLK26M, 800000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
+ FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
+ FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
+ FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
+ FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
+ FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
+ FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
+ FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
+ FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
+ FACTOR0(CLK_TOP_MMPLL380M, CLK_APMIXED_MMPLL, 1, 1),
+ FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
+ FACTOR0(CLK_TOP_MMPLL_200M, CLK_APMIXED_MMPLL, 1, 3),
+ FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
+ FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
+ FACTOR1(CLK_TOP_APLL1_D2, CLK_TOP_APLL1, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_RG_APLL1_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL1_D8, CLK_TOP_RG_APLL1_D4_EN, 1, 2),
+ FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
+ FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_RG_APLL2_D2_EN, 1, 2),
+ FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_RG_APLL2_D4_EN, 1, 2),
+ FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
+ FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
+ FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AHB_INFRA_SEL, 1, 2),
+ FACTOR1(CLK_TOP_NFI1X, CLK_TOP_NFI2X_PAD_SEL, 1, 2),
+ FACTOR1(CLK_TOP_ETH_D2, CLK_TOP_ETH_SEL, 1, 2),
+};
+
+static const int uart0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int gfmux_emi1x_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_DMPLL,
+};
+
+static const int emi_ddrphy_parents[] = {
+ CLK_TOP_GFMUX_EMI1X_SEL,
+ CLK_TOP_GFMUX_EMI1X_SEL,
+};
+
+static const int ahb_infra_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D11,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+};
+
+static const int msdc0_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int uart1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24,
+};
+
+static const int msdc1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2,
+};
+
+static const int pmicspi_parents[] = {
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_USB_PHY48M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK26M,
+};
+
+static const int qaxi_aud26m_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_AHB_INFRA_SEL,
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D22,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D11,
+};
+
+static const int nfi2x_pad_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfi1x_pad_parents[] = {
+ CLK_TOP_AHB_INFRA_SEL,
+ CLK_TOP_NFI1X,
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D16
+};
+
+static const int usb_78m_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D20,
+};
+
+static const int spinor_parents[] = {
+ CLK_TOP_CLK26M_D2,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int msdc2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D6,
+ CLK_TOP_MAINPLL_D8,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_MAINPLL_D16,
+ CLK_TOP_MMPLL_200M,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MMPLL_D2
+};
+
+static const int eth_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D40,
+ CLK_TOP_UNIVPLL_D24,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int aud1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL1
+};
+
+static const int aud2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_APLL2
+};
+
+static const int aud_engen1_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL1_D2_EN,
+ CLK_TOP_RG_APLL1_D4_EN,
+ CLK_TOP_RG_APLL1_D8_EN
+};
+
+static const int aud_engen2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_RG_APLL2_D2_EN,
+ CLK_TOP_RG_APLL2_D4_EN,
+ CLK_TOP_RG_APLL2_D8_EN
+};
+
+static const int i2c_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D20,
+ CLK_TOP_UNIVPLL_D16,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int aud_i2s0_m_parents[] = {
+ CLK_TOP_RG_AUD1,
+ CLK_TOP_RG_AUD2
+};
+
+static const int pwm_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12
+};
+
+static const int spi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D12,
+ CLK_TOP_UNIVPLL_D8,
+ CLK_TOP_UNIVPLL_D6
+};
+
+static const int aud_spdifin_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D2
+};
+
+static const int uart2_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_UNIVPLL_D24
+};
+
+static const int bsi_parents[] = {
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D10,
+ CLK_TOP_MAINPLL_D12,
+ CLK_TOP_MAINPLL_D20
+};
+
+static const int dbg_atclk_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CLK26M,
+ CLK_TOP_MAINPLL_D5,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_UNIVPLL_D5
+};
+
+static const int csw_nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D7,
+ CLK_TOP_MAINPLL_D6,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_MAINPLL_D5
+};
+
+static const int nfiecc_parents[] = {
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_NFI2X_PAD_SEL,
+ CLK_TOP_MAINPLL_D4,
+ CLK_TOP_CLK_NULL,
+ CLK_TOP_CSW_NFIECC_SEL,
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_MUX_SEL0 */
+ MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
+ MUX(CLK_TOP_GFMUX_EMI1X_SEL, gfmux_emi1x_parents, 0x000, 1, 1),
+ MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
+ MUX(CLK_TOP_AHB_INFRA_SEL, ahb_infra_parents, 0x000, 4, 4),
+ MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0x000, 11, 3),
+ MUX(CLK_TOP_UART1_SEL, uart1_parents, 0x000, 19, 1),
+ MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 20, 3),
+ MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 24, 2),
+ MUX(CLK_TOP_QAXI_AUD26M_SEL, qaxi_aud26m_parents, 0x000, 26, 1),
+ MUX(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x000, 27, 3),
+ /* CLK_MUX_SEL1 */
+ MUX(CLK_TOP_NFI2X_PAD_SEL, nfi2x_pad_parents, 0x004, 0, 7),
+ MUX(CLK_TOP_NFI1X_PAD_SEL, nfi1x_pad_parents, 0x004, 7, 1),
+ MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
+ MUX(CLK_TOP_USB_78M_SEL, usb_78m_parents, 0x004, 20, 3),
+ /* CLK_MUX_SEL8 */
+ MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
+ MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0x040, 3, 3),
+ MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
+ MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
+ MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
+ MUX(CLK_TOP_AUD_ENGEN1_SEL, aud_engen1_parents, 0x040, 24, 2),
+ MUX(CLK_TOP_AUD_ENGEN2_SEL, aud_engen2_parents, 0x040, 26, 2),
+ MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 2),
+ /* CLK_MUX_SEL9 */
+ MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
+ MUX(CLK_TOP_AUD_I2S1_M_SEL, aud_i2s0_m_parents, 0x044, 13, 1),
+ MUX(CLK_TOP_AUD_I2S2_M_SEL, aud_i2s0_m_parents, 0x044, 14, 1),
+ MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
+ MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
+ MUX(CLK_TOP_AUD_I2S5_M_SEL, aud_i2s0_m_parents, 0x044, 17, 1),
+ MUX(CLK_TOP_AUD_SPDIF_B_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
+ /* CLK_MUX_SEL13 */
+ MUX(CLK_TOP_PWM_SEL, pwm_parents, 0x07c, 0, 1),
+ MUX(CLK_TOP_SPI_SEL, spi_parents, 0x07c, 1, 2),
+ MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 3, 1),
+ MUX(CLK_TOP_UART2_SEL, uart2_parents, 0x07c, 4, 1),
+ MUX(CLK_TOP_BSI_SEL, bsi_parents, 0x07c, 5, 2),
+ MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
+ MUX(CLK_TOP_CSW_NFIECC_SEL, csw_nfiecc_parents, 0x07c, 10, 3),
+ MUX(CLK_TOP_NFIECC_SEL, nfiecc_parents, 0x07c, 13, 3),
+};
+
+static const struct mtk_gate_regs top1_cg_regs = {
+ .set_ofs = 0x54,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x24,
+};
+
+static const struct mtk_gate_regs top2_cg_regs = {
+ .set_ofs = 0x6c,
+ .clr_ofs = 0x9c,
+ .sta_ofs = 0x3c,
+};
+
+static const struct mtk_gate_regs top3_cg_regs = {
+ .set_ofs = 0xa0,
+ .clr_ofs = 0xb0,
+ .sta_ofs = 0x70,
+};
+
+static const struct mtk_gate_regs top4_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xb4,
+ .sta_ofs = 0x74,
+};
+
+static const struct mtk_gate_regs top5_cg_regs = {
+ .set_ofs = 0x44,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x44,
+};
+
+#define GATE_TOP1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP2_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top2_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP3(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top3_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP4_I(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top4_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_TOP5(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &top5_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate top_clks[] = {
+ /* TOP1 */
+ GATE_TOP1(CLK_TOP_THEM, CLK_TOP_AHB_INFRA_SEL, 1),
+ GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP1(CLK_TOP_I2C0, CLK_IFR_I2C0_SEL, 3),
+ GATE_TOP1(CLK_TOP_I2C1, CLK_IFR_I2C1_SEL, 4),
+ GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_PAD_SEL, 6),
+ GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_RG_NFIECC, 7),
+ GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_RG_DBG_ATCLK, 8),
+ GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AHB_INFRA_SEL, 9),
+ GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
+ GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
+ GATE_TOP1(CLK_TOP_BTIF, CLK_TOP_AHB_INFRA_SEL, 12),
+ GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_78M, 13),
+ GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
+ GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP1(CLK_TOP_I2C2, CLK_IFR_I2C2_SEL, 16),
+ GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
+ GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
+ GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_PAD_SEL, 19),
+ GATE_TOP1(CLK_TOP_PMICWRAP_AP, CLK_TOP_CLK26M, 20),
+ GATE_TOP1(CLK_TOP_SEJ, CLK_TOP_AHB_INFRA_SEL, 21),
+ GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
+ GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI_SEL, 23),
+ GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
+ GATE_TOP1(CLK_TOP_AUDIO, CLK_TOP_CLK26M, 25),
+ GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
+ GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_CLK26M, 28),
+ GATE_TOP1(CLK_TOP_PMICWRAP_26M, CLK_TOP_CLK26M, 29),
+ GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
+ GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
+ /* TOP2 */
+ GATE_TOP2(CLK_TOP_MSDC2, CLK_TOP_AHB_INFRA_SEL, 0),
+ GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
+ GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AHB_INFRA_SEL, 2),
+ GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AHB_INFRA_SEL, 5),
+ GATE_TOP2(CLK_TOP_SEJ_13M, CLK_TOP_CLK26M, 6),
+ GATE_TOP2(CLK_TOP_AES, CLK_TOP_AHB_INFRA_SEL, 7),
+ GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_RG_PWM_INFRA, 8),
+ GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_RG_PWM_INFRA, 9),
+ GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_RG_PWM_INFRA, 10),
+ GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_RG_PWM_INFRA, 11),
+ GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_RG_PWM_INFRA, 12),
+ GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_RG_PWM_INFRA, 13),
+ GATE_TOP2(CLK_TOP_USB_1P, CLK_TOP_USB_78M, 14),
+ GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AHB_INFRA_SEL, 15),
+ GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AHB_INFRA_D2, 19),
+ GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AHB_INFRA_SEL, 20),
+ GATE_TOP2(CLK_TOP_FETH_25M, CLK_IFR_ETH_25M_SEL, 21),
+ GATE_TOP2(CLK_TOP_FETH_50M, CLK_TOP_RG_ETH, 22),
+ GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_AHB_INFRA_SEL, 23),
+ GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AHB_INFRA_SEL, 24),
+ GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
+ GATE_TOP2(CLK_TOP_BSI, CLK_TOP_AHB_INFRA_SEL, 26),
+ GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, CLK_TOP_MSDC0, 28),
+ GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, CLK_TOP_MSDC1, 29),
+ GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, CLK_TOP_RG_MSDC2, 30),
+ GATE_TOP2(CLK_TOP_USB_78M, CLK_TOP_USB_78M_SEL, 31),
+ /* TOP3 */
+ GATE_TOP3(CLK_TOP_RG_SPINOR, CLK_TOP_SPINOR_SEL, 0),
+ GATE_TOP3(CLK_TOP_RG_MSDC2, CLK_TOP_MSDC2_SEL, 1),
+ GATE_TOP3(CLK_TOP_RG_ETH, CLK_TOP_ETH_SEL, 2),
+ GATE_TOP3(CLK_TOP_RG_AUD1, CLK_TOP_AUD1_SEL, 8),
+ GATE_TOP3(CLK_TOP_RG_AUD2, CLK_TOP_AUD2_SEL, 9),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, CLK_TOP_AUD_ENGEN1_SEL, 10),
+ GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, CLK_TOP_AUD_ENGEN2_SEL, 11),
+ GATE_TOP3(CLK_TOP_RG_I2C, CLK_TOP_I2C_SEL, 12),
+ GATE_TOP3(CLK_TOP_RG_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
+ GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
+ GATE_TOP3(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
+ GATE_TOP3(CLK_TOP_RG_BSI, CLK_TOP_BSI_SEL, 16),
+ GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, CLK_TOP_DBG_ATCLK_SEL, 17),
+ GATE_TOP3(CLK_TOP_RG_NFIECC, CLK_TOP_NFIECC_SEL, 18),
+ /* TOP4 */
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, CLK_TOP_APLL1_D2, 8),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, CLK_TOP_APLL1_D4, 9),
+ GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, CLK_TOP_APLL1_D8, 10),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, CLK_TOP_APLL2_D2, 11),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, CLK_TOP_APLL2_D4, 12),
+ GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, CLK_TOP_APLL2_D8, 13),
+ /* TOP5 */
+ GATE_TOP5(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
+ GATE_TOP5(CLK_TOP_APLL12_DIV1, CLK_TOP_APLL12_CK_DIV1, 1),
+ GATE_TOP5(CLK_TOP_APLL12_DIV2, CLK_TOP_APLL12_CK_DIV2, 2),
+ GATE_TOP5(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
+ GATE_TOP5(CLK_TOP_APLL12_DIV4B, CLK_TOP_APLL12_CK_DIV4B, 5),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5, CLK_TOP_APLL12_CK_DIV5, 6),
+ GATE_TOP5(CLK_TOP_APLL12_DIV5B, CLK_TOP_APLL12_CK_DIV5B, 7),
+ GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+ .xtal_rate = 26 * MHZ,
+ .xtal2_rate = 26 * MHZ,
+ .fdivs_offs = CLK_TOP_DMPLL,
+ .muxes_offs = CLK_TOP_UART0_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt8516_apmixedsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt8516_clk_tree);
+}
+
+static int mt8516_topckgen_cg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks);
+}
+
+static const struct udevice_id mt8516_apmixed_compat[] = {
+ { .compatible = "mediatek,mt8516-apmixedsys", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen", },
+ { }
+};
+
+static const struct udevice_id mt8516_topckgen_cg_compat[] = {
+ { .compatible = "mediatek,mt8516-topckgen-cg", },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt8516-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_apmixed_compat,
+ .probe = mt8516_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt8516-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_compat,
+ .probe = mt8516_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+ .name = "mt8516-topckgen-cg",
+ .id = UCLASS_CLK,
+ .of_match = mt8516_topckgen_cg_compat,
+ .probe = mt8516_topckgen_cg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
new file mode 100644
index 0000000000..0efccbab21
--- /dev/null
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 BayLibre, SAS
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8516_H
+#define _DT_BINDINGS_CLK_MT8516_H
+
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
+/* TOPCKGEN */
+
+#define CLK_TOP_CLK_NULL 0
+#define CLK_TOP_I2S_INFRA_BCK 1
+#define CLK_TOP_MEMPLL 2
+#define CLK_TOP_DMPLL 3
+#define CLK_TOP_MAINPLL_D2 4
+#define CLK_TOP_MAINPLL_D4 5
+#define CLK_TOP_MAINPLL_D8 6
+#define CLK_TOP_MAINPLL_D16 7
+#define CLK_TOP_MAINPLL_D11 8
+#define CLK_TOP_MAINPLL_D22 9
+#define CLK_TOP_MAINPLL_D3 10
+#define CLK_TOP_MAINPLL_D6 11
+#define CLK_TOP_MAINPLL_D12 12
+#define CLK_TOP_MAINPLL_D5 13
+#define CLK_TOP_MAINPLL_D10 14
+#define CLK_TOP_MAINPLL_D20 15
+#define CLK_TOP_MAINPLL_D40 16
+#define CLK_TOP_MAINPLL_D7 17
+#define CLK_TOP_MAINPLL_D14 18
+#define CLK_TOP_UNIVPLL_D2 19
+#define CLK_TOP_UNIVPLL_D4 20
+#define CLK_TOP_UNIVPLL_D8 21
+#define CLK_TOP_UNIVPLL_D16 22
+#define CLK_TOP_UNIVPLL_D3 23
+#define CLK_TOP_UNIVPLL_D6 24
+#define CLK_TOP_UNIVPLL_D12 25
+#define CLK_TOP_UNIVPLL_D24 26
+#define CLK_TOP_UNIVPLL_D5 27
+#define CLK_TOP_UNIVPLL_D20 28
+#define CLK_TOP_MMPLL380M 29
+#define CLK_TOP_MMPLL_D2 30
+#define CLK_TOP_MMPLL_200M 31
+#define CLK_TOP_USB_PHY48M 32
+#define CLK_TOP_APLL1 33
+#define CLK_TOP_APLL1_D2 34
+#define CLK_TOP_APLL1_D4 35
+#define CLK_TOP_APLL1_D8 36
+#define CLK_TOP_APLL2 37
+#define CLK_TOP_APLL2_D2 38
+#define CLK_TOP_APLL2_D4 39
+#define CLK_TOP_APLL2_D8 40
+#define CLK_TOP_CLK26M 41
+#define CLK_TOP_CLK26M_D2 42
+#define CLK_TOP_AHB_INFRA_D2 43
+#define CLK_TOP_NFI1X 44
+#define CLK_TOP_ETH_D2 45
+#define CLK_TOP_UART0_SEL 46
+#define CLK_TOP_GFMUX_EMI1X_SEL 47
+#define CLK_TOP_EMI_DDRPHY_SEL 48
+#define CLK_TOP_AHB_INFRA_SEL 49
+#define CLK_TOP_MSDC0_SEL 50
+#define CLK_TOP_UART1_SEL 51
+#define CLK_TOP_MSDC1_SEL 52
+#define CLK_TOP_PMICSPI_SEL 53
+#define CLK_TOP_QAXI_AUD26M_SEL 54
+#define CLK_TOP_AUD_INTBUS_SEL 55
+#define CLK_TOP_NFI2X_PAD_SEL 56
+#define CLK_TOP_NFI1X_PAD_SEL 57
+#define CLK_TOP_DDRPHYCFG_SEL 58
+#define CLK_TOP_USB_78M_SEL 59
+#define CLK_TOP_SPINOR_SEL 60
+#define CLK_TOP_MSDC2_SEL 61
+#define CLK_TOP_ETH_SEL 62
+#define CLK_TOP_AUD1_SEL 63
+#define CLK_TOP_AUD2_SEL 64
+#define CLK_TOP_AUD_ENGEN1_SEL 65
+#define CLK_TOP_AUD_ENGEN2_SEL 66
+#define CLK_TOP_I2C_SEL 67
+#define CLK_TOP_AUD_I2S0_M_SEL 68
+#define CLK_TOP_AUD_I2S1_M_SEL 69
+#define CLK_TOP_AUD_I2S2_M_SEL 70
+#define CLK_TOP_AUD_I2S3_M_SEL 71
+#define CLK_TOP_AUD_I2S4_M_SEL 72
+#define CLK_TOP_AUD_I2S5_M_SEL 73
+#define CLK_TOP_AUD_SPDIF_B_SEL 74
+#define CLK_TOP_PWM_SEL 75
+#define CLK_TOP_SPI_SEL 76
+#define CLK_TOP_AUD_SPDIFIN_SEL 77
+#define CLK_TOP_UART2_SEL 78
+#define CLK_TOP_BSI_SEL 79
+#define CLK_TOP_DBG_ATCLK_SEL 80
+#define CLK_TOP_CSW_NFIECC_SEL 81
+#define CLK_TOP_NFIECC_SEL 82
+#define CLK_TOP_APLL12_CK_DIV0 83
+#define CLK_TOP_APLL12_CK_DIV1 84
+#define CLK_TOP_APLL12_CK_DIV2 85
+#define CLK_TOP_APLL12_CK_DIV3 86
+#define CLK_TOP_APLL12_CK_DIV4 87
+#define CLK_TOP_APLL12_CK_DIV4B 88
+#define CLK_TOP_APLL12_CK_DIV5 89
+#define CLK_TOP_APLL12_CK_DIV5B 90
+#define CLK_TOP_APLL12_CK_DIV6 91
+#define CLK_TOP_NR_CLK 92
+
+/* TOPCKGEN Gates */
+#define CLK_TOP_THEM 0
+#define CLK_TOP_APDMA 1
+#define CLK_TOP_I2C0 2
+#define CLK_TOP_I2C1 3
+#define CLK_TOP_AUXADC1 4
+#define CLK_TOP_NFI 5
+#define CLK_TOP_NFIECC 6
+#define CLK_TOP_DEBUGSYS 7
+#define CLK_TOP_PWM 8
+#define CLK_TOP_UART0 9
+#define CLK_TOP_UART1 10
+#define CLK_TOP_BTIF 11
+#define CLK_TOP_USB 12
+#define CLK_TOP_FLASHIF_26M 13
+#define CLK_TOP_AUXADC2 14
+#define CLK_TOP_I2C2 15
+#define CLK_TOP_MSDC0 16
+#define CLK_TOP_MSDC1 17
+#define CLK_TOP_NFI2X 18
+#define CLK_TOP_PMICWRAP_AP 19
+#define CLK_TOP_SEJ 20
+#define CLK_TOP_MEMSLP_DLYER 21
+#define CLK_TOP_SPI 22
+#define CLK_TOP_APXGPT 23
+#define CLK_TOP_AUDIO 24
+#define CLK_TOP_PMICWRAP_MD 25
+#define CLK_TOP_PMICWRAP_CONN 26
+#define CLK_TOP_PMICWRAP_26M 27
+#define CLK_TOP_AUX_ADC 28
+#define CLK_TOP_AUX_TP 29
+#define CLK_TOP_MSDC2 30
+#define CLK_TOP_RBIST 31
+#define CLK_TOP_NFI_BUS 32
+#define CLK_TOP_TRNG 33
+#define CLK_TOP_SEJ_13M 34
+#define CLK_TOP_AES 35
+#define CLK_TOP_PWM_B 36
+#define CLK_TOP_PWM1_FB 37
+#define CLK_TOP_PWM2_FB 38
+#define CLK_TOP_PWM3_FB 39
+#define CLK_TOP_PWM4_FB 40
+#define CLK_TOP_PWM5_FB 41
+#define CLK_TOP_USB_1P 42
+#define CLK_TOP_FLASHIF_FREERUN 43
+#define CLK_TOP_66M_ETH 44
+#define CLK_TOP_133M_ETH 45
+#define CLK_TOP_FETH_25M 46
+#define CLK_TOP_FETH_50M 47
+#define CLK_TOP_FLASHIF_AXI 48
+#define CLK_TOP_USBIF 49
+#define CLK_TOP_UART2 50
+#define CLK_TOP_BSI 51
+#define CLK_TOP_MSDC0_INFRA 52
+#define CLK_TOP_MSDC1_INFRA 53
+#define CLK_TOP_MSDC2_INFRA 54
+#define CLK_TOP_USB_78M 55
+#define CLK_TOP_RG_SPINOR 56
+#define CLK_TOP_RG_MSDC2 57
+#define CLK_TOP_RG_ETH 58
+#define CLK_TOP_RG_AUD1 59
+#define CLK_TOP_RG_AUD2 60
+#define CLK_TOP_RG_AUD_ENGEN1 61
+#define CLK_TOP_RG_AUD_ENGEN2 62
+#define CLK_TOP_RG_I2C 63
+#define CLK_TOP_RG_PWM_INFRA 64
+#define CLK_TOP_RG_AUD_SPDIF_IN 65
+#define CLK_TOP_RG_UART2 66
+#define CLK_TOP_RG_BSI 67
+#define CLK_TOP_RG_DBG_ATCLK 68
+#define CLK_TOP_RG_NFIECC 69
+#define CLK_TOP_RG_APLL1_D2_EN 70
+#define CLK_TOP_RG_APLL1_D4_EN 71
+#define CLK_TOP_RG_APLL1_D8_EN 72
+#define CLK_TOP_RG_APLL2_D2_EN 73
+#define CLK_TOP_RG_APLL2_D4_EN 74
+#define CLK_TOP_RG_APLL2_D8_EN 75
+#define CLK_TOP_APLL12_DIV0 76
+#define CLK_TOP_APLL12_DIV1 77
+#define CLK_TOP_APLL12_DIV2 78
+#define CLK_TOP_APLL12_DIV3 79
+#define CLK_TOP_APLL12_DIV4 80
+#define CLK_TOP_APLL12_DIV4B 81
+#define CLK_TOP_APLL12_DIV5 82
+#define CLK_TOP_APLL12_DIV5B 83
+#define CLK_TOP_APLL12_DIV6 84
+
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL 0
+#define CLK_IFR_ETH_25M_SEL 1
+#define CLK_IFR_I2C0_SEL 2
+#define CLK_IFR_I2C1_SEL 3
+#define CLK_IFR_I2C2_SEL 4
+#define CLK_IFR_NR_CLK 5
+
+/* AUDIOTOP */
+
+#define CLK_AUD_AFE 0
+#define CLK_AUD_I2S 1
+#define CLK_AUD_22M 2
+#define CLK_AUD_24M 3
+#define CLK_AUD_INTDIR 4
+#define CLK_AUD_APLL2_TUNER 5
+#define CLK_AUD_APLL_TUNER 6
+#define CLK_AUD_SPDF 7
+#define CLK_AUD_ADC 8
+#define CLK_AUD_DAC 9
+#define CLK_AUD_DAC_PREDIS 10
+#define CLK_AUD_TML 11
+#define CLK_AUD_NR_CLK 12
+
+#endif /* _DT_BINDINGS_CLK_MT8516_H */
--
2.20.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [U-Boot] [PATCH v3 6/7] pinctrl: add driver for MT8516
2019-03-24 15:46 [U-Boot] [PATCH v3 0/7] Add support for MT8516 SoC Fabien Parent
` (4 preceding siblings ...)
2019-03-24 15:46 ` [U-Boot] [PATCH v3 5/7] clk: mediatek: add driver for MT8516 Fabien Parent
@ 2019-03-24 15:46 ` Fabien Parent
2019-04-24 13:30 ` [U-Boot] [U-Boot,v3,6/7] " Tom Rini
2019-03-24 15:46 ` [U-Boot] [PATCH v3 7/7] ARM: MediaTek: Add support for MT8516 SoC Fabien Parent
6 siblings, 1 reply; 15+ messages in thread
From: Fabien Parent @ 2019-03-24 15:46 UTC (permalink / raw)
To: u-boot
Add Pinctrl driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
v3:
* Fix incorrect field size for mt8516_pin_mode_range
v2:
* No change
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 391 ++++++++++++++++++++++
3 files changed, 396 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8516.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 1bd9a925a5..9930ca1faf 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,4 +12,8 @@ config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8516
+ bool "MT8516 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index f6ef3627e8..c4f29088d2 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
new file mode 100644
index 0000000000..829b30e5a2
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 BayLibre, SAS
+ * Author: Fabien Parent <fparent@baylibre.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8516_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 124, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_dir_range[] = {
+ PIN_FIELD(0, 124, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_di_range[] = {
+ PIN_FIELD(0, 124, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_do_range[] = {
+ PIN_FIELD(0, 124, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_ies_range[] = {
+ PIN_FIELD(0, 6, 0x900, 0x10, 2, 1),
+ PIN_FIELD(7, 10, 0x900, 0x10, 3, 1),
+ PIN_FIELD(11, 13, 0x900, 0x10, 12, 1),
+ PIN_FIELD(14, 17, 0x900, 0x10, 13, 1),
+ PIN_FIELD(18, 20, 0x910, 0x10, 10, 1),
+ PIN_FIELD(21, 23, 0x900, 0x10, 13, 1),
+ PIN_FIELD(24, 25, 0x900, 0x10, 12, 1),
+ PIN_FIELD(26, 30, 0x900, 0x10, 0, 1),
+ PIN_FIELD(31, 33, 0x900, 0x10, 1, 1),
+ PIN_FIELD(34, 39, 0x900, 0x10, 2, 1),
+ PIN_FIELD(40, 40, 0x910, 0x10, 11, 1),
+ PIN_FIELD(41, 43, 0x900, 0x10, 10, 1),
+ PIN_FIELD(44, 47, 0x900, 0x10, 11, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 14, 1),
+ PIN_FIELD(52, 53, 0x910, 0x10, 0, 1),
+ PIN_FIELD(54, 54, 0x910, 0x10, 2, 1),
+ PIN_FIELD(55, 57, 0x910, 0x10, 4, 1),
+ PIN_FIELD(58, 59, 0x900, 0x10, 15, 1),
+ PIN_FIELD(60, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 65, 0x910, 0x10, 5, 1),
+ PIN_FIELD(66, 67, 0x910, 0x10, 6, 1),
+ PIN_FIELD(68, 68, 0x930, 0x10, 2, 1),
+ PIN_FIELD(69, 69, 0x930, 0x10, 1, 1),
+ PIN_FIELD(70, 70, 0x930, 0x10, 6, 1),
+ PIN_FIELD(71, 71, 0x930, 0x10, 5, 1),
+ PIN_FIELD(72, 72, 0x930, 0x10, 4, 1),
+ PIN_FIELD(73, 73, 0x930, 0x10, 3, 1),
+
+ PIN_FIELD(100, 103, 0x910, 0x10, 7, 1),
+ PIN_FIELD(104, 104, 0x920, 0x10, 12, 1),
+ PIN_FIELD(105, 105, 0x920, 0x10, 11, 1),
+ PIN_FIELD(106, 106, 0x930, 0x10, 0, 1),
+ PIN_FIELD(107, 107, 0x920, 0x10, 15, 1),
+ PIN_FIELD(108, 108, 0x920, 0x10, 14, 1),
+ PIN_FIELD(109, 109, 0x920, 0x10, 13, 1),
+ PIN_FIELD(110, 110, 0x920, 0x10, 9, 1),
+ PIN_FIELD(111, 111, 0x920, 0x10, 8, 1),
+ PIN_FIELD(112, 112, 0x920, 0x10, 7, 1),
+ PIN_FIELD(113, 113, 0x920, 0x10, 6, 1),
+ PIN_FIELD(114, 114, 0x920, 0x10, 10, 1),
+ PIN_FIELD(115, 115, 0x920, 0x10, 1, 1),
+ PIN_FIELD(116, 116, 0x920, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0x920, 0x10, 5, 1),
+ PIN_FIELD(118, 118, 0x920, 0x10, 4, 1),
+ PIN_FIELD(119, 119, 0x920, 0x10, 3, 1),
+ PIN_FIELD(120, 120, 0x920, 0x10, 2, 1),
+ PIN_FIELD(121, 124, 0x910, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_smt_range[] = {
+ PIN_FIELD(0, 6, 0xA00, 0x10, 2, 1),
+ PIN_FIELD(7, 10, 0xA00, 0x10, 3, 1),
+ PIN_FIELD(11, 13, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(14, 17, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(18, 20, 0xA10, 0x10, 10, 1),
+ PIN_FIELD(21, 23, 0xA00, 0x10, 13, 1),
+ PIN_FIELD(24, 25, 0xA00, 0x10, 12, 1),
+ PIN_FIELD(26, 30, 0xA00, 0x10, 0, 1),
+ PIN_FIELD(31, 33, 0xA00, 0x10, 1, 1),
+ PIN_FIELD(40, 40, 0xA10, 0x10, 11, 1),
+ PIN_FIELD(41, 43, 0xA00, 0x10, 10, 1),
+ PIN_FIELD(44, 47, 0xA00, 0x10, 11, 1),
+ PIN_FIELD(48, 51, 0xA00, 0x10, 14, 1),
+ PIN_FIELD(52, 53, 0xA10, 0x10, 0, 1),
+ PIN_FIELD(54, 54, 0xA10, 0x10, 2, 1),
+ PIN_FIELD(55, 57, 0xA10, 0x10, 4, 1),
+ PIN_FIELD(58, 59, 0xA00, 0x10, 15, 1),
+ PIN_FIELD(60, 61, 0xA10, 0x10, 1, 1),
+ PIN_FIELD(62, 65, 0xA10, 0x10, 5, 1),
+ PIN_FIELD(66, 67, 0xA10, 0x10, 6, 1),
+ PIN_FIELD(68, 68, 0xA30, 0x10, 2, 1),
+ PIN_FIELD(69, 69, 0xA30, 0x10, 1, 1),
+ PIN_FIELD(70, 70, 0xA30, 0x10, 3, 1),
+ PIN_FIELD(71, 71, 0xA30, 0x10, 4, 1),
+ PIN_FIELD(72, 72, 0xA30, 0x10, 5, 1),
+ PIN_FIELD(73, 73, 0xA30, 0x10, 6, 1),
+
+ PIN_FIELD(100, 103, 0xA10, 0x10, 7, 1),
+ PIN_FIELD(104, 104, 0xA20, 0x10, 12, 1),
+ PIN_FIELD(105, 105, 0xA20, 0x10, 11, 1),
+ PIN_FIELD(106, 106, 0xA30, 0x10, 13, 1),
+ PIN_FIELD(107, 107, 0xA20, 0x10, 14, 1),
+ PIN_FIELD(108, 108, 0xA20, 0x10, 15, 1),
+ PIN_FIELD(109, 109, 0xA30, 0x10, 0, 1),
+ PIN_FIELD(110, 110, 0xA20, 0x10, 9, 1),
+ PIN_FIELD(111, 111, 0xA20, 0x10, 8, 1),
+ PIN_FIELD(112, 112, 0xA20, 0x10, 7, 1),
+ PIN_FIELD(113, 113, 0xA20, 0x10, 6, 1),
+ PIN_FIELD(114, 114, 0xA20, 0x10, 10, 1),
+ PIN_FIELD(115, 115, 0xA20, 0x10, 1, 1),
+ PIN_FIELD(116, 116, 0xA20, 0x10, 0, 1),
+ PIN_FIELD(117, 117, 0xA20, 0x10, 5, 1),
+ PIN_FIELD(118, 118, 0xA20, 0x10, 4, 1),
+ PIN_FIELD(119, 119, 0xA20, 0x10, 3, 1),
+ PIN_FIELD(120, 120, 0xA20, 0x10, 2, 1),
+ PIN_FIELD(121, 124, 0xA10, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullen_range[] = {
+ PIN_FIELD(0, 13, 0x500, 0x10, 0, 1),
+ PIN_FIELD(18, 20, 0x510, 0x10, 2, 1),
+ PIN_FIELD(24, 31, 0x510, 0x10, 8, 1),
+ PIN_FIELD(32, 39, 0x520, 0x10, 0, 1),
+ PIN_FIELD(44, 47, 0x520, 0x10, 12, 1),
+ PIN_FIELD(48, 63, 0x530, 0x10, 0, 1),
+ PIN_FIELD(64, 67, 0x540, 0x10, 0, 1),
+ PIN_FIELD(100, 103, 0x560, 0x10, 4, 1),
+ PIN_FIELD(121, 124, 0x570, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_pullsel_range[] = {
+ PIN_FIELD(0, 13, 0x600, 0x10, 0, 1),
+ PIN_FIELD(18, 20, 0x610, 0x10, 2, 1),
+ PIN_FIELD(24, 31, 0x610, 0x10, 8, 1),
+ PIN_FIELD(32, 39, 0x620, 0x10, 0, 1),
+ PIN_FIELD(44, 47, 0x620, 0x10, 12, 1),
+ PIN_FIELD(48, 63, 0x630, 0x10, 0, 1),
+ PIN_FIELD(64, 67, 0x640, 0x10, 0, 1),
+ PIN_FIELD(100, 103, 0x660, 0x10, 4, 1),
+ PIN_FIELD(121, 124, 0x670, 0x10, 9, 1),
+};
+
+static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
+ PIN_FIELD(0, 4, 0xd00, 0x10, 0, 4),
+ PIN_FIELD(5, 10, 0xd00, 0x10, 4, 4),
+ PIN_FIELD(11, 13, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(14, 17, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(18, 20, 0xd10, 0x10, 0, 4),
+ PIN_FIELD(21, 23, 0xd00, 0x10, 12, 4),
+ PIN_FIELD(24, 25, 0xd00, 0x10, 8, 4),
+ PIN_FIELD(26, 30, 0xd10, 0x10, 4, 4),
+ PIN_FIELD(31, 33, 0xd10, 0x10, 8, 4),
+ PIN_FIELD(34, 35, 0xd10, 0x10, 12, 4),
+ PIN_FIELD(36, 39, 0xd20, 0x10, 0, 4),
+ PIN_FIELD(40, 40, 0xd20, 0x10, 4, 4),
+ PIN_FIELD(41, 43, 0xd20, 0x10, 8, 4),
+ PIN_FIELD(44, 47, 0xd20, 0x10, 12, 4),
+ PIN_FIELD(48, 51, 0xd30, 0x10, 0, 4),
+ PIN_FIELD(54, 54, 0xd30, 0x10, 8, 4),
+ PIN_FIELD(55, 57, 0xd30, 0x10, 12, 4),
+ PIN_FIELD(62, 67, 0xd40, 0x10, 8, 4),
+ PIN_FIELD(68, 68, 0xd40, 0x10, 12, 4),
+ PIN_FIELD(69, 69, 0xd50, 0x10, 0, 4),
+ PIN_FIELD(70, 73, 0xd50, 0x10, 4, 4),
+ PIN_FIELD(100, 103, 0xd50, 0x10, 8, 4),
+ PIN_FIELD(104, 104, 0xd50, 0x10, 12, 4),
+ PIN_FIELD(105, 105, 0xd60, 0x10, 0, 4),
+ PIN_FIELD(106, 109, 0xd60, 0x10, 4, 4),
+ PIN_FIELD(110, 113, 0xd70, 0x10, 0, 4),
+ PIN_FIELD(114, 114, 0xd70, 0x10, 4, 4),
+ PIN_FIELD(115, 115, 0xd60, 0x10, 12, 4),
+ PIN_FIELD(116, 116, 0xd60, 0x10, 8, 4),
+ PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8516_pin_do_range),
+ [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8516_pin_ies_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8516_pin_smt_range),
+ [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt8516_pin_pullsel_range),
+ [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt8516_pin_pullen_range),
+ [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8516_pin_drv_range),
+};
+
+static const struct mtk_pin_desc mt8516_pins[] = {
+ MTK_PIN(0, "EINT0", DRV_GRP0),
+ MTK_PIN(1, "EINT1", DRV_GRP0),
+ MTK_PIN(2, "EINT2", DRV_GRP0),
+ MTK_PIN(3, "EINT3", DRV_GRP0),
+ MTK_PIN(4, "EINT4", DRV_GRP0),
+ MTK_PIN(5, "EINT5", DRV_GRP0),
+ MTK_PIN(6, "EINT6", DRV_GRP0),
+ MTK_PIN(7, "EINT7", DRV_GRP0),
+ MTK_PIN(8, "EINT8", DRV_GRP0),
+ MTK_PIN(9, "EINT9", DRV_GRP0),
+ MTK_PIN(10, "EINT10", DRV_GRP0),
+ MTK_PIN(11, "EINT11", DRV_GRP0),
+ MTK_PIN(12, "EINT12", DRV_GRP0),
+ MTK_PIN(13, "EINT13", DRV_GRP0),
+ MTK_PIN(14, "EINT14", DRV_GRP2),
+ MTK_PIN(15, "EINT15", DRV_GRP2),
+ MTK_PIN(16, "EINT16", DRV_GRP2),
+ MTK_PIN(17, "EINT17", DRV_GRP2),
+ MTK_PIN(18, "EINT18", DRV_GRP0),
+ MTK_PIN(19, "EINT19", DRV_GRP0),
+ MTK_PIN(20, "EINT20", DRV_GRP0),
+ MTK_PIN(21, "EINT21", DRV_GRP2),
+ MTK_PIN(22, "EINT22", DRV_GRP2),
+ MTK_PIN(23, "EINT23", DRV_GRP2),
+ MTK_PIN(24, "EINT24", DRV_GRP0),
+ MTK_PIN(25, "EINT25", DRV_GRP0),
+ MTK_PIN(26, "PWRAP_SPI0_MI", DRV_GRP4),
+ MTK_PIN(27, "PWRAP_SPI0_MO", DRV_GRP4),
+ MTK_PIN(28, "PWRAP_INT", DRV_GRP4),
+ MTK_PIN(29, "PWRAP_SPIO0_CK", DRV_GRP4),
+ MTK_PIN(30, "PWARP_SPI0_CSN", DRV_GRP4),
+ MTK_PIN(31, "RTC32K_CK", DRV_GRP4),
+ MTK_PIN(32, "WATCHDOG", DRV_GRP4),
+ MTK_PIN(33, "SRCLKENA0", DRV_GRP4),
+ MTK_PIN(34, "URXD2", DRV_GRP0),
+ MTK_PIN(35, "UTXD2", DRV_GRP0),
+ MTK_PIN(36, "MRG_CLK", DRV_GRP0),
+ MTK_PIN(37, "MRG_SYNC", DRV_GRP0),
+ MTK_PIN(38, "MRG_DI", DRV_GRP0),
+ MTK_PIN(39, "MRG_DO", DRV_GRP0),
+ MTK_PIN(40, "KPROW0", DRV_GRP2),
+ MTK_PIN(41, "KPROW1", DRV_GRP2),
+ MTK_PIN(42, "KPCOL0", DRV_GRP2),
+ MTK_PIN(43, "KPCOL1", DRV_GRP2),
+ MTK_PIN(44, "JMTS", DRV_GRP2),
+ MTK_PIN(45, "JTCK", DRV_GRP2),
+ MTK_PIN(46, "JTDI", DRV_GRP2),
+ MTK_PIN(47, "JTDO", DRV_GRP2),
+ MTK_PIN(48, "SPI_CS", DRV_GRP2),
+ MTK_PIN(49, "SPI_CK", DRV_GRP2),
+ MTK_PIN(50, "SPI_MI", DRV_GRP2),
+ MTK_PIN(51, "SPI_MO", DRV_GRP2),
+ MTK_PIN(52, "SDA1", DRV_GRP2),
+ MTK_PIN(53, "SCL1", DRV_GRP2),
+ MTK_PIN(54, "DISP_PWM", DRV_GRP2),
+ MTK_PIN(55, "I2S_DATA_IN", DRV_GRP2),
+ MTK_PIN(56, "I2S_LRCK", DRV_GRP2),
+ MTK_PIN(57, "I2S_BCK", DRV_GRP2),
+ MTK_PIN(58, "SDA0", DRV_GRP2),
+ MTK_PIN(59, "SCL0", DRV_GRP2),
+ MTK_PIN(60, "SDA2", DRV_GRP2),
+ MTK_PIN(61, "SCL2", DRV_GRP2),
+ MTK_PIN(62, "URXD0", DRV_GRP2),
+ MTK_PIN(63, "UTXD0", DRV_GRP2),
+ MTK_PIN(64, "URXD1", DRV_GRP2),
+ MTK_PIN(65, "UTXD1", DRV_GRP2),
+ MTK_PIN(66, "LCM_RST", DRV_GRP2),
+ MTK_PIN(67, "DSI_TE", DRV_GRP2),
+ MTK_PIN(68, "MSDC2_CMD", DRV_GRP4),
+ MTK_PIN(69, "MSDC2_CLK", DRV_GRP4),
+ MTK_PIN(70, "MSDC2_DAT0", DRV_GRP4),
+ MTK_PIN(71, "MSDC2_DAT1", DRV_GRP4),
+ MTK_PIN(72, "MSDC2_DAT2", DRV_GRP4),
+ MTK_PIN(73, "MSDC2_DAT3", DRV_GRP4),
+ MTK_PIN(74, "TDN3", DRV_GRP0),
+ MTK_PIN(75, "TDP3", DRV_GRP0),
+ MTK_PIN(76, "TDN2", DRV_GRP0),
+ MTK_PIN(77, "TDP2", DRV_GRP0),
+ MTK_PIN(78, "TCN", DRV_GRP0),
+ MTK_PIN(79, "TCP", DRV_GRP0),
+ MTK_PIN(80, "TDN1", DRV_GRP0),
+ MTK_PIN(81, "TDP1", DRV_GRP0),
+ MTK_PIN(82, "TDN0", DRV_GRP0),
+ MTK_PIN(83, "TDP0", DRV_GRP0),
+ MTK_PIN(84, "RDN0", DRV_GRP0),
+ MTK_PIN(85, "RDP0", DRV_GRP0),
+ MTK_PIN(86, "RDN1", DRV_GRP0),
+ MTK_PIN(87, "RDP1", DRV_GRP0),
+ MTK_PIN(88, "RCN", DRV_GRP0),
+ MTK_PIN(89, "RCP", DRV_GRP0),
+ MTK_PIN(90, "RDN2", DRV_GRP0),
+ MTK_PIN(91, "RDP2", DRV_GRP0),
+ MTK_PIN(92, "RDN3", DRV_GRP0),
+ MTK_PIN(93, "RDP3", DRV_GRP0),
+ MTK_PIN(94, "RCN_A", DRV_GRP0),
+ MTK_PIN(95, "RCP_A", DRV_GRP0),
+ MTK_PIN(96, "RDN1_A", DRV_GRP0),
+ MTK_PIN(97, "RDP1_A", DRV_GRP0),
+ MTK_PIN(98, "RDN0_A", DRV_GRP0),
+ MTK_PIN(99, "RDP0_A", DRV_GRP0),
+ MTK_PIN(100, "CMDDAT0", DRV_GRP2),
+ MTK_PIN(101, "CMDDAT1", DRV_GRP2),
+ MTK_PIN(102, "CMMCLK", DRV_GRP2),
+ MTK_PIN(103, "CMPCLK", DRV_GRP2),
+ MTK_PIN(104, "MSDC1_CMD", DRV_GRP4),
+ MTK_PIN(105, "MSDC1_CLK", DRV_GRP4),
+ MTK_PIN(106, "MSDC1_DAT0", DRV_GRP4),
+ MTK_PIN(107, "MSDC1_DAT1", DRV_GRP4),
+ MTK_PIN(108, "MSDC1_DAT2", DRV_GRP4),
+ MTK_PIN(109, "MSDC1_DAT3", DRV_GRP4),
+ MTK_PIN(110, "MSDC0_DAT7", DRV_GRP4),
+ MTK_PIN(111, "MSDC0_DAT6", DRV_GRP4),
+ MTK_PIN(112, "MSDC0_DAT5", DRV_GRP4),
+ MTK_PIN(113, "MSDC0_DAT4", DRV_GRP4),
+ MTK_PIN(114, "MSDC0_RSTB", DRV_GRP4),
+ MTK_PIN(115, "MSDC0_CMD", DRV_GRP4),
+ MTK_PIN(116, "MSDC0_CLK", DRV_GRP4),
+ MTK_PIN(117, "MSDC0_DAT3", DRV_GRP4),
+ MTK_PIN(118, "MSDC0_DAT2", DRV_GRP4),
+ MTK_PIN(119, "MSDC0_DAT1", DRV_GRP4),
+ MTK_PIN(120, "MSDC0_DAT0", DRV_GRP4),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins.
+ * The hardware probably has multiple combinations of these pinouts.
+ */
+
+/* UART */
+static int mt8516_uart0_0_rxd_txd_pins[] = { 62, 63, };
+static int mt8516_uart0_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8516_uart1_0_rxd_txd_pins[] = { 64, 65, };
+static int mt8516_uart1_0_rxd_txd_funcs[] = { 1, 1, };
+static int mt8516_uart2_0_rxd_txd_pins[] = { 34, 35, };
+static int mt8516_uart2_0_rxd_txd_funcs[] = { 1, 1, };
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt8516_uart_groups[] = { "uart0_0_rxd_txd",
+ "uart1_0_rxd_txd",
+ "uart2_0_rxd_txd", };
+
+/* MMC0 */
+static int mt8516_msdc0_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117, 118,
+ 119, 120, };
+static int mt8516_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
+
+static const struct mtk_group_desc mt8516_groups[] = {
+ PINCTRL_PIN_GROUP("uart0_0_rxd_txd", mt8516_uart0_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart1_0_rxd_txd", mt8516_uart1_0_rxd_txd),
+ PINCTRL_PIN_GROUP("uart2_0_rxd_txd", mt8516_uart2_0_rxd_txd),
+
+ PINCTRL_PIN_GROUP("msdc0", mt8516_msdc0),
+};
+
+static const char *const mt8516_msdc_groups[] = { "msdc0" };
+
+static const struct mtk_function_desc mt8516_functions[] = {
+ {"uart", mt8516_uart_groups, ARRAY_SIZE(mt8516_uart_groups)},
+ {"msdc", mt8516_msdc_groups, ARRAY_SIZE(mt8516_msdc_groups)},
+};
+
+static struct mtk_pinctrl_soc mt8516_data = {
+ .name = "mt8516_pinctrl",
+ .reg_cal = mt8516_reg_cals,
+ .pins = mt8516_pins,
+ .npins = ARRAY_SIZE(mt8516_pins),
+ .grps = mt8516_groups,
+ .ngrps = ARRAY_SIZE(mt8516_groups),
+ .funcs = mt8516_functions,
+ .nfuncs = ARRAY_SIZE(mt8516_functions),
+};
+
+static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt8516_data);
+}
+
+static const struct udevice_id mt8516_pctrl_match[] = {
+ { .compatible = "mediatek,mt8516-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8516_pinctrl) = {
+ .name = "mt8516_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt8516_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt8516_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
--
2.20.1
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