From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [PATCH 6/7] arm: juno: Enable PCI
Date: Thu, 11 Jun 2020 12:03:20 +0100 [thread overview]
Message-ID: <20200611110321.9574-7-andre.przywara@arm.com> (raw)
In-Reply-To: <20200611110321.9574-1-andre.przywara@arm.com>
The ARM Juno boards in their -r1 and -r2 variants sport a PCIe
controller, which we configure already in board specific code to be ECAM
compliant. Hence we can just enable the generic ECAM driver to let
U-Boot use PCIe devices.
Add the respective options to the Juno defconfig to enable the PCI
framework and the generic ECAM driver, and initialise the driver upon
loading U-Boot.
Make some functions in the Juno PCIe init code static on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
board/armltd/vexpress64/pcie.c | 14 +++++++++-----
configs/vexpress_aemv8a_juno_defconfig | 5 +++++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c
index 02de58b360..733b190e59 100644
--- a/board/armltd/vexpress64/pcie.c
+++ b/board/armltd/vexpress64/pcie.c
@@ -72,9 +72,9 @@
JUNO_RESET_STATUS_PHY | \
JUNO_RESET_STATUS_RC)
-void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
- unsigned long trsl_addr, int window_size,
- int trsl_param)
+static void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
+ unsigned long trsl_addr, int window_size,
+ int trsl_param)
{
/* X3PCI_ATR_SRC_ADDR_LOW:
- bit 0: enable entry,
@@ -94,7 +94,7 @@ void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr,
((u64)1) << window_size, trsl_param);
}
-void xr3pci_setup_atr(void)
+static void xr3pci_setup_atr(void)
{
/* setup PCIe to CPU address translation tables */
unsigned long base = XR3_CONFIG_BASE + XR3PCI_ATR_PCIE_WIN0;
@@ -141,7 +141,7 @@ void xr3pci_setup_atr(void)
XR3_PCI_MEMSPACE64_SIZE, XR3PCI_ATR_TRSLID_PCIE_MEMORY);
}
-void xr3pci_init(void)
+static void xr3pci_init(void)
{
u32 val;
int timeout = 200;
@@ -193,5 +193,9 @@ void xr3pci_init(void)
void vexpress64_pcie_init(void)
{
+ /* Initialise and configure the PCIe host bridge. */
xr3pci_init();
+
+ /* Register the now ECAM complaint PCIe host controller with U-Boot. */
+ pci_init();
}
diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig
index 49acb34310..4866a0e9d5 100644
--- a/configs/vexpress_aemv8a_juno_defconfig
+++ b/configs/vexpress_aemv8a_juno_defconfig
@@ -32,6 +32,11 @@ CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_BOARD=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_ECAM_GENERIC=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_CMD_PCI=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xBFC0000
# CONFIG_MMC is not set
--
2.17.5
next prev parent reply other threads:[~2020-06-11 11:03 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-11 11:03 [PATCH 0/7] arm: Juno board updates and PCIe/SATA enablement Andre Przywara
2020-06-11 11:03 ` [PATCH 1/7] arm: vexpress64: Fix counter frequency Andre Przywara
2020-06-20 20:22 ` Linus Walleij
2020-07-08 3:04 ` Tom Rini
2020-06-11 11:03 ` [PATCH 2/7] net: dm: Remove warning about EEPROM provided MAC address Andre Przywara
2020-06-11 11:09 ` Ramon Fried
2020-06-20 20:23 ` Linus Walleij
2020-07-08 3:04 ` Tom Rini
2020-06-11 11:03 ` [PATCH 3/7] net: smc911x: Properly handle EEPROM " Andre Przywara
2020-06-11 11:10 ` Ramon Fried
2020-06-20 20:25 ` Linus Walleij
2020-07-08 3:04 ` Tom Rini
2020-06-11 11:03 ` [PATCH 4/7] arm: juno: Enable DM_ETH Andre Przywara
2020-06-20 20:26 ` Linus Walleij
2020-07-08 3:04 ` Tom Rini
2020-06-11 11:03 ` [PATCH 5/7] sata_sil: Enable DM_PCI operation Andre Przywara
2020-06-20 20:27 ` Linus Walleij
2020-07-08 3:04 ` Tom Rini
2020-06-11 11:03 ` Andre Przywara [this message]
2020-06-20 20:28 ` [PATCH 6/7] arm: juno: Enable PCI Linus Walleij
2020-07-08 3:05 ` Tom Rini
2020-06-11 11:03 ` [PATCH 7/7] arm: juno: Enable SATA controller Andre Przywara
2020-06-20 20:28 ` Linus Walleij
2020-07-08 3:05 ` Tom Rini
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