From: Sean Anderson <seanga2@gmail.com>
To: u-boot@lists.denx.de
Subject: [PATCH v4 8/8] riscv: Update SiFive device tree for new CLINT driver
Date: Wed, 9 Sep 2020 16:09:30 -0400 [thread overview]
Message-ID: <20200909200930.232174-9-seanga2@gmail.com> (raw)
In-Reply-To: <20200909200930.232174-1-seanga2@gmail.com>
We currently do this in a u-boot specific dts, but hopefully we can get
these bindings added in Linux in the future.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
---
This patch builds but has NOT been tested.
Changes in v4:
- Both the Andes PMLT and Sifive CLINT now fall back on timebase-frequency,
per discussion with Anup Patel
- Rebase
Changes in v3:
- Rebase
Changes in v2:
- Fix SiFive CLINT not getting tick-rate from rtcclk
arch/riscv/dts/fu540-c000-u-boot.dtsi | 8 ++++++--
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi | 4 ++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index 5302677ee4..a06e1b11c6 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -55,9 +55,13 @@
reg = <0x0 0x10070000 0x0 0x1000>;
fuse-count = <0x1000>;
};
- clint at 2000000 {
+ clint: clint at 2000000 {
compatible = "riscv,clint0";
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7>;
reg = <0x0 0x2000000 0x0 0xc0000>;
u-boot,dm-spl;
};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 5d0c928b29..1996149c95 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -34,6 +34,10 @@
};
+&clint {
+ clocks = <&rtcclk>;
+};
+
&qspi0 {
u-boot,dm-spl;
--
2.28.0
next prev parent reply other threads:[~2020-09-09 20:09 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 20:09 [PATCH v4 0/8] riscv: Clean up timer drivers Sean Anderson
2020-09-09 20:09 ` [PATCH v4 1/8] riscv: Rework riscv timer driver to only support S-mode Sean Anderson
2020-09-09 20:09 ` [PATCH v4 2/8] timer: Add helper for drivers using timebase fallback Sean Anderson
2020-09-10 13:38 ` Simon Glass
2020-09-10 15:13 ` Sean Anderson
2020-09-15 7:13 ` Bin Meng
2020-09-09 20:09 ` [PATCH v4 3/8] riscv: Rework Andes PLMT as a UCLASS_TIMER driver Sean Anderson
2020-09-15 7:18 ` Bin Meng
2020-09-15 10:04 ` Sean Anderson
2020-09-09 20:09 ` [PATCH v4 4/8] riscv: Clean up initialization in Andes PLIC Sean Anderson
2020-09-09 20:09 ` [PATCH v4 5/8] riscv: Rework Sifive CLINT as UCLASS_TIMER driver Sean Anderson
2020-09-15 8:09 ` Bin Meng
2020-09-15 10:06 ` Sean Anderson
2020-09-09 20:09 ` [PATCH v4 6/8] riscv: clk: Add CLINT clock to kendryte clock driver Sean Anderson
2020-09-09 20:09 ` [PATCH v4 7/8] riscv: Update Kendryte device tree for new CLINT driver Sean Anderson
2020-09-15 9:07 ` Bin Meng
2020-09-09 20:09 ` Sean Anderson [this message]
2020-09-15 9:13 ` [PATCH v4 8/8] riscv: Update SiFive " Bin Meng
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