From: Stefan Roese <sr@denx.de>
To: u-boot@lists.denx.de
Subject: [PATCH v1 29/50] mips: octeon: Add cvmx-smix-defs.h header file
Date: Fri, 11 Dec 2020 17:05:51 +0100 [thread overview]
Message-ID: <20201211160612.1498780-30-sr@denx.de> (raw)
In-Reply-To: <20201211160612.1498780-1-sr@denx.de>
From: Aaron Williams <awilliams@marvell.com>
Import cvmx-smix-defs.h header file from 2013 U-Boot. It will be used
by the later added drivers to support PCIe and networking on the MIPS
Octeon II / III platforms.
Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
.../mach-octeon/include/mach/cvmx-smix-defs.h | 360 ++++++++++++++++++
1 file changed, 360 insertions(+)
create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
diff --git a/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
new file mode 100644
index 0000000000..c51d71b38f
--- /dev/null
+++ b/arch/mips/mach-octeon/include/mach/cvmx-smix-defs.h
@@ -0,0 +1,360 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ * Configuration and status register (CSR) type definitions for
+ * Octeon smix.
+ */
+
+#ifndef __CVMX_SMIX_DEFS_H__
+#define __CVMX_SMIX_DEFS_H__
+
+static inline u64 CVMX_SMIX_CLK(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000001818ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001180000003818ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001180000003818ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003818ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003818ull + (offset) * 128;
+ }
+ return 0x0001180000003818ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_CMD(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000001800ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001180000003800ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001180000003800ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003800ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003800ull + (offset) * 128;
+ }
+ return 0x0001180000003800ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_EN(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000001820ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001180000003820ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001180000003820ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003820ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003820ull + (offset) * 128;
+ }
+ return 0x0001180000003820ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_RD_DAT(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000001810ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001180000003810ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001180000003810ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003810ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003810ull + (offset) * 128;
+ }
+ return 0x0001180000003810ull + (offset) * 128;
+}
+
+static inline u64 CVMX_SMIX_WR_DAT(unsigned long offset)
+{
+ switch (cvmx_get_octeon_family()) {
+ case OCTEON_CN70XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000001808ull + (offset) * 256;
+ case OCTEON_CN78XX & OCTEON_FAMILY_MASK:
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX_PASS1_X))
+ return 0x0001180000003808ull + (offset) * 128;
+ if (OCTEON_IS_MODEL(OCTEON_CN78XX))
+ return 0x0001180000003808ull + (offset) * 128;
+ case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003808ull + (offset) * 128;
+ case OCTEON_CNF75XX & OCTEON_FAMILY_MASK:
+ case OCTEON_CN73XX & OCTEON_FAMILY_MASK:
+ return 0x0001180000003808ull + (offset) * 128;
+ }
+ return 0x0001180000003808ull + (offset) * 128;
+}
+
+/**
+ * cvmx_smi#_clk
+ *
+ * This register determines the SMI timing characteristics.
+ * If software wants to change SMI CLK timing parameters ([SAMPLE]/[SAMPLE_HI]), software
+ * must delay the SMI_()_CLK CSR write by at least 512 coprocessor-clock cycles after the
+ * previous SMI operation is finished.
+ */
+union cvmx_smix_clk {
+ u64 u64;
+ struct cvmx_smix_clk_s {
+ u64 reserved_25_63 : 39;
+ u64 mode : 1;
+ u64 reserved_21_23 : 3;
+ u64 sample_hi : 5;
+ u64 sample_mode : 1;
+ u64 reserved_14_14 : 1;
+ u64 clk_idle : 1;
+ u64 preamble : 1;
+ u64 sample : 4;
+ u64 phase : 8;
+ } s;
+ struct cvmx_smix_clk_cn30xx {
+ u64 reserved_21_63 : 43;
+ u64 sample_hi : 5;
+ u64 sample_mode : 1;
+ u64 reserved_14_14 : 1;
+ u64 clk_idle : 1;
+ u64 preamble : 1;
+ u64 sample : 4;
+ u64 phase : 8;
+ } cn30xx;
+ struct cvmx_smix_clk_cn30xx cn31xx;
+ struct cvmx_smix_clk_cn30xx cn38xx;
+ struct cvmx_smix_clk_cn30xx cn38xxp2;
+ struct cvmx_smix_clk_s cn50xx;
+ struct cvmx_smix_clk_s cn52xx;
+ struct cvmx_smix_clk_s cn52xxp1;
+ struct cvmx_smix_clk_s cn56xx;
+ struct cvmx_smix_clk_s cn56xxp1;
+ struct cvmx_smix_clk_cn30xx cn58xx;
+ struct cvmx_smix_clk_cn30xx cn58xxp1;
+ struct cvmx_smix_clk_s cn61xx;
+ struct cvmx_smix_clk_s cn63xx;
+ struct cvmx_smix_clk_s cn63xxp1;
+ struct cvmx_smix_clk_s cn66xx;
+ struct cvmx_smix_clk_s cn68xx;
+ struct cvmx_smix_clk_s cn68xxp1;
+ struct cvmx_smix_clk_s cn70xx;
+ struct cvmx_smix_clk_s cn70xxp1;
+ struct cvmx_smix_clk_s cn73xx;
+ struct cvmx_smix_clk_s cn78xx;
+ struct cvmx_smix_clk_s cn78xxp1;
+ struct cvmx_smix_clk_s cnf71xx;
+ struct cvmx_smix_clk_s cnf75xx;
+};
+
+typedef union cvmx_smix_clk cvmx_smix_clk_t;
+
+/**
+ * cvmx_smi#_cmd
+ *
+ * This register forces a read or write command to the PHY. Write operations to this register
+ * create SMI transactions. Software will poll (depending on the transaction type).
+ */
+union cvmx_smix_cmd {
+ u64 u64;
+ struct cvmx_smix_cmd_s {
+ u64 reserved_18_63 : 46;
+ u64 phy_op : 2;
+ u64 reserved_13_15 : 3;
+ u64 phy_adr : 5;
+ u64 reserved_5_7 : 3;
+ u64 reg_adr : 5;
+ } s;
+ struct cvmx_smix_cmd_cn30xx {
+ u64 reserved_17_63 : 47;
+ u64 phy_op : 1;
+ u64 reserved_13_15 : 3;
+ u64 phy_adr : 5;
+ u64 reserved_5_7 : 3;
+ u64 reg_adr : 5;
+ } cn30xx;
+ struct cvmx_smix_cmd_cn30xx cn31xx;
+ struct cvmx_smix_cmd_cn30xx cn38xx;
+ struct cvmx_smix_cmd_cn30xx cn38xxp2;
+ struct cvmx_smix_cmd_s cn50xx;
+ struct cvmx_smix_cmd_s cn52xx;
+ struct cvmx_smix_cmd_s cn52xxp1;
+ struct cvmx_smix_cmd_s cn56xx;
+ struct cvmx_smix_cmd_s cn56xxp1;
+ struct cvmx_smix_cmd_cn30xx cn58xx;
+ struct cvmx_smix_cmd_cn30xx cn58xxp1;
+ struct cvmx_smix_cmd_s cn61xx;
+ struct cvmx_smix_cmd_s cn63xx;
+ struct cvmx_smix_cmd_s cn63xxp1;
+ struct cvmx_smix_cmd_s cn66xx;
+ struct cvmx_smix_cmd_s cn68xx;
+ struct cvmx_smix_cmd_s cn68xxp1;
+ struct cvmx_smix_cmd_s cn70xx;
+ struct cvmx_smix_cmd_s cn70xxp1;
+ struct cvmx_smix_cmd_s cn73xx;
+ struct cvmx_smix_cmd_s cn78xx;
+ struct cvmx_smix_cmd_s cn78xxp1;
+ struct cvmx_smix_cmd_s cnf71xx;
+ struct cvmx_smix_cmd_s cnf75xx;
+};
+
+typedef union cvmx_smix_cmd cvmx_smix_cmd_t;
+
+/**
+ * cvmx_smi#_en
+ *
+ * Enables the SMI interface.
+ *
+ */
+union cvmx_smix_en {
+ u64 u64;
+ struct cvmx_smix_en_s {
+ u64 reserved_1_63 : 63;
+ u64 en : 1;
+ } s;
+ struct cvmx_smix_en_s cn30xx;
+ struct cvmx_smix_en_s cn31xx;
+ struct cvmx_smix_en_s cn38xx;
+ struct cvmx_smix_en_s cn38xxp2;
+ struct cvmx_smix_en_s cn50xx;
+ struct cvmx_smix_en_s cn52xx;
+ struct cvmx_smix_en_s cn52xxp1;
+ struct cvmx_smix_en_s cn56xx;
+ struct cvmx_smix_en_s cn56xxp1;
+ struct cvmx_smix_en_s cn58xx;
+ struct cvmx_smix_en_s cn58xxp1;
+ struct cvmx_smix_en_s cn61xx;
+ struct cvmx_smix_en_s cn63xx;
+ struct cvmx_smix_en_s cn63xxp1;
+ struct cvmx_smix_en_s cn66xx;
+ struct cvmx_smix_en_s cn68xx;
+ struct cvmx_smix_en_s cn68xxp1;
+ struct cvmx_smix_en_s cn70xx;
+ struct cvmx_smix_en_s cn70xxp1;
+ struct cvmx_smix_en_s cn73xx;
+ struct cvmx_smix_en_s cn78xx;
+ struct cvmx_smix_en_s cn78xxp1;
+ struct cvmx_smix_en_s cnf71xx;
+ struct cvmx_smix_en_s cnf75xx;
+};
+
+typedef union cvmx_smix_en cvmx_smix_en_t;
+
+/**
+ * cvmx_smi#_rd_dat
+ *
+ * This register contains the data in a read operation.
+ *
+ */
+union cvmx_smix_rd_dat {
+ u64 u64;
+ struct cvmx_smix_rd_dat_s {
+ u64 reserved_18_63 : 46;
+ u64 pending : 1;
+ u64 val : 1;
+ u64 dat : 16;
+ } s;
+ struct cvmx_smix_rd_dat_s cn30xx;
+ struct cvmx_smix_rd_dat_s cn31xx;
+ struct cvmx_smix_rd_dat_s cn38xx;
+ struct cvmx_smix_rd_dat_s cn38xxp2;
+ struct cvmx_smix_rd_dat_s cn50xx;
+ struct cvmx_smix_rd_dat_s cn52xx;
+ struct cvmx_smix_rd_dat_s cn52xxp1;
+ struct cvmx_smix_rd_dat_s cn56xx;
+ struct cvmx_smix_rd_dat_s cn56xxp1;
+ struct cvmx_smix_rd_dat_s cn58xx;
+ struct cvmx_smix_rd_dat_s cn58xxp1;
+ struct cvmx_smix_rd_dat_s cn61xx;
+ struct cvmx_smix_rd_dat_s cn63xx;
+ struct cvmx_smix_rd_dat_s cn63xxp1;
+ struct cvmx_smix_rd_dat_s cn66xx;
+ struct cvmx_smix_rd_dat_s cn68xx;
+ struct cvmx_smix_rd_dat_s cn68xxp1;
+ struct cvmx_smix_rd_dat_s cn70xx;
+ struct cvmx_smix_rd_dat_s cn70xxp1;
+ struct cvmx_smix_rd_dat_s cn73xx;
+ struct cvmx_smix_rd_dat_s cn78xx;
+ struct cvmx_smix_rd_dat_s cn78xxp1;
+ struct cvmx_smix_rd_dat_s cnf71xx;
+ struct cvmx_smix_rd_dat_s cnf75xx;
+};
+
+typedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t;
+
+/**
+ * cvmx_smi#_wr_dat
+ *
+ * This register provides the data for a write operation.
+ *
+ */
+union cvmx_smix_wr_dat {
+ u64 u64;
+ struct cvmx_smix_wr_dat_s {
+ u64 reserved_18_63 : 46;
+ u64 pending : 1;
+ u64 val : 1;
+ u64 dat : 16;
+ } s;
+ struct cvmx_smix_wr_dat_s cn30xx;
+ struct cvmx_smix_wr_dat_s cn31xx;
+ struct cvmx_smix_wr_dat_s cn38xx;
+ struct cvmx_smix_wr_dat_s cn38xxp2;
+ struct cvmx_smix_wr_dat_s cn50xx;
+ struct cvmx_smix_wr_dat_s cn52xx;
+ struct cvmx_smix_wr_dat_s cn52xxp1;
+ struct cvmx_smix_wr_dat_s cn56xx;
+ struct cvmx_smix_wr_dat_s cn56xxp1;
+ struct cvmx_smix_wr_dat_s cn58xx;
+ struct cvmx_smix_wr_dat_s cn58xxp1;
+ struct cvmx_smix_wr_dat_s cn61xx;
+ struct cvmx_smix_wr_dat_s cn63xx;
+ struct cvmx_smix_wr_dat_s cn63xxp1;
+ struct cvmx_smix_wr_dat_s cn66xx;
+ struct cvmx_smix_wr_dat_s cn68xx;
+ struct cvmx_smix_wr_dat_s cn68xxp1;
+ struct cvmx_smix_wr_dat_s cn70xx;
+ struct cvmx_smix_wr_dat_s cn70xxp1;
+ struct cvmx_smix_wr_dat_s cn73xx;
+ struct cvmx_smix_wr_dat_s cn78xx;
+ struct cvmx_smix_wr_dat_s cn78xxp1;
+ struct cvmx_smix_wr_dat_s cnf71xx;
+ struct cvmx_smix_wr_dat_s cnf75xx;
+};
+
+typedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t;
+
+#endif
--
2.29.2
next prev parent reply other threads:[~2020-12-11 16:05 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-11 16:05 [PATCH v1 00/50] mips: octeon: Add serdes and device helper support incl. DM PCIe driver Stefan Roese
2020-12-11 16:05 ` [PATCH v1 01/50] mips: global_data.h: Add Octeon specific data to arch_global_data struct Stefan Roese
2020-12-11 16:05 ` [PATCH v1 02/50] mips: octeon: Add misc cvmx-helper header files Stefan Roese
2020-12-11 16:05 ` [PATCH v1 03/50] mips: octeon: Add cvmx-agl-defs.h header file Stefan Roese
2020-12-11 16:05 ` [PATCH v1 04/50] mips: octeon: Add cvmx-asxx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 05/50] mips: octeon: Add cvmx-bgxx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 06/50] mips: octeon: Add cvmx-ciu-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 07/50] mips: octeon: Add cvmx-dbg-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 08/50] mips: octeon: Add cvmx-dpi-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 09/50] mips: octeon: Add cvmx-dtx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 10/50] mips: octeon: Add cvmx-fpa-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 11/50] mips: octeon: Add cvmx-gmxx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 12/50] mips: octeon: Add cvmx-gserx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 13/50] mips: octeon: Add cvmx-ipd-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 14/50] mips: octeon: Add cvmx-l2c-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 15/50] mips: octeon: Add cvmx-mio-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 16/50] mips: octeon: Add cvmx-npi-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 17/50] mips: octeon: Add cvmx-pcieepx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 18/50] mips: octeon: Add cvmx-pciercx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 19/50] mips: octeon: Add cvmx-pcsx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 20/50] mips: octeon: Add cvmx-pemx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 21/50] mips: octeon: Add cvmx-pepx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 22/50] mips: octeon: Add cvmx-pip-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 23/50] mips: octeon: Add cvmx-pki-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 24/50] mips: octeon: Add cvmx-pko-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 25/50] mips: octeon: Add cvmx-pow-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 26/50] mips: octeon: Add cvmx-rst-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 27/50] mips: octeon: Add cvmx-sata-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 28/50] mips: octeon: Add cvmx-sli-defs.h " Stefan Roese
2020-12-11 16:05 ` Stefan Roese [this message]
2020-12-11 16:05 ` [PATCH v1 30/50] mips: octeon: Add cvmx-sriomaintx-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 31/50] mips: octeon: Add cvmx-sriox-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 32/50] mips: octeon: Add cvmx-sso-defs.h " Stefan Roese
2020-12-11 16:05 ` [PATCH v1 33/50] mips: octeon: Add misc remaining header files Stefan Roese
2020-12-11 16:05 ` [PATCH v1 34/50] mips: octeon: Misc changes required because of the newly added headers Stefan Roese
2020-12-11 16:05 ` [PATCH v1 35/50] mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach Stefan Roese
2020-12-11 16:05 ` [PATCH v1 36/50] mips: octeon: Add cvmx-helper-cfg.c Stefan Roese
2020-12-11 16:05 ` [PATCH v1 37/50] mips: octeon: Add cvmx-helper-fdt.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 38/50] mips: octeon: Add cvmx-helper-jtag.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 39/50] mips: octeon: Add cvmx-helper-util.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 40/50] mips: octeon: Add cvmx-helper.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 41/50] mips: octeon: Add cvmx-pcie.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 42/50] mips: octeon: Add cvmx-qlm.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 43/50] mips: octeon: Add octeon_fdt.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 44/50] mips: octeon: Add octeon_qlm.c Stefan Roese
2020-12-11 16:06 ` [PATCH v1 45/50] mips: octeon: Makefile: Enable building of the newly added C files Stefan Roese
2020-12-11 16:06 ` [PATCH v1 46/50] mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT Stefan Roese
2020-12-11 16:06 ` [PATCH v1 47/50] mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT node Stefan Roese
2020-12-11 16:06 ` [PATCH v1 48/50] mips: octeon: octeon_ebb7304: Add board specific QLM init code Stefan Roese
2020-12-11 16:06 ` [PATCH v1 49/50] mips: octeon: Add Octeon PCIe host controller driver Stefan Roese
2021-04-07 6:43 ` [PATCH v2 " Stefan Roese
2020-12-11 16:06 ` [PATCH v1 50/50] mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and E1000 Stefan Roese
2021-04-23 3:56 ` [PATCH v2 33/50] mips: octeon: Add misc remaining header files Stefan Roese
2021-04-23 16:38 ` Daniel Schwierzeck
2021-04-23 17:57 ` Stefan Roese
2021-04-23 17:56 ` [PATCH v3 " Stefan Roese
2021-04-24 22:49 ` [PATCH v1 00/50] mips: octeon: Add serdes and device helper support incl. DM PCIe driver Daniel Schwierzeck
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