* [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 15:58 ` Daniel Thompson
2022-07-04 12:58 ` [PATCH 2/8] clocks: sdm845: Import qcom,gcc-sdm845.h Sumit Garg
` (7 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
U-boot specific DT properties belong to *-uboot.dtsi, so remove
corresponding redundant properties.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/dts/sdm845.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 6f2fb20d68..88030156d9 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -18,7 +18,6 @@
compatible = "simple-bus";
gcc: clock-controller@100000 {
- u-boot,dm-pre-reloc;
compatible = "qcom,gcc-sdm845";
reg = <0x100000 0x1f0000>;
#clock-cells = <1>;
@@ -27,7 +26,6 @@
};
gpio_north: gpio_north@3900000 {
- u-boot,dm-pre-reloc;
#gpio-cells = <2>;
compatible = "qcom,sdm845-pinctrl";
reg = <0x3900000 0x400000>;
@@ -38,7 +36,6 @@
};
tlmm_north: pinctrl_north@3900000 {
- u-boot,dm-pre-reloc;
compatible = "qcom,tlmm-sdm845";
reg = <0x3900000 0x400000>;
gpio-count = <150>;
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
2022-07-04 12:58 ` [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties Sumit Garg
@ 2022-07-04 15:58 ` Daniel Thompson
2022-07-05 5:35 ` Sumit Garg
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Thompson @ 2022-07-04 15:58 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski,
stephan, vinod.koul, nicolas.dechesne, mworsfold
On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> U-boot specific DT properties belong to *-uboot.dtsi
... and are already included in starqltechn-uboot.dtsi (which is the
only current consumer of sdm845.dtsi).
Adding fuller comments, such as the above, makes things much easier to
review: it makes clear why you consider the properties redundant rather
then misfiled.
Daniel.
> , so remove
> corresponding redundant properties.
>
> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> ---
> arch/arm/dts/sdm845.dtsi | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> index 6f2fb20d68..88030156d9 100644
> --- a/arch/arm/dts/sdm845.dtsi
> +++ b/arch/arm/dts/sdm845.dtsi
> @@ -18,7 +18,6 @@
> compatible = "simple-bus";
>
> gcc: clock-controller@100000 {
> - u-boot,dm-pre-reloc;
> compatible = "qcom,gcc-sdm845";
> reg = <0x100000 0x1f0000>;
> #clock-cells = <1>;
> @@ -27,7 +26,6 @@
> };
>
> gpio_north: gpio_north@3900000 {
> - u-boot,dm-pre-reloc;
> #gpio-cells = <2>;
> compatible = "qcom,sdm845-pinctrl";
> reg = <0x3900000 0x400000>;
> @@ -38,7 +36,6 @@
> };
>
> tlmm_north: pinctrl_north@3900000 {
> - u-boot,dm-pre-reloc;
> compatible = "qcom,tlmm-sdm845";
> reg = <0x3900000 0x400000>;
> gpio-count = <150>;
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
2022-07-04 15:58 ` Daniel Thompson
@ 2022-07-05 5:35 ` Sumit Garg
2022-07-05 8:57 ` Daniel Thompson
0 siblings, 1 reply; 17+ messages in thread
From: Sumit Garg @ 2022-07-05 5:35 UTC (permalink / raw)
To: Daniel Thompson
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski,
stephan, vinod.koul, nicolas.dechesne, mworsfold
Hi Daniel,
Thanks for your review.
On Mon, 4 Jul 2022 at 21:28, Daniel Thompson <daniel.thompson@linaro.org> wrote:
>
> On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> > U-boot specific DT properties belong to *-uboot.dtsi
>
> ... and are already included in starqltechn-uboot.dtsi (which is the
> only current consumer of sdm845.dtsi).
>
>
> Adding fuller comments, such as the above, makes things much easier to
> review: it makes clear why you consider the properties redundant rather
> then misfiled.
>
I would rather say that this change is to follow the u-boot DT
recommendation [1]. I will update the commit message accordingly. BTW,
it looks like u-boot DT properties are incorrectly specified in
starqltechn-uboot.dtsi here [2] as there aren't any subnodes for the
"gcc" node. I will correct that too.
[1] https://u-boot.readthedocs.io/en/latest/develop/devicetree/control.html#adding-tweaks-for-u-boot
[2] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/starqltechn-uboot.dtsi#L19
-Sumit
>
> Daniel.
>
>
> > , so remove
> > corresponding redundant properties.
> >
> > Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
> > ---
> > arch/arm/dts/sdm845.dtsi | 3 ---
> > 1 file changed, 3 deletions(-)
> >
> > diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
> > index 6f2fb20d68..88030156d9 100644
> > --- a/arch/arm/dts/sdm845.dtsi
> > +++ b/arch/arm/dts/sdm845.dtsi
> > @@ -18,7 +18,6 @@
> > compatible = "simple-bus";
> >
> > gcc: clock-controller@100000 {
> > - u-boot,dm-pre-reloc;
> > compatible = "qcom,gcc-sdm845";
> > reg = <0x100000 0x1f0000>;
> > #clock-cells = <1>;
> > @@ -27,7 +26,6 @@
> > };
> >
> > gpio_north: gpio_north@3900000 {
> > - u-boot,dm-pre-reloc;
> > #gpio-cells = <2>;
> > compatible = "qcom,sdm845-pinctrl";
> > reg = <0x3900000 0x400000>;
> > @@ -38,7 +36,6 @@
> > };
> >
> > tlmm_north: pinctrl_north@3900000 {
> > - u-boot,dm-pre-reloc;
> > compatible = "qcom,tlmm-sdm845";
> > reg = <0x3900000 0x400000>;
> > gpio-count = <150>;
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
2022-07-05 5:35 ` Sumit Garg
@ 2022-07-05 8:57 ` Daniel Thompson
2022-07-11 13:53 ` Ramon Fried
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Thompson @ 2022-07-05 8:57 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski,
stephan, vinod.koul, nicolas.dechesne, mworsfold
On Tue, Jul 05, 2022 at 11:05:04AM +0530, Sumit Garg wrote:
> Hi Daniel,
>
> Thanks for your review.
>
> On Mon, 4 Jul 2022 at 21:28, Daniel Thompson <daniel.thompson@linaro.org> wrote:
> >
> > On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> > > U-boot specific DT properties belong to *-uboot.dtsi
> >
> > ... and are already included in starqltechn-uboot.dtsi (which is the
> > only current consumer of sdm845.dtsi).
> >
> >
> > Adding fuller comments, such as the above, makes things much easier to
> > review: it makes clear why you consider the properties redundant rather
> > then misfiled.
> >
>
> I would rather say that this change is to follow the u-boot DT
> recommendation [1]. I will update the commit message accordingly. BTW,
> it looks like u-boot DT properties are incorrectly specified in
> starqltechn-uboot.dtsi here [2] as there aren't any subnodes for the
> "gcc" node. I will correct that too.
That's fine. The wording was just an example and we written before I
reviewed patch 4 and spotted the inconsistancies there.
Daniel.
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties
2022-07-05 8:57 ` Daniel Thompson
@ 2022-07-11 13:53 ` Ramon Fried
0 siblings, 0 replies; 17+ messages in thread
From: Ramon Fried @ 2022-07-11 13:53 UTC (permalink / raw)
To: Daniel Thompson
Cc: Sumit Garg, U-Boot Mailing List, Peng Fan, Jaehoon Chung,
Simon Glass, Tom Rini,
Дмитрий Санковский,
Stephan Gerhold, vinod.koul, Nicolas Dechesne, mworsfold
On Tue, Jul 5, 2022 at 11:57 AM Daniel Thompson
<daniel.thompson@linaro.org> wrote:
>
> On Tue, Jul 05, 2022 at 11:05:04AM +0530, Sumit Garg wrote:
> > Hi Daniel,
> >
> > Thanks for your review.
> >
> > On Mon, 4 Jul 2022 at 21:28, Daniel Thompson <daniel.thompson@linaro.org> wrote:
> > >
> > > On Mon, Jul 04, 2022 at 06:28:38PM +0530, Sumit Garg wrote:
> > > > U-boot specific DT properties belong to *-uboot.dtsi
> > >
> > > ... and are already included in starqltechn-uboot.dtsi (which is the
> > > only current consumer of sdm845.dtsi).
> > >
> > >
> > > Adding fuller comments, such as the above, makes things much easier to
> > > review: it makes clear why you consider the properties redundant rather
> > > then misfiled.
> > >
> >
> > I would rather say that this change is to follow the u-boot DT
> > recommendation [1]. I will update the commit message accordingly. BTW,
> > it looks like u-boot DT properties are incorrectly specified in
> > starqltechn-uboot.dtsi here [2] as there aren't any subnodes for the
> > "gcc" node. I will correct that too.
>
> That's fine. The wording was just an example and we written before I
> reviewed patch 4 and spotted the inconsistancies there.
>
>
> Daniel.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/8] clocks: sdm845: Import qcom,gcc-sdm845.h
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
2022-07-04 12:58 ` [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 12:58 ` [PATCH 3/8] uart: sdm845: Fix debug UART pinmux Sumit Garg
` (6 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Rather than using magic numbers as clock ids for peripherals import
qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids.
So start using corresponding clk-id macro for debug UART.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/dts/sdm845.dtsi | 3 +-
arch/arm/mach-snapdragon/clock-sdm845.c | 3 +-
include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++++++++++++++++++++
3 files changed, 250 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 88030156d9..b9506f1297 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -8,6 +8,7 @@
/dts-v1/;
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include "skeleton64.dtsi"
/ {
@@ -55,7 +56,7 @@
reg = <0xa84000 0x4000>;
reg-names = "se_phys";
clock-names = "se-clk";
- clocks = <&gcc 0x58>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9>;
qcom,wrapper-core = <0x8a>;
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c
index 9572639238..f69be80898 100644
--- a/arch/arm/mach-snapdragon/clock-sdm845.c
+++ b/arch/arm/mach-snapdragon/clock-sdm845.c
@@ -14,6 +14,7 @@
#include <errno.h>
#include <asm/io.h>
#include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
#include "clock-snapdragon.h"
#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -84,7 +85,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
- case 0x58: /*UART2*/
+ case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
return clk_init_uart(priv, rate);
default:
return 0;
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 0000000000..968fa65b9c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 4
+#define GCC_BOOT_ROM_AHB_CLK 5
+#define GCC_CAMERA_AHB_CLK 6
+#define GCC_CAMERA_AXI_CLK 7
+#define GCC_CAMERA_XO_CLK 8
+#define GCC_CE1_AHB_CLK 9
+#define GCC_CE1_AXI_CLK 10
+#define GCC_CE1_CLK 11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13
+#define GCC_CPUSS_AHB_CLK 14
+#define GCC_CPUSS_AHB_CLK_SRC 15
+#define GCC_CPUSS_RBCPR_CLK 16
+#define GCC_CPUSS_RBCPR_CLK_SRC 17
+#define GCC_DDRSS_GPU_AXI_CLK 18
+#define GCC_DISP_AHB_CLK 19
+#define GCC_DISP_AXI_CLK 20
+#define GCC_DISP_GPLL0_CLK_SRC 21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 22
+#define GCC_DISP_XO_CLK 23
+#define GCC_GP1_CLK 24
+#define GCC_GP1_CLK_SRC 25
+#define GCC_GP2_CLK 26
+#define GCC_GP2_CLK_SRC 27
+#define GCC_GP3_CLK 28
+#define GCC_GP3_CLK_SRC 29
+#define GCC_GPU_CFG_AHB_CLK 30
+#define GCC_GPU_GPLL0_CLK_SRC 31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 32
+#define GCC_GPU_MEMNOC_GFX_CLK 33
+#define GCC_GPU_SNOC_DVM_GFX_CLK 34
+#define GCC_MSS_AXIS2_CLK 35
+#define GCC_MSS_CFG_AHB_CLK 36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC 37
+#define GCC_MSS_MFAB_AXIS_CLK 38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK 39
+#define GCC_MSS_SNOC_AXI_CLK 40
+#define GCC_PCIE_0_AUX_CLK 41
+#define GCC_PCIE_0_AUX_CLK_SRC 42
+#define GCC_PCIE_0_CFG_AHB_CLK 43
+#define GCC_PCIE_0_CLKREF_CLK 44
+#define GCC_PCIE_0_MSTR_AXI_CLK 45
+#define GCC_PCIE_0_PIPE_CLK 46
+#define GCC_PCIE_0_SLV_AXI_CLK 47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
+#define GCC_PCIE_1_AUX_CLK 49
+#define GCC_PCIE_1_AUX_CLK_SRC 50
+#define GCC_PCIE_1_CFG_AHB_CLK 51
+#define GCC_PCIE_1_CLKREF_CLK 52
+#define GCC_PCIE_1_MSTR_AXI_CLK 53
+#define GCC_PCIE_1_PIPE_CLK 54
+#define GCC_PCIE_1_SLV_AXI_CLK 55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56
+#define GCC_PCIE_PHY_AUX_CLK 57
+#define GCC_PCIE_PHY_REFGEN_CLK 58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 59
+#define GCC_PDM2_CLK 60
+#define GCC_PDM2_CLK_SRC 61
+#define GCC_PDM_AHB_CLK 62
+#define GCC_PDM_XO4_CLK 63
+#define GCC_PRNG_AHB_CLK 64
+#define GCC_QMIP_CAMERA_AHB_CLK 65
+#define GCC_QMIP_DISP_AHB_CLK 66
+#define GCC_QMIP_VIDEO_AHB_CLK 67
+#define GCC_QUPV3_WRAP0_S0_CLK 68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 69
+#define GCC_QUPV3_WRAP0_S1_CLK 70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 71
+#define GCC_QUPV3_WRAP0_S2_CLK 72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 73
+#define GCC_QUPV3_WRAP0_S3_CLK 74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 75
+#define GCC_QUPV3_WRAP0_S4_CLK 76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 77
+#define GCC_QUPV3_WRAP0_S5_CLK 78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 79
+#define GCC_QUPV3_WRAP0_S6_CLK 80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 81
+#define GCC_QUPV3_WRAP0_S7_CLK 82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 83
+#define GCC_QUPV3_WRAP1_S0_CLK 84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 85
+#define GCC_QUPV3_WRAP1_S1_CLK 86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 87
+#define GCC_QUPV3_WRAP1_S2_CLK 88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 89
+#define GCC_QUPV3_WRAP1_S3_CLK 90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 91
+#define GCC_QUPV3_WRAP1_S4_CLK 92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 93
+#define GCC_QUPV3_WRAP1_S5_CLK 94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 95
+#define GCC_QUPV3_WRAP1_S6_CLK 96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC 97
+#define GCC_QUPV3_WRAP1_S7_CLK 98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC 99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 103
+#define GCC_SDCC2_AHB_CLK 104
+#define GCC_SDCC2_APPS_CLK 105
+#define GCC_SDCC2_APPS_CLK_SRC 106
+#define GCC_SDCC4_AHB_CLK 107
+#define GCC_SDCC4_APPS_CLK 108
+#define GCC_SDCC4_APPS_CLK_SRC 109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 110
+#define GCC_TSIF_AHB_CLK 111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 112
+#define GCC_TSIF_REF_CLK 113
+#define GCC_TSIF_REF_CLK_SRC 114
+#define GCC_UFS_CARD_AHB_CLK 115
+#define GCC_UFS_CARD_AXI_CLK 116
+#define GCC_UFS_CARD_AXI_CLK_SRC 117
+#define GCC_UFS_CARD_CLKREF_CLK 118
+#define GCC_UFS_CARD_ICE_CORE_CLK 119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120
+#define GCC_UFS_CARD_PHY_AUX_CLK 121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127
+#define GCC_UFS_MEM_CLKREF_CLK 128
+#define GCC_UFS_PHY_AHB_CLK 129
+#define GCC_UFS_PHY_AXI_CLK 130
+#define GCC_UFS_PHY_AXI_CLK_SRC 131
+#define GCC_UFS_PHY_ICE_CORE_CLK 132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133
+#define GCC_UFS_PHY_PHY_AUX_CLK 134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140
+#define GCC_USB30_PRIM_MASTER_CLK 141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144
+#define GCC_USB30_PRIM_SLEEP_CLK 145
+#define GCC_USB30_SEC_MASTER_CLK 146
+#define GCC_USB30_SEC_MASTER_CLK_SRC 147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149
+#define GCC_USB30_SEC_SLEEP_CLK 150
+#define GCC_USB3_PRIM_CLKREF_CLK 151
+#define GCC_USB3_PRIM_PHY_AUX_CLK 152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 155
+#define GCC_USB3_SEC_CLKREF_CLK 156
+#define GCC_USB3_SEC_PHY_AUX_CLK 157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158
+#define GCC_USB3_SEC_PHY_PIPE_CLK 159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 161
+#define GCC_VIDEO_AHB_CLK 162
+#define GCC_VIDEO_AXI_CLK 163
+#define GCC_VIDEO_XO_CLK 164
+#define GPLL0 165
+#define GPLL0_OUT_EVEN 166
+#define GPLL0_OUT_MAIN 167
+#define GCC_GPU_IREF_CLK 168
+#define GCC_SDCC1_AHB_CLK 169
+#define GCC_SDCC1_APPS_CLK 170
+#define GCC_SDCC1_ICE_CORE_CLK 171
+#define GCC_SDCC1_APPS_CLK_SRC 172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 173
+#define GCC_APC_VS_CLK 174
+#define GCC_GPU_VS_CLK 175
+#define GCC_MSS_VS_CLK 176
+#define GCC_VDDA_VS_CLK 177
+#define GCC_VDDCX_VS_CLK 178
+#define GCC_VDDMX_VS_CLK 179
+#define GCC_VS_CTRL_AHB_CLK 180
+#define GCC_VS_CTRL_CLK 181
+#define GCC_VS_CTRL_CLK_SRC 182
+#define GCC_VSENSOR_CLK_SRC 183
+#define GPLL4 184
+#define GCC_CPUSS_DVM_BUS_CLK 185
+#define GCC_CPUSS_GNOC_CLK 186
+#define GCC_QSPI_CORE_CLK_SRC 187
+#define GCC_QSPI_CORE_CLK 188
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 189
+#define GCC_LPASS_Q6_AXI_CLK 190
+#define GCC_LPASS_SWAY_CLK 191
+
+/* GCC Resets */
+#define GCC_MMSS_BCR 0
+#define GCC_PCIE_0_BCR 1
+#define GCC_PCIE_1_BCR 2
+#define GCC_PCIE_PHY_BCR 3
+#define GCC_PDM_BCR 4
+#define GCC_PRNG_BCR 5
+#define GCC_QUPV3_WRAPPER_0_BCR 6
+#define GCC_QUPV3_WRAPPER_1_BCR 7
+#define GCC_QUSB2PHY_PRIM_BCR 8
+#define GCC_QUSB2PHY_SEC_BCR 9
+#define GCC_SDCC2_BCR 10
+#define GCC_SDCC4_BCR 11
+#define GCC_TSIF_BCR 12
+#define GCC_UFS_CARD_BCR 13
+#define GCC_UFS_PHY_BCR 14
+#define GCC_USB30_PRIM_BCR 15
+#define GCC_USB30_SEC_BCR 16
+#define GCC_USB3_PHY_PRIM_BCR 17
+#define GCC_USB3PHY_PHY_PRIM_BCR 18
+#define GCC_USB3_DP_PHY_PRIM_BCR 19
+#define GCC_USB3_PHY_SEC_BCR 20
+#define GCC_USB3PHY_PHY_SEC_BCR 21
+#define GCC_USB3_DP_PHY_SEC_BCR 22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 23
+#define GCC_PCIE_0_PHY_BCR 24
+#define GCC_PCIE_1_PHY_BCR 25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define UFS_CARD_GDSC 2
+#define UFS_PHY_GDSC 3
+#define USB30_PRIM_GDSC 4
+#define USB30_SEC_GDSC 5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/8] uart: sdm845: Fix debug UART pinmux
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
2022-07-04 12:58 ` [PATCH 1/8] arm64: dts: sdm845: Remove redundant u-boot DT properties Sumit Garg
2022-07-04 12:58 ` [PATCH 2/8] clocks: sdm845: Import qcom,gcc-sdm845.h Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 12:58 ` [PATCH 4/8] board: qualcomm: Add support for dragonboard845c Sumit Garg
` (5 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Configure debug UART pins as function: "qup9" rather than being regular
gpios. It fixes a hang seen during pinmux setting.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/dts/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index b9506f1297..df5b6dfcfc 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -47,7 +47,7 @@
/* DEBUG UART */
qup_uart9: qup-uart9-default {
pins = "GPIO_4", "GPIO_5";
- function = "gpio";
+ function = "qup9";
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 4/8] board: qualcomm: Add support for dragonboard845c
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (2 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 3/8] uart: sdm845: Fix debug UART pinmux Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 16:06 ` Daniel Thompson
2022-07-04 12:58 ` [PATCH 5/8] mmc: msm_sdhci: Add SDCC version 5.0.0 support Sumit Garg
` (4 subsequent siblings)
8 siblings, 1 reply; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Add support for 96Boards Dragonboard 845C aka Robotics RB3 development
platform. This board complies with 96Boards Open Platform Specifications.
Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/sdm845.rst, board: dragonboard845c.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++++++
arch/arm/dts/dragonboard845c.dts | 44 ++++++++
arch/arm/mach-snapdragon/Kconfig | 14 +++
board/qualcomm/dragonboard845c/Kconfig | 12 +++
board/qualcomm/dragonboard845c/MAINTAINERS | 6 ++
board/qualcomm/dragonboard845c/Makefile | 9 ++
board/qualcomm/dragonboard845c/db845c.its | 63 +++++++++++
.../dragonboard845c/dragonboard845c.c | 9 ++
configs/dragonboard845c_defconfig | 28 +++++
doc/board/qualcomm/sdm845.rst | 100 +++++++++++++++---
include/configs/dragonboard845c.h | 28 +++++
11 files changed, 337 insertions(+), 13 deletions(-)
create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi
create mode 100644 arch/arm/dts/dragonboard845c.dts
create mode 100644 board/qualcomm/dragonboard845c/Kconfig
create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS
create mode 100644 board/qualcomm/dragonboard845c/Makefile
create mode 100644 board/qualcomm/dragonboard845c/db845c.its
create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c
create mode 100644 configs/dragonboard845c_defconfig
create mode 100644 include/configs/dragonboard845c.h
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
new file mode 100644
index 0000000000..8b5a7ee573
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
+ * (dragonboard845c) pins
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/
+{
+ soc {
+ u-boot,dm-pre-reloc;
+
+ serial@a84000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ clock-controller@100000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_north@3900000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&pm8998_pon {
+ key_vol_down {
+ gpios = <&pm8998_pon 1 0>;
+ label = "key_vol_down";
+ };
+ key_power {
+ gpios = <&pm8998_pon 0 0>;
+ label = "key_power";
+ };
+};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
new file mode 100644
index 0000000000..1722dce33f
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Robotics RB3 Development (dragonboard845c) board device
+ * tree source
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+ model = "Thundercomm Dragonboard 845c";
+ compatible = "thundercomm,db845c", "qcom,sdm845";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &debug_uart;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0xfdfa0000>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc {
+ serial@a84000 {
+ status = "okay";
+ };
+ };
+};
+
+#include "dragonboard845c-uboot.dtsi"
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 12cf02a56a..34af40b915 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -44,6 +44,19 @@ config TARGET_DRAGONBOARD820C
- 3GiB RAM
- 32GiB UFS drive
+config TARGET_DRAGONBOARD845C
+ bool "96Boards Dragonboard 845C"
+ help
+ Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
+ Platform. This board complies with 96Board Open Platform
+ Specifications. Features:
+ - Qualcomm Snapdragon SDA845 SoC
+ - 4GiB RAM
+ - 64GiB UFS drive
+ select MISC_INIT_R
+ select SDM845
+ select DM_ETH if NET
+
config TARGET_STARQLTECHN
bool "Samsung S9 SM-G9600(starqltechn)"
help
@@ -60,6 +73,7 @@ endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
+source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
endif
diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig
new file mode 100644
index 0000000000..52fdff288d
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DRAGONBOARD845C
+
+config SYS_BOARD
+ default "dragonboard845c"
+
+config SYS_CONFIG_NAME
+ default "dragonboard845c"
+
+config SYS_VENDOR
+ default "qualcomm"
+
+endif
diff --git a/board/qualcomm/dragonboard845c/MAINTAINERS b/board/qualcomm/dragonboard845c/MAINTAINERS
new file mode 100644
index 0000000000..e555953df6
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/MAINTAINERS
@@ -0,0 +1,6 @@
+Qualcomm Robotics RB3 Development Platform (dragonboard845c)
+M: Sumit Garg <sumit.garg@linaro.org>
+S: Maintained
+F: board/qualcomm/dragonboard845c/
+F: include/configs/dragonboard845c.h
+F: configs/dragonboard845c_defconfig
diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile
new file mode 100644
index 0000000000..0abefdaf36
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+#
+# This empty file prevents make error.
+# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far.
+#
+
+obj-y += dragonboard845c.o
diff --git a/board/qualcomm/dragonboard845c/db845c.its b/board/qualcomm/dragonboard845c/db845c.its
new file mode 100644
index 0000000000..a2621340d1
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/db845c.its
@@ -0,0 +1,63 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel-1 {
+ description = "5.15.0-qcomlt-arm64";
+ data = /incbin/("./db845c_imgs/Image.gz--5.15-r0-dragonboard-845c-20211218193034-511.bin");
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "gzip";
+ load = <0x80000000>;
+ entry = <0x80000000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ ramdisk-1 {
+ description = "initramfs-test-full-image-dragonboard-845c";
+ data = /incbin/("./db845c_imgs/initramfs-test-full-image-dragonboard-845c-20211218193034-511.rootfs.cpio.gz");
+ type = "ramdisk";
+ arch = "arm64";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-1 {
+ description = "sdm845-db845c-fdt";
+ data = /incbin/("./db845c_imgs/sdm845-db845c--5.15-r0-dragonboard-845c-20211218193034.dtb");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ };
+
+ configurations {
+ default = "config-1";
+
+ config-1 {
+ description = "db845c kernel-5.15.0 configuration";
+ kernel = "kernel-1";
+ ramdisk = "ramdisk-1";
+ fdt = "fdt-1";
+ };
+ };
+};
diff --git a/board/qualcomm/dragonboard845c/dragonboard845c.c b/board/qualcomm/dragonboard845c/dragonboard845c.c
new file mode 100644
index 0000000000..c7685de306
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/dragonboard845c.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This empty file prevents make linking error.
+ * No custom logic for dragonboard845c so far.
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+void noop(void) {}
diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig
new file mode 100644
index 0000000000..a19e46a74b
--- /dev/null
+++ b/configs/dragonboard845c_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
+CONFIG_TARGET_DRAGONBOARD845C=y
+CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_BMP=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_MSM_GPIO=y
+CONFIG_PM8916_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index b6642c9579..8ef4749287 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -35,9 +35,25 @@ Pack android boot image
^^^^^^^^^^^^^^^^^^^^^^^
We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
-with appended dtb, so let's mimic linux to satisfy stock bootloader:
+with appended dtb, so let's mimic linux to satisfy stock bootloader.
-- create dump dtb::
+Boards
+------------
+starqlte
+^^^^^^^^^^^^
+
+The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
+based on the Qualcomm SDM845 SoC.
+
+Steps:
+
+- Build u-boot::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make starqltechn_defconfig
+ $ make
+
+- Create dump dtb::
workdir=/tmp/prepare_payload
mkdir -p "$workdir"
@@ -56,10 +72,15 @@ with appended dtb, so let's mimic linux to satisfy stock bootloader:
};
EOF
-- gzip u-boot ``gzip u-boot.bin``
-- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+- gzip u-boot::
+
+ gzip u-boot.bin
-Now we've got everything to build android boot image:::
+- Append dtb to gzipped u-boot::
+
+ cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
+
+- Now we've got everything to build android boot image::
mkbootimg --base 0x0 --kernel_offset 0x00008000 \
--ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
@@ -68,16 +89,69 @@ Now we've got everything to build android boot image:::
--kernel u-boot.bin.gz-dtb \
-o boot.img
-Flash image with your phone's flashing method.
+- Flash image with your phone's flashing method.
-Boards
-------------
-starqlte
-^^^^^^^^^^^^
+More information can be found on the `Samsung S9 page`_.
-The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
-based on the Qualcomm SDM845 SoC.
+dragonboard845c
+^^^^^^^^^^^^^^^
-More information can be found on the `Samsung S9 page`_.
+The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
+the Qualcomm SDM845 SoC.
+
+Steps:
+
+- Build u-boot::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make dragonboard845c_defconfig
+ $ make
+
+- Create dummy dtb::
+
+ workdir=/tmp/prepare_payload
+ mkdir -p "$workdir"
+ mock_dtb="$workdir"/payload_mock.dtb
+
+ dtc -I dts -O dtb -o "$mock_dtb" << EOF
+ /dts-v1/;
+ / {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ chosen { };
+ };
+ EOF
+
+- gzip u-boot::
+
+ gzip u-boot.bin
+
+- Append dtb to gzipped u-boot::
+
+ cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
+
+- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
+ directory. It expects a folder as ``db845c_imgs/`` in the main directory
+ containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
+ for full path to images::
+
+ mkimage -f db845c.its db845c.itb
+
+- Now we've got everything to build android boot image::
+
+ mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
+ --output boot.img --pagesize 4096 --base 0x80000000
+
+- Flash boot.img using db845c fastboot method.
+
+More information can be found on the `DragonBoard 845c page`_.
.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
+.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/
diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
new file mode 100644
index 0000000000..108dde199b
--- /dev/null
+++ b/include/configs/dragonboard845c.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#ifndef __CONFIGS_SDM845_H
+#define __CONFIGS_SDM845_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-sdm845.h>
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x5000000\0" \
+ "bootm_low=0x80000000\0" \
+ "bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/8] board: qualcomm: Add support for dragonboard845c
2022-07-04 12:58 ` [PATCH 4/8] board: qualcomm: Add support for dragonboard845c Sumit Garg
@ 2022-07-04 16:06 ` Daniel Thompson
2022-07-05 5:40 ` Sumit Garg
0 siblings, 1 reply; 17+ messages in thread
From: Daniel Thompson @ 2022-07-04 16:06 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski,
stephan, vinod.koul, nicolas.dechesne, mworsfold
On Mon, Jul 04, 2022 at 06:28:41PM +0530, Sumit Garg wrote:
> diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
> new file mode 100644
> index 0000000000..8b5a7ee573
> --- /dev/null
> +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
> @@ -0,0 +1,37 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
> + * (dragonboard845c) pins
> + *
> + * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> + */
> +
> +/
> +{
> + soc {
> + u-boot,dm-pre-reloc;
> +
> + serial@a84000 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + clock-controller@100000 {
> + u-boot,dm-pre-reloc;
> + };
> +
> + pinctrl_north@3900000 {
> + u-boot,dm-pre-reloc;
> + };
> + };
> +};
These additional u-boot,dm-pre-reloc changes are different to the ones
that appear in starqltechn-uboot.dtsi . That suggests that either patch 1
is not actually removing redundant properties or that the DB845C port is
wrong.
> +config TARGET_DRAGONBOARD845C
> + bool "96Boards Dragonboard 845C"
> + help
> + Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
> + Platform. This board complies with 96Board Open Platform
Nitpicking but... s/96Board/96Boards/
Daniel.
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/8] board: qualcomm: Add support for dragonboard845c
2022-07-04 16:06 ` Daniel Thompson
@ 2022-07-05 5:40 ` Sumit Garg
0 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-05 5:40 UTC (permalink / raw)
To: Daniel Thompson
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski,
stephan, vinod.koul, nicolas.dechesne, mworsfold
Hi Daniel,
On Mon, 4 Jul 2022 at 21:36, Daniel Thompson <daniel.thompson@linaro.org> wrote:
>
> On Mon, Jul 04, 2022 at 06:28:41PM +0530, Sumit Garg wrote:
> > diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
> > new file mode 100644
> > index 0000000000..8b5a7ee573
> > --- /dev/null
> > +++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
> > @@ -0,0 +1,37 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
> > + * (dragonboard845c) pins
> > + *
> > + * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
> > + */
> > +
> > +/
> > +{
> > + soc {
> > + u-boot,dm-pre-reloc;
> > +
> > + serial@a84000 {
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + clock-controller@100000 {
> > + u-boot,dm-pre-reloc;
> > + };
> > +
> > + pinctrl_north@3900000 {
> > + u-boot,dm-pre-reloc;
> > + };
> > + };
> > +};
>
> These additional u-boot,dm-pre-reloc changes are different to the ones
> that appear in starqltechn-uboot.dtsi .
As I mentioned in the patch #1 review, u-boot properties are specified
incorrectly in starqltechn-uboot.dtsi. I will correct that.
> That suggests that either patch 1
> is not actually removing redundant properties or that the DB845C port is
> wrong.
The other node I left for DB845C without "u-boot,dm-pre-reloc" is
"gpio_north@3900000" as currently I am not using GPIO driver prior to
relocation.
>-Sumit
>
> > +config TARGET_DRAGONBOARD845C
> > + bool "96Boards Dragonboard 845C"
> > + help
> > + Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
> > + Platform. This board complies with 96Board Open Platform
>
> Nitpicking but... s/96Board/96Boards/
>
Okay, I will correct it.
-Sumit
>
> Daniel.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/8] mmc: msm_sdhci: Add SDCC version 5.0.0 support
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (3 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 4/8] board: qualcomm: Add support for dragonboard845c Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 12:58 ` [PATCH 6/8] pinctrl: qcom: Add pinctrl driver for QCS404 SoC Sumit Garg
` (3 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
For SDCC version 5.0.0, MCI registers are removed from SDCC interface
and some registers are moved to HC. So add support to use the new
compatible string "qcom,sdhci-msm-v5". Based on this new msm variant,
pick the relevant variant data and use it to detect MCI presence thereby
configuring register read/write to msm specific registers.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
drivers/mmc/msm_sdhci.c | 96 +++++++++++++++++++++++++++--------------
1 file changed, 64 insertions(+), 32 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index d63d7b3a2c..604f9c3ff9 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -22,18 +22,17 @@
#define SDCC_MCI_POWER_SW_RST BIT(7)
/* This is undocumented register */
-#define SDCC_MCI_VERSION 0x50
-#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
-#define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
-#define SDCC_MCI_VERSION_MINOR_MASK 0xff
+#define SDCC_MCI_VERSION 0x50
+#define SDCC_V5_VERSION 0x318
+
+#define SDCC_VERSION_MAJOR_SHIFT 28
+#define SDCC_VERSION_MAJOR_MASK (0xf << SDCC_VERSION_MAJOR_SHIFT)
+#define SDCC_VERSION_MINOR_MASK 0xff
#define SDCC_MCI_STATUS2 0x6C
#define SDCC_MCI_STATUS2_MCI_ACT 0x1
#define SDCC_MCI_HC_MODE 0x78
-/* Offset to SDHCI registers */
-#define SDCC_SDHCI_OFFSET 0x900
-
/* Non standard (?) SDHCI register */
#define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
@@ -47,6 +46,10 @@ struct msm_sdhc {
void *base;
};
+struct msm_sdhc_variant_info {
+ bool mci_removed;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
@@ -85,25 +88,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
return 0;
}
-static int msm_sdc_probe(struct udevice *dev)
+static int msm_sdc_mci_init(struct msm_sdhc *prv)
{
- struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
- struct msm_sdhc_plat *plat = dev_get_plat(dev);
- struct msm_sdhc *prv = dev_get_priv(dev);
- struct sdhci_host *host = &prv->host;
- u32 core_version, core_minor, core_major;
- u32 caps;
- int ret;
-
- host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
-
- host->max_clk = 0;
-
- /* Init clocks */
- ret = msm_sdc_clk_init(dev);
- if (ret)
- return ret;
-
/* Reset the core and Enable SDHC mode */
writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
prv->base + SDCC_MCI_POWER);
@@ -126,12 +112,45 @@ static int msm_sdc_probe(struct udevice *dev)
/* Enable host-controller mode */
writel(1, prv->base + SDCC_MCI_HC_MODE);
- core_version = readl(prv->base + SDCC_MCI_VERSION);
+ return 0;
+}
- core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
- core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+static int msm_sdc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct msm_sdhc_plat *plat = dev_get_plat(dev);
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
+ struct sdhci_host *host = &prv->host;
+ u32 core_version, core_minor, core_major;
+ u32 caps;
+ int ret;
- core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+
+ host->max_clk = 0;
+
+ /* Init clocks */
+ ret = msm_sdc_clk_init(dev);
+ if (ret)
+ return ret;
+
+ var_info = (void *)dev_get_driver_data(dev);
+ if (!var_info->mci_removed) {
+ ret = msm_sdc_mci_init(prv);
+ if (ret)
+ return ret;
+ }
+
+ if (!var_info->mci_removed)
+ core_version = readl(prv->base + SDCC_MCI_VERSION);
+ else
+ core_version = readl(host->ioaddr + SDCC_V5_VERSION);
+
+ core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
+ core_major >>= SDCC_VERSION_MAJOR_SHIFT;
+
+ core_minor = core_version & SDCC_VERSION_MINOR_MASK;
/*
* Support for some capabilities is not advertised by newer
@@ -161,9 +180,13 @@ static int msm_sdc_probe(struct udevice *dev)
static int msm_sdc_remove(struct udevice *dev)
{
struct msm_sdhc *priv = dev_get_priv(dev);
+ const struct msm_sdhc_variant_info *var_info;
+
+ var_info = (void *)dev_get_driver_data(dev);
- /* Disable host-controller mode */
- writel(0, priv->base + SDCC_MCI_HC_MODE);
+ /* Disable host-controller mode */
+ if (!var_info->mci_removed)
+ writel(0, priv->base + SDCC_MCI_HC_MODE);
return 0;
}
@@ -195,8 +218,17 @@ static int msm_sdc_bind(struct udevice *dev)
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
}
+static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
+ .mci_removed = false,
+};
+
+static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
+ .mci_removed = true,
+};
+
static const struct udevice_id msm_mmc_ids[] = {
- { .compatible = "qcom,sdhci-msm-v4" },
+ { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },
+ { .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var },
{ }
};
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/8] pinctrl: qcom: Add pinctrl driver for QCS404 SoC
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (4 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 5/8] mmc: msm_sdhci: Add SDCC version 5.0.0 support Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 12:58 ` [PATCH 7/8] clocks: qcom: Add clock " Sumit Garg
` (2 subsequent siblings)
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/mach-snapdragon/Makefile | 1 +
arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 +++++++++++++++++++
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
4 files changed, 58 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 962855eb8c..cb8c1aa8d2 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -15,4 +15,5 @@ obj-y += dram.o
obj-y += pinctrl-snapdragon.o
obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
+obj-y += pinctrl-qcs404.o
obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
new file mode 100644
index 0000000000..889ead0f57
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+ "SDC1_RCLK",
+ "SDC1_CLK",
+ "SDC1_CMD",
+ "SDC1_DATA",
+ "SDC2_CLK",
+ "SDC2_CMD",
+ "SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+ {"blsp_uart2", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+ unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ if (selector < 120) {
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ return pin_name;
+ } else {
+ return msm_pinctrl_pins[selector - 120];
+ }
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+ return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data qcs404_data = {
+ .pin_count = 126,
+ .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ .get_function_name = qcs404_get_function_name,
+ .get_function_mux = qcs404_get_function_mux,
+ .get_pin_name = qcs404_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index d1c560dd40..c2148a5d0a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
#ifdef CONFIG_SDM845
{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
#endif
+ { .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
{ }
};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index ea524312a0..178ee01a41 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,5 +28,6 @@ struct pinctrl_function {
extern struct msm_pinctrl_data apq8016_data;
extern struct msm_pinctrl_data apq8096_data;
extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data qcs404_data;
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 7/8] clocks: qcom: Add clock driver for QCS404 SoC
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (5 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 6/8] pinctrl: qcom: Add pinctrl driver for QCS404 SoC Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 12:58 ` [PATCH 8/8] board: qualcomm: Add support for QCS404 EVB Sumit Garg
2022-07-04 13:05 ` [PATCH 0/8] New boards support: db845c and qcs404-evb Peter Robinson
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Currently its a dummy clock driver as clocks for UART and eMMC have been
already enabled by ABL. Along with this import "qcom,gcc-qcs404.h" header
from Linux mainline to support DT bindings.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/mach-snapdragon/clock-qcs404.c | 30 ++++
arch/arm/mach-snapdragon/clock-snapdragon.c | 1 +
include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 ++++++++++++++++++++
3 files changed, 211 insertions(+)
create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
new file mode 100644
index 0000000000..0471adf0ba
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm QCS404
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+ switch (clk->id) {
+ default:
+ /*
+ * Clocks for UART and eMMC enabled in u-boot are already
+ * initialized by ABL. In case any peripheral requires special
+ * clock handling then that should be handled as a separate
+ * case above.
+ */
+ return 0;
+ }
+}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 3deb08ac4a..5652d2fa36 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
{ .compatible = "qcom,gcc-msm8996" },
{ .compatible = "qcom,gcc-apq8096" },
{ .compatible = "qcom,gcc-sdm845" },
+ { .compatible = "qcom,gcc-qcs404" },
{ }
};
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
new file mode 100644
index 0000000000..bc30515433
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+
+#define GCC_APSS_AHB_CLK_SRC 0
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC 1
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC 2
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define GCC_BLSP1_UART0_APPS_CLK_SRC 11
+#define GCC_BLSP1_UART1_APPS_CLK_SRC 12
+#define GCC_BLSP1_UART2_APPS_CLK_SRC 13
+#define GCC_BLSP1_UART3_APPS_CLK_SRC 14
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC 15
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC 16
+#define GCC_BLSP2_UART0_APPS_CLK_SRC 17
+#define GCC_BYTE0_CLK_SRC 18
+#define GCC_EMAC_CLK_SRC 19
+#define GCC_EMAC_PTP_CLK_SRC 20
+#define GCC_ESC0_CLK_SRC 21
+#define GCC_APSS_AHB_CLK 22
+#define GCC_APSS_AXI_CLK 23
+#define GCC_BIMC_APSS_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_MDSS_CLK 26
+#define GCC_BLSP1_AHB_CLK 27
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 31
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 32
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 33
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 34
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 35
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 36
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 37
+#define GCC_BLSP1_UART0_APPS_CLK 38
+#define GCC_BLSP1_UART1_APPS_CLK 39
+#define GCC_BLSP1_UART2_APPS_CLK 40
+#define GCC_BLSP1_UART3_APPS_CLK 41
+#define GCC_BLSP2_AHB_CLK 42
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK 43
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK 44
+#define GCC_BLSP2_UART0_APPS_CLK 45
+#define GCC_BOOT_ROM_AHB_CLK 46
+#define GCC_DCC_CLK 47
+#define GCC_GENI_IR_H_CLK 48
+#define GCC_ETH_AXI_CLK 49
+#define GCC_ETH_PTP_CLK 50
+#define GCC_ETH_RGMII_CLK 51
+#define GCC_ETH_SLAVE_AHB_CLK 52
+#define GCC_GENI_IR_S_CLK 53
+#define GCC_GP1_CLK 54
+#define GCC_GP2_CLK 55
+#define GCC_GP3_CLK 56
+#define GCC_MDSS_AHB_CLK 57
+#define GCC_MDSS_AXI_CLK 58
+#define GCC_MDSS_BYTE0_CLK 59
+#define GCC_MDSS_ESC0_CLK 60
+#define GCC_MDSS_HDMI_APP_CLK 61
+#define GCC_MDSS_HDMI_PCLK_CLK 62
+#define GCC_MDSS_MDP_CLK 63
+#define GCC_MDSS_PCLK0_CLK 64
+#define GCC_MDSS_VSYNC_CLK 65
+#define GCC_OXILI_AHB_CLK 66
+#define GCC_OXILI_GFX3D_CLK 67
+#define GCC_PCIE_0_AUX_CLK 68
+#define GCC_PCIE_0_CFG_AHB_CLK 69
+#define GCC_PCIE_0_MSTR_AXI_CLK 70
+#define GCC_PCIE_0_PIPE_CLK 71
+#define GCC_PCIE_0_SLV_AXI_CLK 72
+#define GCC_PCNOC_USB2_CLK 73
+#define GCC_PCNOC_USB3_CLK 74
+#define GCC_PDM2_CLK 75
+#define GCC_PDM_AHB_CLK 76
+#define GCC_VSYNC_CLK_SRC 77
+#define GCC_PRNG_AHB_CLK 78
+#define GCC_PWM0_XO512_CLK 79
+#define GCC_PWM1_XO512_CLK 80
+#define GCC_PWM2_XO512_CLK 81
+#define GCC_SDCC1_AHB_CLK 82
+#define GCC_SDCC1_APPS_CLK 83
+#define GCC_SDCC1_ICE_CORE_CLK 84
+#define GCC_SDCC2_AHB_CLK 85
+#define GCC_SDCC2_APPS_CLK 86
+#define GCC_SYS_NOC_USB3_CLK 87
+#define GCC_USB20_MOCK_UTMI_CLK 88
+#define GCC_USB2A_PHY_SLEEP_CLK 89
+#define GCC_USB30_MASTER_CLK 90
+#define GCC_USB30_MOCK_UTMI_CLK 91
+#define GCC_USB30_SLEEP_CLK 92
+#define GCC_USB3_PHY_AUX_CLK 93
+#define GCC_USB3_PHY_PIPE_CLK 94
+#define GCC_USB_HS_PHY_CFG_AHB_CLK 95
+#define GCC_USB_HS_SYSTEM_CLK 96
+#define GCC_GFX3D_CLK_SRC 97
+#define GCC_GP1_CLK_SRC 98
+#define GCC_GP2_CLK_SRC 99
+#define GCC_GP3_CLK_SRC 100
+#define GCC_GPLL0_OUT_MAIN 101
+#define GCC_GPLL1_OUT_MAIN 102
+#define GCC_GPLL3_OUT_MAIN 103
+#define GCC_GPLL4_OUT_MAIN 104
+#define GCC_HDMI_APP_CLK_SRC 105
+#define GCC_HDMI_PCLK_CLK_SRC 106
+#define GCC_MDP_CLK_SRC 107
+#define GCC_PCIE_0_AUX_CLK_SRC 108
+#define GCC_PCIE_0_PIPE_CLK_SRC 109
+#define GCC_PCLK0_CLK_SRC 110
+#define GCC_PDM2_CLK_SRC 111
+#define GCC_SDCC1_APPS_CLK_SRC 112
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 113
+#define GCC_SDCC2_APPS_CLK_SRC 114
+#define GCC_USB20_MOCK_UTMI_CLK_SRC 115
+#define GCC_USB30_MASTER_CLK_SRC 116
+#define GCC_USB30_MOCK_UTMI_CLK_SRC 117
+#define GCC_USB3_PHY_AUX_CLK_SRC 118
+#define GCC_USB_HS_SYSTEM_CLK_SRC 119
+#define GCC_GPLL0_AO_CLK_SRC 120
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 122
+#define GCC_GPLL0_AO_OUT_MAIN 123
+#define GCC_GPLL0_SLEEP_CLK_SRC 124
+#define GCC_GPLL6 125
+#define GCC_GPLL6_OUT_AUX 126
+#define GCC_MDSS_MDP_VOTE_CLK 127
+#define GCC_MDSS_ROTATOR_VOTE_CLK 128
+#define GCC_BIMC_GPU_CLK 129
+#define GCC_GTCU_AHB_CLK 130
+#define GCC_GFX_TCU_CLK 131
+#define GCC_GFX_TBU_CLK 132
+#define GCC_SMMU_CFG_CLK 133
+#define GCC_APSS_TCU_CLK 134
+#define GCC_CRYPTO_AHB_CLK 135
+#define GCC_CRYPTO_AXI_CLK 136
+#define GCC_CRYPTO_CLK 137
+#define GCC_MDP_TBU_CLK 138
+#define GCC_QDSS_DAP_CLK 139
+#define GCC_DCC_XO_CLK 140
+#define GCC_WCSS_Q6_AHB_CLK 141
+#define GCC_WCSS_Q6_AXIM_CLK 142
+#define GCC_CDSP_CFG_AHB_CLK 143
+#define GCC_BIMC_CDSP_CLK 144
+#define GCC_CDSP_TBU_CLK 145
+#define GCC_CDSP_BIMC_CLK_SRC 146
+
+#define GCC_GENI_IR_BCR 0
+#define GCC_USB_HS_BCR 1
+#define GCC_USB2_HS_PHY_ONLY_BCR 2
+#define GCC_QUSB2_PHY_BCR 3
+#define GCC_USB_HS_PHY_CFG_AHB_BCR 4
+#define GCC_USB2A_PHY_BCR 5
+#define GCC_USB3_PHY_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB3PHY_PHY_BCR 8
+#define GCC_PCIE_0_BCR 9
+#define GCC_PCIE_0_PHY_BCR 10
+#define GCC_PCIE_0_LINK_DOWN_BCR 11
+#define GCC_PCIEPHY_0_PHY_BCR 12
+#define GCC_EMAC_BCR 13
+#define GCC_CDSP_RESTART 14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 15
+#define GCC_PCIE_0_AHB_ARES 16
+#define GCC_PCIE_0_AXI_SLAVE_ARES 17
+#define GCC_PCIE_0_AXI_MASTER_ARES 18
+#define GCC_PCIE_0_CORE_STICKY_ARES 19
+#define GCC_PCIE_0_SLEEP_ARES 20
+#define GCC_PCIE_0_PIPE_ARES 21
+#define GCC_WDSP_RESTART 22
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 8/8] board: qualcomm: Add support for QCS404 EVB
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (6 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 7/8] clocks: qcom: Add clock " Sumit Garg
@ 2022-07-04 12:58 ` Sumit Garg
2022-07-04 13:05 ` [PATCH 0/8] New boards support: db845c and qcs404-evb Peter Robinson
8 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 12:58 UTC (permalink / raw)
To: u-boot
Cc: rfried.dev, peng.fan, jh80.chung, sjg, trini, dsankouski, stephan,
vinod.koul, nicolas.dechesne, mworsfold, daniel.thompson,
Sumit Garg
Add support for Qualcomm QCS404 SoC based evaluation board.
Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot
U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/qcs404-evb-uboot.dtsi | 24 ++++++
arch/arm/dts/qcs404-evb.dts | 81 +++++++++++++++++++
arch/arm/mach-snapdragon/Kconfig | 11 +++
arch/arm/mach-snapdragon/Makefile | 2 +
.../include/mach/sysmap-qcs404.h | 13 +++
arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++++++
board/qualcomm/qcs404-evb/Kconfig | 15 ++++
board/qualcomm/qcs404-evb/MAINTAINERS | 6 ++
board/qualcomm/qcs404-evb/Makefile | 6 ++
board/qualcomm/qcs404-evb/qcs404-evb.c | 33 ++++++++
board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++++++++++++++
configs/qcs404evb_defconfig | 39 +++++++++
doc/board/qualcomm/index.rst | 1 +
doc/board/qualcomm/qcs404.rst | 79 ++++++++++++++++++
include/configs/qcs404-evb.h | 27 +++++++
16 files changed, 433 insertions(+)
create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi
create mode 100644 arch/arm/dts/qcs404-evb.dts
create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c
create mode 100644 board/qualcomm/qcs404-evb/Kconfig
create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS
create mode 100644 board/qualcomm/qcs404-evb/Makefile
create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c
create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its
create mode 100644 configs/qcs404evb_defconfig
create mode 100644 doc/board/qualcomm/qcs404.rst
create mode 100644 include/configs/qcs404-evb.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a7e0d9f6c0..a561b28cef 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -502,6 +502,7 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
+dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi
new file mode 100644
index 0000000000..c18080a483
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb-uboot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle QCS404 EVB pre-relocation devices
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+
+ pinctrl_north@1300000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ clock-controller@1800000 {
+ u-boot,dm-pre-reloc;
+ };
+
+ serial@78b1000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
new file mode 100644
index 0000000000..4f0ae20bdb
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 based evaluation board device tree source
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCS404 EVB";
+ compatible = "qcom,qcs404-evb", "qcom,qcs404";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &debug_uart;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0 0x40000000>;
+ };
+
+ soc {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ ranges = <0x0 0x0 0x0 0xffffffff>;
+ compatible = "simple-bus";
+
+ pinctrl_north@1300000 {
+ compatible = "qcom,tlmm-qcs404";
+ reg = <0x1300000 0x200000>;
+
+ blsp1_uart2: uart {
+ pins = "GPIO_17", "GPIO_18";
+ function = "blsp_uart2";
+ };
+ };
+
+ gcc: clock-controller@1800000 {
+ compatible = "qcom,gcc-qcs404";
+ reg = <0x1800000 0x80000>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ debug_uart: serial@78b1000 {
+ compatible = "qcom,msm-uartdm-v1.4";
+ reg = <0x78b1000 0x200>;
+ clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ bit-rate = <0xFF>;
+ pinctrl-names = "uart";
+ pinctrl-0 = <&blsp1_uart2>;
+ };
+
+ sdhci@7804000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x7804000 0x1000 0x7805000 0x1000>;
+ clock = <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ bus-width = <0x8>;
+ index = <0x0>;
+ non-removable;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ };
+ };
+};
+
+#include "qcs404-evb-uboot.dtsi"
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 34af40b915..ffd5bfb6dc 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -69,11 +69,22 @@ config TARGET_STARQLTECHN
select SDM845
select DM_ETH if NET
+config TARGET_QCS404EVB
+ bool "Qualcomm Technologies, Inc. QCS404 EVB"
+ select LINUX_KERNEL_IMAGE_HEADER
+ help
+ Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
+ Features:
+ - Qualcomm Snapdragon QCS404 SoC
+ - 1GiB RAM
+ - 8GiB eMMC, uSD slot
+
endchoice
source "board/qualcomm/dragonboard410c/Kconfig"
source "board/qualcomm/dragonboard820c/Kconfig"
source "board/qualcomm/dragonboard845c/Kconfig"
source "board/samsung/starqltechn/Kconfig"
+source "board/qualcomm/qcs404-evb/Kconfig"
endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index cb8c1aa8d2..0d31f10f68 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -17,3 +17,5 @@ obj-y += pinctrl-apq8016.o
obj-y += pinctrl-apq8096.o
obj-y += pinctrl-qcs404.o
obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
+obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
new file mode 100644
index 0000000000..c495f43a6b
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm QCS404 sysmap
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+#ifndef _MACH_SYSMAP_QCS404_H
+#define _MACH_SYSMAP_QCS404_H
+
+#define GICD_BASE (0x0b000000)
+#define GICC_BASE (0x0b002000)
+
+#endif
diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
new file mode 100644
index 0000000000..b7409031a0
--- /dev/null
+++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 memory map
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qcs404_mem_map[] = {
+ {
+ .virt = 0x0UL, /* Peripheral block */
+ .phys = 0x0UL, /* Peripheral block */
+ .size = 0x8000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL, /* DDR */
+ .phys = 0x80000000UL, /* DDR */
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = qcs404_mem_map;
diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig
new file mode 100644
index 0000000000..32657c7d5e
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QCS404EVB
+
+config SYS_BOARD
+ default "qcs404-evb"
+
+config SYS_VENDOR
+ default "qualcomm"
+
+config SYS_SOC
+ default "qcs404"
+
+config SYS_CONFIG_NAME
+ default "qcs404-evb"
+
+endif
diff --git a/board/qualcomm/qcs404-evb/MAINTAINERS b/board/qualcomm/qcs404-evb/MAINTAINERS
new file mode 100644
index 0000000000..0a2e194ff6
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/MAINTAINERS
@@ -0,0 +1,6 @@
+Qualcomm Technologies, Inc. QCS404 evaluation board
+M: Sumit Garg <sumit.garg@linaro.org>
+S: Maintained
+F: board/qualcomm/qcs404-evb/
+F: include/configs/qcs404-evb.h
+F: configs/qcs404evb_defconfig
diff --git a/board/qualcomm/qcs404-evb/Makefile b/board/qualcomm/qcs404-evb/Makefile
new file mode 100644
index 0000000000..4665827e08
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+#
+
+obj-y += qcs404-evb.o
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
new file mode 100644
index 0000000000..f1e6e7f7eb
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for QCS404-EVB
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <asm/arch/dram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+ psci_system_reset();
+}
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.its b/board/qualcomm/qcs404-evb/qcs404-evb.its
new file mode 100644
index 0000000000..c9822827c9
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.its
@@ -0,0 +1,64 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+ description = "Various kernels, ramdisks and FDT blobs";
+ #address-cells = <1>;
+
+ images {
+ kernel-1 {
+ description = "5.18.0-rc1";
+ data = /incbin/("./qcs404_imgs/Image.gz");
+ type = "kernel";
+ arch = "arm64";
+ os = "linux";
+ compression = "gzip";
+ load = <0x80000000>;
+ entry = <0x80000000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ ramdisk-1 {
+ description = "Initial ramdisk";
+ data = /incbin/("./qcs404_imgs/initramfs-tiny-image-qemuarm64-20220618074058-1169.rootfs.cpio.gz");
+ type = "ramdisk";
+ arch = "arm64";
+ os = "linux";
+ compression = "gzip";
+ load = <00000000>;
+ entry = <00000000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ fdt-1 {
+ description = "qcs404-evb-fdt";
+ data = /incbin/("./qcs404_imgs/qcs404-evb-4000.dtb");
+ type = "flat_dt";
+ arch = "arm64";
+ compression = "none";
+ load = <0x83000000>;
+ hash-1 {
+ algo = "sha1";
+ };
+ };
+
+ };
+
+ configurations {
+ default = "config-1";
+
+ config-1 {
+ description = "qcs404-evb kernel-5.18.0-rc1 configuration";
+ kernel = "kernel-1";
+ ramdisk = "ramdisk-1";
+ fdt = "fdt-1";
+ };
+ };
+};
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
new file mode 100644
index 0000000000..7c76e8353e
--- /dev/null
+++ b/configs/qcs404evb_defconfig
@@ -0,0 +1,39 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
+CONFIG_TARGET_QCS404EVB=y
+CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
+CONFIG_SYS_TEXT_BASE=0x0
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_PINCTRL=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MSM_SERIAL=y
+CONFIG_LMB_MAX_REGIONS=64
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 10b98214e9..0f9c429956 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -8,3 +8,4 @@ Qualcomm
dragonboard410c
sdm845
+ qcs404
diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
new file mode 100644
index 0000000000..bbb40b043b
--- /dev/null
+++ b/doc/board/qualcomm/qcs404.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
+
+QCS404 EVB
+==========
+
+About this
+----------
+This document describes the information about Qualcomm QCS404 evaluation board
+and it's usage steps.
+
+U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
+It is loaded as an Android boot image through ABL
+
+Installation
+------------
+Build
+^^^^^
+Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
+
+ $ export CROSS_COMPILE=<aarch64 toolchain prefix>
+ $ make qcs404evb_defconfig
+ $ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Generate FIT image
+^^^^^^^^^^^^^^^^^^
+A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
+It expects a folder as ``qcs404_imgs/`` in the main directory containing
+pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
+images.
+
+- Build FIT image::
+
+ mkimage -f qcs404-evb.its qcs404-evb.itb
+
+Pack android boot image
+^^^^^^^^^^^^^^^^^^^^^^^
+We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
+and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
+with appended dtb, so let's mimic linux to satisfy stock bootloader:
+
+- create dump dtb::
+
+ workdir=/tmp/prepare_payload
+ mkdir -p "$workdir"
+ cd "$workdir"
+ mock_dtb="$workdir"/payload_mock.dtb
+
+ dtc -I dts -O dtb -o "$mock_dtb" << EOF
+ /dts-v1/;
+ / {
+ model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
+ compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ chosen { };
+ };
+ EOF
+
+- gzip u-boot ``gzip u-boot.bin``
+- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+
+Now we've got everything to build android boot image:::
+
+ mkbootimg --kernel u-boot.bin.gz-dtb \
+ --ramdisk qcs404-evb.itb --pagesize 4096 \
+ --base 0x80000000 --output boot.img
+
+Flash image on qcs404-evb using fastboot method.
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
new file mode 100644
index 0000000000..a7f645b613
--- /dev/null
+++ b/include/configs/qcs404-evb.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for QCS404 evaluation board
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#ifndef __CONFIGS_QCS404EVB_H
+#define __CONFIGS_QCS404EVB_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-qcs404.h>
+
+#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootm_size=0x5000000\0" \
+ "bootm_low=0x80000000\0" \
+ "bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 64
+
+#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 0/8] New boards support: db845c and qcs404-evb
2022-07-04 12:58 [PATCH 0/8] New boards support: db845c and qcs404-evb Sumit Garg
` (7 preceding siblings ...)
2022-07-04 12:58 ` [PATCH 8/8] board: qualcomm: Add support for QCS404 EVB Sumit Garg
@ 2022-07-04 13:05 ` Peter Robinson
2022-07-04 13:09 ` Sumit Garg
8 siblings, 1 reply; 17+ messages in thread
From: Peter Robinson @ 2022-07-04 13:05 UTC (permalink / raw)
To: Sumit Garg
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, Simon Glass, trini,
dsankouski, stephan, vinod.koul, nicolas.dechesne, mworsfold,
daniel.thompson
> Add support for two new boards db845c and qcs404-evb:
> - db845c is a 96boards compliant platform aka RB3 based on Qualcomm
> SDM845 SoC.
> - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC.
>
> Both these platforms have one thing in common that u-boot is chain-loaded
> in 64-bit mode via Android Boot Loader (ABL) which is an EFI application.
Can we have some docs on how that works, how to build it, how to set
it up for chain loading etc.
Peter
> Sumit Garg (8):
> arm64: dts: sdm845: Remove redundant u-boot DT properties
> clocks: sdm845: Import qcom,gcc-sdm845.h
> uart: sdm845: Fix debug UART pinmux
> board: qualcomm: Add support for dragonboard845c
> mmc: msm_sdhci: Add SDCC version 5.0.0 support
> pinctrl: qcom: Add pinctrl driver for QCS404 SoC
> clocks: qcom: Add clock driver for QCS404 SoC
> board: qualcomm: Add support for QCS404 EVB
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++
> arch/arm/dts/dragonboard845c.dts | 44 ++++
> arch/arm/dts/qcs404-evb-uboot.dtsi | 24 ++
> arch/arm/dts/qcs404-evb.dts | 81 ++++++
> arch/arm/dts/sdm845.dtsi | 8 +-
> arch/arm/mach-snapdragon/Kconfig | 25 ++
> arch/arm/mach-snapdragon/Makefile | 3 +
> arch/arm/mach-snapdragon/clock-qcs404.c | 30 +++
> arch/arm/mach-snapdragon/clock-sdm845.c | 3 +-
> arch/arm/mach-snapdragon/clock-snapdragon.c | 1 +
> .../include/mach/sysmap-qcs404.h | 13 +
> arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 ++++
> arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
> arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
> arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++
> board/qualcomm/dragonboard845c/Kconfig | 12 +
> board/qualcomm/dragonboard845c/MAINTAINERS | 6 +
> board/qualcomm/dragonboard845c/Makefile | 9 +
> board/qualcomm/dragonboard845c/db845c.its | 63 +++++
> .../dragonboard845c/dragonboard845c.c | 9 +
> board/qualcomm/qcs404-evb/Kconfig | 15 ++
> board/qualcomm/qcs404-evb/MAINTAINERS | 6 +
> board/qualcomm/qcs404-evb/Makefile | 6 +
> board/qualcomm/qcs404-evb/qcs404-evb.c | 33 +++
> board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++++
> configs/dragonboard845c_defconfig | 28 ++
> configs/qcs404evb_defconfig | 39 +++
> doc/board/qualcomm/index.rst | 1 +
> doc/board/qualcomm/qcs404.rst | 79 ++++++
> doc/board/qualcomm/sdm845.rst | 100 ++++++-
> drivers/mmc/msm_sdhci.c | 96 ++++---
> include/configs/dragonboard845c.h | 28 ++
> include/configs/qcs404-evb.h | 27 ++
> include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 +++++++++++++
> include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++++++++++++++++++
> 36 files changed, 1354 insertions(+), 51 deletions(-)
> create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi
> create mode 100644 arch/arm/dts/dragonboard845c.dts
> create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi
> create mode 100644 arch/arm/dts/qcs404-evb.dts
> create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c
> create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
> create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c
> create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c
> create mode 100644 board/qualcomm/dragonboard845c/Kconfig
> create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS
> create mode 100644 board/qualcomm/dragonboard845c/Makefile
> create mode 100644 board/qualcomm/dragonboard845c/db845c.its
> create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c
> create mode 100644 board/qualcomm/qcs404-evb/Kconfig
> create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS
> create mode 100644 board/qualcomm/qcs404-evb/Makefile
> create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c
> create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its
> create mode 100644 configs/dragonboard845c_defconfig
> create mode 100644 configs/qcs404evb_defconfig
> create mode 100644 doc/board/qualcomm/qcs404.rst
> create mode 100644 include/configs/dragonboard845c.h
> create mode 100644 include/configs/qcs404-evb.h
> create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 0/8] New boards support: db845c and qcs404-evb
2022-07-04 13:05 ` [PATCH 0/8] New boards support: db845c and qcs404-evb Peter Robinson
@ 2022-07-04 13:09 ` Sumit Garg
0 siblings, 0 replies; 17+ messages in thread
From: Sumit Garg @ 2022-07-04 13:09 UTC (permalink / raw)
To: Peter Robinson
Cc: u-boot, rfried.dev, peng.fan, jh80.chung, Simon Glass, trini,
dsankouski, stephan, vinod.koul, nicolas.dechesne, mworsfold,
daniel.thompson
Hi Peter,
On Mon, 4 Jul 2022 at 18:35, Peter Robinson <pbrobinson@gmail.com> wrote:
>
> > Add support for two new boards db845c and qcs404-evb:
> > - db845c is a 96boards compliant platform aka RB3 based on Qualcomm
> > SDM845 SoC.
> > - qcs404-evb is an evaluation board from Qualcomm based on QCS404 SoC.
> >
> > Both these platforms have one thing in common that u-boot is chain-loaded
> > in 64-bit mode via Android Boot Loader (ABL) which is an EFI application.
>
> Can we have some docs on how that works, how to build it, how to set
> it up for chain loading etc.
Please follow documentation added/updated by this patch-set [1] [2].
[1] doc/board/qualcomm/sdm845.rst
[2] doc/board/qualcomm/qcs404.rst
-Sumit
>
> Peter
>
> > Sumit Garg (8):
> > arm64: dts: sdm845: Remove redundant u-boot DT properties
> > clocks: sdm845: Import qcom,gcc-sdm845.h
> > uart: sdm845: Fix debug UART pinmux
> > board: qualcomm: Add support for dragonboard845c
> > mmc: msm_sdhci: Add SDCC version 5.0.0 support
> > pinctrl: qcom: Add pinctrl driver for QCS404 SoC
> > clocks: qcom: Add clock driver for QCS404 SoC
> > board: qualcomm: Add support for QCS404 EVB
> >
> > arch/arm/dts/Makefile | 1 +
> > arch/arm/dts/dragonboard845c-uboot.dtsi | 37 +++
> > arch/arm/dts/dragonboard845c.dts | 44 ++++
> > arch/arm/dts/qcs404-evb-uboot.dtsi | 24 ++
> > arch/arm/dts/qcs404-evb.dts | 81 ++++++
> > arch/arm/dts/sdm845.dtsi | 8 +-
> > arch/arm/mach-snapdragon/Kconfig | 25 ++
> > arch/arm/mach-snapdragon/Makefile | 3 +
> > arch/arm/mach-snapdragon/clock-qcs404.c | 30 +++
> > arch/arm/mach-snapdragon/clock-sdm845.c | 3 +-
> > arch/arm/mach-snapdragon/clock-snapdragon.c | 1 +
> > .../include/mach/sysmap-qcs404.h | 13 +
> > arch/arm/mach-snapdragon/pinctrl-qcs404.c | 55 ++++
> > arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 1 +
> > arch/arm/mach-snapdragon/pinctrl-snapdragon.h | 1 +
> > arch/arm/mach-snapdragon/sysmap-qcs404.c | 31 +++
> > board/qualcomm/dragonboard845c/Kconfig | 12 +
> > board/qualcomm/dragonboard845c/MAINTAINERS | 6 +
> > board/qualcomm/dragonboard845c/Makefile | 9 +
> > board/qualcomm/dragonboard845c/db845c.its | 63 +++++
> > .../dragonboard845c/dragonboard845c.c | 9 +
> > board/qualcomm/qcs404-evb/Kconfig | 15 ++
> > board/qualcomm/qcs404-evb/MAINTAINERS | 6 +
> > board/qualcomm/qcs404-evb/Makefile | 6 +
> > board/qualcomm/qcs404-evb/qcs404-evb.c | 33 +++
> > board/qualcomm/qcs404-evb/qcs404-evb.its | 64 +++++
> > configs/dragonboard845c_defconfig | 28 ++
> > configs/qcs404evb_defconfig | 39 +++
> > doc/board/qualcomm/index.rst | 1 +
> > doc/board/qualcomm/qcs404.rst | 79 ++++++
> > doc/board/qualcomm/sdm845.rst | 100 ++++++-
> > drivers/mmc/msm_sdhci.c | 96 ++++---
> > include/configs/dragonboard845c.h | 28 ++
> > include/configs/qcs404-evb.h | 27 ++
> > include/dt-bindings/clock/qcom,gcc-qcs404.h | 180 +++++++++++++
> > include/dt-bindings/clock/qcom,gcc-sdm845.h | 246 ++++++++++++++++++
> > 36 files changed, 1354 insertions(+), 51 deletions(-)
> > create mode 100644 arch/arm/dts/dragonboard845c-uboot.dtsi
> > create mode 100644 arch/arm/dts/dragonboard845c.dts
> > create mode 100644 arch/arm/dts/qcs404-evb-uboot.dtsi
> > create mode 100644 arch/arm/dts/qcs404-evb.dts
> > create mode 100644 arch/arm/mach-snapdragon/clock-qcs404.c
> > create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
> > create mode 100644 arch/arm/mach-snapdragon/pinctrl-qcs404.c
> > create mode 100644 arch/arm/mach-snapdragon/sysmap-qcs404.c
> > create mode 100644 board/qualcomm/dragonboard845c/Kconfig
> > create mode 100644 board/qualcomm/dragonboard845c/MAINTAINERS
> > create mode 100644 board/qualcomm/dragonboard845c/Makefile
> > create mode 100644 board/qualcomm/dragonboard845c/db845c.its
> > create mode 100644 board/qualcomm/dragonboard845c/dragonboard845c.c
> > create mode 100644 board/qualcomm/qcs404-evb/Kconfig
> > create mode 100644 board/qualcomm/qcs404-evb/MAINTAINERS
> > create mode 100644 board/qualcomm/qcs404-evb/Makefile
> > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.c
> > create mode 100644 board/qualcomm/qcs404-evb/qcs404-evb.its
> > create mode 100644 configs/dragonboard845c_defconfig
> > create mode 100644 configs/qcs404evb_defconfig
> > create mode 100644 doc/board/qualcomm/qcs404.rst
> > create mode 100644 include/configs/dragonboard845c.h
> > create mode 100644 include/configs/qcs404-evb.h
> > create mode 100644 include/dt-bindings/clock/qcom,gcc-qcs404.h
> > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm845.h
> >
> > --
> > 2.25.1
> >
^ permalink raw reply [flat|nested] 17+ messages in thread