From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <u-boot@lists.denx.de>
Cc: <ycliang@andestech.com>, <rick@andestech.com>,
<prabhakar.csengg@gmail.com>,
Yu Chien Peter Lin <peterlin@andestech.com>
Subject: [PATCH v2 05/10] riscv: ae350: dts: Update L2 cache compatible string
Date: Mon, 6 Feb 2023 16:10:48 +0800 [thread overview]
Message-ID: <20230206081053.1716-6-peterlin@andestech.com> (raw)
In-Reply-To: <20230206081053.1716-1-peterlin@andestech.com>
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
arch/riscv/dts/ae350_32.dts | 2 +-
arch/riscv/dts/ae350_64.dts | 2 +-
drivers/cache/cache-v5l2.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 96ef8bd8dd..61af6d5465 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -112,7 +112,7 @@
};
L2: l2-cache@e0500000 {
- compatible = "v5l2cache";
+ compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0xe0500000 0x40000>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index cddbaec98a..8c7db29b4f 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -112,7 +112,7 @@
};
L2: l2-cache@e0500000 {
- compatible = "v5l2cache";
+ compatible = "cache";
cache-level = <2>;
cache-size = <0x40000>;
reg = <0x0 0xe0500000 0x0 0x40000>;
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
index e782430c57..c6d3a8f893 100644
--- a/drivers/cache/cache-v5l2.c
+++ b/drivers/cache/cache-v5l2.c
@@ -184,7 +184,7 @@ static int v5l2_probe(struct udevice *dev)
}
static const struct udevice_id v5l2_cache_ids[] = {
- { .compatible = "v5l2cache" },
+ { .compatible = "cache" },
{}
};
--
2.34.1
next prev parent reply other threads:[~2023-02-06 8:12 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-06 8:10 [PATCH v2 00/10] cache operation cleanups for Andes AE350 platform Yu Chien Peter Lin
2023-02-06 8:10 ` [PATCH v2 01/10] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" Yu Chien Peter Lin
2023-02-06 8:10 ` [PATCH v2 02/10] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() Yu Chien Peter Lin
2023-02-06 8:10 ` [PATCH v2 03/10] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform Yu Chien Peter Lin
[not found] ` <PU1PR03MB299780A8F8A9E40700D3AFF1C1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 1:37 ` Rick Chen
2023-02-06 8:10 ` [PATCH v2 04/10] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() Yu Chien Peter Lin
[not found] ` <PU1PR03MB2997F3D15C2AEE4EA0622A9EC1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 1:43 ` Rick Chen
2023-02-06 8:10 ` Yu Chien Peter Lin [this message]
[not found] ` <PU1PR03MB29979A932AB9E25300FA0B3DC1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 1:50 ` [PATCH v2 05/10] riscv: ae350: dts: Update L2 cache compatible string Rick Chen
2023-02-06 8:10 ` [PATCH v2 06/10] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL Yu Chien Peter Lin
[not found] ` <PU1PR03MB29979831919688FE773ECD5DC1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 1:55 ` Rick Chen
2023-02-06 8:10 ` [PATCH v2 07/10] configs: ae350: Enable v5l2 cache for AE350 platforms " Yu Chien Peter Lin
[not found] ` <PU1PR03MB29970FA2B9B1C5190208AB58C1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 2:02 ` Rick Chen
2023-02-06 8:10 ` [PATCH v2 08/10] configs: ae350: Increase maximum retry count for AE350 platforms Yu Chien Peter Lin
2023-02-06 8:10 ` [PATCH v2 09/10] configs: ae350: Display CPU and board info " Yu Chien Peter Lin
[not found] ` <PU1PR03MB2997124FC7A3EC9330D26D12C1D89@PU1PR03MB2997.apcprd03.prod.outlook.com>
2023-02-08 2:20 ` Rick Chen
2023-02-06 8:10 ` [PATCH v2 10/10] driver: cache-v5l2: Fix type casting warning on RV32 Yu Chien Peter Lin
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