* [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified
2023-03-13 12:42 [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3 Sinthu Raja
@ 2023-03-13 12:42 ` Sinthu Raja
2023-03-30 1:54 ` Tom Rini
2023-03-13 12:42 ` [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap Sinthu Raja
2023-03-15 9:25 ` [EXTERNAL] [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3 Ravi Gunasekaran
2 siblings, 1 reply; 6+ messages in thread
From: Sinthu Raja @ 2023-03-13 12:42 UTC (permalink / raw)
To: u-boot, Tom Rini, Ravi Gunasekaran, Vignesh Raghavendra; +Cc: Sinthu Raja
From: Sinthu Raja <sinthu.raja@ti.com>
It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.
Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---
drivers/phy/ti/phy-j721e-wiz.c | 38 ++++++++++++++++++++++++++--------
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 6646b15d41..8e29f39cd8 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -329,6 +329,7 @@ struct wiz {
u32 num_lanes;
struct gpio_desc *gpio_typec_dir;
u32 lane_phy_type[WIZ_MAX_LANES];
+ u32 master_lane_num[WIZ_MAX_LANES];
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
unsigned int id;
const struct wiz_data *data;
@@ -586,14 +587,31 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
return ret;
/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
- if (id == 0 && wiz->gpio_typec_dir) {
- if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
- regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
- WIZ_SERDES_TYPEC_LN10_SWAP,
- WIZ_SERDES_TYPEC_LN10_SWAP);
- } else {
- regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
- WIZ_SERDES_TYPEC_LN10_SWAP, 0);
+ if (id == 0) {
+ if (wiz->gpio_typec_dir) {
+ if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
+ regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+ WIZ_SERDES_TYPEC_LN10_SWAP,
+ WIZ_SERDES_TYPEC_LN10_SWAP);
+ } else {
+ regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+ WIZ_SERDES_TYPEC_LN10_SWAP, 0);
+ }
+ }
+ } else {
+ /* if no typec-dir gpio was specified and PHY type is
+ * USB3 with master lane number is '0', set LN10 SWAP
+ * bit to '1'
+ */
+ u32 num_lanes = wiz->num_lanes;
+ int i;
+
+ for (i = 0; i < num_lanes; i++) {
+ if (wiz->lane_phy_type[i] == PHY_TYPE_USB3)
+ if (wiz->master_lane_num[i] == 0)
+ regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+ WIZ_SERDES_TYPEC_LN10_SWAP,
+ WIZ_SERDES_TYPEC_LN10_SWAP);
}
}
@@ -1100,8 +1118,10 @@ static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
reg, reg + num_lanes - 1, phy_type);
- for (i = reg; i < reg + num_lanes; i++)
+ for (i = reg; i < reg + num_lanes; i++) {
wiz->lane_phy_type[i] = phy_type;
+ wiz->master_lane_num[i] = reg;
+ }
}
return 0;
--
2.36.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified
2023-03-13 12:42 ` [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified Sinthu Raja
@ 2023-03-30 1:54 ` Tom Rini
0 siblings, 0 replies; 6+ messages in thread
From: Tom Rini @ 2023-03-30 1:54 UTC (permalink / raw)
To: Sinthu Raja; +Cc: u-boot, Ravi Gunasekaran, Vignesh Raghavendra, Sinthu Raja
[-- Attachment #1: Type: text/plain, Size: 593 bytes --]
On Mon, Mar 13, 2023 at 06:12:23PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
>
> It's possible that the Type-C plug orientation on the DIR line will be
> implemented through hardware design. In that situation, there won't be
> an external GPIO line available, but the driver still needs to address
> this since the DT won't use the typec-dir-gpios property.
>
> Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
> specified in DT.
>
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Applied to u-boot/next, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
2023-03-13 12:42 [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3 Sinthu Raja
2023-03-13 12:42 ` [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified Sinthu Raja
@ 2023-03-13 12:42 ` Sinthu Raja
2023-03-30 1:54 ` Tom Rini
2023-03-15 9:25 ` [EXTERNAL] [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3 Ravi Gunasekaran
2 siblings, 1 reply; 6+ messages in thread
From: Sinthu Raja @ 2023-03-13 12:42 UTC (permalink / raw)
To: u-boot, Tom Rini, Ravi Gunasekaran, Vignesh Raghavendra; +Cc: Sinthu Raja
From: Sinthu Raja <sinthu.raja@ti.com>
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
---
drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 8e29f39cd8..23397175d3 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -39,6 +39,7 @@
#define WIZ_DIV_NUM_CLOCKS_10G 1
#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
+#define WIZ_SERDES_TYPEC_LN23_SWAP BIT(31)
enum wiz_lane_standard_mode {
LANE_MODE_GEN1,
@@ -65,6 +66,14 @@ enum wiz_clock_input {
WIZ_EXT_REFCLK1,
};
+/*
+ * List of master lanes used for lane swapping
+ */
+enum wiz_typec_master_lane {
+ LANE0 = 0,
+ LANE2 = 2,
+};
+
static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
@@ -607,11 +616,22 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
int i;
for (i = 0; i < num_lanes; i++) {
- if (wiz->lane_phy_type[i] == PHY_TYPE_USB3)
- if (wiz->master_lane_num[i] == 0)
+ if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
+ switch (wiz->master_lane_num[i]) {
+ case LANE0:
regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
WIZ_SERDES_TYPEC_LN10_SWAP,
WIZ_SERDES_TYPEC_LN10_SWAP);
+ break;
+ case LANE2:
+ regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
+ WIZ_SERDES_TYPEC_LN23_SWAP,
+ WIZ_SERDES_TYPEC_LN23_SWAP);
+ break;
+ default:
+ break;
+ }
+ }
}
}
--
2.36.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
2023-03-13 12:42 ` [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap Sinthu Raja
@ 2023-03-30 1:54 ` Tom Rini
0 siblings, 0 replies; 6+ messages in thread
From: Tom Rini @ 2023-03-30 1:54 UTC (permalink / raw)
To: Sinthu Raja; +Cc: u-boot, Ravi Gunasekaran, Vignesh Raghavendra, Sinthu Raja
[-- Attachment #1: Type: text/plain, Size: 661 bytes --]
On Mon, Mar 13, 2023 at 06:12:24PM +0530, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
>
> The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
> for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
> USB PHY that is integrated into the SerDes IP. The WIZ control register
> has to be configured to support this lane swap feature.
>
> The support for swapping lanes 2 and 3 is missing and therefore
> add support to configure the control register to swap between
> lanes 2 and 3 if PHY type is USB.
>
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Applied to u-boot/next, thanks!
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [EXTERNAL] [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3
2023-03-13 12:42 [PATCH 0/2] phy: ti: j721e-wiz: Add support to manage type-C swap on Lane2 and lane3 Sinthu Raja
2023-03-13 12:42 ` [PATCH 1/2] phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified Sinthu Raja
2023-03-13 12:42 ` [PATCH 2/2] phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap Sinthu Raja
@ 2023-03-15 9:25 ` Ravi Gunasekaran
2 siblings, 0 replies; 6+ messages in thread
From: Ravi Gunasekaran @ 2023-03-15 9:25 UTC (permalink / raw)
To: Sinthu Raja, u-boot, Tom Rini, Vignesh Raghavendra; +Cc: Sinthu Raja
On 13/03/23 6:12 pm, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
>
> Hi All,
> This series of patch add support to enable lane2 and lane3 swap by
> configuring the LN23 bit. Also, it's possible that the Type-C plug orientation
> on the DIR line will be implemented through hardware design. In that
> situation, there won't be an external GPIO line available, but the
> driver still needs to address this since the DT won't use the
> typec-gpio-dir property. Update code to handle if typec-dir-gpios property
> is not specified in DT.
>
> Sinthu Raja (2):
> phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not
> specified
> phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
>
> drivers/phy/ti/phy-j721e-wiz.c | 58 ++++++++++++++++++++++++++++------
> 1 file changed, 49 insertions(+), 9 deletions(-)
>
Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
--
Regards,
Ravi
^ permalink raw reply [flat|nested] 6+ messages in thread