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From: Roger Quadros <rogerq@kernel.org>
To: trini@konsulko.com, michael@amarulasolutions.com,
	dario.binacchi@amarulasolutions.com
Cc: nm@ti.com, afd@ti.com, vigneshr@ti.com, praneeth@ti.com,
	srk@ti.com, r-gunasekaran@ti.com, u-boot@lists.denx.de,
	Roger Quadros <rogerq@kernel.org>
Subject: [PATCH 2/4] mtd: rawnand: omap_gpmc: Use DT provided IO address
Date: Tue,  9 Jan 2024 14:26:03 +0200	[thread overview]
Message-ID: <20240109122605.51951-3-rogerq@kernel.org> (raw)
In-Reply-To: <20240109122605.51951-1-rogerq@kernel.org>

For DM case we can get the NAND chip's IO address from DT
so we don't need to rely on CFG_SYS_NAND_BASE.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
---
 drivers/mtd/nand/raw/omap_gpmc.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c
index 0e25bd5dc2..f827c578d9 100644
--- a/drivers/mtd/nand/raw/omap_gpmc.c
+++ b/drivers/mtd/nand/raw/omap_gpmc.c
@@ -8,13 +8,15 @@
 #include <log.h>
 #include <system-constants.h>
 #include <asm/io.h>
-#include <dm/uclass.h>
+#include <dm.h>
 #include <linux/errno.h>
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
 #include <asm/arch/mem.h>
 #endif
 
+#include <linux/io.h>
+#include <linux/ioport.h>
 #include <linux/mtd/omap_gpmc.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/rawnand.h>
@@ -1124,7 +1126,7 @@ int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
  *   nand_scan about special functionality. See the defines for further
  *   explanation
  */
-int gpmc_nand_init(struct nand_chip *nand)
+int gpmc_nand_init(struct nand_chip *nand, void __iomem *nand_base)
 {
 	int32_t gpmc_config = 0;
 	int cs = cs_next++;
@@ -1164,7 +1166,7 @@ int gpmc_nand_init(struct nand_chip *nand)
 	info->control = NULL;
 	info->cs = cs;
 	info->ws = wscfg[cs];
-	info->fifo = (void __iomem *)CFG_SYS_NAND_BASE;
+	info->fifo = nand_base;
 	nand_set_controller_data(nand, &omap_nand_info[cs]);
 	nand->cmd_ctrl	= omap_nand_hwcontrol;
 	nand->options	|= NAND_NO_PADDING | NAND_CACHEPRG;
@@ -1214,9 +1216,16 @@ static int gpmc_nand_probe(struct udevice *dev)
 {
 	struct nand_chip *nand = dev_get_priv(dev);
 	struct mtd_info *mtd = nand_to_mtd(nand);
+	struct resource res;
+	void __iomem *base;
 	int ret;
 
-	gpmc_nand_init(nand);
+	ret = dev_read_resource(dev, 0, &res);
+	if (ret)
+		return ret;
+
+	base = devm_ioremap(dev, res.start, resource_size(&res));
+	gpmc_nand_init(nand, base);
 
 	ret = nand_scan(mtd, CONFIG_SYS_NAND_MAX_CHIPS);
 	if (ret)
@@ -1270,7 +1279,7 @@ void board_nand_init(void)
 
 int board_nand_init(struct nand_chip *nand)
 {
-	return gpmc_nand_init(nand);
+	return gpmc_nand_init(nand, (void __iomem *)CFG_SYS_NAND_BASE);
 }
 
 #endif /* CONFIG_SYS_NAND_SELF_INIT */
-- 
2.34.1


  parent reply	other threads:[~2024-01-09 12:26 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-09 12:26 [PATCH 0/4] arm: mach-k3: am64: Add NAND configuration Roger Quadros
2024-01-09 12:26 ` [PATCH 1/4] memory: ti-gpmc: Fix build Roger Quadros
2024-01-09 12:26 ` Roger Quadros [this message]
2024-01-09 12:26 ` [PATCH 3/4] arm: mach-k3: am642: Define NAND boot device Roger Quadros
2024-01-09 12:26 ` [PATCH 4/4] configs: am64x_evm_a53_defconfig: Enable NAND Roger Quadros
2024-01-09 19:16   ` Nishanth Menon
2024-01-09 19:48     ` Tom Rini
2024-01-09 20:00       ` Nishanth Menon
2024-01-09 20:35         ` Tom Rini
2024-01-09 19:18   ` Nishanth Menon
2024-01-09 19:54     ` Tom Rini
2024-01-09 20:00       ` Francesco Dolcini
2024-01-09 20:22         ` Nishanth Menon
2024-01-10  9:34         ` Roger Quadros
2024-01-10 16:06           ` Roger Quadros
2024-01-10 16:30             ` Tom Rini
2024-01-09 19:17 ` [PATCH 0/4] arm: mach-k3: am64: Add NAND configuration Nishanth Menon
2024-01-11 12:15   ` Roger Quadros

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