* [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399
@ 2025-03-28 15:34 Simon Glass
2025-03-28 15:34 ` [PATCH v3 01/31] spl: Adjust xPL symbols Simon Glass
` (30 more replies)
0 siblings, 31 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Alex Shumsky, Alexandre Vicenzi, Alper Nebi Yasak,
Anand Moon, Andy Yan, Chris Morgan, Christopher Obbard,
David Bauer, Dragan Simic, FUKAUMI Naoki, Frank Wunderlich,
Greg Malysa, Heiko Stuebner, Jeffy Chen, Jerome Forissier,
Johan Jonker, Jonas Karlman, Loic Devulder, Manivannan Sadhasivam,
Mattijs Korpershoek, Matwey V. Kornilov, Maxim Moskalets,
Nathan Barrett-Morrison, Nicolas Frattaroli, Oliver Gaskell,
Patrick Rudolph, Peter Robinson, Sam Edwards, Sebastian Kropatsch,
Stefan Roese, Sughosh Ganu, Sumit Garg, Suniel Mahesh,
Tianling Shen, Tim Lunn, Tom Rini, Wadim Egorov, Xiaobo Tian
This series completes the work to enable VBE on a suitable board. Most
of it is rockchip-specific patches to support the VPL phase, i.e. the
one which decides which boot patch to take (A, B or recovery).
A good chunk of this series is adding an image for VBE, by creating a
new Binman image. Future work in Binman may make this more automated /
easier, but for now it is written out in full. The work is undertaken
piecemeal so it is easier to review the steps.
VBE allows similar boards to share firmware images, with perhaps just
TPL (around 75K) being different for each board. Using a common image
for VPL, SPL and U-Boot saves a lot of space in the image and makes
builds easier. Of course, each board still needs a separate devicetree.
Here is the layout of the image:
Name Image-pos Size Entry-type Offset Uncomp-size
----------------------------------------------------------------------------------------------
image 0 1b960cf section 0
alternates-fdt 8000 31000 alternates-fdt 8000
mkimage 8000 31000 mkimage 0
u-boot-tpl 8048 12a11 u-boot-tpl 48
vpl 208000 16200 fit 208000
image-vpl 209400 a5a3 section 1400
section 209400 a5a3 section 0
u-boot-vpl-nodtb 10348 u-boot-vpl-nodtb 0
u-boot-vpl-bss-pad 20 u-boot-vpl-bss-pad 10348
@fdt-SEQ 0 0 section 0
vbe-a 800000 39b200 section 800000
spl-a 800000 100000 fit 0
spl 801400 10c97 section 1400
section 801400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
@fdt-SEQ 0 0 section 0
u-boot-a 900000 29b200 fit 100000
spl 902400 10c97 section 2400
section 902400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
u-boot 913200 e4250 section 13200
u-boot-nodtb 913200 e4250 u-boot-nodtb 0
@atf-SEQ 0 0 section 0
atf-bl31 0 0 atf-bl31 0
@tee-SEQ 0 0 section 0
tee-os 0 0 tee-os 0
@fdt-SEQ 0 0 section 0
vbe-b 1000000 39b200 section 1000000
spl-b 1000000 100000 fit 0
spl 1001400 10c97 section 1400
section 1001400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
@fdt-SEQ 0 0 section 0
u-boot-b 1100000 29b200 fit 100000
spl 1102400 10c97 section 2400
section 1102400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
u-boot 1113200 e4250 section 13200
u-boot-nodtb 1113200 e4250 u-boot-nodtb 0
@atf-SEQ 0 0 section 0
atf-bl31 0 0 atf-bl31 0
@tee-SEQ 0 0 section 0
tee-os 0 0 tee-os 0
@fdt-SEQ 0 0 section 0
vbe-recovery 1800000 39b200 section 1800000
spl-recovery 1800000 100000 fit 0
spl 1801400 10c97 section 1400
section 1801400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
@fdt-SEQ 0 0 section 0
u-boot-recovery 1900000 29b200 fit 100000
spl 1902400 10c97 section 2400
section 1902400 10c97 section 0
u-boot-spl-nodtb 1a908 u-boot-spl-nodtb 0
u-boot-spl-bss-pad 1b0 u-boot-spl-bss-pad 1a908
u-boot 1913200 e4250 section 13200
u-boot-nodtb 1913200 e4250 u-boot-nodtb 0
@atf-SEQ 0 0 section 0
atf-bl31 0 0 atf-bl31 0
@tee-SEQ 0 0 section 0
tee-os 0 0 tee-os 0
@fdt-SEQ 0 0 section 0
fdtmap 1b9b200 2ecf fdtmap 1b9b200
This series still includes the bloblist reverts, at the end, just so
that the board doesn't have on boot, but I have a series locally which
should improve things, so I will send that when complete.
This is (mostly) the final VBE series, but there are a few loose ends to
tidy up:
- cache is disabled in SPL, which slows the boot a little
- pinctrl init needs to be tidied up to avoid warnings
- bloblist logic as above
- bloblist-relocation is partly in board-specific code, partly generic
Other things may become apparently after more usage / testing.
Changes in v3:
- Add blank lines before the node
- Use HAS_FIT for the SPI node also
- Leave fit { node open within #ifdef HAS_FIT
- Move placement of CONFIG_SPL_PAD_TO
- Keep the FIT filename
- Keep the filename for the SPI FIT
- Add a comment about the offsets
- Move template to the vpl file
- Add the BLOBLIST_RELOC condition as well
Changes in v2:
- Put this patch before 'Factor out arch and compression'
- Move VPL things into a separate file
- Mention RK3399 with respect to the memory limit
- Move VPL things into a separate file
- Only enable MMC when VPM is in use.
- Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
- Skip spl-boot-order.c for VPL (rather than modifying it)
- Reword commit to mention comments from Jonas
- Rename to rk3399-generic-ddr3
- Update devicetree to match firefly-rk3399
- Use the firefly devicetree as the default for this board
- Move this patch to the end of the series
- Drop 0x8000 offset for SPI
- Add new patch with a bootmeth driver for abrec
- Split out the fixes for skip-at-start into a new patch
- Move this logic into board-specific code
- Move the actual relocation code to a previous board-specific patch
Simon Glass (31):
spl: Adjust xPL symbols
spl: Allow VBE to handle xPL size
vbe: Show the margin when using SPL_RELOC
rockchip: Allow RAM init to happen in SPL on rk3399
rockchip: dts: Correct the OS for U-Boot
rockchip: dts: Factor out arch and compression
rockchip: dts: Add an fdtmap
rockchip: dts: Create a template for the FIT
rockchip: dts: Un-indent the FIT template
rockchip: dts: Use the new binman template for the SPI image too
rockchip: dts: Specify the phase in the image
rockchip: Provide a bootstd configuration
rockchip: Add SPL into the main FIT
rockchip: Include a compatible string in each configuration
rockchip: Add a template for SPL
rockchip: Add a VPL image
rockchip: Add TPL alternatives
rockchip: Update rk3399 bootph-tags for VPL
rockchip: Provide a VPL phase on rk3399
rockchip: Add symbols for spl_reloc
rockchip: rk3399: Adjust initial TPL-stack to match SPL
rockchip: Allow SPL to set up SDRAM
rockchip: Add a generic-ddr3 rk3399 board
rockchip: Add documentation for VBE
gitlab: Add an VBE board to the sjg lab
rockchip: Set the skip-at-start property correctly
vbe: Add a bootmeth driver for abrec
rockchip: Update binman image for new skip-at-start setup
RFC: Revert "bloblist: Load the bloblist from the previous loader"
rockchip: Relocate bloblist at the end of the SPL phase
bloblist: Allow using a different bloblist address
.gitlab-ci.yml | 5 +
arch/arm/dts/rk3399-u-boot.dtsi | 11 +-
arch/arm/dts/rockchip-u-boot.dtsi | 285 ++++++++++--------
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 218 ++++++++++++++
arch/arm/include/asm/spl.h | 1 +
arch/arm/mach-rockchip/Kconfig | 25 +-
arch/arm/mach-rockchip/Makefile | 11 +-
arch/arm/mach-rockchip/rk3399/Kconfig | 11 +-
arch/arm/mach-rockchip/spl.c | 18 ++
arch/arm/mach-rockchip/tpl.c | 12 +-
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 13 +
arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++
arch/arm/mach-rockchip/vpl.c | 53 ++++
board/rockchip/evb_rk3399/MAINTAINERS | 6 +
boot/vbe_abrec.c | 99 ++++++
cmd/vbe.c | 8 +-
common/Kconfig | 20 ++
common/bloblist.c | 77 ++---
common/spl/Kconfig | 1 +
common/spl/spl.c | 2 +
common/spl/spl_reloc.c | 14 +-
configs/anbernic-rgxx3-rk3566_defconfig | 2 +-
configs/bpi-r2-pro-rk3568_defconfig | 2 +-
configs/chromebit_mickey_defconfig | 2 +-
configs/chromebook_bob_defconfig | 2 +-
configs/chromebook_jerry_defconfig | 2 +-
configs/chromebook_kevin_defconfig | 2 +-
configs/chromebook_minnie_defconfig | 2 +-
configs/chromebook_speedy_defconfig | 2 +-
configs/cm3588-nas-rk3588_defconfig | 2 +-
configs/coolpi-4b-rk3588s_defconfig | 2 +-
configs/coolpi-cm5-evb-rk3588_defconfig | 2 +-
configs/coolpi-cm5-genbook-rk3588_defconfig | 2 +-
configs/eaidk-610-rk3399_defconfig | 2 +-
configs/evb-px30_defconfig | 2 +-
configs/evb-px5_defconfig | 2 +-
configs/evb-rk3036_defconfig | 2 +-
configs/evb-rk3229_defconfig | 2 +-
configs/evb-rk3288_defconfig | 2 +-
configs/evb-rk3308_defconfig | 2 +-
configs/evb-rk3328_defconfig | 2 +-
configs/evb-rk3399_defconfig | 2 +-
configs/evb-rk3568_defconfig | 2 +-
configs/evb-rk3588_defconfig | 2 +-
configs/ficus-rk3399_defconfig | 2 +-
configs/firefly-px30_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/firefly-rk3399_defconfig | 2 +-
configs/generic-rk3568_defconfig | 2 +-
configs/generic-rk3588_defconfig | 2 +-
configs/jaguar-rk3588_defconfig | 2 +-
configs/khadas-edge-captain-rk3399_defconfig | 2 +-
configs/khadas-edge-rk3399_defconfig | 2 +-
configs/khadas-edge-v-rk3399_defconfig | 2 +-
configs/khadas-edge2-rk3588s_defconfig | 2 +-
configs/kylin-rk3036_defconfig | 2 +-
configs/leez-rk3399_defconfig | 2 +-
configs/lubancat-2-rk3568_defconfig | 2 +-
configs/miqi-rk3288_defconfig | 2 +-
configs/mk808_defconfig | 2 +-
configs/nanopc-t4-rk3399_defconfig | 2 +-
configs/nanopc-t6-rk3588_defconfig | 2 +-
configs/nanopi-m4-2gb-rk3399_defconfig | 2 +-
configs/nanopi-m4-rk3399_defconfig | 2 +-
configs/nanopi-m4b-rk3399_defconfig | 2 +-
configs/nanopi-neo4-rk3399_defconfig | 2 +-
configs/nanopi-r2c-plus-rk3328_defconfig | 2 +-
configs/nanopi-r2c-rk3328_defconfig | 2 +-
configs/nanopi-r2s-plus-rk3328_defconfig | 2 +-
configs/nanopi-r2s-rk3328_defconfig | 2 +-
configs/nanopi-r3s-rk3566_defconfig | 2 +-
configs/nanopi-r4s-rk3399_defconfig | 2 +-
configs/nanopi-r5c-rk3568_defconfig | 2 +-
configs/nanopi-r5s-rk3568_defconfig | 2 +-
configs/nanopi-r6c-rk3588s_defconfig | 2 +-
configs/nanopi-r6s-rk3588s_defconfig | 2 +-
configs/neu2-io-rv1126_defconfig | 2 +-
configs/neu6a-io-rk3588_defconfig | 2 +-
configs/neu6b-io-rk3588_defconfig | 2 +-
configs/nova-rk3588s_defconfig | 2 +-
configs/odroid-go2_defconfig | 2 +-
configs/odroid-m1-rk3568_defconfig | 2 +-
configs/odroid-m1s-rk3566_defconfig | 2 +-
configs/odroid-m2-rk3588s_defconfig | 2 +-
configs/orangepi-3b-rk3566_defconfig | 2 +-
configs/orangepi-5-plus-rk3588_defconfig | 2 +-
configs/orangepi-5-rk3588s_defconfig | 2 +-
configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 +-
configs/orangepi-r1-plus-rk3328_defconfig | 2 +-
configs/orangepi-rk3399_defconfig | 2 +-
configs/phycore-rk3288_defconfig | 2 +-
configs/pinebook-pro-rk3399_defconfig | 2 +-
configs/pinephone-pro-rk3399_defconfig | 2 +-
configs/pinetab2-rk3566_defconfig | 2 +-
configs/popmetal-rk3288_defconfig | 2 +-
configs/powkiddy-x55-rk3566_defconfig | 2 +-
configs/puma-rk3399_defconfig | 2 +-
configs/px30-core-ctouch2-of10-px30_defconfig | 2 +-
configs/px30-core-ctouch2-px30_defconfig | 2 +-
configs/px30-core-edimm2.2-px30_defconfig | 2 +-
configs/qnap-ts433-rk3568_defconfig | 2 +-
configs/quartz64-a-rk3566_defconfig | 2 +-
configs/quartz64-b-rk3566_defconfig | 2 +-
configs/quartzpro64-rk3588_defconfig | 2 +-
configs/radxa-cm3-io-rk3566_defconfig | 2 +-
configs/radxa-e25-rk3568_defconfig | 2 +-
configs/radxa-zero-3-rk3566_defconfig | 2 +-
configs/rk3399-generic-ddr3_defconfig | 124 ++++++++
configs/roc-cc-rk3308_defconfig | 2 +-
configs/roc-cc-rk3328_defconfig | 2 +-
configs/roc-pc-mezzanine-rk3399_defconfig | 2 +-
configs/roc-pc-rk3399_defconfig | 2 +-
configs/rock-3a-rk3568_defconfig | 2 +-
configs/rock-3b-rk3568_defconfig | 2 +-
configs/rock-3c-rk3566_defconfig | 2 +-
configs/rock-4c-plus-rk3399_defconfig | 2 +-
configs/rock-4se-rk3399_defconfig | 2 +-
configs/rock-5-itx-rk3588_defconfig | 2 +-
configs/rock-5c-rk3588s_defconfig | 2 +-
configs/rock-pi-4-rk3399_defconfig | 2 +-
configs/rock-pi-4c-rk3399_defconfig | 2 +-
configs/rock-pi-e-rk3328_defconfig | 2 +-
configs/rock-pi-e-v3-rk3328_defconfig | 2 +-
configs/rock-pi-n10-rk3399pro_defconfig | 2 +-
configs/rock-pi-n8-rk3288_defconfig | 2 +-
configs/rock-pi-s-rk3308_defconfig | 2 +-
configs/rock-s0-rk3308_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/rock5a-rk3588s_defconfig | 2 +-
configs/rock5b-rk3588_defconfig | 2 +-
configs/rock64-rk3328_defconfig | 2 +-
configs/rock960-rk3399_defconfig | 2 +-
configs/rock_defconfig | 2 +-
configs/rockpro64-rk3399_defconfig | 2 +-
configs/sige7-rk3588_defconfig | 2 +-
configs/sonoff-ihost-rv1126_defconfig | 2 +-
configs/soquartz-blade-rk3566_defconfig | 2 +-
configs/soquartz-cm4-rk3566_defconfig | 2 +-
configs/soquartz-model-a-rk3566_defconfig | 2 +-
configs/tiger-rk3588_defconfig | 2 +-
configs/tinker-rk3288_defconfig | 2 +-
configs/tinker-s-rk3288_defconfig | 2 +-
configs/toybrick-rk3588_defconfig | 2 +-
configs/turing-rk1-rk3588_defconfig | 2 +-
configs/vyasa-rk3288_defconfig | 2 +-
doc/board/rockchip/rockchip.rst | 13 +
drivers/ram/rockchip/sdram_rk3399.c | 6 +-
include/bloblist.h | 10 -
include/vbe.h | 3 +
149 files changed, 1074 insertions(+), 325 deletions(-)
create mode 100644 arch/arm/dts/rockchip-vpl-u-boot.dtsi
create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
create mode 100644 arch/arm/mach-rockchip/vpl.c
create mode 100644 configs/rk3399-generic-ddr3_defconfig
--
2.43.0
base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
branch: vbi3
^ permalink raw reply [flat|nested] 51+ messages in thread
* [PATCH v3 01/31] spl: Adjust xPL symbols
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 02/31] spl: Allow VBE to handle xPL size Simon Glass
` (29 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Tom Rini
Update for the new xPL naming, which was missed in a previous patch
which purported to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
(no changes since v1)
common/spl/spl_reloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl_reloc.c b/common/spl/spl_reloc.c
index 324b98eaf98..216c0f36623 100644
--- a/common/spl/spl_reloc.c
+++ b/common/spl/spl_reloc.c
@@ -59,7 +59,7 @@ static int setup_layout(struct spl_image_info *image, ulong *addrp)
uint need_size = image->size + image->fdt_size;
margin = buf_size - need_size;
log_debug("spl_reloc %s->%s: margin%s%lx limit %lx fdt_size %lx base %lx avail %x image %x fdt %lx need %x\n",
- spl_phase_name(spl_phase()), spl_phase_name(spl_phase() + 1),
+ xpl_name(xpl_phase()), xpl_name(xpl_phase() + 1),
margin >= 0 ? " " : " -", abs(margin), limit, fdt_size, base,
buf_size, image->size, image->fdt_size, need_size);
if (margin < 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 02/31] spl: Allow VBE to handle xPL size
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
2025-03-28 15:34 ` [PATCH v3 01/31] spl: Adjust xPL symbols Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 03/31] vbe: Show the margin when using SPL_RELOC Simon Glass
` (28 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Quentin Schulz, Sean Anderson, Sughosh Ganu,
Tom Rini
When VBE is in use, the size of each phase is obtained by reading it
from a FIT. Avoid using binman symbols unless necessary, i.e. in TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
common/spl/spl.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 6b75910e243..e7157df1ff9 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -200,6 +200,8 @@ ulong spl_get_image_size(void)
#ifdef CONFIG_VPL
if (xpl_next_phase() == PHASE_VPL)
return binman_sym(ulong, u_boot_vpl_any, size);
+
+ return 0; /* VBE handles this */
#endif
return xpl_next_phase() == PHASE_SPL ?
binman_sym(ulong, u_boot_spl_any, size) :
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 03/31] vbe: Show the margin when using SPL_RELOC
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
2025-03-28 15:34 ` [PATCH v3 01/31] spl: Adjust xPL symbols Simon Glass
2025-03-28 15:34 ` [PATCH v3 02/31] spl: Allow VBE to handle xPL size Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 04/31] rockchip: Allow RAM init to happen in SPL on rk3399 Simon Glass
` (27 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Tom Rini
Collect information about the memory-margin in each phase which uses
this feature. Update the 'vbe state' command to show it.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
cmd/vbe.c | 8 ++++++--
common/spl/spl_reloc.c | 12 ++++++++++++
include/vbe.h | 3 +++
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/cmd/vbe.c b/cmd/vbe.c
index 186f6e6860d..02d224ad286 100644
--- a/cmd/vbe.c
+++ b/cmd/vbe.c
@@ -92,9 +92,13 @@ static int do_vbe_state(struct cmd_tbl *cmdtp, int flag, int argc,
printf("Phases:");
for (i = PHASE_NONE; i < PHASE_COUNT; i++) {
- if (handoff->phases & (1 << i))
- printf(" %s", xpl_name(i));
+ if (handoff->phases & (1 << i)) {
+ int margin = handoff->reloc_margin[i];
+ printf(" %s", xpl_name(i));
+ if (margin)
+ printf(" (margin %x) ", margin);
+ }
}
if (!handoff->phases)
printf(" (none)");
diff --git a/common/spl/spl_reloc.c b/common/spl/spl_reloc.c
index 216c0f36623..6bfc75bc484 100644
--- a/common/spl/spl_reloc.c
+++ b/common/spl/spl_reloc.c
@@ -4,11 +4,13 @@
* Written by Simon Glass <sjg@chromium.org>
*/
+#include <bloblist.h>
#include <gzip.h>
#include <image.h>
#include <log.h>
#include <mapmem.h>
#include <spl.h>
+#include <vbe.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/sections.h>
@@ -58,6 +60,16 @@ static int setup_layout(struct spl_image_info *image, ulong *addrp)
buf_size = rcode_base - base;
uint need_size = image->size + image->fdt_size;
margin = buf_size - need_size;
+
+ if (CONFIG_IS_ENABLED(BLOBLIST)) {
+ struct vbe_handoff *handoff;
+
+ handoff = bloblist_find(BLOBLISTT_VBE,
+ sizeof(struct vbe_handoff));
+ if (handoff)
+ handoff->reloc_margin[xpl_phase()] = margin;
+ }
+
log_debug("spl_reloc %s->%s: margin%s%lx limit %lx fdt_size %lx base %lx avail %x image %x fdt %lx need %x\n",
xpl_name(xpl_phase()), xpl_name(xpl_phase() + 1),
margin >= 0 ? " " : " -", abs(margin), limit, fdt_size, base,
diff --git a/include/vbe.h b/include/vbe.h
index 61bfa0e557d..84a996cdf7f 100644
--- a/include/vbe.h
+++ b/include/vbe.h
@@ -11,6 +11,7 @@
#define __VBE_H
#include <linux/types.h>
+#include <spl.h>
/**
* enum vbe_phase_t - current phase of VBE
@@ -47,12 +48,14 @@ enum vbe_pick_t {
* @size: Size of the area containing the FIT
* @phases: Indicates which phases used the VBE bootmeth (1 << PHASE_...)
* @pick: Indicates which firmware pick was used (enum vbe_pick_t)
+ * @reloc_margin: Indicates the number of bytes of margin coming into this phase
*/
struct vbe_handoff {
ulong offset;
ulong size;
u8 phases;
u8 pick;
+ int reloc_margin[PHASE_COUNT];
};
/**
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 04/31] rockchip: Allow RAM init to happen in SPL on rk3399
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (2 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 03/31] vbe: Show the margin when using SPL_RELOC Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 05/31] rockchip: dts: Correct the OS for U-Boot Simon Glass
` (26 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich,
Quentin Schulz, Tom Rini, huang lin
TPL runs before VPL. The earliest updatable phase with VBE is SPL. We
want to be able to update the RAM-init code in the field.
So when VPL is being used, init the RAM later, in SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
drivers/ram/rockchip/sdram_rk3399.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 6fa8f268770..9ac16dfdc71 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -194,6 +194,7 @@ struct io_setting {
static bool phase_sdram_init(void)
{
return xpl_phase() == PHASE_TPL ||
+ (IS_ENABLED(CONFIG_VPL) && xpl_phase() == PHASE_SPL) ||
(!IS_ENABLED(CONFIG_TPL) &&
!IS_ENABLED(CONFIG_ROCKCHIP_EXTERNAL_TPL) &&
!not_xpl());
@@ -3195,8 +3196,9 @@ U_BOOT_DRIVER(dmc_rk3399) = {
.of_to_plat = rk3399_dmc_of_to_plat,
.probe = rk3399_dmc_probe,
.priv_auto = sizeof(struct dram_info),
-#if defined(CONFIG_TPL_BUILD) || \
- (!defined(CONFIG_TPL) && defined(CONFIG_XPL_BUILD))
+#if defined(CONFIG_VPL) && defined(CONFIG_SPL_BUILD) || \
+ !defined(CONFIG_VPL) && defined(CONFIG_TPL_BUILD) || \
+ !defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)
.plat_auto = sizeof(struct rockchip_dmc_plat),
#endif
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 05/31] rockchip: dts: Correct the OS for U-Boot
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (3 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 04/31] rockchip: Allow RAM init to happen in SPL on rk3399 Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 06/31] rockchip: dts: Factor out arch and compression Simon Glass
` (25 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
The U-Boot section is currently getting an invalid OS. Use the correct
value to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
(no changes since v2)
Changes in v2:
- Put this patch before 'Factor out arch and compression'
arch/arm/dts/rockchip-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index c8c928c7e50..e9ed1d4b573 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -50,7 +50,7 @@
u-boot {
description = "U-Boot";
type = "standalone";
- os = "U-Boot";
+ os = "u-boot";
#ifdef CONFIG_ARM64
arch = "arm64";
#else
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 06/31] rockchip: dts: Factor out arch and compression
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (4 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 05/31] rockchip: dts: Correct the OS for U-Boot Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 07/31] rockchip: dts: Add an fdtmap Simon Glass
` (24 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Declare these at the top of the file to avoid needing #ifdefs in every
usage.
Add a few comments to help with the remaining #ifdefs
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
(no changes since v1)
arch/arm/dts/rockchip-u-boot.dtsi | 44 +++++++++++++++----------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index e9ed1d4b573..2b01dc66056 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -5,6 +5,20 @@
#include <config.h>
+#ifdef CONFIG_ARM64
+#define ARCH "arm64"
+#else
+#define ARCH "arm"
+#endif
+
+#if defined(CONFIG_SPL_GZIP)
+#define COMP "gzip"
+#elif defined(CONFIG_SPL_LZMA)
+#define COMP "lzma"
+#else
+#define COMP "none"
+#endif
+
/ {
binman: binman {
multiple-images;
@@ -51,26 +65,12 @@
description = "U-Boot";
type = "standalone";
os = "u-boot";
-#ifdef CONFIG_ARM64
- arch = "arm64";
-#else
- arch = "arm";
-#endif
-#if defined(CONFIG_SPL_GZIP)
- compression = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
- compression = "lzma";
-#else
- compression = "none";
-#endif
+ arch = ARCH;
+ compression = COMP;
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
u-boot-nodtb {
-#if defined(CONFIG_SPL_GZIP)
- compress = "gzip";
-#elif defined(CONFIG_SPL_LZMA)
- compress = "lzma";
-#endif
+ compress = COMP;
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
@@ -84,7 +84,7 @@
fit,operation = "split-elf";
description = "ARM Trusted Firmware";
type = "firmware";
- arch = "arm64";
+ arch = ARCH;
os = "arm-trusted-firmware";
compression = "none";
fit,load;
@@ -103,7 +103,7 @@
fit,operation = "split-elf";
description = "TEE";
type = "tee";
- arch = "arm64";
+ arch = ARCH;
os = "tee";
compression = "none";
fit,load;
@@ -119,11 +119,11 @@
};
#endif
};
-#else
+#else /* !CONFIG_ARM64 */
op-tee {
description = "OP-TEE";
type = "tee";
- arch = "arm";
+ arch = ARCH;
os = "tee";
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
@@ -137,7 +137,7 @@
};
#endif
};
-#endif
+#endif /* CONFIG_ARM64 */
@fdt-SEQ {
description = "fdt-NAME";
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 07/31] rockchip: dts: Add an fdtmap
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (5 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 06/31] rockchip: dts: Factor out arch and compression Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 08/31] rockchip: dts: Create a template for the FIT Simon Glass
` (23 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Add an fdtmap so it is possible to look at the image with 'binman ls'.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v3:
- Add blank lines before the node
arch/arm/dts/rockchip-u-boot.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 2b01dc66056..8aea2e6f571 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -170,6 +170,9 @@
offset = <CONFIG_SPL_PAD_TO>;
};
#endif
+
+ fdtmap {
+ };
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
@@ -203,6 +206,9 @@
/* Sync with u-boot,spl-payload-offset if present */
offset = <CONFIG_SYS_SPI_U_BOOT_OFFS>;
};
+
+ fdtmap {
+ };
};
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE */
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 08/31] rockchip: dts: Create a template for the FIT
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (6 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 07/31] rockchip: dts: Add an fdtmap Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 16:26 ` Jonas Karlman
2025-03-28 15:34 ` [PATCH v3 09/31] rockchip: dts: Un-indent the FIT template Simon Glass
` (22 subsequent siblings)
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Move the FIT description into a template so that it can (later) be used
in multiple places in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v3:
- Use HAS_FIT for the SPI node also
- Leave fit { node open within #ifdef HAS_FIT
- Move placement of CONFIG_SPL_PAD_TO
- Keep the FIT filename
arch/arm/dts/rockchip-u-boot.dtsi | 61 ++++++++++++++++++-------------
1 file changed, 35 insertions(+), 26 deletions(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 8aea2e6f571..460bf15e003 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -19,6 +19,10 @@
#define COMP "none"
#endif
+#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
+#define HAS_FIT
+#endif
+
/ {
binman: binman {
multiple-images;
@@ -27,28 +31,9 @@
#ifdef CONFIG_SPL
&binman {
- simple-bin {
- filename = "u-boot-rockchip.bin";
- pad-byte = <0xff>;
-
- mkimage {
- filename = "idbloader.img";
- args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
- multiple-data-files;
-
-#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
- rockchip-tpl {
- };
-#elif defined(CONFIG_TPL)
- u-boot-tpl {
- };
-#endif
- u-boot-spl {
- };
- };
-
-#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
- fit: fit {
+#ifdef HAS_FIT
+ common_part: template-1 {
+ type = "fit";
#ifdef CONFIG_ARM64
description = "FIT image for U-Boot with bl31 (TF-A)";
#else
@@ -56,10 +41,8 @@
#endif
#address-cells = <1>;
fit,fdt-list = "of-list";
- filename = "u-boot.itb";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,align = <512>;
- offset = <CONFIG_SPL_PAD_TO>;
images {
u-boot {
description = "U-Boot";
@@ -164,12 +147,38 @@
fit,loadables;
};
};
+ };
+#endif /* HAS_FIT */
+
+ simple-bin {
+ filename = "u-boot-rockchip.bin";
+ pad-byte = <0xff>;
+
+ mkimage {
+ filename = "idbloader.img";
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ multiple-data-files;
+
+#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
+ rockchip-tpl {
+ };
+#elif defined(CONFIG_TPL)
+ u-boot-tpl {
+ };
+#endif
+ u-boot-spl {
+ };
};
+
+#ifdef HAS_FIT
+ fit {
+ filename = "u-boot.itb";
+ insert-template = <&common_part>;
#else
u-boot-img {
+#endif
offset = <CONFIG_SPL_PAD_TO>;
};
-#endif
fdtmap {
};
@@ -196,7 +205,7 @@
};
};
-#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
+#ifdef HAS_FIT
fit {
type = "blob";
filename = "u-boot.itb";
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 09/31] rockchip: dts: Un-indent the FIT template
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (7 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 08/31] rockchip: dts: Create a template for the FIT Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too Simon Glass
` (21 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Fix the indentation on the template. This is done in a separate patch
so that it is easier to review.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
(no changes since v1)
arch/arm/dts/rockchip-u-boot.dtsi | 176 +++++++++++++++---------------
1 file changed, 88 insertions(+), 88 deletions(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 460bf15e003..1e4d6f71123 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -33,120 +33,120 @@
&binman {
#ifdef HAS_FIT
common_part: template-1 {
- type = "fit";
+ type = "fit";
#ifdef CONFIG_ARM64
- description = "FIT image for U-Boot with bl31 (TF-A)";
+ description = "FIT image for U-Boot with bl31 (TF-A)";
#else
- description = "FIT image with OP-TEE";
+ description = "FIT image with OP-TEE";
#endif
- #address-cells = <1>;
- fit,fdt-list = "of-list";
- fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
- fit,align = <512>;
- images {
- u-boot {
- description = "U-Boot";
- type = "standalone";
- os = "u-boot";
- arch = ARCH;
- compression = COMP;
- load = <CONFIG_TEXT_BASE>;
- entry = <CONFIG_TEXT_BASE>;
- u-boot-nodtb {
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+ fit,align = <512>;
+ images {
+ u-boot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "u-boot";
+ arch = ARCH;
+ compression = COMP;
+ load = <CONFIG_TEXT_BASE>;
+ entry = <CONFIG_TEXT_BASE>;
+ u-boot-nodtb {
compress = COMP;
- };
+ };
#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
+ hash {
+ algo = "sha256";
};
+#endif
+ };
#ifdef CONFIG_ARM64
- @atf-SEQ {
- fit,operation = "split-elf";
- description = "ARM Trusted Firmware";
- type = "firmware";
- arch = ARCH;
- os = "arm-trusted-firmware";
- compression = "none";
- fit,load;
- fit,entry;
- fit,data;
-
- atf-bl31 {
- };
+ @atf-SEQ {
+ fit,operation = "split-elf";
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = ARCH;
+ os = "arm-trusted-firmware";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ atf-bl31 {
+ };
#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
+ hash {
+ algo = "sha256";
+ };
#endif
+ };
+ @tee-SEQ {
+ fit,operation = "split-elf";
+ description = "TEE";
+ type = "tee";
+ arch = ARCH;
+ os = "tee";
+ compression = "none";
+ fit,load;
+ fit,entry;
+ fit,data;
+
+ tee-os {
+ optional;
};
- @tee-SEQ {
- fit,operation = "split-elf";
- description = "TEE";
- type = "tee";
- arch = ARCH;
- os = "tee";
- compression = "none";
- fit,load;
- fit,entry;
- fit,data;
-
- tee-os {
- optional;
- };
#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
+ hash {
+ algo = "sha256";
};
+#endif
+ };
#else /* !CONFIG_ARM64 */
- op-tee {
- description = "OP-TEE";
- type = "tee";
- arch = ARCH;
- os = "tee";
- compression = "none";
- load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
- entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
-
- tee-os {
- };
+ op-tee {
+ description = "OP-TEE";
+ type = "tee";
+ arch = ARCH;
+ os = "tee";
+ compression = "none";
+ load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+
+ tee-os {
+ };
#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
+ hash {
+ algo = "sha256";
};
+#endif
+ };
#endif /* CONFIG_ARM64 */
- @fdt-SEQ {
- description = "fdt-NAME";
- compression = "none";
- type = "flat_dt";
+ @fdt-SEQ {
+ description = "fdt-NAME";
+ compression = "none";
+ type = "flat_dt";
#ifdef CONFIG_SPL_FIT_SIGNATURE
- hash {
- algo = "sha256";
- };
-#endif
+ hash {
+ algo = "sha256";
};
+#endif
};
+ };
- configurations {
- default = "@config-DEFAULT-SEQ";
- @config-SEQ {
- description = "NAME.dtb";
- fdt = "fdt-SEQ";
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "NAME.dtb";
+ fdt = "fdt-SEQ";
#ifdef CONFIG_ARM64
- fit,firmware = "atf-1", "u-boot";
+ fit,firmware = "atf-1", "u-boot";
#else
- fit,firmware = "op-tee", "u-boot";
+ fit,firmware = "op-tee", "u-boot";
#endif
- fit,loadables;
- };
+ fit,loadables;
};
+ };
};
#endif /* HAS_FIT */
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (8 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 09/31] rockchip: dts: Un-indent the FIT template Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 18:19 ` Jonas Karlman
2025-03-28 15:34 ` [PATCH v3 11/31] rockchip: dts: Specify the phase in the image Simon Glass
` (20 subsequent siblings)
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
At present simple-bin-spi relies on the u-boot.itb file created by the
simple-bin image. Use the template to avoid this, since Binman may
change to process images in parallel in the future.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Suggested-by: Jonas Karlman <jonas@kwiboo.se>
---
Changes in v3:
- Keep the filename for the SPI FIT
arch/arm/dts/rockchip-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 1e4d6f71123..fb304540787 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -207,8 +207,8 @@
#ifdef HAS_FIT
fit {
- type = "blob";
filename = "u-boot.itb";
+ insert-template = <&common_part>;
#else
u-boot-img {
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 11/31] rockchip: dts: Specify the phase in the image
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (9 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 12/31] rockchip: Provide a bootstd configuration Simon Glass
` (19 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Jonas Karlman, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Add 'u-boot' as the phase for the images intended for use with U-Boot
proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/dts/rockchip-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index fb304540787..465f54b8b09 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -52,6 +52,7 @@
compression = COMP;
load = <CONFIG_TEXT_BASE>;
entry = <CONFIG_TEXT_BASE>;
+ phase = "u-boot";
u-boot-nodtb {
compress = COMP;
};
@@ -70,6 +71,7 @@
arch = ARCH;
os = "arm-trusted-firmware";
compression = "none";
+ phase = "u-boot";
fit,load;
fit,entry;
fit,data;
@@ -89,6 +91,7 @@
arch = ARCH;
os = "tee";
compression = "none";
+ phase = "u-boot";
fit,load;
fit,entry;
fit,data;
@@ -111,6 +114,7 @@
compression = "none";
load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>;
+ phase = "u-boot";
tee-os {
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 12/31] rockchip: Provide a bootstd configuration
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (10 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 11/31] rockchip: dts: Specify the phase in the image Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 13/31] rockchip: Add SPL into the main FIT Simon Glass
` (18 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Jonas Karlman, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Add bootstd information for VBE. Put it in a separate file to avoid
cluttering the main one.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- Add a comment about the offsets
Changes in v2:
- Move VPL things into a separate file
arch/arm/dts/rockchip-u-boot.dtsi | 4 +++
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 40 +++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
create mode 100644 arch/arm/dts/rockchip-vpl-u-boot.dtsi
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 465f54b8b09..85a89e3a596 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -226,3 +226,7 @@
#endif /* CONFIG_ROCKCHIP_SPI_IMAGE */
};
#endif /* CONFIG_SPL */
+
+#ifdef CONFIG_VPL
+#include "rockchip-vpl-u-boot.dtsi"
+#endif
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
new file mode 100644
index 00000000000..475dbc53796
--- /dev/null
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+/ {
+ bootstd {
+ bootph-verify;
+ compatible = "u-boot,boot-std";
+
+ /*
+ * This is used for the VBE OS-request tests. A FAT filesystem
+ * created in a partition with the VBE information appearing
+ * before the partition starts.
+ *
+ * Offsets are aligned to the media block-size, typically 0x200
+ *
+ * The start of the VBE area is set at 8MB, adjusted for the
+ * skip-at-start offset. Before that is a block containing the
+ * version information and before that is the state. These could
+ * be stored in a different storage device if available, but so
+ * far VBE only supports MMC.
+ *
+ * The total area size is 8MB which should be enough for a FIT
+ * containing U-Boot and a number of devicetrees.
+ */
+ firmware0 {
+ bootph-verify;
+ compatible = "fwupd,vbe-abrec";
+ storage = "mmc0";
+ skip-offset = <0x8000>;
+ area-start = <0x7f8000>;
+ area-size = <0x800000>;
+ state-offset = <(0x7f8000 - 0x400)>;
+ state-size = <0x40>;
+ version-offset = <(0x7f8000 - 0x200)>;
+ version-size = <0x100>;
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 13/31] rockchip: Add SPL into the main FIT
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (11 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 12/31] rockchip: Provide a bootstd configuration Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 14/31] rockchip: Include a compatible string in each configuration Simon Glass
` (17 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, Tom Rini,
huang lin
VBE may want to load the SPL image from the same FIT as contains U-Boot,
if there is enough memory, so add it.
Changes in v2:
- Move VPL things into a separate file
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 29 +++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index 475dbc53796..b3759b88db5 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -38,3 +38,32 @@
};
};
};
+
+&binman {
+ template-1 {
+ images {
+ spl {
+ description = "U-Boot SPL";
+ type = "firmware";
+ os = "u-boot";
+ arch = ARCH;
+ compression = "lz4";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ phase = "spl";
+ section {
+ compress = "lz4";
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-bss-pad {
+ };
+ };
+ };
+ };
+ configurations {
+ @config-SEQ {
+ fit,firmware = "atf-1", "u-boot", "spl";
+ };
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 14/31] rockchip: Include a compatible string in each configuration
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (12 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 13/31] rockchip: Add SPL into the main FIT Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 15/31] rockchip: Add a template for SPL Simon Glass
` (16 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jonas Karlman, Jeffy Chen, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
Provide a compatible string so that U-Boot can decide which
configuration to use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
---
(no changes since v1)
arch/arm/dts/rockchip-u-boot.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 85a89e3a596..ef1f24fe29c 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -149,6 +149,7 @@
fit,firmware = "op-tee", "u-boot";
#endif
fit,loadables;
+ fit,compatible;
};
};
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 15/31] rockchip: Add a template for SPL
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (13 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 14/31] rockchip: Include a compatible string in each configuration Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 16/31] rockchip: Add a VPL image Simon Glass
` (15 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, Tom Rini,
huang lin
The SPL phase has a single SPL binary plus a devicetree for each board
we need to support.
The devicetree is run through fdtgrep to remove unwanted nodes and
properties and reduce its size.
While it would be nicer to just have a single FIT holding both the SPL
and U-Boot images, there may not be enough SRAM to support that. So we
end up providing this special image just for SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
Changes in v3:
- Move template to the vpl file
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 43 +++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index b3759b88db5..d15c593bf7f 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -66,4 +66,47 @@
};
};
};
+
+ spl_template: template-2 {
+ type = "fit";
+ description = "FIT image for U-Boot SPL";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,align = <512>;
+ fit,external-offset = <0>;
+ images {
+ spl {
+ description = "U-Boot SPL";
+ type = "firmware";
+ os = "u-boot";
+ arch = ARCH;
+ compression = "lz4";
+ load = <CONFIG_SPL_TEXT_BASE>;
+ entry = <CONFIG_SPL_TEXT_BASE>;
+ section {
+ compress = "lz4";
+ u-boot-spl-nodtb {
+ };
+ u-boot-spl-bss-pad {
+ };
+ };
+ };
+ @fdt-SEQ {
+ description = "fdt-NAME";
+ compression = "none";
+ type = "flat_dt";
+ fit,fdt-phase = "spl";
+ };
+ };
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "NAME.dtb";
+ fdt = "fdt-SEQ";
+ fit,firmware = "spl";
+ fit,loadables;
+ fit,compatible;
+ };
+ };
+ };
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 16/31] rockchip: Add a VPL image
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (14 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 15/31] rockchip: Add a template for SPL Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 17/31] rockchip: Add TPL alternatives Simon Glass
` (14 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, Tom Rini,
huang lin
The VPL image is immutable and has a single VPL binary plus a devicetree
for each board we need to support.
The devicetree is run through fdtgrep to remove unwanted nodes and
properties and reduce its size.
Changes in v2:
- Move VPL things into a separate file
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 91 +++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index d15c593bf7f..eee57db5478 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -109,4 +109,95 @@
};
};
};
+
+ simple-bin {
+ vpl {
+ type = "fit";
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 0x200 + 0x8000)>;
+ description = "FIT image for U-Boot TPL";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+ fit,align = <512>;
+ fit,external-offset = <0>;
+ images {
+ image-vpl {
+ description = "U-Boot VPL";
+ type = "firmware";
+ os = "u-boot";
+ arch = ARCH;
+ compression = "lz4";
+ load = <CONFIG_VPL_TEXT_BASE>;
+ entry = <CONFIG_VPL_TEXT_BASE>;
+ section {
+ compress = "lz4";
+ u-boot-vpl-nodtb {
+ symbols-base = <0>;
+ };
+ u-boot-vpl-bss-pad {
+ };
+ };
+ };
+ @fdt-SEQ {
+ description = "fdt-NAME";
+ compression = "none";
+ type = "flat_dt";
+ fit,fdt-phase = "vpl";
+ };
+ };
+ configurations {
+ default = "@config-DEFAULT-SEQ";
+ @config-SEQ {
+ description = "NAME.dtb";
+ fdt = "fdt-SEQ";
+ fit,firmware = "image-vpl";
+ fit,loadables;
+ fit,compatible;
+ };
+ };
+ };
+# ifdef CONFIG_BOOTMETH_VBE_ABREC
+ vbe-a {
+ type = "section";
+ offset = <(CONFIG_SPL_PAD_TO + 0x8000)>;
+ spl-a {
+ insert-template = <&spl_template>;
+ size = <0x100000>;
+ };
+
+ u-boot-a {
+ insert-template = <&common_part>;
+ };
+ };
+ vbe-b {
+ type = "section";
+ offset = <0x1000000>;
+ spl-b {
+ insert-template = <&spl_template>;
+ size = <0x100000>;
+ };
+
+ u-boot-b {
+ insert-template = <&common_part>;
+ };
+ };
+ vbe-recovery {
+ type = "section";
+ offset = <0x1800000>;
+ spl-recovery {
+ insert-template = <&spl_template>;
+ size = <0x100000>;
+ };
+
+ u-boot-recovery {
+ insert-template = <&common_part>;
+ };
+ };
+# else /* CONFIG_BOOTMETH_VBE_SIMPLE */
+ vbe {
+ type = "fit";
+ offset = <(CONFIG_SPL_PAD_TO + 0x8000)>;
+ insert-template = <&common_part>;
+ };
+# endif /* VBE method */
+ };
};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 17/31] rockchip: Add TPL alternatives
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (15 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 16/31] rockchip: Add a VPL image Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL Simon Glass
` (13 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Jonas Karlman, Kever Yang,
Philipp Tomsich, Tom Rini, huang lin
The TPL image must be built for each board we need to support. It is the
only part of the image which is board-specific.
This helps to save space and reduce the size of TPL, so that it can fit
within the internal 192K IRAM of the RK3399 SoC.
As with other phases, the TPL devicetree is run through fdtgrep to
remove unwanted nodes and properties and reduce its size.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Mention RK3399 with respect to the memory limit
- Move VPL things into a separate file
arch/arm/dts/rockchip-u-boot.dtsi | 2 ++
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 16 ++++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index ef1f24fe29c..366d52de4ee 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -159,6 +159,7 @@
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
+#ifndef CONFIG_VPL
mkimage {
filename = "idbloader.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
@@ -184,6 +185,7 @@
#endif
offset = <CONFIG_SPL_PAD_TO>;
};
+#endif /* VPL */
fdtmap {
};
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index eee57db5478..5367a40c543 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -111,6 +111,22 @@
};
simple-bin {
+ alternates-fdt {
+ fdt-list-dir = "dts/upstream/src/arm64/rockchip";
+ filename-pattern = "alt-NAME.bin";
+ fdt-phase = "tpl";
+
+ mkimage {
+ filename = "idbloader.img";
+ args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
+ multiple-data-files;
+
+ u-boot-tpl {
+ symbols-base = <0>;
+ };
+ };
+ };
+
vpl {
type = "fit";
offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 0x200 + 0x8000)>;
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (16 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 17/31] rockchip: Add TPL alternatives Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 16:11 ` Jonas Karlman
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
` (12 subsequent siblings)
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Dragan Simic, Jeffy Chen, Jonas Karlman, Kever Yang,
Peter Robinson, Philipp Tomsich, Quentin Schulz, Tom Rini,
huang lin
When VPL is in use, memory init happens in SPL, so there is no need to
include the DMC device before that. Adjust the tags to save space.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Only enable MMC when VPM is in use.
arch/arm/dts/rk3399-u-boot.dtsi | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 81a3c6fc972..c3d0da62c8f 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -71,7 +71,12 @@
0x0 0xffa88800 0x0 0x1800
0x0 0xffa8a000 0x0 0x2000
0x0 0xffa8c000 0x0 0x1000>;
- bootph-all;
+#ifdef CONFIG_VPL
+ bootph-pre-ram;
+ bootph-some-ram;
+#else
+ bootph-all;
+#endif
status = "okay";
};
@@ -118,6 +123,10 @@
};
&sdmmc {
+#ifdef CONFIG_VPL
+ bootph-pre-sram;
+ bootph-verify;
+#endif
bootph-pre-ram;
bootph-some-ram;
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (17 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL Simon Glass
@ 2025-03-28 15:34 ` Simon Glass
2025-03-28 16:16 ` Jonas Karlman
` (2 more replies)
2025-03-28 15:35 ` [PATCH v3 20/31] rockchip: Add symbols for spl_reloc Simon Glass
` (11 subsequent siblings)
30 siblings, 3 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:34 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Jonas Karlman, Kever Yang, Lukas Funke,
Marek Vasut, Nathan Barrett-Morrison, Oliver Gaskell,
Paul Kocialkowski, Philipp Tomsich, Quentin Schulz,
Richard Henderson, Tom Rini, Trevor Woerner, huang lin
Add support for this new phase, which runs after TPL. It determines the
state of the machine, then selects which SPL image to use. SDRAM init is
then done in SPL, so that it is updatable.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
- Skip spl-boot-order.c for VPL (rather than modifying it)
arch/arm/include/asm/spl.h | 1 +
arch/arm/mach-rockchip/Kconfig | 25 +++++-
arch/arm/mach-rockchip/Makefile | 11 ++-
arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
arch/arm/mach-rockchip/spl.c | 3 +
arch/arm/mach-rockchip/tpl.c | 2 +-
arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
common/spl/Kconfig | 1 +
9 files changed, 205 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
create mode 100644 arch/arm/mach-rockchip/vpl.c
diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index ee79a19c05c..62844d64cab 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -30,6 +30,7 @@ enum {
BOOT_DEVICE_XIP,
BOOT_DEVICE_BOOTROM,
BOOT_DEVICE_SMH,
+ BOOT_DEVICE_VBE,
BOOT_DEVICE_NONE
};
#endif
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 4c515593718..58ba0e0468f 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -252,13 +252,15 @@ config ROCKCHIP_RK3399
select SPL_ATF
select SPL_BOARD_INIT if SPL
select SPL_LOAD_FIT
- select SPL_CLK if SPL
+ select SPL_CLK if SPL && !VPL
select SPL_PINCTRL if SPL
select SPL_RAM if SPL
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
select TPL_HAVE_INIT_STACK if TPL
- select SPL_SEPARATE_BSS
+ select VPL_HAVE_INIT_STACK if VPL
+ select SPL_SEPARATE_BSS if !VPL
+ select SPL_RAW_IMAGE_SUPPORT if VPL
select CLK
select FIT
select PINCTRL
@@ -268,6 +270,7 @@ config ROCKCHIP_RK3399
select DM_PMIC
select DM_REGULATOR_FIXED
select BOARD_LATE_INIT
+ select SUPPORT_VPL
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
imply BOOTSTD_FULL
@@ -296,13 +299,14 @@ config ROCKCHIP_RK3399
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_OF_CONTROL
- imply TPL_RAM
+ imply TPL_RAM if !VPL
imply TPL_REGMAP
imply TPL_ROCKCHIP_COMMON_BOARD
imply TPL_SERIAL
imply TPL_SYS_MALLOC_SIMPLE
imply TPL_SYSCON
imply TPL_TINY_MEMSET
+ imply TPL_DM_MMC if VPL
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
and quad-core Cortex-A53.
@@ -457,7 +461,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
config TPL_ROCKCHIP_BACK_TO_BROM
bool "TPL returns to bootrom"
- default y
+ default y if !VPL
select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
select TPL_BOOTROM_SUPPORT
depends on TPL
@@ -498,6 +502,16 @@ config ROCKCHIP_EXTERNAL_TPL
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
include the external TPL in the image built by binman.
+config VPL_ROCKCHIP_COMMON_BOARD
+ bool "Rockchip VPL common board file"
+ depends on VPL
+ default y
+ help
+ Enable the VPL phase for rockchip, which selects which SPL/U-Boot
+ will be used on each boot. With this flow, used by Verified Boot for
+ Embedded (VBE), TPL is loaded by the boot ROM. Then TPL loads VPL,
+ VPL loads SPL and SPL loads U-Boot.
+
config ROCKCHIP_BOOT_MODE_REG
hex "Rockchip boot mode flag register address"
help
@@ -589,6 +603,9 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
config SPL_MMC
default y if !SPL_ROCKCHIP_BACK_TO_BROM
+config TPL_MMC
+ default y if !TPL_ROCKCHIP_BACK_TO_BROM
+
config ROCKCHIP_SPI_IMAGE
bool "Build a SPI image for rockchip"
help
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5e7edc99cdc..c39de1f78bb 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -8,11 +8,16 @@
# inaccessible/protected memory (and the bootrom-helper assumes that
# the stack-pointer is valid before switching to the U-Boot stack).
obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
-obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o spl_common.o
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl_common.o
+ifndef CONFIG_VPL
+obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl-boot-order.o
+endif
obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
+obj-vpl-$(CONFIG_VPL_ROCKCHIP_COMMON_BOARD) += vpl.o
+
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
@@ -47,9 +52,11 @@ obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
-# Clear out SPL objects, in case this is a TPL build
+# Clear out SPL objects, in case this is a TPL or VPL build
obj-spl-$(CONFIG_TPL_BUILD) =
+obj-spl-$(CONFIG_VPL_BUILD) =
# Now add SPL/TPL objects back into the main build
obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y)
obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
+obj-$(CONFIG_VPL_BUILD) += $(obj-vpl-y)
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index 04a84e2f6a0..fc55b498111 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -164,6 +164,15 @@ config TPL_STACK
config TPL_TEXT_BASE
default 0xff8c2000
+config VPL_STACK
+ default 0xff8eff00
+
+config VPL_TEXT_BASE
+ default 0xff8c2000
+
+config VPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-vpl-v8.lds"
+
config SPL_STACK_R_ADDR
default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index f4d29bbdd17..305373a161c 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -61,6 +61,9 @@ u32 spl_boot_device(void)
{
u32 boot_device = BOOT_DEVICE_MMC1;
+ if (IS_ENABLED(CONFIG_VPL))
+ return BOOT_DEVICE_VBE;
+
#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index 6b880f19f84..cc794a7dca2 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -84,5 +84,5 @@ int board_return_to_bootrom(struct spl_image_info *spl_image,
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_BOOTROM;
+ return IS_ENABLED(CONFIG_VPL) ? BOOT_DEVICE_VBE : BOOT_DEVICE_BOOTROM;
}
diff --git a/arch/arm/mach-rockchip/u-boot-vpl-v8.lds b/arch/arm/mach-rockchip/u-boot-vpl-v8.lds
new file mode 100644
index 00000000000..d2a5cf61581
--- /dev/null
+++ b/arch/arm/mach-rockchip/u-boot-vpl-v8.lds
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019
+ * Rockchip Electronics Co., Ltd
+ * Kever Yang<kever.yang@rock-chips.com>
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ * Aneesh V <aneesh@ti.com>
+ */
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ .text : {
+ . = ALIGN(8);
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+
+ /* put relocation code all together */
+ //. = . + 0xc0;
+ _rcode_start = .;
+ *(.text.rcode)
+ *(.text.rdata)
+ _rcode_end = .;
+
+ *(.text*)
+ }
+
+ .rodata : {
+ . = ALIGN(8);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ }
+
+ .data : {
+ . = ALIGN(8);
+ *(.data*)
+ }
+
+ __u_boot_list : {
+ . = ALIGN(8);
+ KEEP(*(SORT(__u_boot_list*)));
+ }
+
+ .image_copy_end : {
+ . = ALIGN(8);
+ *(.__image_copy_end)
+ }
+
+ .end : {
+ . = ALIGN(8);
+ *(.__end)
+ }
+
+ _image_binary_end = .;
+ _end = .;
+ __image_copy_end = .;
+
+ __bss_start = .;
+ .bss_start (NOLOAD) : {
+ . = ALIGN(8);
+ KEEP(*(.__bss_start));
+ }
+
+ .bss (NOLOAD) : {
+ *(.bss*)
+ . = ALIGN(8);
+ }
+
+ .bss_end (NOLOAD) : {
+ KEEP(*(.__bss_end));
+ }
+ __bss_end = .;
+ __bss_size = __bss_end - __bss_start;
+
+ /DISCARD/ : { *(.dynsym) }
+ /DISCARD/ : { *(.dynstr*) }
+ /DISCARD/ : { *(.dynamic*) }
+ /DISCARD/ : { *(.plt*) }
+ /DISCARD/ : { *(.interp*) }
+ /DISCARD/ : { *(.gnu*) }
+}
+
+#if defined(CONFIG_TPL_MAX_SIZE)
+ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \
+ "TPL image too big");
+#endif
+
+#if defined(CONFIG_TPL_BSS_MAX_SIZE)
+ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \
+ "TPL image BSS too big");
+#endif
+
+#if defined(CONFIG_TPL_MAX_FOOTPRINT)
+ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \
+ "TPL image plus BSS too big");
+#endif
diff --git a/arch/arm/mach-rockchip/vpl.c b/arch/arm/mach-rockchip/vpl.c
new file mode 100644
index 00000000000..55a8dabc2da
--- /dev/null
+++ b/arch/arm/mach-rockchip/vpl.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#include <bootstage.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <spl.h>
+#include <version.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <linux/bitops.h>
+
+#if CONFIG_IS_ENABLED(BANNER_PRINT)
+#include <timestamp.h>
+#endif
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_VPL_SERIAL)
+ /*
+ * Debug UART can be used from here if required:
+ *
+ * debug_uart_init();
+ * printch('a');
+ * printhex8(0x1234);
+ * printascii("string");
+ */
+ debug_uart_init();
+#ifdef CONFIG_VPL_BANNER_PRINT
+ printascii("\nU-Boot VPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
+ U_BOOT_TIME ")\n");
+#endif
+#endif
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_VBE;
+}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 85566385c21..4e89b17815d 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -572,6 +572,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
default 0x200 if ARCH_SOCFPGA || ARCH_AT91
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
+ default 0x800 if ARCH_ROCKCHIP && VPL
default 0x4000 if ARCH_ROCKCHIP
default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 20/31] rockchip: Add symbols for spl_reloc
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (18 preceding siblings ...)
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 16:29 ` Jonas Karlman
2025-03-28 15:35 ` [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL Simon Glass
` (10 subsequent siblings)
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich,
Richard Henderson, Tom Rini, huang lin
Add various symbols so that this feature works as intended. This allows
xPL to copy the relocating-jump code up to the top of memory, then use
it to decompress and start the next phase.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 958a1b70aef..842bd4eb07f 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -25,10 +25,21 @@ SECTIONS
__image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
+ __image_copy_start = .;
CPUDIR/start.o (.text*)
+
+ /* put relocation code all together */
+ //. = . + 0xc0;
+ _rcode_start = .;
+ *(.text.rcode)
+ *(.text.rdata)
+ _rcode_end = .;
+
*(.text*)
}
+ _rcode_size = _rcode_end - _rcode_start;
+
.rodata : {
. = ALIGN(8);
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
@@ -48,6 +59,7 @@ SECTIONS
__image_copy_end = .;
_end = .;
_image_binary_end = .;
+ __image_copy_end = .;
.bss ALIGN(8) : {
__bss_start = .;
@@ -55,6 +67,7 @@ SECTIONS
. = ALIGN(8);
__bss_end = .;
}
+ __bss_size = __bss_end - __bss_start;
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (19 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 20/31] rockchip: Add symbols for spl_reloc Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 17:28 ` Jonas Karlman
2025-03-28 15:35 ` [PATCH v3 22/31] rockchip: Allow SPL to set up SDRAM Simon Glass
` (9 subsequent siblings)
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, Tom Rini,
huang lin
There doesn't seem to be a good reason to use a different value for TPL
than SPL. Change the TPL value, since it allows a 256-byte bloblist to
be safely located above the stack in all phases.
Note that for most boards, SDRAM init happens in TPL so the SPL stack
ends up in DRAM, at address CONFIG_SPL_STACK_R_ADDR.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Reword commit to mention comments from Jonas
arch/arm/mach-rockchip/rk3399/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index fc55b498111..8064b6286fc 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -159,7 +159,7 @@ config TPL_LDSCRIPT
default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
config TPL_STACK
- default 0xff8effff
+ default 0xff8eff00
config TPL_TEXT_BASE
default 0xff8c2000
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 22/31] rockchip: Allow SPL to set up SDRAM
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (20 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 23/31] rockchip: Add a generic-ddr3 rk3399 board Simon Glass
` (8 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Dragan Simic, Jeffy Chen, Kever Yang,
Paul Kocialkowski, Philipp Tomsich, Quentin Schulz, Tom Rini,
huang lin
The current logic assumes that if TPL exists then it must be setting up
the SDRAM. This is not true with VBE, so allow this to be controlled by
whether CONFIG_TPL_RAM is enabled, or not.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
arch/arm/mach-rockchip/tpl.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
index cc794a7dca2..2a261199179 100644
--- a/arch/arm/mach-rockchip/tpl.c
+++ b/arch/arm/mach-rockchip/tpl.c
@@ -60,10 +60,12 @@ void board_init_f(ulong dummy)
tpl_board_init();
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
- printf("DRAM init failed: %d\n", ret);
- return;
+ if (CONFIG_IS_ENABLED(RAM)) {
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ printf("DRAM init failed: %d\n", ret);
+ return;
+ }
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 23/31] rockchip: Add a generic-ddr3 rk3399 board
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (21 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 22/31] rockchip: Allow SPL to set up SDRAM Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 24/31] rockchip: Add documentation for VBE Simon Glass
` (7 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Jonas Karlman, Kever Yang,
Peter Robinson, Philipp Tomsich, Quentin Schulz, Tom Rini,
huang lin
This build-target is used to build an image which can run on multiple
rk3399 boards, using VBE to boot.
To use it, the TPL binary for a particular board must be placed into the
first part of the image. The rest of the image (i.e. VPL, SPL and
U-Boot) are largely generic and can work on any supported board.
With VBE, memory-init happens in SPL so that this code is updatable in
the field. Due to size constraints, the type of memory on the board is
defined at build-time. So it is not possible to use the same VBE image
on boards with different SDRAM (DDR3 vs LPDDR4 for example). This may
become possible with newer boards with more SRAM.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Rename to rk3399-generic-ddr3
- Update devicetree to match firefly-rk3399
- Use the firefly devicetree as the default for this board
board/rockchip/evb_rk3399/MAINTAINERS | 6 ++
configs/rk3399-generic-ddr3_defconfig | 124 ++++++++++++++++++++++++++
2 files changed, 130 insertions(+)
create mode 100644 configs/rk3399-generic-ddr3_defconfig
diff --git a/board/rockchip/evb_rk3399/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS
index 8dab3fa70f5..73793c6ccbb 100644
--- a/board/rockchip/evb_rk3399/MAINTAINERS
+++ b/board/rockchip/evb_rk3399/MAINTAINERS
@@ -89,3 +89,9 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/rock-pi-n10-rk3399pro_defconfig
F: arch/arm/dts/rk3399pro-rock-pi-n10*
+
+RK3399-GENERIC-DDR3
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: configs/rk3399-generic-ddr3_defconfig
+F: arch/arm/dts/rockchip-vpl-u-boot.dtsi
diff --git a/configs/rk3399-generic-ddr3_defconfig b/configs/rk3399-generic-ddr3_defconfig
new file mode 100644
index 00000000000..490bc72ee92
--- /dev/null
+++ b/configs/rk3399-generic-ddr3_defconfig
@@ -0,0 +1,124 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3f00000
+CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_ENV_OFFSET=0x3F8000
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3399-firefly"
+CONFIG_DM_RESET=y
+CONFIG_ROCKCHIP_RK3399=y
+CONFIG_TARGET_EVB_RK3399=y
+CONFIG_SPL_STACK=0xff8eff00
+CONFIG_SPL_TEXT_BASE=0xff8c2000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x30000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_DEBUG_UART_BASE=0xFF1A0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_VPL_LOAD_FIT_FULL=y
+# CONFIG_VPL_FIT_PRINT is not set
+# CONFIG_VPL_FIT_SIGNATURE is not set
+# CONFIG_VPL_BOOTSTD is not set
+# CONFIG_BOOTMETH_VBE_SIMPLE is not set
+CONFIG_BOOTMETH_VBE_ABREC=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-generic.dtb"
+CONFIG_LOG=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_BLOBLIST=y
+CONFIG_BLOBLIST_FIXED=y
+CONFIG_BLOBLIST_ADDR=0xff8eff00
+CONFIG_BLOBLIST_SIZE=0x100
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_HAVE_INIT_STACK=y
+# CONFIG_SPL_SEPARATE_BSS is not set
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1000
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_TPL=y
+CONFIG_TPL_RELOC_LOADER=y
+CONFIG_VPL=y
+CONFIG_VPL_RELOC_LOADER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="rockchip/rk3399-nanopc-t4 rockchip/rk3399-nanopi-m4 rockchip/rk3399-nanopi-m4b rockchip/rk3399-nanopi-neo4 rockchip/rk3399-evb rockchip/rk3399-ficus rockchip/rk3399-firefly rockchip/rk3399-orangepi rockchip/rk3399-puma-haikou"
+CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TPL_DM_SEQ_ALIAS=y
+CONFIG_VPL_REGMAP=y
+CONFIG_VPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_NVME_PCI=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_TYPEC=y
+# CONFIG_SPL_DM_PMIC is not set
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+# CONFIG_VPL_SYSRESET is not set
+CONFIG_USB=y
+# CONFIG_SPL_DM_USB is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DISPLAY_ROCKCHIP_HDMI=y
+CONFIG_VPL_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_CMD_DHRYSTONE=y
+# CONFIG_SPL_SHA1 is not set
+# CONFIG_VPL_SHA1 is not set
+# CONFIG_VPL_SHA256 is not set
+CONFIG_TPL_CRC8=y
+CONFIG_TPL_LZ4=y
+CONFIG_VPL_LZ4=y
+# CONFIG_VPL_LZMA is not set
+CONFIG_ERRNO_STR=y
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 24/31] rockchip: Add documentation for VBE
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (22 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 23/31] rockchip: Add a generic-ddr3 rk3399 board Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 25/31] gitlab: Add an VBE board to the sjg lab Simon Glass
` (6 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Chris Morgan, Heiko Stuebner, Jeffy Chen,
Jonas Karlman, Kever Yang, Peter Robinson, Philipp Tomsich,
Quentin Schulz, Sebastian Kropatsch, Tom Rini, huang lin
Now that VBE is running at a basic level on rk3399, add mention of it in
the documentation.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
doc/board/rockchip/rockchip.rst | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 1407080f1f4..73d7c7de923 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -490,6 +490,19 @@ config-flash.ini:
[OUTPUT]
PATH=RK30xxLoader_uboot.bin
+Verified Boot for Embedded (VBE)
+--------------------------------
+
+VBE is supported on rk3399 at present, with SDRAM being set up in SPL. The full
+A/B/recovery flow is supported in U-Boot.
+
+To build this, use the rk3399-generic board, setting CONFIG_OF_LIST to the list
+of boards you want to support. All boards must use the same SDRAM type.
+
+VBE uses internal SRAM (IRAM) for the TPL, VPL and early SPL phases. The stack
+stop is near the top of this (0xff8eff00) with the 256-byte bloblist immediately
+following.
+
TODO
----
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 25/31] gitlab: Add an VBE board to the sjg lab
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (23 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 24/31] rockchip: Add documentation for VBE Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 26/31] rockchip: Set the skip-at-start property correctly Simon Glass
` (5 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Tom Rini
Add a rockchip rk3399 board which runs Verified Boot for Embedded.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
.gitlab-ci.yml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 0a7eef0a1d7..32c7b8e4a09 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -752,4 +752,9 @@ qemu-x86_64:
variables:
ROLE: qemu-x86_64
TEST_PY_TEST_SPEC: "and not sleep"
+
+# Firefly-RK3399 board running the rk3399-generic build
+vbe:
+ variables:
+ ROLE: vbe
<<: *lab_dfn
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 26/31] rockchip: Set the skip-at-start property correctly
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (24 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 25/31] gitlab: Add an VBE board to the sjg lab Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 27/31] vbe: Add a bootmeth driver for abrec Simon Glass
` (4 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Alexandre Vicenzi, Alper Nebi Yasak, Anand Moon,
Andy Yan, Banglang Huang, Chris Morgan, Christopher Obbard,
David Bauer, Dragan Simic, FUKAUMI Naoki, Frank Wunderlich,
Heiko Stuebner, Jeffy Chen, Jernej Skrabec, Jerome Forissier,
Johan Jonker, John Clark, Jonas Karlman, Joseph Chen, Joshua Riek,
Loic Devulder, Manivannan Sadhasivam, Matwey V. Kornilov,
Maxim Moskalets, Michael Trimarchi, Nicolas Frattaroli,
Peter Robinson, Sam Edwards, Sebastian Kropatsch,
Sebastian Reichel, Sumit Garg, Suniel Mahesh, Tianling Shen,
Tim Lunn, Tom Rini, Wadim Egorov, Xiaobo Tian, huang lin
The rockchip image is written to the media at block 64, which is a 32K
offset, so set the skip-at-start property to 0x8000
Update CONFIG_SPL_PAD_TO to point to the offset in the image, since
Binman is dealing with the 'missing' 32K now.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Move this patch to the end of the series
- Drop 0x8000 offset for SPI
arch/arm/dts/rockchip-u-boot.dtsi | 1 +
configs/anbernic-rgxx3-rk3566_defconfig | 2 +-
configs/bpi-r2-pro-rk3568_defconfig | 2 +-
configs/chromebit_mickey_defconfig | 2 +-
configs/chromebook_bob_defconfig | 2 +-
configs/chromebook_jerry_defconfig | 2 +-
configs/chromebook_kevin_defconfig | 2 +-
configs/chromebook_minnie_defconfig | 2 +-
configs/chromebook_speedy_defconfig | 2 +-
configs/cm3588-nas-rk3588_defconfig | 2 +-
configs/coolpi-4b-rk3588s_defconfig | 2 +-
configs/coolpi-cm5-evb-rk3588_defconfig | 2 +-
configs/coolpi-cm5-genbook-rk3588_defconfig | 2 +-
configs/eaidk-610-rk3399_defconfig | 2 +-
configs/evb-px30_defconfig | 2 +-
configs/evb-px5_defconfig | 2 +-
configs/evb-rk3036_defconfig | 2 +-
configs/evb-rk3229_defconfig | 2 +-
configs/evb-rk3288_defconfig | 2 +-
configs/evb-rk3308_defconfig | 2 +-
configs/evb-rk3328_defconfig | 2 +-
configs/evb-rk3399_defconfig | 2 +-
configs/evb-rk3568_defconfig | 2 +-
configs/evb-rk3588_defconfig | 2 +-
configs/ficus-rk3399_defconfig | 2 +-
configs/firefly-px30_defconfig | 2 +-
configs/firefly-rk3288_defconfig | 2 +-
configs/firefly-rk3399_defconfig | 2 +-
configs/generic-rk3568_defconfig | 2 +-
configs/generic-rk3588_defconfig | 2 +-
configs/jaguar-rk3588_defconfig | 2 +-
configs/khadas-edge-captain-rk3399_defconfig | 2 +-
configs/khadas-edge-rk3399_defconfig | 2 +-
configs/khadas-edge-v-rk3399_defconfig | 2 +-
configs/khadas-edge2-rk3588s_defconfig | 2 +-
configs/kylin-rk3036_defconfig | 2 +-
configs/leez-rk3399_defconfig | 2 +-
configs/lubancat-2-rk3568_defconfig | 2 +-
configs/miqi-rk3288_defconfig | 2 +-
configs/mk808_defconfig | 2 +-
configs/nanopc-t4-rk3399_defconfig | 2 +-
configs/nanopc-t6-rk3588_defconfig | 2 +-
configs/nanopi-m4-2gb-rk3399_defconfig | 2 +-
configs/nanopi-m4-rk3399_defconfig | 2 +-
configs/nanopi-m4b-rk3399_defconfig | 2 +-
configs/nanopi-neo4-rk3399_defconfig | 2 +-
configs/nanopi-r2c-plus-rk3328_defconfig | 2 +-
configs/nanopi-r2c-rk3328_defconfig | 2 +-
configs/nanopi-r2s-plus-rk3328_defconfig | 2 +-
configs/nanopi-r2s-rk3328_defconfig | 2 +-
configs/nanopi-r3s-rk3566_defconfig | 2 +-
configs/nanopi-r4s-rk3399_defconfig | 2 +-
configs/nanopi-r5c-rk3568_defconfig | 2 +-
configs/nanopi-r5s-rk3568_defconfig | 2 +-
configs/nanopi-r6c-rk3588s_defconfig | 2 +-
configs/nanopi-r6s-rk3588s_defconfig | 2 +-
configs/neu2-io-rv1126_defconfig | 2 +-
configs/neu6a-io-rk3588_defconfig | 2 +-
configs/neu6b-io-rk3588_defconfig | 2 +-
configs/nova-rk3588s_defconfig | 2 +-
configs/odroid-go2_defconfig | 2 +-
configs/odroid-m1-rk3568_defconfig | 2 +-
configs/odroid-m1s-rk3566_defconfig | 2 +-
configs/odroid-m2-rk3588s_defconfig | 2 +-
configs/orangepi-3b-rk3566_defconfig | 2 +-
configs/orangepi-5-plus-rk3588_defconfig | 2 +-
configs/orangepi-5-rk3588s_defconfig | 2 +-
configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 +-
configs/orangepi-r1-plus-rk3328_defconfig | 2 +-
configs/orangepi-rk3399_defconfig | 2 +-
configs/phycore-rk3288_defconfig | 2 +-
configs/pinebook-pro-rk3399_defconfig | 2 +-
configs/pinephone-pro-rk3399_defconfig | 2 +-
configs/pinetab2-rk3566_defconfig | 2 +-
configs/popmetal-rk3288_defconfig | 2 +-
configs/powkiddy-x55-rk3566_defconfig | 2 +-
configs/puma-rk3399_defconfig | 2 +-
configs/px30-core-ctouch2-of10-px30_defconfig | 2 +-
configs/px30-core-ctouch2-px30_defconfig | 2 +-
configs/px30-core-edimm2.2-px30_defconfig | 2 +-
configs/qnap-ts433-rk3568_defconfig | 2 +-
configs/quartz64-a-rk3566_defconfig | 2 +-
configs/quartz64-b-rk3566_defconfig | 2 +-
configs/quartzpro64-rk3588_defconfig | 2 +-
configs/radxa-cm3-io-rk3566_defconfig | 2 +-
configs/radxa-e25-rk3568_defconfig | 2 +-
configs/radxa-zero-3-rk3566_defconfig | 2 +-
configs/rk3399-generic-ddr3_defconfig | 2 +-
configs/roc-cc-rk3308_defconfig | 2 +-
configs/roc-cc-rk3328_defconfig | 2 +-
configs/roc-pc-mezzanine-rk3399_defconfig | 2 +-
configs/roc-pc-rk3399_defconfig | 2 +-
configs/rock-3a-rk3568_defconfig | 2 +-
configs/rock-3b-rk3568_defconfig | 2 +-
configs/rock-3c-rk3566_defconfig | 2 +-
configs/rock-4c-plus-rk3399_defconfig | 2 +-
configs/rock-4se-rk3399_defconfig | 2 +-
configs/rock-5-itx-rk3588_defconfig | 2 +-
configs/rock-5c-rk3588s_defconfig | 2 +-
configs/rock-pi-4-rk3399_defconfig | 2 +-
configs/rock-pi-4c-rk3399_defconfig | 2 +-
configs/rock-pi-e-rk3328_defconfig | 2 +-
configs/rock-pi-e-v3-rk3328_defconfig | 2 +-
configs/rock-pi-n10-rk3399pro_defconfig | 2 +-
configs/rock-pi-n8-rk3288_defconfig | 2 +-
configs/rock-pi-s-rk3308_defconfig | 2 +-
configs/rock-s0-rk3308_defconfig | 2 +-
configs/rock2_defconfig | 2 +-
configs/rock5a-rk3588s_defconfig | 2 +-
configs/rock5b-rk3588_defconfig | 2 +-
configs/rock64-rk3328_defconfig | 2 +-
configs/rock960-rk3399_defconfig | 2 +-
configs/rock_defconfig | 2 +-
configs/rockpro64-rk3399_defconfig | 2 +-
configs/sige7-rk3588_defconfig | 2 +-
configs/sonoff-ihost-rv1126_defconfig | 2 +-
configs/soquartz-blade-rk3566_defconfig | 2 +-
configs/soquartz-cm4-rk3566_defconfig | 2 +-
configs/soquartz-model-a-rk3566_defconfig | 2 +-
configs/tiger-rk3588_defconfig | 2 +-
configs/tinker-rk3288_defconfig | 2 +-
configs/tinker-s-rk3288_defconfig | 2 +-
configs/toybrick-rk3588_defconfig | 2 +-
configs/turing-rk1-rk3588_defconfig | 2 +-
configs/vyasa-rk3288_defconfig | 2 +-
125 files changed, 125 insertions(+), 124 deletions(-)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
index 366d52de4ee..dcebe5d2f2f 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -158,6 +158,7 @@
simple-bin {
filename = "u-boot-rockchip.bin";
pad-byte = <0xff>;
+ skip-at-start = <0x8000>;
#ifndef CONFIG_VPL
mkimage {
diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig
index 14c97b4c5bf..972d4c71b14 100644
--- a/configs/anbernic-rgxx3-rk3566_defconfig
+++ b/configs/anbernic-rgxx3-rk3566_defconfig
@@ -28,7 +28,7 @@ CONFIG_BOARD_TYPES=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_RNG_SEED=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig
index d84ea2f955f..e5eaf7f6449 100644
--- a/configs/bpi-r2-pro-rk3568_defconfig
+++ b/configs/bpi-r2-pro-rk3568_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2-pro.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_SYS_PROMPT="BPI-R2PRO> "
diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig
index d834c1886a5..fe85ba2f50d 100644
--- a/configs/chromebit_mickey_defconfig
+++ b/configs/chromebit_mickey_defconfig
@@ -36,7 +36,7 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/chromebook_bob_defconfig b/configs/chromebook_bob_defconfig
index 8fbd6fcbf94..47739d0ff67 100644
--- a/configs/chromebook_bob_defconfig
+++ b/configs/chromebook_bob_defconfig
@@ -41,7 +41,7 @@ CONFIG_BLOBLIST_FIXED=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_SPL_MAX_SIZE=0x1e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig
index f4b9caeb34f..d268e55f083 100644
--- a/configs/chromebook_jerry_defconfig
+++ b/configs/chromebook_jerry_defconfig
@@ -35,7 +35,7 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/chromebook_kevin_defconfig b/configs/chromebook_kevin_defconfig
index ff184115311..f00a4529095 100644
--- a/configs/chromebook_kevin_defconfig
+++ b/configs/chromebook_kevin_defconfig
@@ -42,7 +42,7 @@ CONFIG_BLOBLIST_FIXED=y
CONFIG_BLOBLIST_ADDR=0x100000
CONFIG_BLOBLIST_SIZE=0x1000
CONFIG_SPL_MAX_SIZE=0x1e000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_HANDOFF=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig
index 3a0be3078ab..a31052ca4f8 100644
--- a/configs/chromebook_minnie_defconfig
+++ b/configs/chromebook_minnie_defconfig
@@ -36,7 +36,7 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 78ab62c3392..fed4b1d9bde 100644
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -36,7 +36,7 @@ CONFIG_LOG=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/cm3588-nas-rk3588_defconfig b/configs/cm3588-nas-rk3588_defconfig
index fd0a32d6d79..abd60abc177 100644
--- a/configs/cm3588-nas-rk3588_defconfig
+++ b/configs/cm3588-nas-rk3588_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-friendlyelec-cm3588-nas.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/coolpi-4b-rk3588s_defconfig b/configs/coolpi-4b-rk3588s_defconfig
index ea985b81670..7b90bc59afb 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig b/configs/coolpi-cm5-evb-rk3588_defconfig
index 58ffe7baf5f..10d07332ad6 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/coolpi-cm5-genbook-rk3588_defconfig b/configs/coolpi-cm5-genbook-rk3588_defconfig
index 3eb5dc968af..ab867e758cc 100644
--- a/configs/coolpi-cm5-genbook-rk3588_defconfig
+++ b/configs/coolpi-cm5-genbook-rk3588_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-genbook.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/eaidk-610-rk3399_defconfig b/configs/eaidk-610-rk3399_defconfig
index 8f9a76157f1..7f3215628a4 100644
--- a/configs/eaidk-610-rk3399_defconfig
+++ b/configs/eaidk-610-rk3399_defconfig
@@ -15,7 +15,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-eaidk-610.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig
index 50dd29fcb01..9335dfd1dad 100644
--- a/configs/evb-px30_defconfig
+++ b/configs/evb-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
diff --git a/configs/evb-px5_defconfig b/configs/evb-px5_defconfig
index c9262417139..9dcf6badc78 100644
--- a/configs/evb-px5_defconfig
+++ b/configs/evb-px5_defconfig
@@ -41,7 +41,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig
index 4e471f0ebb3..a1d9590c841 100644
--- a/configs/evb-rk3036_defconfig
+++ b/configs/evb-rk3036_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3036-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig
index 3cbc22662a6..030abfc6b6e 100644
--- a/configs/evb-rk3229_defconfig
+++ b/configs/evb-rk3229_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x100000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPT=y
diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig
index f6b72a2b7a0..024127944c2 100644
--- a/configs/evb-rk3288_defconfig
+++ b/configs/evb-rk3288_defconfig
@@ -33,7 +33,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-evb-rk808.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig
index c8e1753b281..f07234a5024 100644
--- a/configs/evb-rk3308_defconfig
+++ b/configs/evb-rk3308_defconfig
@@ -17,7 +17,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig
index fd528535838..cb4a5386033 100644
--- a/configs/evb-rk3328_defconfig
+++ b/configs/evb-rk3328_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 9481dfae7e4..8f1b7570a35 100644
--- a/configs/evb-rk3399_defconfig
+++ b/configs/evb-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig
index a068bc6846c..9ab3583b4a0 100644
--- a/configs/evb-rk3568_defconfig
+++ b/configs/evb-rk3568_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index 3d4d2747145..9ea4ea1c6ab 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-evb1-v10.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig
index b32ca726b6c..b750df55e68 100644
--- a/configs/ficus-rk3399_defconfig
+++ b/configs/ficus-rk3399_defconfig
@@ -17,7 +17,7 @@ CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-ficus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/firefly-px30_defconfig b/configs/firefly-px30_defconfig
index 7398d06274f..eab55f669cf 100644
--- a/configs/firefly-px30_defconfig
+++ b/configs/firefly-px30_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig
index d8a671b7a8a..2205ec2f3e5 100644
--- a/configs/firefly-rk3288_defconfig
+++ b/configs/firefly-rk3288_defconfig
@@ -25,7 +25,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-firefly.dtb"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/firefly-rk3399_defconfig b/configs/firefly-rk3399_defconfig
index 3871627318b..aaea58b6b4a 100644
--- a/configs/firefly-rk3399_defconfig
+++ b/configs/firefly-rk3399_defconfig
@@ -17,7 +17,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig
index f79f0e84400..10d7616296f 100644
--- a/configs/generic-rk3568_defconfig
+++ b/configs/generic-rk3568_defconfig
@@ -23,7 +23,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/generic-rk3588_defconfig b/configs/generic-rk3588_defconfig
index 51e31dce3a9..b77f2a76dd6 100644
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -19,7 +19,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig
index 6e853991d1d..01cf1bb90c9 100644
--- a/configs/jaguar-rk3588_defconfig
+++ b/configs/jaguar-rk3588_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-jaguar.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CYCLIC=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/khadas-edge-captain-rk3399_defconfig b/configs/khadas-edge-captain-rk3399_defconfig
index 89611a0535e..0cac100784f 100644
--- a/configs/khadas-edge-captain-rk3399_defconfig
+++ b/configs/khadas-edge-captain-rk3399_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/khadas-edge-rk3399_defconfig b/configs/khadas-edge-rk3399_defconfig
index 3816f4327a6..5b5e39d8306 100644
--- a/configs/khadas-edge-rk3399_defconfig
+++ b/configs/khadas-edge-rk3399_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/khadas-edge-v-rk3399_defconfig b/configs/khadas-edge-v-rk3399_defconfig
index 35e20942572..07bf6bc595d 100644
--- a/configs/khadas-edge-v-rk3399_defconfig
+++ b/configs/khadas-edge-v-rk3399_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtb"
CONFIG_SYS_PBSIZE=1048
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/khadas-edge2-rk3588s_defconfig b/configs/khadas-edge2-rk3588s_defconfig
index 208c72ca425..b55f88d64f8 100644
--- a/configs/khadas-edge2-rk3588s_defconfig
+++ b/configs/khadas-edge2-rk3588s_defconfig
@@ -24,7 +24,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-khadas-edge2.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_MMC_WRITE=y
diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig
index 1ebb703c6fa..995d2af74a0 100644
--- a/configs/kylin-rk3036_defconfig
+++ b/configs/kylin-rk3036_defconfig
@@ -30,7 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3036-kylin.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
diff --git a/configs/leez-rk3399_defconfig b/configs/leez-rk3399_defconfig
index 57b097377fa..ac4c8b06f2f 100644
--- a/configs/leez-rk3399_defconfig
+++ b/configs/leez-rk3399_defconfig
@@ -15,7 +15,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-leez-p710.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig
index 46cc3c03fff..51f1f6ad5f8 100644
--- a/configs/lubancat-2-rk3568_defconfig
+++ b/configs/lubancat-2-rk3568_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat-2.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig
index 166468fd4e7..21747abe2bc 100644
--- a/configs/miqi-rk3288_defconfig
+++ b/configs/miqi-rk3288_defconfig
@@ -24,7 +24,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-miqi.dtb"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/mk808_defconfig b/configs/mk808_defconfig
index 8c7f4deb843..2b1d5b88d18 100644
--- a/configs/mk808_defconfig
+++ b/configs/mk808_defconfig
@@ -43,7 +43,7 @@ CONFIG_SYS_PBSIZE=276
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_MAX_SIZE=0x32000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SEPARATE_BSS=y
diff --git a/configs/nanopc-t4-rk3399_defconfig b/configs/nanopc-t4-rk3399_defconfig
index 26c12c51078..95276602a42 100644
--- a/configs/nanopc-t4-rk3399_defconfig
+++ b/configs/nanopc-t4-rk3399_defconfig
@@ -17,7 +17,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopc-t6-rk3588_defconfig b/configs/nanopc-t6-rk3588_defconfig
index 772b7df1555..31be93dc2e8 100644
--- a/configs/nanopc-t6-rk3588_defconfig
+++ b/configs/nanopc-t6-rk3588_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-nanopc-t6.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/nanopi-m4-2gb-rk3399_defconfig b/configs/nanopi-m4-2gb-rk3399_defconfig
index d24b7bc6d17..fa1839baa96 100644
--- a/configs/nanopi-m4-2gb-rk3399_defconfig
+++ b/configs/nanopi-m4-2gb-rk3399_defconfig
@@ -18,7 +18,7 @@ CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4-2gb.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopi-m4-rk3399_defconfig b/configs/nanopi-m4-rk3399_defconfig
index da3e44af841..ae84be9f5b9 100644
--- a/configs/nanopi-m4-rk3399_defconfig
+++ b/configs/nanopi-m4-rk3399_defconfig
@@ -18,7 +18,7 @@ CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopi-m4b-rk3399_defconfig b/configs/nanopi-m4b-rk3399_defconfig
index 247056ab58b..0815534618b 100644
--- a/configs/nanopi-m4b-rk3399_defconfig
+++ b/configs/nanopi-m4b-rk3399_defconfig
@@ -18,7 +18,7 @@ CONFIG_AHCI=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopi-neo4-rk3399_defconfig b/configs/nanopi-neo4-rk3399_defconfig
index 305877d2079..5ac47919e0a 100644
--- a/configs/nanopi-neo4-rk3399_defconfig
+++ b/configs/nanopi-neo4-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig
index bef1e22d644..c867c044b0a 100644
--- a/configs/nanopi-r2c-plus-rk3328_defconfig
+++ b/configs/nanopi-r2c-plus-rk3328_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig
index 4d66a76c7dc..37648c87e87 100644
--- a/configs/nanopi-r2c-rk3328_defconfig
+++ b/configs/nanopi-r2c-rk3328_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/nanopi-r2s-plus-rk3328_defconfig b/configs/nanopi-r2s-plus-rk3328_defconfig
index 3a75566ed4d..05a3e51dfb6 100644
--- a/configs/nanopi-r2s-plus-rk3328_defconfig
+++ b/configs/nanopi-r2s-plus-rk3328_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
index 2b9193d1ff5..ef458b221be 100644
--- a/configs/nanopi-r2s-rk3328_defconfig
+++ b/configs/nanopi-r2s-rk3328_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig
index 870613f690a..1b4a89637e4 100644
--- a/configs/nanopi-r3s-rk3566_defconfig
+++ b/configs/nanopi-r3s-rk3566_defconfig
@@ -20,7 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index a6dafe3d9eb..e60888a529f 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig
index 4a43b17ccb1..036e9158929 100644
--- a/configs/nanopi-r5c-rk3568_defconfig
+++ b/configs/nanopi-r5c-rk3568_defconfig
@@ -20,7 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig
index a60d229fbbf..8abd77879f7 100644
--- a/configs/nanopi-r5s-rk3568_defconfig
+++ b/configs/nanopi-r5s-rk3568_defconfig
@@ -20,7 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-nanopi-r5s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/nanopi-r6c-rk3588s_defconfig b/configs/nanopi-r6c-rk3588s_defconfig
index c4de5518a72..eaef4d23a33 100644
--- a/configs/nanopi-r6c-rk3588s_defconfig
+++ b/configs/nanopi-r6c-rk3588s_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig
index 2726729b9ac..3318b07736f 100644
--- a/configs/nanopi-r6s-rk3588s_defconfig
+++ b/configs/nanopi-r6s-rk3588s_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-nanopi-r6s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/neu2-io-rv1126_defconfig b/configs/neu2-io-rv1126_defconfig
index 18230859b18..431803e1e64 100644
--- a/configs/neu2-io-rv1126_defconfig
+++ b/configs/neu2-io-rv1126_defconfig
@@ -18,7 +18,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rv1126-edgeble-neu2-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig
index 291e0d26d42..cbcf1434d5e 100644
--- a/configs/neu6a-io-rk3588_defconfig
+++ b/configs/neu6a-io-rk3588_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6a-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig
index 4e22852f23c..6f4b35510a6 100644
--- a/configs/neu6b-io-rk3588_defconfig
+++ b/configs/neu6b-io-rk3588_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-edgeble-neu6b-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPT=y
diff --git a/configs/nova-rk3588s_defconfig b/configs/nova-rk3588s_defconfig
index fb30dfd1db8..d25405fbb72 100644
--- a/configs/nova-rk3588s_defconfig
+++ b/configs/nova-rk3588s_defconfig
@@ -20,7 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-indiedroid-nova.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/odroid-go2_defconfig b/configs/odroid-go2_defconfig
index 492802dddae..69bd559c5a9 100644
--- a/configs/odroid-go2_defconfig
+++ b/configs/odroid-go2_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig
index a8e8a8781e1..8e0e2353bf6 100644
--- a/configs/odroid-m1-rk3568_defconfig
+++ b/configs/odroid-m1-rk3568_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-odroid-m1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
diff --git a/configs/odroid-m1s-rk3566_defconfig b/configs/odroid-m1s-rk3566_defconfig
index 39e815ad317..0078a33dbc7 100644
--- a/configs/odroid-m1s-rk3566_defconfig
+++ b/configs/odroid-m1s-rk3566_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-odroid-m1s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/odroid-m2-rk3588s_defconfig b/configs/odroid-m2-rk3588s_defconfig
index 4c3fa8500d8..0bdc262bad0 100644
--- a/configs/odroid-m2-rk3588s_defconfig
+++ b/configs/odroid-m2-rk3588s_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-odroid-m2.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/orangepi-3b-rk3566_defconfig b/configs/orangepi-3b-rk3566_defconfig
index 2181c9caf58..83ca7bb27b5 100644
--- a/configs/orangepi-3b-rk3566_defconfig
+++ b/configs/orangepi-3b-rk3566_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-orangepi-3b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/orangepi-5-plus-rk3588_defconfig b/configs/orangepi-5-plus-rk3588_defconfig
index 9050fceda45..214d8363313 100644
--- a/configs/orangepi-5-plus-rk3588_defconfig
+++ b/configs/orangepi-5-plus-rk3588_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-orangepi-5-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/orangepi-5-rk3588s_defconfig b/configs/orangepi-5-rk3588s_defconfig
index 6e2ff7d338a..844dd22a1a8 100644
--- a/configs/orangepi-5-rk3588s_defconfig
+++ b/configs/orangepi-5-rk3588s_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-orangepi-5.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig
index 6d5d8b9dcc9..0874a013046 100644
--- a/configs/orangepi-r1-plus-lts-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus-lts.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig
index b382f9b9f18..1bd51675cc4 100644
--- a/configs/orangepi-r1-plus-rk3328_defconfig
+++ b/configs/orangepi-r1-plus-rk3328_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/orangepi-rk3399_defconfig b/configs/orangepi-rk3399_defconfig
index fdf3d698939..1d1cf412b43 100644
--- a/configs/orangepi-rk3399_defconfig
+++ b/configs/orangepi-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig
index ff03a59b48d..ac2944160b8 100644
--- a/configs/phycore-rk3288_defconfig
+++ b/configs/phycore-rk3288_defconfig
@@ -31,7 +31,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/pinebook-pro-rk3399_defconfig b/configs/pinebook-pro-rk3399_defconfig
index dfa927ccb17..195bc01152f 100644
--- a/configs/pinebook-pro-rk3399_defconfig
+++ b/configs/pinebook-pro-rk3399_defconfig
@@ -25,7 +25,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/pinephone-pro-rk3399_defconfig b/configs/pinephone-pro-rk3399_defconfig
index 5e16749ba7d..d5a70015ed6 100644
--- a/configs/pinephone-pro-rk3399_defconfig
+++ b/configs/pinephone-pro-rk3399_defconfig
@@ -23,7 +23,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinephone-pro.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/pinetab2-rk3566_defconfig b/configs/pinetab2-rk3566_defconfig
index 45e63b42d19..cf10abc4c8f 100644
--- a/configs/pinetab2-rk3566_defconfig
+++ b/configs/pinetab2-rk3566_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-pinetab2-v2.0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig
index ae7869ae5fa..4c29afe924e 100644
--- a/configs/popmetal-rk3288_defconfig
+++ b/configs/popmetal-rk3288_defconfig
@@ -30,7 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/powkiddy-x55-rk3566_defconfig b/configs/powkiddy-x55-rk3566_defconfig
index 85280839889..3b96c8d3c07 100644
--- a/configs/powkiddy-x55-rk3566_defconfig
+++ b/configs/powkiddy-x55-rk3566_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-powkiddy-x55.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 7a180b14130..55e15612260 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb"
CONFIG_CONSOLE_MUX=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x2e000
-CONFIG_SPL_PAD_TO=0x38000
+CONFIG_SPL_PAD_TO=0x40000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
CONFIG_SPL_I2C=y
diff --git a/configs/px30-core-ctouch2-of10-px30_defconfig b/configs/px30-core-ctouch2-of10-px30_defconfig
index 97a6d45f39b..23743683aa8 100644
--- a/configs/px30-core-ctouch2-of10-px30_defconfig
+++ b/configs/px30-core-ctouch2-of10-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2-of10.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
diff --git a/configs/px30-core-ctouch2-px30_defconfig b/configs/px30-core-ctouch2-px30_defconfig
index 0d20546a746..c3870f70d67 100644
--- a/configs/px30-core-ctouch2-px30_defconfig
+++ b/configs/px30-core-ctouch2-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-ctouch2.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
diff --git a/configs/px30-core-edimm2.2-px30_defconfig b/configs/px30-core-edimm2.2-px30_defconfig
index 6d7ec8f3598..1c0a1c63488 100644
--- a/configs/px30-core-edimm2.2-px30_defconfig
+++ b/configs/px30-core-edimm2.2-px30_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/px30-engicam-px30-core-edimm2.2.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
CONFIG_SPL_MAX_SIZE=0x20000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_BOOTROM_SUPPORT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
diff --git a/configs/qnap-ts433-rk3568_defconfig b/configs/qnap-ts433-rk3568_defconfig
index ceef0d25dc0..cb70e2bcdaf 100644
--- a/configs/qnap-ts433-rk3568_defconfig
+++ b/configs/qnap-ts433-rk3568_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-qnap-ts433.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/quartz64-a-rk3566_defconfig b/configs/quartz64-a-rk3566_defconfig
index fe3fa37611a..2578b5d65a0 100644
--- a/configs/quartz64-a-rk3566_defconfig
+++ b/configs/quartz64-a-rk3566_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/quartz64-b-rk3566_defconfig b/configs/quartz64-b-rk3566_defconfig
index 929736f76af..d8e7e3036a8 100644
--- a/configs/quartz64-b-rk3566_defconfig
+++ b/configs/quartz64-b-rk3566_defconfig
@@ -27,7 +27,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-quartz64-b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/quartzpro64-rk3588_defconfig b/configs/quartzpro64-rk3588_defconfig
index ade7be27e92..40dd6ff84bf 100644
--- a/configs/quartzpro64-rk3588_defconfig
+++ b/configs/quartzpro64-rk3588_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-quartzpro64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/radxa-cm3-io-rk3566_defconfig b/configs/radxa-cm3-io-rk3566_defconfig
index 2655fdc3170..690c56ec3b2 100644
--- a/configs/radxa-cm3-io-rk3566_defconfig
+++ b/configs/radxa-cm3-io-rk3566_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-cm3-io.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig
index 4df594ddc01..9d63d04034c 100644
--- a/configs/radxa-e25-rk3568_defconfig
+++ b/configs/radxa-e25-rk3568_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-radxa-e25.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/radxa-zero-3-rk3566_defconfig b/configs/radxa-zero-3-rk3566_defconfig
index 5989b07ad79..d75ae675b93 100644
--- a/configs/radxa-zero-3-rk3566_defconfig
+++ b/configs/radxa-zero-3-rk3566_defconfig
@@ -20,7 +20,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-radxa-zero-3w.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/rk3399-generic-ddr3_defconfig b/configs/rk3399-generic-ddr3_defconfig
index 490bc72ee92..9d550207ea9 100644
--- a/configs/rk3399-generic-ddr3_defconfig
+++ b/configs/rk3399-generic-ddr3_defconfig
@@ -41,7 +41,7 @@ CONFIG_BLOBLIST_FIXED=y
CONFIG_BLOBLIST_ADDR=0xff8eff00
CONFIG_BLOBLIST_SIZE=0x100
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
# CONFIG_SPL_SEPARATE_BSS is not set
diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig
index fb81d3bccfb..b08d0a4c1fb 100644
--- a/configs/roc-cc-rk3308_defconfig
+++ b/configs/roc-cc-rk3308_defconfig
@@ -17,7 +17,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig
index 183332ab7ce..80a44449328 100644
--- a/configs/roc-cc-rk3328_defconfig
+++ b/configs/roc-cc-rk3328_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-roc-cc.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/roc-pc-mezzanine-rk3399_defconfig b/configs/roc-pc-mezzanine-rk3399_defconfig
index 3ab5fd69c62..bac62d3b8a0 100644
--- a/configs/roc-pc-mezzanine-rk3399_defconfig
+++ b/configs/roc-pc-mezzanine-rk3399_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc-mezzanine.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_defconfig
index 0ef86748778..dad038e6020 100644
--- a/configs/roc-pc-rk3399_defconfig
+++ b/configs/roc-pc-rk3399_defconfig
@@ -24,7 +24,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/rock-3a-rk3568_defconfig b/configs/rock-3a-rk3568_defconfig
index 733ce631457..ebb24491205 100644
--- a/configs/rock-3a-rk3568_defconfig
+++ b/configs/rock-3a-rk3568_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/rock-3b-rk3568_defconfig b/configs/rock-3b-rk3568_defconfig
index 2023feb36c2..349a20349b0 100644
--- a/configs/rock-3b-rk3568_defconfig
+++ b/configs/rock-3b-rk3568_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/rock-3c-rk3566_defconfig b/configs/rock-3c-rk3566_defconfig
index 2528c7c639c..db8f6163627 100644
--- a/configs/rock-3c-rk3566_defconfig
+++ b/configs/rock-3c-rk3566_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-rock-3c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/rock-4c-plus-rk3399_defconfig b/configs/rock-4c-plus-rk3399_defconfig
index 0c73a212ea1..97ad1c52c92 100644
--- a/configs/rock-4c-plus-rk3399_defconfig
+++ b/configs/rock-4c-plus-rk3399_defconfig
@@ -23,7 +23,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4c-plus.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/rock-4se-rk3399_defconfig b/configs/rock-4se-rk3399_defconfig
index 3ae19692155..ed128429c8a 100644
--- a/configs/rock-4se-rk3399_defconfig
+++ b/configs/rock-4se-rk3399_defconfig
@@ -25,7 +25,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-4se.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/rock-5-itx-rk3588_defconfig b/configs/rock-5-itx-rk3588_defconfig
index d0dd1c20ece..47817435f67 100644
--- a/configs/rock-5-itx-rk3588_defconfig
+++ b/configs/rock-5-itx-rk3588_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5-itx.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/rock-5c-rk3588s_defconfig b/configs/rock-5c-rk3588s_defconfig
index 59f9f25edcb..5089597da7e 100644
--- a/configs/rock-5c-rk3588s_defconfig
+++ b/configs/rock-5c-rk3588s_defconfig
@@ -21,7 +21,7 @@ CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_ADC=y
diff --git a/configs/rock-pi-4-rk3399_defconfig b/configs/rock-pi-4-rk3399_defconfig
index f3a5c2c45f3..cb01181c651 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -25,7 +25,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/rock-pi-4c-rk3399_defconfig b/configs/rock-pi-4c-rk3399_defconfig
index 9bda50c8c77..1cbd5972463 100644
--- a/configs/rock-pi-4c-rk3399_defconfig
+++ b/configs/rock-pi-4c-rk3399_defconfig
@@ -25,7 +25,7 @@ CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4c.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig
index 52dad765a8a..532f420e544 100644
--- a/configs/rock-pi-e-rk3328_defconfig
+++ b/configs/rock-pi-e-rk3328_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/rock-pi-e-v3-rk3328_defconfig b/configs/rock-pi-e-v3-rk3328_defconfig
index 518ea4ebe51..fb2bc8cc9c9 100644
--- a/configs/rock-pi-e-v3-rk3328_defconfig
+++ b/configs/rock-pi-e-v3-rk3328_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock-pi-e.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_ATF=y
diff --git a/configs/rock-pi-n10-rk3399pro_defconfig b/configs/rock-pi-n10-rk3399pro_defconfig
index a9c6d8a907a..4ae0ddd3059 100644
--- a/configs/rock-pi-n10-rk3399pro_defconfig
+++ b/configs/rock-pi-n10-rk3399pro_defconfig
@@ -18,7 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399pro-rock-pi-n10.dtb"
# CONFIG_CONSOLE_MUX is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig
index 92ffc72cd7a..c64e8f080a3 100644
--- a/configs/rock-pi-n8-rk3288_defconfig
+++ b/configs/rock-pi-n8-rk3288_defconfig
@@ -29,7 +29,7 @@ CONFIG_DEBUG_UART=y
CONFIG_USE_PREBOOT=y
CONFIG_SILENT_CONSOLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_CMD_SPL=y
diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig
index 4b08af309b1..3c357b5cec6 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -17,7 +17,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/rock-s0-rk3308_defconfig b/configs/rock-s0-rk3308_defconfig
index 0a46e7bb187..8d7ed5d1434 100644
--- a/configs/rock-s0-rk3308_defconfig
+++ b/configs/rock-s0-rk3308_defconfig
@@ -17,7 +17,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-s0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig
index b356df23ec6..4255e37c448 100644
--- a/configs/rock2_defconfig
+++ b/configs/rock2_defconfig
@@ -30,7 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb"
CONFIG_SILENT_CONSOLE=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_CMD_GPIO=y
diff --git a/configs/rock5a-rk3588s_defconfig b/configs/rock5a-rk3588s_defconfig
index 9618d590009..2449f33abc5 100644
--- a/configs/rock5a-rk3588s_defconfig
+++ b/configs/rock5a-rk3588s_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 47ee2109f8e..80781eef2d1 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -29,7 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig
index 6d00b52e62f..12e248c05c1 100644
--- a/configs/rock64-rk3328_defconfig
+++ b/configs/rock64-rk3328_defconfig
@@ -25,7 +25,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index aebfa73459c..1c361b019b7 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -16,7 +16,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
CONFIG_SYS_PBSIZE=1052
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_TPL=y
diff --git a/configs/rock_defconfig b/configs/rock_defconfig
index d2a84710cb0..09740abf55c 100644
--- a/configs/rock_defconfig
+++ b/configs/rock_defconfig
@@ -30,7 +30,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3188-radxarock.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x7800
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_CMD_I2C=y
diff --git a/configs/rockpro64-rk3399_defconfig b/configs/rockpro64-rk3399_defconfig
index 75322073285..fdd80e72bf1 100644
--- a/configs/rockpro64-rk3399_defconfig
+++ b/configs/rockpro64-rk3399_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
diff --git a/configs/sige7-rk3588_defconfig b/configs/sige7-rk3588_defconfig
index 8b033e22b84..c374ff8d337 100644
--- a/configs/sige7-rk3588_defconfig
+++ b/configs/sige7-rk3588_defconfig
@@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-armsom-sige7.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/sonoff-ihost-rv1126_defconfig b/configs/sonoff-ihost-rv1126_defconfig
index 78ca7a3859e..74deef49737 100644
--- a/configs/sonoff-ihost-rv1126_defconfig
+++ b/configs/sonoff-ihost-rv1126_defconfig
@@ -19,7 +19,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_DEFAULT_FDT_FILE="rv1126-sonoff-ihost.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
diff --git a/configs/soquartz-blade-rk3566_defconfig b/configs/soquartz-blade-rk3566_defconfig
index a1a51b2c657..a29310ede62 100644
--- a/configs/soquartz-blade-rk3566_defconfig
+++ b/configs/soquartz-blade-rk3566_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-blade.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/soquartz-cm4-rk3566_defconfig b/configs/soquartz-cm4-rk3566_defconfig
index a8bca0eaccc..4652879be6c 100644
--- a/configs/soquartz-cm4-rk3566_defconfig
+++ b/configs/soquartz-cm4-rk3566_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-cm4.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/soquartz-model-a-rk3566_defconfig b/configs/soquartz-model-a-rk3566_defconfig
index f080d2e36d2..913cb87b12d 100644
--- a/configs/soquartz-model-a-rk3566_defconfig
+++ b/configs/soquartz-model-a-rk3566_defconfig
@@ -21,7 +21,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-soquartz-model-a.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
index f962ac416f3..a3952ff55da 100644
--- a/configs/tiger-rk3588_defconfig
+++ b/configs/tiger-rk3588_defconfig
@@ -28,7 +28,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_CYCLIC=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
# CONFIG_BOOTM_NETBSD is not set
diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig
index bc5379d4343..fd7f60008d6 100644
--- a/configs/tinker-rk3288_defconfig
+++ b/configs/tinker-rk3288_defconfig
@@ -24,7 +24,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker.dtb"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig
index f0c8cc5bbc1..240d8bd9b5f 100644
--- a/configs/tinker-s-rk3288_defconfig
+++ b/configs/tinker-s-rk3288_defconfig
@@ -24,7 +24,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3288-tinker-s.dtb"
CONFIG_MISC_INIT_R=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
diff --git a/configs/toybrick-rk3588_defconfig b/configs/toybrick-rk3588_defconfig
index 5e70341c987..7da1b5cbc3b 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -19,7 +19,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/turing-rk1-rk3588_defconfig b/configs/turing-rk1-rk3588_defconfig
index 0eddf15833c..73d7b32e300 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -22,7 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig
index 3b4dc5b5699..d3b88269134 100644
--- a/configs/vyasa-rk3288_defconfig
+++ b/configs/vyasa-rk3288_defconfig
@@ -30,7 +30,7 @@ CONFIG_USE_PREBOOT=y
CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb"
CONFIG_SILENT_CONSOLE=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_PAD_TO=0x7f8000
+CONFIG_SPL_PAD_TO=0x800000
CONFIG_SPL_NO_BSS_LIMIT=y
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_OS_BOOT=y
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 27/31] vbe: Add a bootmeth driver for abrec
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (25 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 26/31] rockchip: Set the skip-at-start property correctly Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 28/31] rockchip: Update binman image for new skip-at-start setup Simon Glass
` (3 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List; +Cc: Simon Glass, Tom Rini
Add a VBE-ABrec bootmeth so that the VBE state can be accessed.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Add new patch with a bootmeth driver for abrec
boot/vbe_abrec.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/boot/vbe_abrec.c b/boot/vbe_abrec.c
index 6d0f622262d..8593082fd79 100644
--- a/boot/vbe_abrec.c
+++ b/boot/vbe_abrec.c
@@ -8,6 +8,7 @@
#define LOG_CATEGORY LOGC_BOOT
+#include <bootmeth.h>
#include <dm.h>
#include <memalign.h>
#include <mmc.h>
@@ -81,3 +82,101 @@ int abrec_read_state(struct udevice *dev, struct abrec_state *state)
return 0;
}
+
+static int vbe_abrec_get_state_desc(struct udevice *dev, char *buf,
+ int maxsize)
+{
+ struct abrec_state state;
+ int ret;
+
+ ret = abrec_read_state(dev, &state);
+ if (ret)
+ return log_msg_ret("read", ret);
+
+ if (maxsize < 30)
+ return -ENOSPC;
+ snprintf(buf, maxsize, "Version: %s\nVernum: %x/%x", state.fw_version,
+ state.fw_vernum >> FWVER_KEY_SHIFT,
+ state.fw_vernum & FWVER_FW_MASK);
+
+ return 0;
+}
+
+static int vbe_abrec_read_bootflow(struct udevice *dev, struct bootflow *bflow)
+{
+ int ret;
+
+ if (CONFIG_IS_ENABLED(BOOTMETH_VBE_ABREC_FW)) {
+ if (vbe_phase() == VBE_PHASE_FIRMWARE) {
+ ret = abrec_read_bootflow_fw(dev, bflow);
+ if (ret)
+ return log_msg_ret("fw", ret);
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int vbe_abrec_read_file(struct udevice *dev, struct bootflow *bflow,
+ const char *file_path, ulong addr,
+ enum bootflow_img_t type, ulong *sizep)
+{
+ int ret;
+
+ if (vbe_phase() == VBE_PHASE_OS) {
+ ret = bootmeth_common_read_file(dev, bflow, file_path, addr,
+ type, sizep);
+ if (ret)
+ return log_msg_ret("os", ret);
+ }
+
+ /* To be implemented */
+ return -EINVAL;
+}
+
+static struct bootmeth_ops bootmeth_vbe_abrec_ops = {
+ .get_state_desc = vbe_abrec_get_state_desc,
+ .read_bootflow = vbe_abrec_read_bootflow,
+ .read_file = vbe_abrec_read_file,
+};
+
+static int bootmeth_vbe_abrec_probe(struct udevice *dev)
+{
+ struct abrec_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = abrec_read_priv(dev_ofnode(dev), priv);
+ if (ret)
+ return log_msg_ret("abp", ret);
+
+ return 0;
+}
+
+static int bootmeth_vbe_abrec_bind(struct udevice *dev)
+{
+ struct bootmeth_uc_plat *plat = dev_get_uclass_plat(dev);
+
+ plat->desc = "VBE A/B/recovery";
+ plat->flags = BOOTMETHF_GLOBAL;
+
+ return 0;
+}
+
+#if CONFIG_IS_ENABLED(OF_REAL)
+static const struct udevice_id generic_simple_vbe_abrec_ids[] = {
+ { .compatible = "fwupd,vbe-abrec" },
+ { }
+};
+#endif
+
+U_BOOT_DRIVER(vbe_abrec) = {
+ .name = "vbe_abrec",
+ .id = UCLASS_BOOTMETH,
+ .of_match = of_match_ptr(generic_simple_vbe_abrec_ids),
+ .ops = &bootmeth_vbe_abrec_ops,
+ .bind = bootmeth_vbe_abrec_bind,
+ .probe = bootmeth_vbe_abrec_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+ .priv_auto = sizeof(struct abrec_priv),
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 28/31] rockchip: Update binman image for new skip-at-start setup
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (26 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 27/31] vbe: Add a bootmeth driver for abrec Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader" Simon Glass
` (2 subsequent siblings)
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Jeffy Chen, Kever Yang, Philipp Tomsich, Tom Rini,
huang lin
Now that the skip-at-start feature is properly used in Binman, drop the
various workarounds in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Split out the fixes for skip-at-start into a new patch
arch/arm/dts/rockchip-vpl-u-boot.dtsi | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rockchip-vpl-u-boot.dtsi b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
index 5367a40c543..0ac1bf0a09b 100644
--- a/arch/arm/dts/rockchip-vpl-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-vpl-u-boot.dtsi
@@ -28,7 +28,6 @@
bootph-verify;
compatible = "fwupd,vbe-abrec";
storage = "mmc0";
- skip-offset = <0x8000>;
area-start = <0x7f8000>;
area-size = <0x800000>;
state-offset = <(0x7f8000 - 0x400)>;
@@ -129,7 +128,7 @@
vpl {
type = "fit";
- offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 0x200 + 0x8000)>;
+ offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 0x200)>;
description = "FIT image for U-Boot TPL";
#address-cells = <1>;
fit,fdt-list = "of-list";
@@ -174,7 +173,7 @@
# ifdef CONFIG_BOOTMETH_VBE_ABREC
vbe-a {
type = "section";
- offset = <(CONFIG_SPL_PAD_TO + 0x8000)>;
+ offset = <CONFIG_SPL_PAD_TO>;
spl-a {
insert-template = <&spl_template>;
size = <0x100000>;
@@ -211,7 +210,7 @@
# else /* CONFIG_BOOTMETH_VBE_SIMPLE */
vbe {
type = "fit";
- offset = <(CONFIG_SPL_PAD_TO + 0x8000)>;
+ offset = <CONFIG_SPL_PAD_TO>;
insert-template = <&common_part>;
};
# endif /* VBE method */
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader"
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (27 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 28/31] rockchip: Update binman image for new skip-at-start setup Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:50 ` Raymond Mao
2025-03-28 15:35 ` [PATCH v3 30/31] rockchip: Relocate bloblist at the end of the SPL phase Simon Glass
2025-03-28 15:35 ` [PATCH v3 31/31] bloblist: Allow using a different bloblist address Simon Glass
30 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Levi Yun, Patrick Rudolph, Raymond Mao, Tom Rini
The logic of this has become too confusing.
The primary issue with the patch is that U-Boot needs to set up a
bloblist in the first phase where BLOBLIST is enabled. Subsequent
phases can then use that bloblist.
But the first phase of U-Boot cannot assume that one exists.
Reverting this commit seems like a better starting point for getting
things working for all use-cases.
Note: The work to tidy this up is apparently underway. For this series,
a revert is the easiest path.
This reverts commit 66131310d8ff1ba228f989b41bd8812f43be41c3.
https://lore.kernel.org/u-boot/CAPnjgZ3hMHtiH=f5ZKXNniOfV_-vFryq1Gn7QZ5hKU8Wjo8igw@mail.gmail.com/
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v1)
common/bloblist.c | 64 ++++++++++++++--------------------------------
include/bloblist.h | 10 --------
2 files changed, 19 insertions(+), 55 deletions(-)
diff --git a/common/bloblist.c b/common/bloblist.c
index bc752b5fdf5..3f8c7f669a7 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -500,57 +500,37 @@ int bloblist_reloc(void *to, uint to_size)
return 0;
}
-/*
- * Weak default function for getting bloblist from boot args.
- */
-int __weak xferlist_from_boot_arg(ulong __always_unused addr,
- ulong __always_unused size)
-{
- return -ENOENT;
-}
-
int bloblist_init(void)
{
bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
int ret = -ENOENT;
- ulong addr = 0, size;
- /*
- * If U-Boot is not in the first phase, an existing bloblist must be
- * at a fixed address.
- */
- bool from_addr = fixed && !xpl_is_first_phase();
- /*
- * If U-Boot is in the first phase that an arch custom routine should
- * install the bloblist passed from previous loader to this fixed
+ ulong addr, size;
+ bool expected;
+
+ /**
+ * We don't expect to find an existing bloblist in the first phase of
+ * U-Boot that runs. Also we have no way to receive the address of an
+ * allocated bloblist from a previous stage, so it must be at a fixed
* address.
*/
- bool from_boot_arg = fixed && xpl_is_first_phase();
-
+ expected = fixed && !xpl_is_first_phase();
if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
- from_addr = false;
+ expected = false;
if (fixed)
addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
CONFIG_BLOBLIST_ADDR);
size = CONFIG_BLOBLIST_SIZE;
-
- if (from_boot_arg)
- ret = xferlist_from_boot_arg(addr, size);
- else if (from_addr)
+ if (expected) {
ret = bloblist_check(addr, size);
-
- if (ret)
- log_warning("Bloblist at %lx not found (err=%d)\n",
- addr, ret);
- else
- /* Get the real size */
- size = gd->bloblist->total_size;
-
+ if (ret) {
+ log_warning("Expected bloblist at %lx not found (err=%d)\n",
+ addr, ret);
+ } else {
+ /* Get the real size, if it is not what we expected */
+ size = gd->bloblist->total_size;
+ }
+ }
if (ret) {
- /*
- * If we don't have a bloblist from a fixed address, or the one
- * in the fixed address is not valid. we must allocate the
- * memory for it now.
- */
if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) {
void *ptr = memalign(BLOBLIST_ALIGN, size);
@@ -558,8 +538,7 @@ int bloblist_init(void)
return log_msg_ret("alloc", -ENOMEM);
addr = map_to_sysmem(ptr);
} else if (!fixed) {
- return log_msg_ret("BLOBLIST_FIXED is not enabled",
- ret);
+ return log_msg_ret("!fixed", ret);
}
log_debug("Creating new bloblist size %lx at %lx\n", size,
addr);
@@ -572,11 +551,6 @@ int bloblist_init(void)
return log_msg_ret("ini", ret);
gd->flags |= GD_FLG_BLOBLIST_READY;
-#ifdef DEBUG
- bloblist_show_stats();
- bloblist_show_list();
-#endif
-
return 0;
}
diff --git a/include/bloblist.h b/include/bloblist.h
index dfe6a700e5e..191b9aa1d54 100644
--- a/include/bloblist.h
+++ b/include/bloblist.h
@@ -500,14 +500,4 @@ static inline int bloblist_maybe_init(void)
*/
int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig);
-/**
- * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it
- * to the specified address.
- *
- * @addr: Address for the bloblist
- * @size: Size of space reserved for the bloblist
- * Return: 0 if OK, else on error
- */
-int xferlist_from_boot_arg(ulong addr, ulong size);
-
#endif /* __BLOBLIST_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 30/31] rockchip: Relocate bloblist at the end of the SPL phase
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (28 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader" Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 31/31] bloblist: Allow using a different bloblist address Simon Glass
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Raymond Mao, Dragan Simic, Jeffy Chen, Jonas Karlman,
Kever Yang, Philipp Tomsich, Quentin Schulz, Tom Rini, huang lin
Where the bloblist is located in internal memory and TF-A's BL31 blob
removes access to this memory, the best option seems to be to relocate
the bloblist just before running TF-A.
Do this at the end of SPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Raymond Mao <raymond.mao@linaro.org>
---
Changes in v3:
- Add the BLOBLIST_RELOC condition as well
Changes in v2:
- Move this logic into board-specific code
arch/arm/mach-rockchip/spl.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 305373a161c..a919246c4aa 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -3,6 +3,7 @@
* (C) Copyright 2019 Rockchip Electronics Co., Ltd
*/
+#include <bloblist.h>
#include <cpu_func.h>
#include <debug_uart.h>
#include <dm.h>
@@ -133,6 +134,20 @@ void board_init_f(ulong dummy)
void spl_board_prepare_for_boot(void)
{
+ /*
+ * On RK3399, TF-A is executed after SPL and before U-Boot. It removes
+ * our access to the IRAM. So move the bloblist to RAM.
+ */
+ if (xpl_phase() == PHASE_SPL && IS_ENABLED(CONFIG_VPL) &&
+ CONFIG_IS_ENABLED(BLOBLIST_RELOC)) {
+ ulong addr = CONFIG_IF_ENABLED_INT(BLOBLIST_RELOC,
+ BLOBLIST_RELOC_ADDR);
+
+ log_debug("Relocating bloblist %p to %lx\n", gd_bloblist(),
+ addr);
+ bloblist_reloc(map_sysmem(addr, 0), bloblist_get_total_size());
+ }
+
if (!IS_ENABLED(CONFIG_ARM64) || CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* [PATCH v3 31/31] bloblist: Allow using a different bloblist address
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
` (29 preceding siblings ...)
2025-03-28 15:35 ` [PATCH v3 30/31] rockchip: Relocate bloblist at the end of the SPL phase Simon Glass
@ 2025-03-28 15:35 ` Simon Glass
30 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 15:35 UTC (permalink / raw)
To: U-Boot Mailing List
Cc: Simon Glass, Alex Shumsky, Jaehoon Chung, Jagan Teki,
Jerome Forissier, Jiaxun Yang, Joshua Watt, Levi Yun,
Mattijs Korpershoek, Patrick Rudolph, Raymond Mao, Stefan Roese,
Tom Rini
Where the bloblist is located in internal memory and TF-A's BL31 blob
removes access to this memory, the best option seems to be to relocate
the bloblist just before running TF-A.
We can do the relocation in board-specific code, but need an option to
pick up the correct address within U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
---
(no changes since v2)
Changes in v2:
- Move the actual relocation code to a previous board-specific patch
common/Kconfig | 20 ++++++++++++++++++++
common/bloblist.c | 15 ++++++++++++++-
2 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/common/Kconfig b/common/Kconfig
index 7685914fa6f..778ac6275c4 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -1127,6 +1127,26 @@ config SPL_BLOBLIST_ALLOC
endchoice
+config SPL_BLOBLIST_RELOC
+ bool "Relocate the bloblist before existing SPL"
+ depends on BLOBLIST_FIXED
+ help
+ Some platforms locate the bloblist in SRAM in SPL. In some cases,
+ the TF-A BL31 blob removes access to SRAM, e.g. with Rockchip RK3399.
+
+ Enable this option to make U-Boot copy the bloblist from SRAM to SDRAM
+ before leaving SPL.
+
+config SPL_BLOBLIST_RELOC_ADDR
+ hex "Relocate the bloblist before existing SPL"
+ depends on SPL_BLOBLIST_RELOC
+ default BLOBLIST_ADDR
+ help
+ Sets the address to which the bloblist is relocated at the end of SPL.
+ U-Boot proper uses this address when it starts up. Note that U-Boot
+ always relocates the bloblist again as part of its own relocation
+ process.
+
endif # SPL_BLOBLIST
if TPL_BLOBLIST
diff --git a/common/bloblist.c b/common/bloblist.c
index 3f8c7f669a7..effb38dff9c 100644
--- a/common/bloblist.c
+++ b/common/bloblist.c
@@ -516,9 +516,22 @@ int bloblist_init(void)
expected = fixed && !xpl_is_first_phase();
if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
expected = false;
- if (fixed)
+ if (fixed) {
addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
CONFIG_BLOBLIST_ADDR);
+
+ if (xpl_phase() == PHASE_BOARD_F &&
+ IS_ENABLED(CONFIG_SPL_BLOBLIST_RELOC)) {
+ ulong addr = IF_ENABLED_INT(CONFIG_SPL_BLOBLIST_RELOC,
+ CONFIG_SPL_BLOBLIST_RELOC_ADDR);
+
+ log_debug("Using bloblist at %lx\n", addr);
+ bloblist_reloc(map_sysmem(addr, 0),
+ bloblist_get_total_size());
+ }
+ log_debug("bloblist addr=%lx\n", addr);
+ }
+
size = CONFIG_BLOBLIST_SIZE;
if (expected) {
ret = bloblist_check(addr, size);
--
2.43.0
^ permalink raw reply related [flat|nested] 51+ messages in thread
* Re: [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader"
2025-03-28 15:35 ` [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader" Simon Glass
@ 2025-03-28 15:50 ` Raymond Mao
2025-03-28 16:13 ` Tom Rini
0 siblings, 1 reply; 51+ messages in thread
From: Raymond Mao @ 2025-03-28 15:50 UTC (permalink / raw)
To: Simon Glass; +Cc: U-Boot Mailing List, Levi Yun, Patrick Rudolph, Tom Rini
Hi Simon,
On Fri, 28 Mar 2025 at 11:36, Simon Glass <sjg@chromium.org> wrote:
>
> The logic of this has become too confusing.
>
> The primary issue with the patch is that U-Boot needs to set up a
> bloblist in the first phase where BLOBLIST is enabled. Subsequent
> phases can then use that bloblist.
>
> But the first phase of U-Boot cannot assume that one exists.
>
> Reverting this commit seems like a better starting point for getting
> things working for all use-cases.
>
> Note: The work to tidy this up is apparently underway. For this series,
> a revert is the easiest path.
>
> This reverts commit 66131310d8ff1ba228f989b41bd8812f43be41c3.
>
> https://lore.kernel.org/u-boot/CAPnjgZ3hMHtiH=f5ZKXNniOfV_-vFryq1Gn7QZ5hKU8Wjo8igw@mail.gmail.com/
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
Is this same as something we discussed in the thread below?
https://lore.kernel.org/u-boot/20250205015606.2686149-29-sjg@chromium.org/
I am a bit confused since I think we had agreed that it should not be reverted.
Regards,
Raymond
> common/bloblist.c | 64 ++++++++++++++--------------------------------
> include/bloblist.h | 10 --------
> 2 files changed, 19 insertions(+), 55 deletions(-)
>
> diff --git a/common/bloblist.c b/common/bloblist.c
> index bc752b5fdf5..3f8c7f669a7 100644
> --- a/common/bloblist.c
> +++ b/common/bloblist.c
> @@ -500,57 +500,37 @@ int bloblist_reloc(void *to, uint to_size)
> return 0;
> }
>
> -/*
> - * Weak default function for getting bloblist from boot args.
> - */
> -int __weak xferlist_from_boot_arg(ulong __always_unused addr,
> - ulong __always_unused size)
> -{
> - return -ENOENT;
> -}
> -
> int bloblist_init(void)
> {
> bool fixed = IS_ENABLED(CONFIG_BLOBLIST_FIXED);
> int ret = -ENOENT;
> - ulong addr = 0, size;
> - /*
> - * If U-Boot is not in the first phase, an existing bloblist must be
> - * at a fixed address.
> - */
> - bool from_addr = fixed && !xpl_is_first_phase();
> - /*
> - * If U-Boot is in the first phase that an arch custom routine should
> - * install the bloblist passed from previous loader to this fixed
> + ulong addr, size;
> + bool expected;
> +
> + /**
> + * We don't expect to find an existing bloblist in the first phase of
> + * U-Boot that runs. Also we have no way to receive the address of an
> + * allocated bloblist from a previous stage, so it must be at a fixed
> * address.
> */
> - bool from_boot_arg = fixed && xpl_is_first_phase();
> -
> + expected = fixed && !xpl_is_first_phase();
> if (xpl_prev_phase() == PHASE_TPL && !IS_ENABLED(CONFIG_TPL_BLOBLIST))
> - from_addr = false;
> + expected = false;
> if (fixed)
> addr = IF_ENABLED_INT(CONFIG_BLOBLIST_FIXED,
> CONFIG_BLOBLIST_ADDR);
> size = CONFIG_BLOBLIST_SIZE;
> -
> - if (from_boot_arg)
> - ret = xferlist_from_boot_arg(addr, size);
> - else if (from_addr)
> + if (expected) {
> ret = bloblist_check(addr, size);
> -
> - if (ret)
> - log_warning("Bloblist at %lx not found (err=%d)\n",
> - addr, ret);
> - else
> - /* Get the real size */
> - size = gd->bloblist->total_size;
> -
> + if (ret) {
> + log_warning("Expected bloblist at %lx not found (err=%d)\n",
> + addr, ret);
> + } else {
> + /* Get the real size, if it is not what we expected */
> + size = gd->bloblist->total_size;
> + }
> + }
> if (ret) {
> - /*
> - * If we don't have a bloblist from a fixed address, or the one
> - * in the fixed address is not valid. we must allocate the
> - * memory for it now.
> - */
> if (CONFIG_IS_ENABLED(BLOBLIST_ALLOC)) {
> void *ptr = memalign(BLOBLIST_ALIGN, size);
>
> @@ -558,8 +538,7 @@ int bloblist_init(void)
> return log_msg_ret("alloc", -ENOMEM);
> addr = map_to_sysmem(ptr);
> } else if (!fixed) {
> - return log_msg_ret("BLOBLIST_FIXED is not enabled",
> - ret);
> + return log_msg_ret("!fixed", ret);
> }
> log_debug("Creating new bloblist size %lx at %lx\n", size,
> addr);
> @@ -572,11 +551,6 @@ int bloblist_init(void)
> return log_msg_ret("ini", ret);
> gd->flags |= GD_FLG_BLOBLIST_READY;
>
> -#ifdef DEBUG
> - bloblist_show_stats();
> - bloblist_show_list();
> -#endif
> -
> return 0;
> }
>
> diff --git a/include/bloblist.h b/include/bloblist.h
> index dfe6a700e5e..191b9aa1d54 100644
> --- a/include/bloblist.h
> +++ b/include/bloblist.h
> @@ -500,14 +500,4 @@ static inline int bloblist_maybe_init(void)
> */
> int bloblist_check_reg_conv(ulong rfdt, ulong rzero, ulong rsig);
>
> -/**
> - * xferlist_from_boot_arg() - Get bloblist from the boot args and relocate it
> - * to the specified address.
> - *
> - * @addr: Address for the bloblist
> - * @size: Size of space reserved for the bloblist
> - * Return: 0 if OK, else on error
> - */
> -int xferlist_from_boot_arg(ulong addr, ulong size);
> -
> #endif /* __BLOBLIST_H */
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL
2025-03-28 15:34 ` [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL Simon Glass
@ 2025-03-28 16:11 ` Jonas Karlman
0 siblings, 0 replies; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 16:11 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Jeffy Chen, Kever Yang,
Peter Robinson, Philipp Tomsich, Quentin Schulz, Tom Rini,
huang lin
Hi Simon,
On 2025-03-28 16:34, Simon Glass wrote:
> When VPL is in use, memory init happens in SPL, so there is no need to
> include the DMC device before that. Adjust the tags to save space.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Only enable MMC when VPM is in use.
>
> arch/arm/dts/rk3399-u-boot.dtsi | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
> index 81a3c6fc972..c3d0da62c8f 100644
> --- a/arch/arm/dts/rk3399-u-boot.dtsi
> +++ b/arch/arm/dts/rk3399-u-boot.dtsi
> @@ -71,7 +71,12 @@
> 0x0 0xffa88800 0x0 0x1800
> 0x0 0xffa8a000 0x0 0x2000
> 0x0 0xffa8c000 0x0 0x1000>;
> - bootph-all;
> +#ifdef CONFIG_VPL
> + bootph-pre-ram;
> + bootph-some-ram;
> +#else
> + bootph-all;
Please use correct indentation for above bootph- props,
they now use two instead of one tab.
Regards,
Jonas
> +#endif
> status = "okay";
> };
>
> @@ -118,6 +123,10 @@
> };
>
> &sdmmc {
> +#ifdef CONFIG_VPL
> + bootph-pre-sram;
> + bootph-verify;
> +#endif
> bootph-pre-ram;
> bootph-some-ram;
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader"
2025-03-28 15:50 ` Raymond Mao
@ 2025-03-28 16:13 ` Tom Rini
2025-03-28 23:38 ` Simon Glass
0 siblings, 1 reply; 51+ messages in thread
From: Tom Rini @ 2025-03-28 16:13 UTC (permalink / raw)
To: Raymond Mao, Simon Glass; +Cc: U-Boot Mailing List, Levi Yun, Patrick Rudolph
[-- Attachment #1: Type: text/plain, Size: 1699 bytes --]
On Fri, Mar 28, 2025 at 11:50:14AM -0400, Raymond Mao wrote:
> Hi Simon,
>
>
> On Fri, 28 Mar 2025 at 11:36, Simon Glass <sjg@chromium.org> wrote:
> >
> > The logic of this has become too confusing.
> >
> > The primary issue with the patch is that U-Boot needs to set up a
> > bloblist in the first phase where BLOBLIST is enabled. Subsequent
> > phases can then use that bloblist.
> >
> > But the first phase of U-Boot cannot assume that one exists.
> >
> > Reverting this commit seems like a better starting point for getting
> > things working for all use-cases.
> >
> > Note: The work to tidy this up is apparently underway. For this series,
> > a revert is the easiest path.
> >
> > This reverts commit 66131310d8ff1ba228f989b41bd8812f43be41c3.
> >
> > https://lore.kernel.org/u-boot/CAPnjgZ3hMHtiH=f5ZKXNniOfV_-vFryq1Gn7QZ5hKU8Wjo8igw@mail.gmail.com/
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > (no changes since v1)
> >
>
> Is this same as something we discussed in the thread below?
> https://lore.kernel.org/u-boot/20250205015606.2686149-29-sjg@chromium.org/
>
> I am a bit confused since I think we had agreed that it should not be reverted.
Yes, it is extremely frustrating to have posted both this:
https://patchwork.ozlabs.org/project/uboot/list/?series=450425&state=*
as the first pass at doing what was agreed on the path forward while
also posting this thread which cannot be against either next nor next
with the above applied and so isn't worth anyone elses time. I suspect
this thread also includes various rockchip patches that were requested
to be broken out and posted by themselves instead.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
@ 2025-03-28 16:16 ` Jonas Karlman
2025-03-28 23:40 ` Simon Glass
2025-03-28 16:51 ` Peter Robinson
2025-03-28 18:35 ` Jonas Karlman
2 siblings, 1 reply; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 16:16 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Simon,
On 2025-03-28 16:34, Simon Glass wrote:
> Add support for this new phase, which runs after TPL. It determines the
> state of the machine, then selects which SPL image to use. SDRAM init is
> then done in SPL, so that it is updatable.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> - Skip spl-boot-order.c for VPL (rather than modifying it)
>
> arch/arm/include/asm/spl.h | 1 +
> arch/arm/mach-rockchip/Kconfig | 25 +++++-
> arch/arm/mach-rockchip/Makefile | 11 ++-
> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> arch/arm/mach-rockchip/spl.c | 3 +
> arch/arm/mach-rockchip/tpl.c | 2 +-
> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> common/spl/Kconfig | 1 +
> 9 files changed, 205 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> create mode 100644 arch/arm/mach-rockchip/vpl.c
>
This patch and therefore this series does not apply to the next branch.
Are there any depends that are missing or are you only testing based on
your own fork?
Regards,
Jonas
[snip]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 08/31] rockchip: dts: Create a template for the FIT
2025-03-28 15:34 ` [PATCH v3 08/31] rockchip: dts: Create a template for the FIT Simon Glass
@ 2025-03-28 16:26 ` Jonas Karlman
0 siblings, 0 replies; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 16:26 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Jeffy Chen, Kever Yang, Philipp Tomsich,
Tom Rini, huang lin
Hi Simon,
On 2025-03-28 16:34, Simon Glass wrote:
> Move the FIT description into a template so that it can (later) be used
> in multiple places in the image.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
> ---
>
> Changes in v3:
> - Use HAS_FIT for the SPI node also
> - Leave fit { node open within #ifdef HAS_FIT
> - Move placement of CONFIG_SPL_PAD_TO
> - Keep the FIT filename
>
> arch/arm/dts/rockchip-u-boot.dtsi | 61 ++++++++++++++++++-------------
> 1 file changed, 35 insertions(+), 26 deletions(-)
>
> diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
> index 8aea2e6f571..460bf15e003 100644
> --- a/arch/arm/dts/rockchip-u-boot.dtsi
> +++ b/arch/arm/dts/rockchip-u-boot.dtsi
> @@ -19,6 +19,10 @@
> #define COMP "none"
> #endif
>
> +#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
> +#define HAS_FIT
> +#endif
> +
> / {
> binman: binman {
> multiple-images;
> @@ -27,28 +31,9 @@
>
> #ifdef CONFIG_SPL
> &binman {
> - simple-bin {
> - filename = "u-boot-rockchip.bin";
> - pad-byte = <0xff>;
> -
> - mkimage {
> - filename = "idbloader.img";
> - args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
> - multiple-data-files;
> -
> -#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
> - rockchip-tpl {
> - };
> -#elif defined(CONFIG_TPL)
> - u-boot-tpl {
> - };
> -#endif
> - u-boot-spl {
> - };
> - };
> -
> -#if defined(CONFIG_SPL_FIT) && (defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE))
> - fit: fit {
> +#ifdef HAS_FIT
> + common_part: template-1 {
This name may be a little bit too generic, maybe fit_template could be
more specific and matches closer to your later added spl_template.
Regards,
Jonas
> + type = "fit";
> #ifdef CONFIG_ARM64
> description = "FIT image for U-Boot with bl31 (TF-A)";
> #else
> @@ -56,10 +41,8 @@
> #endif
> #address-cells = <1>;
> fit,fdt-list = "of-list";
> - filename = "u-boot.itb";
> fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
> fit,align = <512>;
> - offset = <CONFIG_SPL_PAD_TO>;
> images {
> u-boot {
> description = "U-Boot";
> @@ -164,12 +147,38 @@
> fit,loadables;
> };
> };
> + };
> +#endif /* HAS_FIT */
> +
> + simple-bin {
> + filename = "u-boot-rockchip.bin";
> + pad-byte = <0xff>;
> +
> + mkimage {
> + filename = "idbloader.img";
> + args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
> + multiple-data-files;
> +
> +#ifdef CONFIG_ROCKCHIP_EXTERNAL_TPL
> + rockchip-tpl {
> + };
> +#elif defined(CONFIG_TPL)
> + u-boot-tpl {
> + };
> +#endif
> + u-boot-spl {
> + };
> };
> +
> +#ifdef HAS_FIT
> + fit {
> + filename = "u-boot.itb";
> + insert-template = <&common_part>;
> #else
> u-boot-img {
> +#endif
> offset = <CONFIG_SPL_PAD_TO>;
> };
> -#endif
>
> fdtmap {
> };
> @@ -196,7 +205,7 @@
> };
> };
>
> -#if defined(CONFIG_ARM64) || defined(CONFIG_SPL_OPTEE_IMAGE)
> +#ifdef HAS_FIT
> fit {
> type = "blob";
> filename = "u-boot.itb";
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 20/31] rockchip: Add symbols for spl_reloc
2025-03-28 15:35 ` [PATCH v3 20/31] rockchip: Add symbols for spl_reloc Simon Glass
@ 2025-03-28 16:29 ` Jonas Karlman
0 siblings, 0 replies; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 16:29 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Jeffy Chen, Kever Yang, Philipp Tomsich,
Richard Henderson, Tom Rini, huang lin
Hi Simon,
On 2025-03-28 16:35, Simon Glass wrote:
> Add various symbols so that this feature works as intended. This allows
> xPL to copy the relocating-jump code up to the top of memory, then use
> it to decompress and start the next phase.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v1)
>
> arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
> index 958a1b70aef..842bd4eb07f 100644
> --- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
> +++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
> @@ -25,10 +25,21 @@ SECTIONS
> __image_copy_start = ADDR(.text);
> .text : {
> . = ALIGN(8);
> + __image_copy_start = .;
__image_copy_start is defined a few lines above,
why is this duplication needed?
> CPUDIR/start.o (.text*)
> +
> + /* put relocation code all together */
> + //. = . + 0xc0;
> + _rcode_start = .;
> + *(.text.rcode)
> + *(.text.rdata)
> + _rcode_end = .;
> +
> *(.text*)
> }
>
> + _rcode_size = _rcode_end - _rcode_start;
> +
> .rodata : {
> . = ALIGN(8);
> *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
> @@ -48,6 +59,7 @@ SECTIONS
> __image_copy_end = .;
> _end = .;
> _image_binary_end = .;
> + __image_copy_end = .;
__image_copy_end is defined a few lines above,
why is this duplication needed?
Regards,
Jonas
>
> .bss ALIGN(8) : {
> __bss_start = .;
> @@ -55,6 +67,7 @@ SECTIONS
> . = ALIGN(8);
> __bss_end = .;
> }
> + __bss_size = __bss_end - __bss_start;
>
> /DISCARD/ : { *(.dynsym) }
> /DISCARD/ : { *(.dynstr*) }
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
2025-03-28 16:16 ` Jonas Karlman
@ 2025-03-28 16:51 ` Peter Robinson
2025-03-28 23:41 ` Simon Glass
2025-03-28 18:35 ` Jonas Karlman
2 siblings, 1 reply; 51+ messages in thread
From: Peter Robinson @ 2025-03-28 16:51 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Jonas Karlman, Kever Yang, Lukas Funke,
Marek Vasut, Nathan Barrett-Morrison, Oliver Gaskell,
Paul Kocialkowski, Philipp Tomsich, Quentin Schulz,
Richard Henderson, Tom Rini, Trevor Woerner, huang lin
Hi Simon,
On Fri, 28 Mar 2025 at 15:38, Simon Glass <sjg@chromium.org> wrote:
> Add support for this new phase, which runs after TPL. It determines the
> state of the machine, then selects which SPL image to use. SDRAM init is
> then done in SPL, so that it is updatable.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> - Skip spl-boot-order.c for VPL (rather than modifying it)
>
> arch/arm/include/asm/spl.h | 1 +
> arch/arm/mach-rockchip/Kconfig | 25 +++++-
> arch/arm/mach-rockchip/Makefile | 11 ++-
> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> arch/arm/mach-rockchip/spl.c | 3 +
> arch/arm/mach-rockchip/tpl.c | 2 +-
> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> common/spl/Kconfig | 1 +
> 9 files changed, 205 insertions(+), 7 deletions(-)
> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> create mode 100644 arch/arm/mach-rockchip/vpl.c
>
> diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
> index ee79a19c05c..62844d64cab 100644
> --- a/arch/arm/include/asm/spl.h
> +++ b/arch/arm/include/asm/spl.h
> @@ -30,6 +30,7 @@ enum {
> BOOT_DEVICE_XIP,
> BOOT_DEVICE_BOOTROM,
> BOOT_DEVICE_SMH,
> + BOOT_DEVICE_VBE,
> BOOT_DEVICE_NONE
> };
> #endif
> diff --git a/arch/arm/mach-rockchip/Kconfig
> b/arch/arm/mach-rockchip/Kconfig
> index 4c515593718..58ba0e0468f 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -252,13 +252,15 @@ config ROCKCHIP_RK3399
> select SPL_ATF
> select SPL_BOARD_INIT if SPL
> select SPL_LOAD_FIT
> - select SPL_CLK if SPL
> + select SPL_CLK if SPL && !VPL
> select SPL_PINCTRL if SPL
> select SPL_RAM if SPL
> select SPL_REGMAP if SPL
> select SPL_SYSCON if SPL
> select TPL_HAVE_INIT_STACK if TPL
> - select SPL_SEPARATE_BSS
> + select VPL_HAVE_INIT_STACK if VPL
> + select SPL_SEPARATE_BSS if !VPL
> + select SPL_RAW_IMAGE_SUPPORT if VPL
> select CLK
> select FIT
> select PINCTRL
> @@ -268,6 +270,7 @@ config ROCKCHIP_RK3399
> select DM_PMIC
> select DM_REGULATOR_FIXED
> select BOARD_LATE_INIT
> + select SUPPORT_VPL
> imply ARMV8_CRYPTO
> imply ARMV8_SET_SMPEN
> imply BOOTSTD_FULL
> @@ -296,13 +299,14 @@ config ROCKCHIP_RK3399
> imply TPL_LIBCOMMON_SUPPORT
> imply TPL_LIBGENERIC_SUPPORT
> imply TPL_OF_CONTROL
> - imply TPL_RAM
> + imply TPL_RAM if !VPL
> imply TPL_REGMAP
> imply TPL_ROCKCHIP_COMMON_BOARD
> imply TPL_SERIAL
> imply TPL_SYS_MALLOC_SIMPLE
> imply TPL_SYSCON
> imply TPL_TINY_MEMSET
> + imply TPL_DM_MMC if VPL
> help
> The Rockchip RK3399 is a ARM-based SoC with a dual-core
> Cortex-A72
> and quad-core Cortex-A53.
> @@ -457,7 +461,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
>
> config TPL_ROCKCHIP_BACK_TO_BROM
> bool "TPL returns to bootrom"
> - default y
> + default y if !VPL
> select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
> select TPL_BOOTROM_SUPPORT
> depends on TPL
> @@ -498,6 +502,16 @@ config ROCKCHIP_EXTERNAL_TPL
> Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin
> to
> include the external TPL in the image built by binman.
>
> +config VPL_ROCKCHIP_COMMON_BOARD
> + bool "Rockchip VPL common board file"
> + depends on VPL
> + default y
>
This should be optional and opt in, at least to begin with. I honestly
don't see what value VBE provides, and I've not seen you describe your
vision for it anyway.
> + help
> + Enable the VPL phase for rockchip, which selects which SPL/U-Boot
> + will be used on each boot. With this flow, used by Verified Boot
> for
> + Embedded (VBE), TPL is loaded by the boot ROM. Then TPL loads
> VPL,
> + VPL loads SPL and SPL loads U-Boot.
> +
> config ROCKCHIP_BOOT_MODE_REG
> hex "Rockchip boot mode flag register address"
> help
> @@ -589,6 +603,9 @@ config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
> config SPL_MMC
> default y if !SPL_ROCKCHIP_BACK_TO_BROM
>
> +config TPL_MMC
> + default y if !TPL_ROCKCHIP_BACK_TO_BROM
> +
> config ROCKCHIP_SPI_IMAGE
> bool "Build a SPI image for rockchip"
> help
> diff --git a/arch/arm/mach-rockchip/Makefile
> b/arch/arm/mach-rockchip/Makefile
> index 5e7edc99cdc..c39de1f78bb 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -8,11 +8,16 @@
> # inaccessible/protected memory (and the bootrom-helper assumes that
> # the stack-pointer is valid before switching to the U-Boot stack).
> obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
> -obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl-boot-order.o
> spl_common.o
> +obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl.o spl_common.o
> +ifndef CONFIG_VPL
> +obj-spl-$(CONFIG_SPL_ROCKCHIP_COMMON_BOARD) += spl-boot-order.o
> +endif
> obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o
> obj-tpl-$(CONFIG_TPL_ROCKCHIP_COMMON_BOARD) += tpl.o spl_common.o
> obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-board-tpl.o
>
> +obj-vpl-$(CONFIG_VPL_ROCKCHIP_COMMON_BOARD) += vpl.o
> +
> obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
>
> ifeq ($(CONFIG_XPL_BUILD)$(CONFIG_TPL_BUILD),)
> @@ -47,9 +52,11 @@ obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
> obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
> obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
>
> -# Clear out SPL objects, in case this is a TPL build
> +# Clear out SPL objects, in case this is a TPL or VPL build
> obj-spl-$(CONFIG_TPL_BUILD) =
> +obj-spl-$(CONFIG_VPL_BUILD) =
>
> # Now add SPL/TPL objects back into the main build
> obj-$(CONFIG_XPL_BUILD) += $(obj-spl-y)
> obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y)
> +obj-$(CONFIG_VPL_BUILD) += $(obj-vpl-y)
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig
> b/arch/arm/mach-rockchip/rk3399/Kconfig
> index 04a84e2f6a0..fc55b498111 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -164,6 +164,15 @@ config TPL_STACK
> config TPL_TEXT_BASE
> default 0xff8c2000
>
> +config VPL_STACK
> + default 0xff8eff00
> +
> +config VPL_TEXT_BASE
> + default 0xff8c2000
> +
> +config VPL_LDSCRIPT
> + default "arch/arm/mach-rockchip/u-boot-vpl-v8.lds"
> +
> config SPL_STACK_R_ADDR
> default 0x04000000 if !SPL_SHARES_INIT_SP_ADDR
>
> diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
> index f4d29bbdd17..305373a161c 100644
> --- a/arch/arm/mach-rockchip/spl.c
> +++ b/arch/arm/mach-rockchip/spl.c
> @@ -61,6 +61,9 @@ u32 spl_boot_device(void)
> {
> u32 boot_device = BOOT_DEVICE_MMC1;
>
> + if (IS_ENABLED(CONFIG_VPL))
> + return BOOT_DEVICE_VBE;
> +
> #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
> defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
> defined(CONFIG_TARGET_CHROMEBOOK_MINNIE) || \
> diff --git a/arch/arm/mach-rockchip/tpl.c b/arch/arm/mach-rockchip/tpl.c
> index 6b880f19f84..cc794a7dca2 100644
> --- a/arch/arm/mach-rockchip/tpl.c
> +++ b/arch/arm/mach-rockchip/tpl.c
> @@ -84,5 +84,5 @@ int board_return_to_bootrom(struct spl_image_info
> *spl_image,
>
> u32 spl_boot_device(void)
> {
> - return BOOT_DEVICE_BOOTROM;
> + return IS_ENABLED(CONFIG_VPL) ? BOOT_DEVICE_VBE :
> BOOT_DEVICE_BOOTROM;
> }
> diff --git a/arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> b/arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> new file mode 100644
> index 00000000000..d2a5cf61581
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2019
> + * Rockchip Electronics Co., Ltd
> + * Kever Yang<kever.yang@rock-chips.com>
> + *
> + * (C) Copyright 2013
> + * David Feng <fenghua@phytium.com.cn>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
> + *
> + * (C) Copyright 2010
> + * Texas Instruments, <www.ti.com>
> + * Aneesh V <aneesh@ti.com>
> + */
> +
> +OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
> "elf64-littleaarch64")
> +OUTPUT_ARCH(aarch64)
> +ENTRY(_start)
> +SECTIONS
> +{
> + . = 0x00000000;
> +
> + .text : {
> + . = ALIGN(8);
> + __image_copy_start = .;
> + CPUDIR/start.o (.text*)
> +
> + /* put relocation code all together */
> + //. = . + 0xc0;
> + _rcode_start = .;
> + *(.text.rcode)
> + *(.text.rdata)
> + _rcode_end = .;
> +
> + *(.text*)
> + }
> +
> + .rodata : {
> + . = ALIGN(8);
> + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
> + }
> +
> + .data : {
> + . = ALIGN(8);
> + *(.data*)
> + }
> +
> + __u_boot_list : {
> + . = ALIGN(8);
> + KEEP(*(SORT(__u_boot_list*)));
> + }
> +
> + .image_copy_end : {
> + . = ALIGN(8);
> + *(.__image_copy_end)
> + }
> +
> + .end : {
> + . = ALIGN(8);
> + *(.__end)
> + }
> +
> + _image_binary_end = .;
> + _end = .;
> + __image_copy_end = .;
> +
> + __bss_start = .;
> + .bss_start (NOLOAD) : {
> + . = ALIGN(8);
> + KEEP(*(.__bss_start));
> + }
> +
> + .bss (NOLOAD) : {
> + *(.bss*)
> + . = ALIGN(8);
> + }
> +
> + .bss_end (NOLOAD) : {
> + KEEP(*(.__bss_end));
> + }
> + __bss_end = .;
> + __bss_size = __bss_end - __bss_start;
> +
> + /DISCARD/ : { *(.dynsym) }
> + /DISCARD/ : { *(.dynstr*) }
> + /DISCARD/ : { *(.dynamic*) }
> + /DISCARD/ : { *(.plt*) }
> + /DISCARD/ : { *(.interp*) }
> + /DISCARD/ : { *(.gnu*) }
> +}
> +
> +#if defined(CONFIG_TPL_MAX_SIZE)
> +ASSERT(__image_copy_end - __image_copy_start < (CONFIG_TPL_MAX_SIZE), \
> + "TPL image too big");
> +#endif
> +
> +#if defined(CONFIG_TPL_BSS_MAX_SIZE)
> +ASSERT(__bss_end - __bss_start < (CONFIG_TPL_BSS_MAX_SIZE), \
> + "TPL image BSS too big");
> +#endif
> +
> +#if defined(CONFIG_TPL_MAX_FOOTPRINT)
> +ASSERT(__bss_end - _start < (CONFIG_TPL_MAX_FOOTPRINT), \
> + "TPL image plus BSS too big");
> +#endif
> diff --git a/arch/arm/mach-rockchip/vpl.c b/arch/arm/mach-rockchip/vpl.c
> new file mode 100644
> index 00000000000..55a8dabc2da
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/vpl.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2019 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <bootstage.h>
> +#include <debug_uart.h>
> +#include <dm.h>
> +#include <hang.h>
> +#include <init.h>
> +#include <log.h>
> +#include <ram.h>
> +#include <spl.h>
> +#include <version.h>
> +#include <asm/io.h>
> +#include <asm/arch-rockchip/bootrom.h>
> +#include <linux/bitops.h>
> +
> +#if CONFIG_IS_ENABLED(BANNER_PRINT)
> +#include <timestamp.h>
> +#endif
> +
> +void board_init_f(ulong dummy)
> +{
> + int ret;
> +
> +#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_VPL_SERIAL)
> + /*
> + * Debug UART can be used from here if required:
> + *
> + * debug_uart_init();
> + * printch('a');
> + * printhex8(0x1234);
> + * printascii("string");
> + */
> + debug_uart_init();
> +#ifdef CONFIG_VPL_BANNER_PRINT
> + printascii("\nU-Boot VPL " PLAIN_VERSION " (" U_BOOT_DATE " - "
> + U_BOOT_TIME ")\n");
> +#endif
> +#endif
> +
> + ret = spl_early_init();
> + if (ret) {
> + debug("spl_early_init() failed: %d\n", ret);
> + hang();
> + }
> +}
> +
> +u32 spl_boot_device(void)
> +{
> + return BOOT_DEVICE_VBE;
> +}
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index 85566385c21..4e89b17815d 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -572,6 +572,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
> default 0x200 if ARCH_SOCFPGA || ARCH_AT91
> default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
> OMAP54XX || AM33XX || AM43XX || ARCH_K3
> + default 0x800 if ARCH_ROCKCHIP && VPL
> default 0x4000 if ARCH_ROCKCHIP
> default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
> help
> --
> 2.43.0
>
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL
2025-03-28 15:35 ` [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL Simon Glass
@ 2025-03-28 17:28 ` Jonas Karlman
0 siblings, 0 replies; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 17:28 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Jeffy Chen, Kever Yang, Philipp Tomsich,
Tom Rini, huang lin
Hi Simon,
On 2025-03-28 16:35, Simon Glass wrote:
> There doesn't seem to be a good reason to use a different value for TPL
> than SPL.
This reference to SPL stack addr is still a little bit confusing, all
RK3399 boards now use a SPL stack addr in DRAM and not i SRAM.
So SPL and TPL stack addr will continue to use a different addr after
this patch.
Regards,
Jonas
> Change the TPL value, since it allows a 256-byte bloblist to
> be safely located above the stack in all phases.
>
> Note that for most boards, SDRAM init happens in TPL so the SPL stack
> ends up in DRAM, at address CONFIG_SPL_STACK_R_ADDR.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Reword commit to mention comments from Jonas
>
> arch/arm/mach-rockchip/rk3399/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
> index fc55b498111..8064b6286fc 100644
> --- a/arch/arm/mach-rockchip/rk3399/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3399/Kconfig
> @@ -159,7 +159,7 @@ config TPL_LDSCRIPT
> default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
>
> config TPL_STACK
> - default 0xff8effff
> + default 0xff8eff00
>
> config TPL_TEXT_BASE
> default 0xff8c2000
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too
2025-03-28 15:34 ` [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too Simon Glass
@ 2025-03-28 18:19 ` Jonas Karlman
2025-03-28 18:25 ` Simon Glass
0 siblings, 1 reply; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 18:19 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Jeffy Chen, Kever Yang, Philipp Tomsich,
Tom Rini, huang lin
Hi Simon,
Patch 05 to 10 should still be split out to a separate series.
They help fix an issue that already have a different conflicting patch
on mailing list [1].
The request to split these patches out was to help/ease work for other
U-Boot developers such as myself. I have a follow up patch to split out
HASH and to add support for using crc32 as hash algo, for an upcoming
RK3506 series. And I have already send a separate series to add RAM boot
that depends on the fit-template added in patch 08, see [2].
Still keeping these rockchip: dts: patches that are ready to be merged
in a series that in v3 still does not apply to master or next is
disappointing. And because it is not possible to apply this series, a
proper review and testing has not yet been done, something that is just
delaying your work more than it has to.
I can send these patches as a separate series if you do not have time to
split these patches out to a separate series, and would also include my
HASH crc32 patch.
[1] http://lore.kernel.org/r/20250220-has_rom-u-boot-rockchip-spi-bin-v2-3-d1768ee87808@cherry.de
[2] http://lore.kernel.org/r/20250220231358.432367-3-jonas@kwiboo.se
Regards,
Jonas
On 2025-03-28 16:34, Simon Glass wrote:
> At present simple-bin-spi relies on the u-boot.itb file created by the
> simple-bin image. Use the template to avoid this, since Binman may
> change to process images in parallel in the future.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
> Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> ---
>
> Changes in v3:
> - Keep the filename for the SPI FIT
>
> arch/arm/dts/rockchip-u-boot.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
> index 1e4d6f71123..fb304540787 100644
> --- a/arch/arm/dts/rockchip-u-boot.dtsi
> +++ b/arch/arm/dts/rockchip-u-boot.dtsi
> @@ -207,8 +207,8 @@
>
> #ifdef HAS_FIT
> fit {
> - type = "blob";
> filename = "u-boot.itb";
> + insert-template = <&common_part>;
> #else
> u-boot-img {
> #endif
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too
2025-03-28 18:19 ` Jonas Karlman
@ 2025-03-28 18:25 ` Simon Glass
0 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 18:25 UTC (permalink / raw)
To: Jonas Karlman
Cc: U-Boot Mailing List, Jeffy Chen, Kever Yang, Philipp Tomsich,
Tom Rini, huang lin
Hi Jonas,
On Fri, 28 Mar 2025 at 12:19, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Simon,
>
> Patch 05 to 10 should still be split out to a separate series.
>
> They help fix an issue that already have a different conflicting patch
> on mailing list [1].
>
> The request to split these patches out was to help/ease work for other
> U-Boot developers such as myself. I have a follow up patch to split out
> HASH and to add support for using crc32 as hash algo, for an upcoming
> RK3506 series. And I have already send a separate series to add RAM boot
> that depends on the fit-template added in patch 08, see [2].
>
> Still keeping these rockchip: dts: patches that are ready to be merged
> in a series that in v3 still does not apply to master or next is
> disappointing. And because it is not possible to apply this series, a
> proper review and testing has not yet been done, something that is just
> delaying your work more than it has to.
>
> I can send these patches as a separate series if you do not have time to
> split these patches out to a separate series, and would also include my
> HASH crc32 patch.
Yes, please go ahead and thank you. You might also consider the
skip-at-start patches at the end.
I have several rockchip boards in my lab, so I'm pretty confident
about the general changes. But perhaps one board is different from the
others. I doubt anyone has all boards.
Regards,
SImon
>
> [1] http://lore.kernel.org/r/20250220-has_rom-u-boot-rockchip-spi-bin-v2-3-d1768ee87808@cherry.de
> [2] http://lore.kernel.org/r/20250220231358.432367-3-jonas@kwiboo.se
>
> Regards,
> Jonas
>
> On 2025-03-28 16:34, Simon Glass wrote:
> > At present simple-bin-spi relies on the u-boot.itb file created by the
> > simple-bin image. Use the template to avoid this, since Binman may
> > change to process images in parallel in the future.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
> > Suggested-by: Jonas Karlman <jonas@kwiboo.se>
> > ---
> >
> > Changes in v3:
> > - Keep the filename for the SPI FIT
> >
> > arch/arm/dts/rockchip-u-boot.dtsi | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/dts/rockchip-u-boot.dtsi b/arch/arm/dts/rockchip-u-boot.dtsi
> > index 1e4d6f71123..fb304540787 100644
> > --- a/arch/arm/dts/rockchip-u-boot.dtsi
> > +++ b/arch/arm/dts/rockchip-u-boot.dtsi
> > @@ -207,8 +207,8 @@
> >
> > #ifdef HAS_FIT
> > fit {
> > - type = "blob";
> > filename = "u-boot.itb";
> > + insert-template = <&common_part>;
> > #else
> > u-boot-img {
> > #endif
>
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
2025-03-28 16:16 ` Jonas Karlman
2025-03-28 16:51 ` Peter Robinson
@ 2025-03-28 18:35 ` Jonas Karlman
2 siblings, 0 replies; 51+ messages in thread
From: Jonas Karlman @ 2025-03-28 18:35 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Simon,
On 2025-03-28 16:34, Simon Glass wrote:
> Add support for this new phase, which runs after TPL. It determines the
> state of the machine, then selects which SPL image to use. SDRAM init is
> then done in SPL, so that it is updatable.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> - Skip spl-boot-order.c for VPL (rather than modifying it)
[snip]
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 4c515593718..58ba0e0468f 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -252,13 +252,15 @@ config ROCKCHIP_RK3399
> select SPL_ATF
> select SPL_BOARD_INIT if SPL
> select SPL_LOAD_FIT
> - select SPL_CLK if SPL
> + select SPL_CLK if SPL && !VPL
> select SPL_PINCTRL if SPL
> select SPL_RAM if SPL
> select SPL_REGMAP if SPL
> select SPL_SYSCON if SPL
> select TPL_HAVE_INIT_STACK if TPL
> - select SPL_SEPARATE_BSS
> + select VPL_HAVE_INIT_STACK if VPL
> + select SPL_SEPARATE_BSS if !VPL
SPL_SEPARATE_BSS is already implied by ARM64, so we could probably just
drop the select SPL_SEPARATE_BSS here.
> + select SPL_RAW_IMAGE_SUPPORT if VPL
We have this disabled in all RK3399 defconfigs so this can probably be
dropped. We really do not want this accidentally enabled for !VPL.
> select CLK
> select FIT
> select PINCTRL
> @@ -268,6 +270,7 @@ config ROCKCHIP_RK3399
> select DM_PMIC
> select DM_REGULATOR_FIXED
> select BOARD_LATE_INIT
> + select SUPPORT_VPL
Probably better to keep this next to the other SUPPORT_xPL.
> imply ARMV8_CRYPTO
> imply ARMV8_SET_SMPEN
> imply BOOTSTD_FULL
> @@ -296,13 +299,14 @@ config ROCKCHIP_RK3399
> imply TPL_LIBCOMMON_SUPPORT
> imply TPL_LIBGENERIC_SUPPORT
> imply TPL_OF_CONTROL
> - imply TPL_RAM
> + imply TPL_RAM if !VPL
> imply TPL_REGMAP
> imply TPL_ROCKCHIP_COMMON_BOARD
> imply TPL_SERIAL
> imply TPL_SYS_MALLOC_SIMPLE
> imply TPL_SYSCON
> imply TPL_TINY_MEMSET
> + imply TPL_DM_MMC if VPL
Please try to keep the imply statements in alphabetical order after the
commit d8ff591d9263 ("rockchip: rk3399: Sort imply statements
alphabetically").
Regards,
Jonas
> help
> The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
> and quad-core Cortex-A53.
[snip]
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader"
2025-03-28 16:13 ` Tom Rini
@ 2025-03-28 23:38 ` Simon Glass
0 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 23:38 UTC (permalink / raw)
To: Tom Rini; +Cc: Raymond Mao, U-Boot Mailing List, Levi Yun, Patrick Rudolph
Hi Tom, Raymond,
On Fri, 28 Mar 2025 at 10:13, Tom Rini <trini@konsulko.com> wrote:
>
> On Fri, Mar 28, 2025 at 11:50:14AM -0400, Raymond Mao wrote:
> > Hi Simon,
> >
> >
> > On Fri, 28 Mar 2025 at 11:36, Simon Glass <sjg@chromium.org> wrote:
> > >
> > > The logic of this has become too confusing.
> > >
> > > The primary issue with the patch is that U-Boot needs to set up a
> > > bloblist in the first phase where BLOBLIST is enabled. Subsequent
> > > phases can then use that bloblist.
> > >
> > > But the first phase of U-Boot cannot assume that one exists.
> > >
> > > Reverting this commit seems like a better starting point for getting
> > > things working for all use-cases.
> > >
> > > Note: The work to tidy this up is apparently underway. For this series,
> > > a revert is the easiest path.
> > >
> > > This reverts commit 66131310d8ff1ba228f989b41bd8812f43be41c3.
> > >
> > > https://lore.kernel.org/u-boot/CAPnjgZ3hMHtiH=f5ZKXNniOfV_-vFryq1Gn7QZ5hKU8Wjo8igw@mail.gmail.com/
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > (no changes since v1)
> > >
> >
> > Is this same as something we discussed in the thread below?
> > https://lore.kernel.org/u-boot/20250205015606.2686149-29-sjg@chromium.org/
> >
> > I am a bit confused since I think we had agreed that it should not be reverted.
>
> Yes, it is extremely frustrating to have posted both this:
> https://patchwork.ozlabs.org/project/uboot/list/?series=450425&state=*
> as the first pass at doing what was agreed on the path forward while
> also posting this thread which cannot be against either next nor next
> with the above applied and so isn't worth anyone elses time. I suspect
> this thread also includes various rockchip patches that were requested
> to be broken out and posted by themselves instead.
Please check the cover letter where I have covered that. If the
bloblist series I sent lands, then yes, I can drop these final
patches.
Let's not talk about frustration where bloblist is concerned, given
that my boards were broken for a *year* because of all this.
Regards,
Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 16:16 ` Jonas Karlman
@ 2025-03-28 23:40 ` Simon Glass
2025-03-29 0:07 ` Tom Rini
2025-03-29 16:46 ` Jonas Karlman
0 siblings, 2 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 23:40 UTC (permalink / raw)
To: Jonas Karlman
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Tom,
On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Simon,
>
> On 2025-03-28 16:34, Simon Glass wrote:
> > Add support for this new phase, which runs after TPL. It determines the
> > state of the machine, then selects which SPL image to use. SDRAM init is
> > then done in SPL, so that it is updatable.
> >
> > Signed-off-by: Simon Glass <sjg@chromium.org>
> > ---
> >
> > (no changes since v2)
> >
> > Changes in v2:
> > - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> > - Skip spl-boot-order.c for VPL (rather than modifying it)
> >
> > arch/arm/include/asm/spl.h | 1 +
> > arch/arm/mach-rockchip/Kconfig | 25 +++++-
> > arch/arm/mach-rockchip/Makefile | 11 ++-
> > arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> > arch/arm/mach-rockchip/spl.c | 3 +
> > arch/arm/mach-rockchip/tpl.c | 2 +-
> > arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> > arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> > common/spl/Kconfig | 1 +
> > 9 files changed, 205 insertions(+), 7 deletions(-)
> > create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> > create mode 100644 arch/arm/mach-rockchip/vpl.c
> >
>
> This patch and therefore this series does not apply to the next branch.
>
> Are there any depends that are missing or are you only testing based on
> your own fork?
Until we are ready to apply things, yes I am using the sjg tree. See
the tags in the cover letters of patches I send. For this one it is:
base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
branch: vbi3
So no, there is nothing else that this series depends on and if you
can review it I can send a PR for Tom for -next one all necessary
changes are made.
Regards,
Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 16:51 ` Peter Robinson
@ 2025-03-28 23:41 ` Simon Glass
0 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-03-28 23:41 UTC (permalink / raw)
To: Peter Robinson
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Jonas Karlman, Kever Yang, Lukas Funke,
Marek Vasut, Nathan Barrett-Morrison, Oliver Gaskell,
Paul Kocialkowski, Philipp Tomsich, Quentin Schulz,
Richard Henderson, Tom Rini, Trevor Woerner, huang lin
Hi Peter,
On Fri, 28 Mar 2025 at 10:51, Peter Robinson <pbrobinson@gmail.com> wrote:
>
> Hi Simon,
>
> On Fri, 28 Mar 2025 at 15:38, Simon Glass <sjg@chromium.org> wrote:
>>
>> Add support for this new phase, which runs after TPL. It determines the
>> state of the machine, then selects which SPL image to use. SDRAM init is
>> then done in SPL, so that it is updatable.
>>
>> Signed-off-by: Simon Glass <sjg@chromium.org>
>> ---
>>
>> (no changes since v2)
>>
>> Changes in v2:
>> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
>> - Skip spl-boot-order.c for VPL (rather than modifying it)
>>
>> arch/arm/include/asm/spl.h | 1 +
>> arch/arm/mach-rockchip/Kconfig | 25 +++++-
>> arch/arm/mach-rockchip/Makefile | 11 ++-
>> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
>> arch/arm/mach-rockchip/spl.c | 3 +
>> arch/arm/mach-rockchip/tpl.c | 2 +-
>> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
>> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
>> common/spl/Kconfig | 1 +
>> 9 files changed, 205 insertions(+), 7 deletions(-)
>> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
>> create mode 100644 arch/arm/mach-rockchip/vpl.c
>>
>> diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
>> index ee79a19c05c..62844d64cab 100644
>> --- a/arch/arm/include/asm/spl.h
>> +++ b/arch/arm/include/asm/spl.h
>> @@ -30,6 +30,7 @@ enum {
>> BOOT_DEVICE_XIP,
>> BOOT_DEVICE_BOOTROM,
>> BOOT_DEVICE_SMH,
>> + BOOT_DEVICE_VBE,
>> BOOT_DEVICE_NONE
>> };
>> #endif
>> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
>> index 4c515593718..58ba0e0468f 100644
>> --- a/arch/arm/mach-rockchip/Kconfig
>> +++ b/arch/arm/mach-rockchip/Kconfig
>> @@ -252,13 +252,15 @@ config ROCKCHIP_RK3399
>> select SPL_ATF
>> select SPL_BOARD_INIT if SPL
>> select SPL_LOAD_FIT
>> - select SPL_CLK if SPL
>> + select SPL_CLK if SPL && !VPL
>> select SPL_PINCTRL if SPL
>> select SPL_RAM if SPL
>> select SPL_REGMAP if SPL
>> select SPL_SYSCON if SPL
>> select TPL_HAVE_INIT_STACK if TPL
>> - select SPL_SEPARATE_BSS
>> + select VPL_HAVE_INIT_STACK if VPL
>> + select SPL_SEPARATE_BSS if !VPL
>> + select SPL_RAW_IMAGE_SUPPORT if VPL
>> select CLK
>> select FIT
>> select PINCTRL
>> @@ -268,6 +270,7 @@ config ROCKCHIP_RK3399
>> select DM_PMIC
>> select DM_REGULATOR_FIXED
>> select BOARD_LATE_INIT
>> + select SUPPORT_VPL
>> imply ARMV8_CRYPTO
>> imply ARMV8_SET_SMPEN
>> imply BOOTSTD_FULL
>> @@ -296,13 +299,14 @@ config ROCKCHIP_RK3399
>> imply TPL_LIBCOMMON_SUPPORT
>> imply TPL_LIBGENERIC_SUPPORT
>> imply TPL_OF_CONTROL
>> - imply TPL_RAM
>> + imply TPL_RAM if !VPL
>> imply TPL_REGMAP
>> imply TPL_ROCKCHIP_COMMON_BOARD
>> imply TPL_SERIAL
>> imply TPL_SYS_MALLOC_SIMPLE
>> imply TPL_SYSCON
>> imply TPL_TINY_MEMSET
>> + imply TPL_DM_MMC if VPL
>> help
>> The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
>> and quad-core Cortex-A53.
>> @@ -457,7 +461,7 @@ config SPL_ROCKCHIP_BACK_TO_BROM
>>
>> config TPL_ROCKCHIP_BACK_TO_BROM
>> bool "TPL returns to bootrom"
>> - default y
>> + default y if !VPL
>> select ROCKCHIP_BROM_HELPER if !ROCKCHIP_RK3066
>> select TPL_BOOTROM_SUPPORT
>> depends on TPL
>> @@ -498,6 +502,16 @@ config ROCKCHIP_EXTERNAL_TPL
>> Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
>> include the external TPL in the image built by binman.
>>
>> +config VPL_ROCKCHIP_COMMON_BOARD
>> + bool "Rockchip VPL common board file"
>> + depends on VPL
>> + default y
>
>
> This should be optional and opt in, at least to begin with.
Yes, agreed. In this case, it depends on VPL, which is only enabled
for the new board being added here.
> I honestly don't see what value VBE provides, and I've not seen you describe your vision for it anyway.
Some docs:
https://docs.u-boot.org/en/latest/develop/vbe.html
Talk at osfc: https://elinux.org/Boot_Loaders#U-Boot
Alex Graf was kind enough to do another one at Embedded World 2022 but
I don't have a link.
If you are using UEFI, it won't provide any benefits.
Regards,
Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 23:40 ` Simon Glass
@ 2025-03-29 0:07 ` Tom Rini
2025-03-29 16:46 ` Jonas Karlman
1 sibling, 0 replies; 51+ messages in thread
From: Tom Rini @ 2025-03-29 0:07 UTC (permalink / raw)
To: Simon Glass
Cc: Jonas Karlman, U-Boot Mailing List, Dragan Simic, Greg Malysa,
Jeffy Chen, Jerome Forissier, Kever Yang, Lukas Funke,
Marek Vasut, Nathan Barrett-Morrison, Oliver Gaskell,
Paul Kocialkowski, Philipp Tomsich, Quentin Schulz,
Richard Henderson, Trevor Woerner, huang lin
[-- Attachment #1: Type: text/plain, Size: 2362 bytes --]
On Fri, Mar 28, 2025 at 11:40:01PM +0000, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
> >
> > Hi Simon,
> >
> > On 2025-03-28 16:34, Simon Glass wrote:
> > > Add support for this new phase, which runs after TPL. It determines the
> > > state of the machine, then selects which SPL image to use. SDRAM init is
> > > then done in SPL, so that it is updatable.
> > >
> > > Signed-off-by: Simon Glass <sjg@chromium.org>
> > > ---
> > >
> > > (no changes since v2)
> > >
> > > Changes in v2:
> > > - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> > > - Skip spl-boot-order.c for VPL (rather than modifying it)
> > >
> > > arch/arm/include/asm/spl.h | 1 +
> > > arch/arm/mach-rockchip/Kconfig | 25 +++++-
> > > arch/arm/mach-rockchip/Makefile | 11 ++-
> > > arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> > > arch/arm/mach-rockchip/spl.c | 3 +
> > > arch/arm/mach-rockchip/tpl.c | 2 +-
> > > arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> > > arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> > > common/spl/Kconfig | 1 +
> > > 9 files changed, 205 insertions(+), 7 deletions(-)
> > > create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> > > create mode 100644 arch/arm/mach-rockchip/vpl.c
> > >
> >
> > This patch and therefore this series does not apply to the next branch.
> >
> > Are there any depends that are missing or are you only testing based on
> > your own fork?
>
> Until we are ready to apply things, yes I am using the sjg tree. See
> the tags in the cover letters of patches I send. For this one it is:
>
> base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
> branch: vbi3
>
> So no, there is nothing else that this series depends on and if you
> can review it I can send a PR for Tom for -next one all necessary
> changes are made.
If you want something to be reviewed you need to base it on next and not
your tree. Your experiment with posting stuff on top of your own tree is
already making other members of the community have trouble reviewing
your code and they should not be expected to look in your own tree to
have to test changes as that's wasting their time.
--
Tom
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-28 23:40 ` Simon Glass
2025-03-29 0:07 ` Tom Rini
@ 2025-03-29 16:46 ` Jonas Karlman
2025-04-01 15:42 ` Simon Glass
1 sibling, 1 reply; 51+ messages in thread
From: Jonas Karlman @ 2025-03-29 16:46 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Simon,
On 2025-03-29 00:40, Simon Glass wrote:
> Hi Tom,
>
> On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> Hi Simon,
>>
>> On 2025-03-28 16:34, Simon Glass wrote:
>>> Add support for this new phase, which runs after TPL. It determines the
>>> state of the machine, then selects which SPL image to use. SDRAM init is
>>> then done in SPL, so that it is updatable.
>>>
>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>> ---
>>>
>>> (no changes since v2)
>>>
>>> Changes in v2:
>>> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
>>> - Skip spl-boot-order.c for VPL (rather than modifying it)
>>>
>>> arch/arm/include/asm/spl.h | 1 +
>>> arch/arm/mach-rockchip/Kconfig | 25 +++++-
>>> arch/arm/mach-rockchip/Makefile | 11 ++-
>>> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
>>> arch/arm/mach-rockchip/spl.c | 3 +
>>> arch/arm/mach-rockchip/tpl.c | 2 +-
>>> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
>>> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
>>> common/spl/Kconfig | 1 +
>>> 9 files changed, 205 insertions(+), 7 deletions(-)
>>> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
>>> create mode 100644 arch/arm/mach-rockchip/vpl.c
>>>
>>
>> This patch and therefore this series does not apply to the next branch.
>>
>> Are there any depends that are missing or are you only testing based on
>> your own fork?
>
> Until we are ready to apply things, yes I am using the sjg tree. See
> the tags in the cover letters of patches I send. For this one it is:
>
> base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
> branch: vbi3
This base-commit does not even exist in your vbi3 branch :-/
>
> So no, there is nothing else that this series depends on and if you
> can review it I can send a PR for Tom for -next one all necessary
> changes are made.
Sorry, this does not help, my main concern is testing that this does not
break or affect anything for the remaining Rockchip boards. Something
that is hard to test and validate when patches do not even apply to any
of the mainline master or next branches.
Sending patches based on a tree that has diverged with around 677 files
changed, 20072 insertions(+), 17023 deletions(-), if my git fu is
correct, and then expect us to test based on this diverged tree does not
help with gaining confidence in this series.
I can understand keeping a personal tree that will diverge at times,
i.e. my personal tree has ~120-150 patches on top of mainline master.
However, I always try to keep my work-in-progress branches rebased on
top of master or next.
For v4, please send a series based on mainline master or next branch,
as stated in "General Patch Submission Rules" [1] in the U-Boot docs.
If the series has some depends, I suggest you also publish a branch
to a public repo with any limited depends applied on top of master or
next along with the patches in your series.
[1] https://docs.u-boot.org/en/latest/develop/sending_patches.html
Regards,
Jonas
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-03-29 16:46 ` Jonas Karlman
@ 2025-04-01 15:42 ` Simon Glass
2025-04-01 17:27 ` Jonas Karlman
0 siblings, 1 reply; 51+ messages in thread
From: Simon Glass @ 2025-04-01 15:42 UTC (permalink / raw)
To: Jonas Karlman
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Jonas,
On Sun, 30 Mar 2025 at 05:46, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Simon,
>
> On 2025-03-29 00:40, Simon Glass wrote:
> > Hi Tom,
> >
> > On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>
> >> Hi Simon,
> >>
> >> On 2025-03-28 16:34, Simon Glass wrote:
> >>> Add support for this new phase, which runs after TPL. It determines the
> >>> state of the machine, then selects which SPL image to use. SDRAM init is
> >>> then done in SPL, so that it is updatable.
> >>>
> >>> Signed-off-by: Simon Glass <sjg@chromium.org>
> >>> ---
> >>>
> >>> (no changes since v2)
> >>>
> >>> Changes in v2:
> >>> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> >>> - Skip spl-boot-order.c for VPL (rather than modifying it)
> >>>
> >>> arch/arm/include/asm/spl.h | 1 +
> >>> arch/arm/mach-rockchip/Kconfig | 25 +++++-
> >>> arch/arm/mach-rockchip/Makefile | 11 ++-
> >>> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> >>> arch/arm/mach-rockchip/spl.c | 3 +
> >>> arch/arm/mach-rockchip/tpl.c | 2 +-
> >>> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> >>> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> >>> common/spl/Kconfig | 1 +
> >>> 9 files changed, 205 insertions(+), 7 deletions(-)
> >>> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> >>> create mode 100644 arch/arm/mach-rockchip/vpl.c
> >>>
> >>
> >> This patch and therefore this series does not apply to the next branch.
> >>
> >> Are there any depends that are missing or are you only testing based on
> >> your own fork?
> >
> > Until we are ready to apply things, yes I am using the sjg tree. See
> > the tags in the cover letters of patches I send. For this one it is:
> >
> > base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
> > branch: vbi3
>
> This base-commit does not even exist in your vbi3 branch :-/
Are you sure? The base commit works fine for me:
$ pe 3f76d803db9b500f43bc534465945a8d2836bb3e
3f76d803db9 (ci/master) Merge branch 'ci' into 'master'
d07049b9f28 (el/ci) arm: Support a separate stack for VPL
abfff044f26 spl: Use CONFIG_VAL() to obtain the SPL stack
7a032a125f5 spl: Add an SPL_HAVE_INIT_STACK option
8d319b22019 tpl: Rename TPL_NEEDS_SEPARATE_STACK to TPL_HAVE_INIT_STACK
794124b3258 Merge branch 'ci' into 'master'
The branch name is a local branch, not necessarily pushed anywhere. Is
there some better terminology that I should use there? Perhaps
'local-branch' ?
>
> >
> > So no, there is nothing else that this series depends on and if you
> > can review it I can send a PR for Tom for -next one all necessary
> > changes are made.
>
> Sorry, this does not help, my main concern is testing that this does not
> break or affect anything for the remaining Rockchip boards. Something
> that is hard to test and validate when patches do not even apply to any
> of the mainline master or next branches.
>
> Sending patches based on a tree that has diverged with around 677 files
> changed, 20072 insertions(+), 17023 deletions(-), if my git fu is
> correct, and then expect us to test based on this diverged tree does not
> help with gaining confidence in this series.
>
> I can understand keeping a personal tree that will diverge at times,
> i.e. my personal tree has ~120-150 patches on top of mainline master.
> However, I always try to keep my work-in-progress branches rebased on
> top of master or next.
>
> For v4, please send a series based on mainline master or next branch,
> as stated in "General Patch Submission Rules" [1] in the U-Boot docs.
>
> If the series has some depends, I suggest you also publish a branch
> to a public repo with any limited depends applied on top of master or
> next along with the patches in your series.
For now I am going to wait until you pick up your clean-up of part of
my series. Then I can pull that in any try to send the final VBE
series again.
I haven't had any rockchip patches rejected, so we should be able to
resolve this.
>
> [1] https://docs.u-boot.org/en/latest/develop/sending_patches.html
Regards,
Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-04-01 15:42 ` Simon Glass
@ 2025-04-01 17:27 ` Jonas Karlman
2025-04-01 17:56 ` Simon Glass
0 siblings, 1 reply; 51+ messages in thread
From: Jonas Karlman @ 2025-04-01 17:27 UTC (permalink / raw)
To: Simon Glass
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Simon,
On 2025-04-01 17:42, Simon Glass wrote:
> Hi Jonas,
>
> On Sun, 30 Mar 2025 at 05:46, Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> Hi Simon,
>>
>> On 2025-03-29 00:40, Simon Glass wrote:
>>> Hi Tom,
>>>
>>> On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
>>>>
>>>> Hi Simon,
>>>>
>>>> On 2025-03-28 16:34, Simon Glass wrote:
>>>>> Add support for this new phase, which runs after TPL. It determines the
>>>>> state of the machine, then selects which SPL image to use. SDRAM init is
>>>>> then done in SPL, so that it is updatable.
>>>>>
>>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
>>>>> ---
>>>>>
>>>>> (no changes since v2)
>>>>>
>>>>> Changes in v2:
>>>>> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
>>>>> - Skip spl-boot-order.c for VPL (rather than modifying it)
>>>>>
>>>>> arch/arm/include/asm/spl.h | 1 +
>>>>> arch/arm/mach-rockchip/Kconfig | 25 +++++-
>>>>> arch/arm/mach-rockchip/Makefile | 11 ++-
>>>>> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
>>>>> arch/arm/mach-rockchip/spl.c | 3 +
>>>>> arch/arm/mach-rockchip/tpl.c | 2 +-
>>>>> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
>>>>> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
>>>>> common/spl/Kconfig | 1 +
>>>>> 9 files changed, 205 insertions(+), 7 deletions(-)
>>>>> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
>>>>> create mode 100644 arch/arm/mach-rockchip/vpl.c
>>>>>
>>>>
>>>> This patch and therefore this series does not apply to the next branch.
>>>>
>>>> Are there any depends that are missing or are you only testing based on
>>>> your own fork?
>>>
>>> Until we are ready to apply things, yes I am using the sjg tree. See
>>> the tags in the cover letters of patches I send. For this one it is:
>>>
>>> base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
>>> branch: vbi3
>>
>> This base-commit does not even exist in your vbi3 branch :-/
>
> Are you sure? The base commit works fine for me:
>
> $ pe 3f76d803db9b500f43bc534465945a8d2836bb3e
> 3f76d803db9 (ci/master) Merge branch 'ci' into 'master'
> d07049b9f28 (el/ci) arm: Support a separate stack for VPL
> abfff044f26 spl: Use CONFIG_VAL() to obtain the SPL stack
> 7a032a125f5 spl: Add an SPL_HAVE_INIT_STACK option
> 8d319b22019 tpl: Rename TPL_NEEDS_SEPARATE_STACK to TPL_HAVE_INIT_STACK
> 794124b3258 Merge branch 'ci' into 'master'
>
> The branch name is a local branch, not necessarily pushed anywhere. Is
> there some better terminology that I should use there? Perhaps
> 'local-branch' ?
Probably, I did a git fetch of you public vbi3 branch:
git fetch https://sjg.u-boot.org/u-boot/u-boot.git vbi3
And that did not include 3f76d803db9b500f43bc534465945a8d2836bb3e:
fatal: bad object 3f76d803db9b500f43bc534465945a8d2836bb3e
So yes, if you keep a public branch with same name as you say in your
patches, I would expect it to be somewhat up to date.
>
>>
>>>
>>> So no, there is nothing else that this series depends on and if you
>>> can review it I can send a PR for Tom for -next one all necessary
>>> changes are made.
>>
>> Sorry, this does not help, my main concern is testing that this does not
>> break or affect anything for the remaining Rockchip boards. Something
>> that is hard to test and validate when patches do not even apply to any
>> of the mainline master or next branches.
>>
>> Sending patches based on a tree that has diverged with around 677 files
>> changed, 20072 insertions(+), 17023 deletions(-), if my git fu is
>> correct, and then expect us to test based on this diverged tree does not
>> help with gaining confidence in this series.
>>
>> I can understand keeping a personal tree that will diverge at times,
>> i.e. my personal tree has ~120-150 patches on top of mainline master.
>> However, I always try to keep my work-in-progress branches rebased on
>> top of master or next.
>>
>> For v4, please send a series based on mainline master or next branch,
>> as stated in "General Patch Submission Rules" [1] in the U-Boot docs.
>>
>> If the series has some depends, I suggest you also publish a branch
>> to a public repo with any limited depends applied on top of master or
>> next along with the patches in your series.
>
> For now I am going to wait until you pick up your clean-up of part of
> my series. Then I can pull that in any try to send the final VBE
> series again.
I sent out a "rockchip: binman: Use a template for FIT and other
improvements" series [2] that picked up some of your rockchip binman
image related patches.
[2] https://patchwork.ozlabs.org/cover/2066701/
>
> I haven't had any rockchip patches rejected, so we should be able to
> resolve this.
They have not been properly reviewed (or tested) yet, as they have never
applied cleanly on any mainline tree, with repeated requests to fix that.
For me to review something, I want to be able to run the code, and run it
on a code base as close as possible to where it intends to be merged.
E.g. v1 was broken and had hidden depends that you had applied to your
personal tree, and only later was sent out and now merged into mainline.
I have some other concerns to validate, but have waited on a version
that can be applied before continuing a review. Please consider this a
NAK until it can properly be tested (i.e. reviewed) using a branch with
a minimal diff to mainline master or next.
Regards,
Jonas
>
>>
>> [1] https://docs.u-boot.org/en/latest/develop/sending_patches.html
>
> Regards,
> Simon
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399
2025-04-01 17:27 ` Jonas Karlman
@ 2025-04-01 17:56 ` Simon Glass
0 siblings, 0 replies; 51+ messages in thread
From: Simon Glass @ 2025-04-01 17:56 UTC (permalink / raw)
To: Jonas Karlman
Cc: U-Boot Mailing List, Dragan Simic, Greg Malysa, Jeffy Chen,
Jerome Forissier, Kever Yang, Lukas Funke, Marek Vasut,
Nathan Barrett-Morrison, Oliver Gaskell, Paul Kocialkowski,
Philipp Tomsich, Quentin Schulz, Richard Henderson, Tom Rini,
Trevor Woerner, huang lin
Hi Jonas,
On Wed, 2 Apr 2025 at 06:27, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Simon,
>
> On 2025-04-01 17:42, Simon Glass wrote:
> > Hi Jonas,
> >
> > On Sun, 30 Mar 2025 at 05:46, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>
> >> Hi Simon,
> >>
> >> On 2025-03-29 00:40, Simon Glass wrote:
> >>> Hi Tom,
> >>>
> >>> On Fri, 28 Mar 2025 at 10:16, Jonas Karlman <jonas@kwiboo.se> wrote:
> >>>>
> >>>> Hi Simon,
> >>>>
> >>>> On 2025-03-28 16:34, Simon Glass wrote:
> >>>>> Add support for this new phase, which runs after TPL. It determines the
> >>>>> state of the machine, then selects which SPL image to use. SDRAM init is
> >>>>> then done in SPL, so that it is updatable.
> >>>>>
> >>>>> Signed-off-by: Simon Glass <sjg@chromium.org>
> >>>>> ---
> >>>>>
> >>>>> (no changes since v2)
> >>>>>
> >>>>> Changes in v2:
> >>>>> - Rewrite help for VPL_ROCKCHIP_COMMON_BOARD
> >>>>> - Skip spl-boot-order.c for VPL (rather than modifying it)
> >>>>>
> >>>>> arch/arm/include/asm/spl.h | 1 +
> >>>>> arch/arm/mach-rockchip/Kconfig | 25 +++++-
> >>>>> arch/arm/mach-rockchip/Makefile | 11 ++-
> >>>>> arch/arm/mach-rockchip/rk3399/Kconfig | 9 ++
> >>>>> arch/arm/mach-rockchip/spl.c | 3 +
> >>>>> arch/arm/mach-rockchip/tpl.c | 2 +-
> >>>>> arch/arm/mach-rockchip/u-boot-vpl-v8.lds | 107 +++++++++++++++++++++++
> >>>>> arch/arm/mach-rockchip/vpl.c | 53 +++++++++++
> >>>>> common/spl/Kconfig | 1 +
> >>>>> 9 files changed, 205 insertions(+), 7 deletions(-)
> >>>>> create mode 100644 arch/arm/mach-rockchip/u-boot-vpl-v8.lds
> >>>>> create mode 100644 arch/arm/mach-rockchip/vpl.c
> >>>>>
> >>>>
> >>>> This patch and therefore this series does not apply to the next branch.
> >>>>
> >>>> Are there any depends that are missing or are you only testing based on
> >>>> your own fork?
> >>>
> >>> Until we are ready to apply things, yes I am using the sjg tree. See
> >>> the tags in the cover letters of patches I send. For this one it is:
> >>>
> >>> base-commit: 3f76d803db9b500f43bc534465945a8d2836bb3e
> >>> branch: vbi3
> >>
> >> This base-commit does not even exist in your vbi3 branch :-/
> >
> > Are you sure? The base commit works fine for me:
> >
> > $ pe 3f76d803db9b500f43bc534465945a8d2836bb3e
> > 3f76d803db9 (ci/master) Merge branch 'ci' into 'master'
> > d07049b9f28 (el/ci) arm: Support a separate stack for VPL
> > abfff044f26 spl: Use CONFIG_VAL() to obtain the SPL stack
> > 7a032a125f5 spl: Add an SPL_HAVE_INIT_STACK option
> > 8d319b22019 tpl: Rename TPL_NEEDS_SEPARATE_STACK to TPL_HAVE_INIT_STACK
> > 794124b3258 Merge branch 'ci' into 'master'
> >
> > The branch name is a local branch, not necessarily pushed anywhere. Is
> > there some better terminology that I should use there? Perhaps
> > 'local-branch' ?
>
> Probably, I did a git fetch of you public vbi3 branch:
>
> git fetch https://sjg.u-boot.org/u-boot/u-boot.git vbi3
>
> And that did not include 3f76d803db9b500f43bc534465945a8d2836bb3e:
>
> fatal: bad object 3f76d803db9b500f43bc534465945a8d2836bb3e
Oh I see. You should just use 'git fetch' and get the whole tree.
>
> So yes, if you keep a public branch with same name as you say in your
> patches, I would expect it to be somewhat up to date.
OK I'll have to think about how to handle that. I used to name every
branch with a '-working' suffix, to make it clear that it can change
at any time. But I got tired of doing that in the end, so I stopped
for my new tree.
>
> >
> >>
> >>>
> >>> So no, there is nothing else that this series depends on and if you
> >>> can review it I can send a PR for Tom for -next one all necessary
> >>> changes are made.
> >>
> >> Sorry, this does not help, my main concern is testing that this does not
> >> break or affect anything for the remaining Rockchip boards. Something
> >> that is hard to test and validate when patches do not even apply to any
> >> of the mainline master or next branches.
> >>
> >> Sending patches based on a tree that has diverged with around 677 files
> >> changed, 20072 insertions(+), 17023 deletions(-), if my git fu is
> >> correct, and then expect us to test based on this diverged tree does not
> >> help with gaining confidence in this series.
> >>
> >> I can understand keeping a personal tree that will diverge at times,
> >> i.e. my personal tree has ~120-150 patches on top of mainline master.
> >> However, I always try to keep my work-in-progress branches rebased on
> >> top of master or next.
> >>
> >> For v4, please send a series based on mainline master or next branch,
> >> as stated in "General Patch Submission Rules" [1] in the U-Boot docs.
> >>
> >> If the series has some depends, I suggest you also publish a branch
> >> to a public repo with any limited depends applied on top of master or
> >> next along with the patches in your series.
> >
> > For now I am going to wait until you pick up your clean-up of part of
> > my series. Then I can pull that in any try to send the final VBE
> > series again.
>
> I sent out a "rockchip: binman: Use a template for FIT and other
> improvements" series [2] that picked up some of your rockchip binman
> image related patches.
>
> [2] https://patchwork.ozlabs.org/cover/2066701/
>
> >
> > I haven't had any rockchip patches rejected, so we should be able to
> > resolve this.
>
> They have not been properly reviewed (or tested) yet, as they have never
> applied cleanly on any mainline tree, with repeated requests to fix that.
>
> For me to review something, I want to be able to run the code, and run it
> on a code base as close as possible to where it intends to be merged.
>
> E.g. v1 was broken and had hidden depends that you had applied to your
> personal tree, and only later was sent out and now merged into mainline.
>
> I have some other concerns to validate, but have waited on a version
> that can be applied before continuing a review. Please consider this a
> NAK until it can properly be tested (i.e. reviewed) using a branch with
> a minimal diff to mainline master or next.
That's fine, but how about I hold off sending it until you pull in your series?
Regards,
Simon
>
> Regards,
> Jonas
>
> >
> >>
> >> [1] https://docs.u-boot.org/en/latest/develop/sending_patches.html
^ permalink raw reply [flat|nested] 51+ messages in thread
end of thread, other threads:[~2025-04-01 17:57 UTC | newest]
Thread overview: 51+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-28 15:34 [PATCH v3 00/31] VBE serial part H: Implement VBE on Rockchip RK3399 Simon Glass
2025-03-28 15:34 ` [PATCH v3 01/31] spl: Adjust xPL symbols Simon Glass
2025-03-28 15:34 ` [PATCH v3 02/31] spl: Allow VBE to handle xPL size Simon Glass
2025-03-28 15:34 ` [PATCH v3 03/31] vbe: Show the margin when using SPL_RELOC Simon Glass
2025-03-28 15:34 ` [PATCH v3 04/31] rockchip: Allow RAM init to happen in SPL on rk3399 Simon Glass
2025-03-28 15:34 ` [PATCH v3 05/31] rockchip: dts: Correct the OS for U-Boot Simon Glass
2025-03-28 15:34 ` [PATCH v3 06/31] rockchip: dts: Factor out arch and compression Simon Glass
2025-03-28 15:34 ` [PATCH v3 07/31] rockchip: dts: Add an fdtmap Simon Glass
2025-03-28 15:34 ` [PATCH v3 08/31] rockchip: dts: Create a template for the FIT Simon Glass
2025-03-28 16:26 ` Jonas Karlman
2025-03-28 15:34 ` [PATCH v3 09/31] rockchip: dts: Un-indent the FIT template Simon Glass
2025-03-28 15:34 ` [PATCH v3 10/31] rockchip: dts: Use the new binman template for the SPI image too Simon Glass
2025-03-28 18:19 ` Jonas Karlman
2025-03-28 18:25 ` Simon Glass
2025-03-28 15:34 ` [PATCH v3 11/31] rockchip: dts: Specify the phase in the image Simon Glass
2025-03-28 15:34 ` [PATCH v3 12/31] rockchip: Provide a bootstd configuration Simon Glass
2025-03-28 15:34 ` [PATCH v3 13/31] rockchip: Add SPL into the main FIT Simon Glass
2025-03-28 15:34 ` [PATCH v3 14/31] rockchip: Include a compatible string in each configuration Simon Glass
2025-03-28 15:34 ` [PATCH v3 15/31] rockchip: Add a template for SPL Simon Glass
2025-03-28 15:34 ` [PATCH v3 16/31] rockchip: Add a VPL image Simon Glass
2025-03-28 15:34 ` [PATCH v3 17/31] rockchip: Add TPL alternatives Simon Glass
2025-03-28 15:34 ` [PATCH v3 18/31] rockchip: Update rk3399 bootph-tags for VPL Simon Glass
2025-03-28 16:11 ` Jonas Karlman
2025-03-28 15:34 ` [PATCH v3 19/31] rockchip: Provide a VPL phase on rk3399 Simon Glass
2025-03-28 16:16 ` Jonas Karlman
2025-03-28 23:40 ` Simon Glass
2025-03-29 0:07 ` Tom Rini
2025-03-29 16:46 ` Jonas Karlman
2025-04-01 15:42 ` Simon Glass
2025-04-01 17:27 ` Jonas Karlman
2025-04-01 17:56 ` Simon Glass
2025-03-28 16:51 ` Peter Robinson
2025-03-28 23:41 ` Simon Glass
2025-03-28 18:35 ` Jonas Karlman
2025-03-28 15:35 ` [PATCH v3 20/31] rockchip: Add symbols for spl_reloc Simon Glass
2025-03-28 16:29 ` Jonas Karlman
2025-03-28 15:35 ` [PATCH v3 21/31] rockchip: rk3399: Adjust initial TPL-stack to match SPL Simon Glass
2025-03-28 17:28 ` Jonas Karlman
2025-03-28 15:35 ` [PATCH v3 22/31] rockchip: Allow SPL to set up SDRAM Simon Glass
2025-03-28 15:35 ` [PATCH v3 23/31] rockchip: Add a generic-ddr3 rk3399 board Simon Glass
2025-03-28 15:35 ` [PATCH v3 24/31] rockchip: Add documentation for VBE Simon Glass
2025-03-28 15:35 ` [PATCH v3 25/31] gitlab: Add an VBE board to the sjg lab Simon Glass
2025-03-28 15:35 ` [PATCH v3 26/31] rockchip: Set the skip-at-start property correctly Simon Glass
2025-03-28 15:35 ` [PATCH v3 27/31] vbe: Add a bootmeth driver for abrec Simon Glass
2025-03-28 15:35 ` [PATCH v3 28/31] rockchip: Update binman image for new skip-at-start setup Simon Glass
2025-03-28 15:35 ` [PATCH v3 29/31] RFC: Revert "bloblist: Load the bloblist from the previous loader" Simon Glass
2025-03-28 15:50 ` Raymond Mao
2025-03-28 16:13 ` Tom Rini
2025-03-28 23:38 ` Simon Glass
2025-03-28 15:35 ` [PATCH v3 30/31] rockchip: Relocate bloblist at the end of the SPL phase Simon Glass
2025-03-28 15:35 ` [PATCH v3 31/31] bloblist: Allow using a different bloblist address Simon Glass
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