[PATCH v3 17/26] powerpc: mpc85xx: Remove MPC8540 support

[Bradley Morgan <brads@mainlining.org>]

No board in the tree selects ARCH_MPC8540, and the SoC is unmaintained.
Remove its architecture configuration, DUART definitions, and CPU
specific cache handling.

Signed-off-by: Bradley Morgan <brads@mainlining.org>
---
 README                                |  2 +-
 arch/powerpc/cpu/mpc85xx/Kconfig      | 12 ++-------
 arch/powerpc/cpu/mpc85xx/cpu.c        |  2 +-
 arch/powerpc/cpu/mpc85xx/cpu_init.c   |  4 +--
 arch/powerpc/cpu/mpc85xx/fdt.c        |  4 +--
 arch/powerpc/cpu/mpc85xx/speed.c      |  2 +-
 arch/powerpc/cpu/mpc8xxx/cpu.c        |  1 -
 arch/powerpc/include/asm/fsl_lbc.h    |  3 +--
 arch/powerpc/include/asm/immap_85xx.h | 35 ---------------------------
 arch/powerpc/include/asm/processor.h  |  1 -
 10 files changed, 10 insertions(+), 56 deletions(-)

diff --git a/README b/README
index 7060bc5ac0c..830aa9b722f 100644
--- a/README
+++ b/README
@@ -137,7 +137,7 @@ The following options need to be configured:
 
 - CPU Type:	Define exactly one, e.g. CONFIG_MPC85XX.
 
-- Board Type:	Define exactly one, e.g. CONFIG_MPC8540ADS.
+- Board Type:	Define exactly one.
 
 - 85xx CPU Options:
 		CONFIG_SYS_PPC64
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 8391ea23cdb..2d405501c57 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -321,11 +321,6 @@ config ARCH_BSC9132
 	imply CMD_PCI
 	imply CMD_REGINFO
 
-config ARCH_MPC8540
-	bool
-	select FSL_LAW
-	select SYS_FSL_HAS_DDR1
-
 config ARCH_MPC8544
 	bool
 	select BTB
@@ -760,7 +755,6 @@ config SYS_CCSRBAR_DEFAULT
 	hex "Default CCSRBAR address"
 	default	0xff700000 if	ARCH_BSC9131	|| \
 				ARCH_BSC9132	|| \
-				ARCH_MPC8540	|| \
 				ARCH_MPC8544	|| \
 				ARCH_MPC8560	|| \
 				ARCH_P1010	|| \
@@ -975,8 +969,7 @@ config SYS_FSL_NUM_LAWS
 			ARCH_P1024	|| \
 			ARCH_P2020
 	default 10 if ARCH_MPC8544
-	default 8 if	ARCH_MPC8540	|| \
-			ARCH_MPC8560
+	default 8 if	ARCH_MPC8560
 	help
 	  Number of local access windows. This is fixed per SoC.
 	  If not sure, do not change.
@@ -1111,8 +1104,7 @@ config SYS_FSL_IFC_CLK_DIV
 
 config SYS_FSL_LBC_CLK_DIV
 	int "Divider of platform clock"
-	depends on FSL_ELBC || ARCH_MPC8540 || \
-		ARCH_MPC8560
+	depends on FSL_ELBC || ARCH_MPC8560
 
 	default 2 if	ARCH_P2041
 	default 1
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index ab4ef154729..c33250faac6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -302,7 +302,7 @@ int checkcpu (void)
 int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 /* Everything after the first generation of PQ3 parts has RSTCR */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8560)
 	unsigned long val, msr;
 
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 710b3b31354..c6923a797f9 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -546,7 +546,7 @@ int l2cache_init(void)
 		return -1;
 		break;
 	case 0x1:
-		if (ver == SVR_8540 || ver == SVR_8560   ||
+		if (ver == SVR_8560 ||
 		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("128 KiB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
@@ -557,7 +557,7 @@ int l2cache_init(void)
 		}
 		break;
 	case 0x2:
-		if (ver == SVR_8540 || ver == SVR_8560   ||
+		if (ver == SVR_8560 ||
 		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("256 KiB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 7de6a033ce2..e115c19cf8d 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -229,14 +229,14 @@ static inline u32 l2cache_size(void)
 	case 0x0:
 		break;
 	case 0x1:
-		if (ver == SVR_8540 || ver == SVR_8560   ||
+		if (ver == SVR_8560 ||
 		    ver == SVR_8541 || ver == SVR_8555)
 			return 128;
 		else
 			return 256;
 		break;
 	case 0x2:
-		if (ver == SVR_8540 || ver == SVR_8560   ||
+		if (ver == SVR_8560 ||
 		    ver == SVR_8541 || ver == SVR_8555)
 			return 256;
 		else
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 01fe85ffd57..8e9808953dc 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -593,7 +593,7 @@ int get_clocks(void)
 	 * for that SOC. This information is taken from application note
 	 * AN2919.
 	 */
-#if defined(CONFIG_ARCH_MPC8540) || defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_ARCH_MPC8560)
 	gd->arch.i2c1_clk = sys_info.freq_systembus;
 #elif defined(CONFIG_ARCH_MPC8544)
 	/*
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 1e5d733ffce..ff6087904ba 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -26,7 +26,6 @@ static struct cpu_type cpu_type_list[] = {
 #if defined(CONFIG_MPC85xx)
 	CPU_TYPE_ENTRY(8533, 8533, 1),
 	CPU_TYPE_ENTRY(8535, 8535, 1),
-	CPU_TYPE_ENTRY(8540, 8540, 1),
 	CPU_TYPE_ENTRY(8541, 8541, 1),
 	CPU_TYPE_ENTRY(8543, 8543, 1),
 	CPU_TYPE_ENTRY(8544, 8544, 1),
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index f07535cb5ea..d98673c40b3 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -321,8 +321,7 @@ void lbc_sdram_init(void);
  */
 #define LCRR_CLKDIV			0x0000001F
 #define LCRR_CLKDIV_SHIFT		0
-#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8540) || \
-	defined(CONFIG_ARCH_MPC8560)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_ARCH_MPC8560)
 #define LCRR_CLKDIV_2			0x00000002
 #define LCRR_CLKDIV_4			0x00000004
 #define LCRR_CLKDIV_8			0x00000008
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 695c89f2237..4479ef813c8 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -123,44 +123,9 @@ typedef struct ccsr_i2c {
 	u8	res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 
-#if defined(CONFIG_ARCH_MPC8540)
-/* DUART Registers */
-typedef struct ccsr_duart {
-	u8	res1[1280];
-/* URBR1, UTHR1, UDLB1 with the same addr */
-	u8	urbr1_uthr1_udlb1;
-/* UIER1, UDMB1 with the same addr01 */
-	u8	uier1_udmb1;
-/* UIIR1, UFCR1, UAFR1 with the same addr */
-	u8	uiir1_ufcr1_uafr1;
-	u8	ulcr1;		/* UART1 Line Control */
-	u8	umcr1;		/* UART1 Modem Control */
-	u8	ulsr1;		/* UART1 Line Status */
-	u8	umsr1;		/* UART1 Modem Status */
-	u8	uscr1;		/* UART1 Scratch */
-	u8	res2[8];
-	u8	udsr1;		/* UART1 DMA Status */
-	u8	res3[239];
-/* URBR2, UTHR2, UDLB2 with the same addr */
-	u8	urbr2_uthr2_udlb2;
-/* UIER2, UDMB2 with the same addr */
-	u8	uier2_udmb2;
-/* UIIR2, UFCR2, UAFR2 with the same addr */
-	u8	uiir2_ufcr2_uafr2;
-	u8	ulcr2;		/* UART2 Line Control */
-	u8	umcr2;		/* UART2 Modem Control */
-	u8	ulsr2;		/* UART2 Line Status */
-	u8	umsr2;		/* UART2 Modem Status */
-	u8	uscr2;		/* UART2 Scratch */
-	u8	res4[8];
-	u8	udsr2;		/* UART2 DMA Status */
-	u8	res5[2543];
-} ccsr_duart_t;
-#else /* MPC8560 uses UART on its CPM */
 typedef struct ccsr_duart {
 	u8 res[4096];
 } ccsr_duart_t;
-#endif
 
 /* eSPI Registers */
 typedef struct ccsr_espi {
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index e11498c6e78..77414c05aba 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1014,7 +1014,6 @@
 
 #define SVR_8533	0x803400
 #define SVR_8535	0x803701
-#define SVR_8540	0x803000
 #define SVR_8541	0x807200
 #define SVR_8543	0x803200
 #define SVR_8544	0x803401
-- 
2.47.3