* [PATCH 01/20] dt-bindings: clock, reset: Add support for rk3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-03 3:07 ` Kever Yang
2024-11-21 14:27 ` [PATCH 02/20] dt-bindings: clock, reset: fix top-comment indentation rk3576 headers Heiko Stuebner
` (20 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Elaine Zhang, Sugar Zhang, Rob Herring
From: Detlev Casanova <detlev.casanova@collabora.com>
Add clock and reset ID defines for rk3576.
Compared to the downstream bindings written by Elaine, this uses
continous gapless IDs starting at 0. Thus all numbers are
different between downstream and upstream, but names are kept
exactly the same.
Also add documentation for the rk3576 CRU core.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: 49c04453db81fc806906e26ef9fc53bdb635ff39 ]
(cherry picked from commit 6f1c891c492348ef3cc4595f66d7fd7a4a824199)
---
.../Bindings/clock/rockchip,rk3576-cru.yaml | 56 ++
.../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++
.../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++
3 files changed, 1212 insertions(+)
create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
diff --git a/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
new file mode 100644
index 00000000000..9c9b36049c7
--- /dev/null
+++ b/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip rk3576 Family Clock and Reset Control Module
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+ - Detlev Casanova <detlev.casanova@collabora.com>
+
+description:
+ The RK3576 clock controller generates the clock and also implements a reset
+ controller for SoC peripherals. For example it provides SCLK_UART2 and
+ PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
+ module.
+
+properties:
+ compatible:
+ const: rockchip,rk3576-cru
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: xin24m
+ - const: xin32k
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@27200000 {
+ compatible = "rockchip,rk3576-cru";
+ reg = <0xfd7c0000 0x5c000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
new file mode 100644
index 00000000000..a2933021be8
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
@@ -0,0 +1,592 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+* Copyright (c) 2024 Collabora Ltd.
+*
+* Author: Elaine Zhang <zhangqing@rock-chips.com>
+* Author: Detlev Casanova <detlev.casanova@collabora.com>
+*/
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_BPLL 0
+#define PLL_LPLL 1
+#define PLL_VPLL 2
+#define PLL_AUPLL 3
+#define PLL_CPLL 4
+#define PLL_GPLL 5
+#define PLL_PPLL 6
+#define ARMCLK_L 7
+#define ARMCLK_B 8
+
+/* cru clocks */
+#define CLK_CPLL_DIV20 9
+#define CLK_CPLL_DIV10 10
+#define CLK_GPLL_DIV8 11
+#define CLK_GPLL_DIV6 12
+#define CLK_CPLL_DIV4 13
+#define CLK_GPLL_DIV4 14
+#define CLK_SPLL_DIV2 15
+#define CLK_GPLL_DIV3 16
+#define CLK_CPLL_DIV2 17
+#define CLK_GPLL_DIV2 18
+#define CLK_SPLL_DIV1 19
+#define PCLK_TOP_ROOT 20
+#define ACLK_TOP 21
+#define HCLK_TOP 22
+#define CLK_AUDIO_FRAC_0 23
+#define CLK_AUDIO_FRAC_1 24
+#define CLK_AUDIO_FRAC_2 25
+#define CLK_AUDIO_FRAC_3 26
+#define CLK_UART_FRAC_0 27
+#define CLK_UART_FRAC_1 28
+#define CLK_UART_FRAC_2 29
+#define CLK_UART1_SRC_TOP 30
+#define CLK_AUDIO_INT_0 31
+#define CLK_AUDIO_INT_1 32
+#define CLK_AUDIO_INT_2 33
+#define CLK_PDM0_SRC_TOP 34
+#define CLK_PDM1_OUT 35
+#define CLK_GMAC0_125M_SRC 36
+#define CLK_GMAC1_125M_SRC 37
+#define LCLK_ASRC_SRC_0 38
+#define LCLK_ASRC_SRC_1 39
+#define REF_CLK0_OUT_PLL 40
+#define REF_CLK1_OUT_PLL 41
+#define REF_CLK2_OUT_PLL 42
+#define REFCLKO25M_GMAC0_OUT 43
+#define REFCLKO25M_GMAC1_OUT 44
+#define CLK_CIFOUT_OUT 45
+#define CLK_GMAC0_RMII_CRU 46
+#define CLK_GMAC1_RMII_CRU 47
+#define CLK_OTPC_AUTO_RD_G 48
+#define CLK_OTP_PHY_G 49
+#define CLK_MIPI_CAMERAOUT_M0 50
+#define CLK_MIPI_CAMERAOUT_M1 51
+#define CLK_MIPI_CAMERAOUT_M2 52
+#define MCLK_PDM0_SRC_TOP 53
+#define HCLK_AUDIO_ROOT 54
+#define HCLK_ASRC_2CH_0 55
+#define HCLK_ASRC_2CH_1 56
+#define HCLK_ASRC_4CH_0 57
+#define HCLK_ASRC_4CH_1 58
+#define CLK_ASRC_2CH_0 59
+#define CLK_ASRC_2CH_1 60
+#define CLK_ASRC_4CH_0 61
+#define CLK_ASRC_4CH_1 62
+#define MCLK_SAI0_8CH_SRC 63
+#define MCLK_SAI0_8CH 64
+#define HCLK_SAI0_8CH 65
+#define HCLK_SPDIF_RX0 66
+#define MCLK_SPDIF_RX0 67
+#define HCLK_SPDIF_RX1 68
+#define MCLK_SPDIF_RX1 69
+#define MCLK_SAI1_8CH_SRC 70
+#define MCLK_SAI1_8CH 71
+#define HCLK_SAI1_8CH 72
+#define MCLK_SAI2_2CH_SRC 73
+#define MCLK_SAI2_2CH 74
+#define HCLK_SAI2_2CH 75
+#define MCLK_SAI3_2CH_SRC 76
+#define MCLK_SAI3_2CH 77
+#define HCLK_SAI3_2CH 78
+#define MCLK_SAI4_2CH_SRC 79
+#define MCLK_SAI4_2CH 80
+#define HCLK_SAI4_2CH 81
+#define HCLK_ACDCDIG_DSM 82
+#define MCLK_ACDCDIG_DSM 83
+#define CLK_PDM1 84
+#define HCLK_PDM1 85
+#define MCLK_PDM1 86
+#define HCLK_SPDIF_TX0 87
+#define MCLK_SPDIF_TX0 88
+#define HCLK_SPDIF_TX1 89
+#define MCLK_SPDIF_TX1 90
+#define CLK_SAI1_MCLKOUT 91
+#define CLK_SAI2_MCLKOUT 92
+#define CLK_SAI3_MCLKOUT 93
+#define CLK_SAI4_MCLKOUT 94
+#define CLK_SAI0_MCLKOUT 95
+#define HCLK_BUS_ROOT 96
+#define PCLK_BUS_ROOT 97
+#define ACLK_BUS_ROOT 98
+#define HCLK_CAN0 99
+#define CLK_CAN0 100
+#define HCLK_CAN1 101
+#define CLK_CAN1 102
+#define CLK_KEY_SHIFT 103
+#define PCLK_I2C1 104
+#define PCLK_I2C2 105
+#define PCLK_I2C3 106
+#define PCLK_I2C4 107
+#define PCLK_I2C5 108
+#define PCLK_I2C6 109
+#define PCLK_I2C7 110
+#define PCLK_I2C8 111
+#define PCLK_I2C9 112
+#define PCLK_WDT_BUSMCU 113
+#define TCLK_WDT_BUSMCU 114
+#define ACLK_GIC 115
+#define CLK_I2C1 116
+#define CLK_I2C2 117
+#define CLK_I2C3 118
+#define CLK_I2C4 119
+#define CLK_I2C5 120
+#define CLK_I2C6 121
+#define CLK_I2C7 122
+#define CLK_I2C8 123
+#define CLK_I2C9 124
+#define PCLK_SARADC 125
+#define CLK_SARADC 126
+#define PCLK_TSADC 127
+#define CLK_TSADC 128
+#define PCLK_UART0 129
+#define PCLK_UART2 130
+#define PCLK_UART3 131
+#define PCLK_UART4 132
+#define PCLK_UART5 133
+#define PCLK_UART6 134
+#define PCLK_UART7 135
+#define PCLK_UART8 136
+#define PCLK_UART9 137
+#define PCLK_UART10 138
+#define PCLK_UART11 139
+#define SCLK_UART0 140
+#define SCLK_UART2 141
+#define SCLK_UART3 142
+#define SCLK_UART4 143
+#define SCLK_UART5 144
+#define SCLK_UART6 145
+#define SCLK_UART7 146
+#define SCLK_UART8 147
+#define SCLK_UART9 148
+#define SCLK_UART10 149
+#define SCLK_UART11 150
+#define PCLK_SPI0 151
+#define PCLK_SPI1 152
+#define PCLK_SPI2 153
+#define PCLK_SPI3 154
+#define PCLK_SPI4 155
+#define CLK_SPI0 156
+#define CLK_SPI1 157
+#define CLK_SPI2 158
+#define CLK_SPI3 159
+#define CLK_SPI4 160
+#define PCLK_WDT0 161
+#define TCLK_WDT0 162
+#define PCLK_PWM1 163
+#define CLK_PWM1 164
+#define CLK_OSC_PWM1 165
+#define CLK_RC_PWM1 166
+#define PCLK_BUSTIMER0 167
+#define PCLK_BUSTIMER1 168
+#define CLK_TIMER0_ROOT 169
+#define CLK_TIMER0 170
+#define CLK_TIMER1 171
+#define CLK_TIMER2 172
+#define CLK_TIMER3 173
+#define CLK_TIMER4 174
+#define CLK_TIMER5 175
+#define PCLK_MAILBOX0 176
+#define PCLK_GPIO1 177
+#define DBCLK_GPIO1 178
+#define PCLK_GPIO2 179
+#define DBCLK_GPIO2 180
+#define PCLK_GPIO3 181
+#define DBCLK_GPIO3 182
+#define PCLK_GPIO4 183
+#define DBCLK_GPIO4 184
+#define ACLK_DECOM 185
+#define PCLK_DECOM 186
+#define DCLK_DECOM 187
+#define CLK_TIMER1_ROOT 188
+#define CLK_TIMER6 189
+#define CLK_TIMER7 190
+#define CLK_TIMER8 191
+#define CLK_TIMER9 192
+#define CLK_TIMER10 193
+#define CLK_TIMER11 194
+#define ACLK_DMAC0 195
+#define ACLK_DMAC1 196
+#define ACLK_DMAC2 197
+#define ACLK_SPINLOCK 198
+#define HCLK_I3C0 199
+#define HCLK_I3C1 200
+#define HCLK_BUS_CM0_ROOT 201
+#define FCLK_BUS_CM0_CORE 202
+#define CLK_BUS_CM0_RTC 203
+#define PCLK_PMU2 204
+#define PCLK_PWM2 205
+#define CLK_PWM2 206
+#define CLK_RC_PWM2 207
+#define CLK_OSC_PWM2 208
+#define CLK_FREQ_PWM1 209
+#define CLK_COUNTER_PWM1 210
+#define SAI_SCLKIN_FREQ 211
+#define SAI_SCLKIN_COUNTER 212
+#define CLK_I3C0 213
+#define CLK_I3C1 214
+#define PCLK_CSIDPHY1 215
+#define PCLK_DDR_ROOT 216
+#define PCLK_DDR_MON_CH0 217
+#define TMCLK_DDR_MON_CH0 218
+#define ACLK_DDR_ROOT 219
+#define HCLK_DDR_ROOT 220
+#define FCLK_DDR_CM0_CORE 221
+#define CLK_DDR_TIMER_ROOT 222
+#define CLK_DDR_TIMER0 223
+#define CLK_DDR_TIMER1 224
+#define TCLK_WDT_DDR 225
+#define PCLK_WDT 226
+#define PCLK_TIMER 227
+#define CLK_DDR_CM0_RTC 228
+#define ACLK_RKNN0 229
+#define ACLK_RKNN1 230
+#define HCLK_RKNN_ROOT 231
+#define CLK_RKNN_DSU0 232
+#define PCLK_NPUTOP_ROOT 233
+#define PCLK_NPU_TIMER 234
+#define CLK_NPUTIMER_ROOT 235
+#define CLK_NPUTIMER0 236
+#define CLK_NPUTIMER1 237
+#define PCLK_NPU_WDT 238
+#define TCLK_NPU_WDT 239
+#define ACLK_RKNN_CBUF 240
+#define HCLK_NPU_CM0_ROOT 241
+#define FCLK_NPU_CM0_CORE 242
+#define CLK_NPU_CM0_RTC 243
+#define HCLK_RKNN_CBUF 244
+#define HCLK_NVM_ROOT 245
+#define ACLK_NVM_ROOT 246
+#define SCLK_FSPI_X2 247
+#define HCLK_FSPI 248
+#define CCLK_SRC_EMMC 249
+#define HCLK_EMMC 250
+#define ACLK_EMMC 251
+#define BCLK_EMMC 252
+#define TCLK_EMMC 253
+#define PCLK_PHP_ROOT 254
+#define ACLK_PHP_ROOT 255
+#define PCLK_PCIE0 256
+#define CLK_PCIE0_AUX 257
+#define ACLK_PCIE0_MST 258
+#define ACLK_PCIE0_SLV 259
+#define ACLK_PCIE0_DBI 260
+#define ACLK_USB3OTG1 261
+#define CLK_REF_USB3OTG1 262
+#define CLK_SUSPEND_USB3OTG1 263
+#define ACLK_MMU0 264
+#define ACLK_SLV_MMU0 265
+#define ACLK_MMU1 266
+#define ACLK_SLV_MMU1 267
+#define PCLK_PCIE1 268
+#define CLK_PCIE1_AUX 269
+#define ACLK_PCIE1_MST 270
+#define ACLK_PCIE1_SLV 271
+#define ACLK_PCIE1_DBI 272
+#define CLK_RXOOB0 273
+#define CLK_RXOOB1 274
+#define CLK_PMALIVE0 275
+#define CLK_PMALIVE1 276
+#define ACLK_SATA0 277
+#define ACLK_SATA1 278
+#define CLK_USB3OTG1_PIPE_PCLK 279
+#define CLK_USB3OTG1_UTMI 280
+#define CLK_USB3OTG0_PIPE_PCLK 281
+#define CLK_USB3OTG0_UTMI 282
+#define HCLK_SDGMAC_ROOT 283
+#define ACLK_SDGMAC_ROOT 284
+#define PCLK_SDGMAC_ROOT 285
+#define ACLK_GMAC0 286
+#define ACLK_GMAC1 287
+#define PCLK_GMAC0 288
+#define PCLK_GMAC1 289
+#define CCLK_SRC_SDIO 290
+#define HCLK_SDIO 291
+#define CLK_GMAC1_PTP_REF 292
+#define CLK_GMAC0_PTP_REF 293
+#define CLK_GMAC1_PTP_REF_SRC 294
+#define CLK_GMAC0_PTP_REF_SRC 295
+#define CCLK_SRC_SDMMC0 296
+#define HCLK_SDMMC0 297
+#define SCLK_FSPI1_X2 298
+#define HCLK_FSPI1 299
+#define ACLK_DSMC_ROOT 300
+#define ACLK_DSMC 301
+#define PCLK_DSMC 302
+#define CLK_DSMC_SYS 303
+#define HCLK_HSGPIO 304
+#define CLK_HSGPIO_TX 305
+#define CLK_HSGPIO_RX 306
+#define ACLK_HSGPIO 307
+#define PCLK_PHPPHY_ROOT 308
+#define PCLK_PCIE2_COMBOPHY0 309
+#define PCLK_PCIE2_COMBOPHY1 310
+#define CLK_PCIE_100M_SRC 311
+#define CLK_PCIE_100M_NDUTY_SRC 312
+#define CLK_REF_PCIE0_PHY 313
+#define CLK_REF_PCIE1_PHY 314
+#define CLK_REF_MPHY_26M 315
+#define HCLK_RKVDEC_ROOT 316
+#define ACLK_RKVDEC_ROOT 317
+#define HCLK_RKVDEC 318
+#define CLK_RKVDEC_HEVC_CA 319
+#define CLK_RKVDEC_CORE 320
+#define ACLK_UFS_ROOT 321
+#define ACLK_USB_ROOT 322
+#define PCLK_USB_ROOT 323
+#define ACLK_USB3OTG0 324
+#define CLK_REF_USB3OTG0 325
+#define CLK_SUSPEND_USB3OTG0 326
+#define ACLK_MMU2 327
+#define ACLK_SLV_MMU2 328
+#define ACLK_UFS_SYS 329
+#define ACLK_VPU_ROOT 330
+#define ACLK_VPU_MID_ROOT 331
+#define HCLK_VPU_ROOT 332
+#define ACLK_JPEG_ROOT 333
+#define ACLK_VPU_LOW_ROOT 334
+#define HCLK_RGA2E_0 335
+#define ACLK_RGA2E_0 336
+#define CLK_CORE_RGA2E_0 337
+#define ACLK_JPEG 338
+#define HCLK_JPEG 339
+#define HCLK_VDPP 340
+#define ACLK_VDPP 341
+#define CLK_CORE_VDPP 342
+#define HCLK_RGA2E_1 343
+#define ACLK_RGA2E_1 344
+#define CLK_CORE_RGA2E_1 345
+#define DCLK_EBC_FRAC_SRC 346
+#define HCLK_EBC 347
+#define ACLK_EBC 348
+#define DCLK_EBC 349
+#define HCLK_VEPU0_ROOT 350
+#define ACLK_VEPU0_ROOT 351
+#define HCLK_VEPU0 352
+#define ACLK_VEPU0 353
+#define CLK_VEPU0_CORE 354
+#define ACLK_VI_ROOT 355
+#define HCLK_VI_ROOT 356
+#define PCLK_VI_ROOT 357
+#define DCLK_VICAP 358
+#define ACLK_VICAP 359
+#define HCLK_VICAP 360
+#define CLK_ISP_CORE 361
+#define CLK_ISP_CORE_MARVIN 362
+#define CLK_ISP_CORE_VICAP 363
+#define ACLK_ISP 364
+#define HCLK_ISP 365
+#define ACLK_VPSS 366
+#define HCLK_VPSS 367
+#define CLK_CORE_VPSS 368
+#define PCLK_CSI_HOST_0 369
+#define PCLK_CSI_HOST_1 370
+#define PCLK_CSI_HOST_2 371
+#define PCLK_CSI_HOST_3 372
+#define PCLK_CSI_HOST_4 373
+#define ICLK_CSIHOST01 374
+#define ICLK_CSIHOST0 375
+#define CLK_ISP_PVTPLL_SRC 376
+#define ACLK_VI_ROOT_INTER 377
+#define CLK_VICAP_I0CLK 378
+#define CLK_VICAP_I1CLK 379
+#define CLK_VICAP_I2CLK 380
+#define CLK_VICAP_I3CLK 381
+#define CLK_VICAP_I4CLK 382
+#define ACLK_VOP_ROOT 383
+#define HCLK_VOP_ROOT 384
+#define PCLK_VOP_ROOT 385
+#define HCLK_VOP 386
+#define ACLK_VOP 387
+#define DCLK_VP0_SRC 388
+#define DCLK_VP1_SRC 389
+#define DCLK_VP2_SRC 390
+#define DCLK_VP0 391
+#define DCLK_VP1 392
+#define DCLK_VP2 393
+#define PCLK_VOPGRF 394
+#define ACLK_VO0_ROOT 395
+#define HCLK_VO0_ROOT 396
+#define PCLK_VO0_ROOT 397
+#define PCLK_VO0_GRF 398
+#define ACLK_HDCP0 399
+#define HCLK_HDCP0 400
+#define PCLK_HDCP0 401
+#define CLK_TRNG0_SKP 402
+#define PCLK_DSIHOST0 403
+#define CLK_DSIHOST0 404
+#define PCLK_HDMITX0 405
+#define CLK_HDMITX0_EARC 406
+#define CLK_HDMITX0_REF 407
+#define PCLK_EDP0 408
+#define CLK_EDP0_24M 409
+#define CLK_EDP0_200M 410
+#define MCLK_SAI5_8CH_SRC 411
+#define MCLK_SAI5_8CH 412
+#define HCLK_SAI5_8CH 413
+#define MCLK_SAI6_8CH_SRC 414
+#define MCLK_SAI6_8CH 415
+#define HCLK_SAI6_8CH 416
+#define HCLK_SPDIF_TX2 417
+#define MCLK_SPDIF_TX2 418
+#define HCLK_SPDIF_RX2 419
+#define MCLK_SPDIF_RX2 420
+#define HCLK_SAI8_8CH 421
+#define MCLK_SAI8_8CH_SRC 422
+#define MCLK_SAI8_8CH 423
+#define ACLK_VO1_ROOT 424
+#define HCLK_VO1_ROOT 425
+#define PCLK_VO1_ROOT 426
+#define MCLK_SAI7_8CH_SRC 427
+#define MCLK_SAI7_8CH 428
+#define HCLK_SAI7_8CH 429
+#define HCLK_SPDIF_TX3 430
+#define HCLK_SPDIF_TX4 431
+#define HCLK_SPDIF_TX5 432
+#define MCLK_SPDIF_TX3 433
+#define CLK_AUX16MHZ_0 434
+#define ACLK_DP0 435
+#define PCLK_DP0 436
+#define PCLK_VO1_GRF 437
+#define ACLK_HDCP1 438
+#define HCLK_HDCP1 439
+#define PCLK_HDCP1 440
+#define CLK_TRNG1_SKP 441
+#define HCLK_SAI9_8CH 442
+#define MCLK_SAI9_8CH_SRC 443
+#define MCLK_SAI9_8CH 444
+#define MCLK_SPDIF_TX4 445
+#define MCLK_SPDIF_TX5 446
+#define CLK_GPU_SRC_PRE 447
+#define CLK_GPU 448
+#define PCLK_GPU_ROOT 449
+#define ACLK_CENTER_ROOT 450
+#define ACLK_CENTER_LOW_ROOT 451
+#define HCLK_CENTER_ROOT 452
+#define PCLK_CENTER_ROOT 453
+#define ACLK_DMA2DDR 454
+#define ACLK_DDR_SHAREMEM 455
+#define PCLK_DMA2DDR 456
+#define PCLK_SHAREMEM 457
+#define HCLK_VEPU1_ROOT 458
+#define ACLK_VEPU1_ROOT 459
+#define HCLK_VEPU1 460
+#define ACLK_VEPU1 461
+#define CLK_VEPU1_CORE 462
+#define CLK_JDBCK_DAP 463
+#define PCLK_MIPI_DCPHY 464
+#define CLK_32K_USB2DEBUG 465
+#define PCLK_CSIDPHY 466
+#define PCLK_USBDPPHY 467
+#define CLK_PMUPHY_REF_SRC 468
+#define CLK_USBDP_COMBO_PHY_IMMORTAL 469
+#define CLK_HDMITXHDP 470
+#define PCLK_MPHY 471
+#define CLK_REF_OSC_MPHY 472
+#define CLK_REF_UFS_CLKOUT 473
+#define HCLK_PMU1_ROOT 474
+#define HCLK_PMU_CM0_ROOT 475
+#define CLK_200M_PMU_SRC 476
+#define CLK_100M_PMU_SRC 477
+#define CLK_50M_PMU_SRC 478
+#define FCLK_PMU_CM0_CORE 479
+#define CLK_PMU_CM0_RTC 480
+#define PCLK_PMU1 481
+#define CLK_PMU1 482
+#define PCLK_PMU1WDT 483
+#define TCLK_PMU1WDT 484
+#define PCLK_PMUTIMER 485
+#define CLK_PMUTIMER_ROOT 486
+#define CLK_PMUTIMER0 487
+#define CLK_PMUTIMER1 488
+#define PCLK_PMU1PWM 489
+#define CLK_PMU1PWM 490
+#define CLK_PMU1PWM_OSC 491
+#define PCLK_PMUPHY_ROOT 492
+#define PCLK_I2C0 493
+#define CLK_I2C0 494
+#define SCLK_UART1 495
+#define PCLK_UART1 496
+#define CLK_PMU1PWM_RC 497
+#define CLK_PDM0 498
+#define HCLK_PDM0 499
+#define MCLK_PDM0 500
+#define HCLK_VAD 501
+#define CLK_OSCCHK_PVTM 502
+#define CLK_PDM0_OUT 503
+#define CLK_HPTIMER_SRC 504
+#define PCLK_PMU0_ROOT 505
+#define PCLK_PMU0 506
+#define PCLK_GPIO0 507
+#define DBCLK_GPIO0 508
+#define CLK_OSC0_PMU1 509
+#define PCLK_PMU1_ROOT 510
+#define XIN_OSC0_DIV 511
+#define ACLK_USB 512
+#define ACLK_UFS 513
+#define ACLK_SDGMAC 514
+#define HCLK_SDGMAC 515
+#define PCLK_SDGMAC 516
+#define HCLK_VO1 517
+#define HCLK_VO0 518
+#define PCLK_CCI_ROOT 519
+#define ACLK_CCI_ROOT 520
+#define HCLK_VO0VOP_CHANNEL 521
+#define ACLK_VO0VOP_CHANNEL 522
+#define ACLK_TOP_MID 523
+#define ACLK_SECURE_HIGH 524
+#define CLK_USBPHY_REF_SRC 525
+#define CLK_PHY_REF_SRC 526
+#define CLK_CPLL_REF_SRC 527
+#define CLK_AUPLL_REF_SRC 528
+#define PCLK_SECURE_NS 529
+#define HCLK_SECURE_NS 530
+#define ACLK_SECURE_NS 531
+#define PCLK_OTPC_NS 532
+#define HCLK_CRYPTO_NS 533
+#define HCLK_TRNG_NS 534
+#define CLK_OTPC_NS 535
+#define SCLK_DSU 536
+#define SCLK_DDR 537
+#define ACLK_CRYPTO_NS 538
+#define CLK_PKA_CRYPTO_NS 539
+#define ACLK_RKVDEC_ROOT_BAK 540
+#define CLK_AUDIO_FRAC_0_SRC 541
+#define CLK_AUDIO_FRAC_1_SRC 542
+#define CLK_AUDIO_FRAC_2_SRC 543
+#define CLK_AUDIO_FRAC_3_SRC 544
+#define PCLK_HDPTX_APB 545
+
+/* secure clk */
+#define CLK_STIMER0_ROOT 546
+#define CLK_STIMER1_ROOT 547
+#define PCLK_SECURE_S 548
+#define HCLK_SECURE_S 549
+#define ACLK_SECURE_S 550
+#define CLK_PKA_CRYPTO_S 551
+#define HCLK_VO1_S 552
+#define PCLK_VO1_S 553
+#define HCLK_VO0_S 554
+#define PCLK_VO0_S 555
+#define PCLK_KLAD 556
+#define HCLK_CRYPTO_S 557
+#define HCLK_KLAD 558
+#define ACLK_CRYPTO_S 559
+#define HCLK_TRNG_S 560
+#define PCLK_OTPC_S 561
+#define CLK_OTPC_S 562
+#define PCLK_WDT_S 563
+#define TCLK_WDT_S 564
+#define PCLK_HDCP0_TRNG 565
+#define PCLK_HDCP1_TRNG 566
+#define HCLK_HDCP_KEY0 567
+#define HCLK_HDCP_KEY1 568
+#define PCLK_EDP_S 569
+#define ACLK_KLAD 570
+
+#endif
diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
new file mode 100644
index 00000000000..291fec0ecba
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
@@ -0,0 +1,564 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+* Copyright (c) 2024 Collabora Ltd.
+*
+* Author: Elaine Zhang <zhangqing@rock-chips.com>
+* Author: Detlev Casanova <detlev.casanova@collabora.com>
+*/
+
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
+
+#define SRST_A_TOP_BIU 0
+#define SRST_P_TOP_BIU 1
+#define SRST_A_TOP_MID_BIU 2
+#define SRST_A_SECURE_HIGH_BIU 3
+#define SRST_H_TOP_BIU 4
+
+#define SRST_H_VO0VOP_CHANNEL_BIU 5
+#define SRST_A_VO0VOP_CHANNEL_BIU 6
+
+#define SRST_BISRINTF 7
+
+#define SRST_H_AUDIO_BIU 8
+#define SRST_H_ASRC_2CH_0 9
+#define SRST_H_ASRC_2CH_1 10
+#define SRST_H_ASRC_4CH_0 11
+#define SRST_H_ASRC_4CH_1 12
+#define SRST_ASRC_2CH_0 13
+#define SRST_ASRC_2CH_1 14
+#define SRST_ASRC_4CH_0 15
+#define SRST_ASRC_4CH_1 16
+#define SRST_M_SAI0_8CH 17
+#define SRST_H_SAI0_8CH 18
+#define SRST_H_SPDIF_RX0 19
+#define SRST_M_SPDIF_RX0 20
+
+#define SRST_H_SPDIF_RX1 21
+#define SRST_M_SPDIF_RX1 22
+#define SRST_M_SAI1_8CH 23
+#define SRST_H_SAI1_8CH 24
+#define SRST_M_SAI2_2CH 25
+#define SRST_H_SAI2_2CH 26
+#define SRST_M_SAI3_2CH 27
+#define SRST_H_SAI3_2CH 28
+
+#define SRST_M_SAI4_2CH 29
+#define SRST_H_SAI4_2CH 30
+#define SRST_H_ACDCDIG_DSM 31
+#define SRST_M_ACDCDIG_DSM 32
+#define SRST_PDM1 33
+#define SRST_H_PDM1 34
+#define SRST_M_PDM1 35
+#define SRST_H_SPDIF_TX0 36
+#define SRST_M_SPDIF_TX0 37
+#define SRST_H_SPDIF_TX1 38
+#define SRST_M_SPDIF_TX1 39
+
+#define SRST_A_BUS_BIU 40
+#define SRST_P_BUS_BIU 41
+#define SRST_P_CRU 42
+#define SRST_H_CAN0 43
+#define SRST_CAN0 44
+#define SRST_H_CAN1 45
+#define SRST_CAN1 46
+#define SRST_P_INTMUX2BUS 47
+#define SRST_P_VCCIO_IOC 48
+#define SRST_H_BUS_BIU 49
+#define SRST_KEY_SHIFT 50
+
+#define SRST_P_I2C1 51
+#define SRST_P_I2C2 52
+#define SRST_P_I2C3 53
+#define SRST_P_I2C4 54
+#define SRST_P_I2C5 55
+#define SRST_P_I2C6 56
+#define SRST_P_I2C7 57
+#define SRST_P_I2C8 58
+#define SRST_P_I2C9 59
+#define SRST_P_WDT_BUSMCU 60
+#define SRST_T_WDT_BUSMCU 61
+#define SRST_A_GIC 62
+#define SRST_I2C1 63
+#define SRST_I2C2 64
+#define SRST_I2C3 65
+#define SRST_I2C4 66
+
+#define SRST_I2C5 67
+#define SRST_I2C6 68
+#define SRST_I2C7 69
+#define SRST_I2C8 70
+#define SRST_I2C9 71
+#define SRST_P_SARADC 72
+#define SRST_SARADC 73
+#define SRST_P_TSADC 74
+#define SRST_TSADC 75
+#define SRST_P_UART0 76
+#define SRST_P_UART2 77
+#define SRST_P_UART3 78
+#define SRST_P_UART4 79
+#define SRST_P_UART5 80
+#define SRST_P_UART6 81
+
+#define SRST_P_UART7 82
+#define SRST_P_UART8 83
+#define SRST_P_UART9 84
+#define SRST_P_UART10 85
+#define SRST_P_UART11 86
+#define SRST_S_UART0 87
+#define SRST_S_UART2 88
+#define SRST_S_UART3 89
+#define SRST_S_UART4 90
+#define SRST_S_UART5 91
+
+#define SRST_S_UART6 92
+#define SRST_S_UART7 93
+#define SRST_S_UART8 94
+#define SRST_S_UART9 95
+#define SRST_S_UART10 96
+#define SRST_S_UART11 97
+#define SRST_P_SPI0 98
+#define SRST_P_SPI1 99
+#define SRST_P_SPI2 100
+
+#define SRST_P_SPI3 101
+#define SRST_P_SPI4 102
+#define SRST_SPI0 103
+#define SRST_SPI1 104
+#define SRST_SPI2 105
+#define SRST_SPI3 106
+#define SRST_SPI4 107
+#define SRST_P_WDT0 108
+#define SRST_T_WDT0 109
+#define SRST_P_SYS_GRF 110
+#define SRST_P_PWM1 111
+#define SRST_PWM1 112
+
+#define SRST_P_BUSTIMER0 113
+#define SRST_P_BUSTIMER1 114
+#define SRST_TIMER0 115
+#define SRST_TIMER1 116
+#define SRST_TIMER2 117
+#define SRST_TIMER3 118
+#define SRST_TIMER4 119
+#define SRST_TIMER5 120
+#define SRST_P_BUSIOC 121
+#define SRST_P_MAILBOX0 122
+#define SRST_P_GPIO1 123
+
+#define SRST_GPIO1 124
+#define SRST_P_GPIO2 125
+#define SRST_GPIO2 126
+#define SRST_P_GPIO3 127
+#define SRST_GPIO3 128
+#define SRST_P_GPIO4 129
+#define SRST_GPIO4 130
+#define SRST_A_DECOM 131
+#define SRST_P_DECOM 132
+#define SRST_D_DECOM 133
+#define SRST_TIMER6 134
+#define SRST_TIMER7 135
+#define SRST_TIMER8 136
+#define SRST_TIMER9 137
+#define SRST_TIMER10 138
+
+#define SRST_TIMER11 139
+#define SRST_A_DMAC0 140
+#define SRST_A_DMAC1 141
+#define SRST_A_DMAC2 142
+#define SRST_A_SPINLOCK 143
+#define SRST_REF_PVTPLL_BUS 144
+#define SRST_H_I3C0 145
+#define SRST_H_I3C1 146
+#define SRST_H_BUS_CM0_BIU 147
+#define SRST_F_BUS_CM0_CORE 148
+#define SRST_T_BUS_CM0_JTAG 149
+
+#define SRST_P_INTMUX2PMU 150
+#define SRST_P_INTMUX2DDR 151
+#define SRST_P_PVTPLL_BUS 152
+#define SRST_P_PWM2 153
+#define SRST_PWM2 154
+#define SRST_FREQ_PWM1 155
+#define SRST_COUNTER_PWM1 156
+#define SRST_I3C0 157
+#define SRST_I3C1 158
+
+#define SRST_P_DDR_MON_CH0 159
+#define SRST_P_DDR_BIU 160
+#define SRST_P_DDR_UPCTL_CH0 161
+#define SRST_TM_DDR_MON_CH0 162
+#define SRST_A_DDR_BIU 163
+#define SRST_DFI_CH0 164
+#define SRST_DDR_MON_CH0 165
+#define SRST_P_DDR_HWLP_CH0 166
+#define SRST_P_DDR_MON_CH1 167
+#define SRST_P_DDR_HWLP_CH1 168
+
+#define SRST_P_DDR_UPCTL_CH1 169
+#define SRST_TM_DDR_MON_CH1 170
+#define SRST_DFI_CH1 171
+#define SRST_A_DDR01_MSCH0 172
+#define SRST_A_DDR01_MSCH1 173
+#define SRST_DDR_MON_CH1 174
+#define SRST_DDR_SCRAMBLE_CH0 175
+#define SRST_DDR_SCRAMBLE_CH1 176
+#define SRST_P_AHB2APB 177
+#define SRST_H_AHB2APB 178
+#define SRST_H_DDR_BIU 179
+#define SRST_F_DDR_CM0_CORE 180
+
+#define SRST_P_DDR01_MSCH0 181
+#define SRST_P_DDR01_MSCH1 182
+#define SRST_DDR_TIMER0 183
+#define SRST_DDR_TIMER1 184
+#define SRST_T_WDT_DDR 185
+#define SRST_P_WDT 186
+#define SRST_P_TIMER 187
+#define SRST_T_DDR_CM0_JTAG 188
+#define SRST_P_DDR_GRF 189
+
+#define SRST_DDR_UPCTL_CH0 190
+#define SRST_A_DDR_UPCTL_0_CH0 191
+#define SRST_A_DDR_UPCTL_1_CH0 192
+#define SRST_A_DDR_UPCTL_2_CH0 193
+#define SRST_A_DDR_UPCTL_3_CH0 194
+#define SRST_A_DDR_UPCTL_4_CH0 195
+
+#define SRST_DDR_UPCTL_CH1 196
+#define SRST_A_DDR_UPCTL_0_CH1 197
+#define SRST_A_DDR_UPCTL_1_CH1 198
+#define SRST_A_DDR_UPCTL_2_CH1 199
+#define SRST_A_DDR_UPCTL_3_CH1 200
+#define SRST_A_DDR_UPCTL_4_CH1 201
+
+#define SRST_REF_PVTPLL_DDR 202
+#define SRST_P_PVTPLL_DDR 203
+
+#define SRST_A_RKNN0 204
+#define SRST_A_RKNN0_BIU 205
+#define SRST_L_RKNN0_BIU 206
+
+#define SRST_A_RKNN1 207
+#define SRST_A_RKNN1_BIU 208
+#define SRST_L_RKNN1_BIU 209
+
+#define SRST_NPU_DAP 210
+#define SRST_L_NPUSUBSYS_BIU 211
+#define SRST_P_NPUTOP_BIU 212
+#define SRST_P_NPU_TIMER 213
+#define SRST_NPUTIMER0 214
+#define SRST_NPUTIMER1 215
+#define SRST_P_NPU_WDT 216
+#define SRST_T_NPU_WDT 217
+
+#define SRST_A_RKNN_CBUF 218
+#define SRST_A_RVCORE0 219
+#define SRST_P_NPU_GRF 220
+#define SRST_P_PVTPLL_NPU 221
+#define SRST_NPU_PVTPLL 222
+#define SRST_H_NPU_CM0_BIU 223
+#define SRST_F_NPU_CM0_CORE 224
+#define SRST_T_NPU_CM0_JTAG 225
+#define SRST_A_RKNNTOP_BIU 226
+#define SRST_H_RKNN_CBUF 227
+#define SRST_H_RKNNTOP_BIU 228
+
+#define SRST_H_NVM_BIU 229
+#define SRST_A_NVM_BIU 230
+#define SRST_S_FSPI 231
+#define SRST_H_FSPI 232
+#define SRST_C_EMMC 233
+#define SRST_H_EMMC 234
+#define SRST_A_EMMC 235
+#define SRST_B_EMMC 236
+#define SRST_T_EMMC 237
+
+#define SRST_P_GRF 238
+#define SRST_P_PHP_BIU 239
+#define SRST_A_PHP_BIU 240
+#define SRST_P_PCIE0 241
+#define SRST_PCIE0_POWER_UP 242
+
+#define SRST_A_USB3OTG1 243
+#define SRST_A_MMU0 244
+#define SRST_A_SLV_MMU0 245
+#define SRST_A_MMU1 246
+
+#define SRST_A_SLV_MMU1 247
+#define SRST_P_PCIE1 248
+#define SRST_PCIE1_POWER_UP 249
+
+#define SRST_RXOOB0 250
+#define SRST_RXOOB1 251
+#define SRST_PMALIVE0 252
+#define SRST_PMALIVE1 253
+#define SRST_A_SATA0 254
+#define SRST_A_SATA1 255
+#define SRST_ASIC1 256
+#define SRST_ASIC0 257
+
+#define SRST_P_CSIDPHY1 258
+#define SRST_SCAN_CSIDPHY1 259
+
+#define SRST_P_SDGMAC_GRF 260
+#define SRST_P_SDGMAC_BIU 261
+#define SRST_A_SDGMAC_BIU 262
+#define SRST_H_SDGMAC_BIU 263
+#define SRST_A_GMAC0 264
+#define SRST_A_GMAC1 265
+#define SRST_P_GMAC0 266
+#define SRST_P_GMAC1 267
+#define SRST_H_SDIO 268
+
+#define SRST_H_SDMMC0 269
+#define SRST_S_FSPI1 270
+#define SRST_H_FSPI1 271
+#define SRST_A_DSMC_BIU 272
+#define SRST_A_DSMC 273
+#define SRST_P_DSMC 274
+#define SRST_H_HSGPIO 275
+#define SRST_HSGPIO 276
+#define SRST_A_HSGPIO 277
+
+#define SRST_H_RKVDEC 278
+#define SRST_H_RKVDEC_BIU 279
+#define SRST_A_RKVDEC_BIU 280
+#define SRST_RKVDEC_HEVC_CA 281
+#define SRST_RKVDEC_CORE 282
+
+#define SRST_A_USB_BIU 283
+#define SRST_P_USBUFS_BIU 284
+#define SRST_A_USB3OTG0 285
+#define SRST_A_UFS_BIU 286
+#define SRST_A_MMU2 287
+#define SRST_A_SLV_MMU2 288
+#define SRST_A_UFS_SYS 289
+
+#define SRST_A_UFS 290
+#define SRST_P_USBUFS_GRF 291
+#define SRST_P_UFS_GRF 292
+
+#define SRST_H_VPU_BIU 293
+#define SRST_A_JPEG_BIU 294
+#define SRST_A_RGA_BIU 295
+#define SRST_A_VDPP_BIU 296
+#define SRST_A_EBC_BIU 297
+#define SRST_H_RGA2E_0 298
+#define SRST_A_RGA2E_0 299
+#define SRST_CORE_RGA2E_0 300
+
+#define SRST_A_JPEG 301
+#define SRST_H_JPEG 302
+#define SRST_H_VDPP 303
+#define SRST_A_VDPP 304
+#define SRST_CORE_VDPP 305
+#define SRST_H_RGA2E_1 306
+#define SRST_A_RGA2E_1 307
+#define SRST_CORE_RGA2E_1 308
+#define SRST_H_EBC 309
+#define SRST_A_EBC 310
+#define SRST_D_EBC 311
+
+#define SRST_H_VEPU0_BIU 312
+#define SRST_A_VEPU0_BIU 313
+#define SRST_H_VEPU0 314
+#define SRST_A_VEPU0 315
+#define SRST_VEPU0_CORE 316
+
+#define SRST_A_VI_BIU 317
+#define SRST_H_VI_BIU 318
+#define SRST_P_VI_BIU 319
+#define SRST_D_VICAP 320
+#define SRST_A_VICAP 321
+#define SRST_H_VICAP 322
+#define SRST_ISP0 323
+#define SRST_ISP0_VICAP 324
+
+#define SRST_CORE_VPSS 325
+#define SRST_P_CSI_HOST_0 326
+#define SRST_P_CSI_HOST_1 327
+#define SRST_P_CSI_HOST_2 328
+#define SRST_P_CSI_HOST_3 329
+#define SRST_P_CSI_HOST_4 330
+
+#define SRST_CIFIN 331
+#define SRST_VICAP_I0CLK 332
+#define SRST_VICAP_I1CLK 333
+#define SRST_VICAP_I2CLK 334
+#define SRST_VICAP_I3CLK 335
+#define SRST_VICAP_I4CLK 336
+
+#define SRST_A_VOP_BIU 337
+#define SRST_A_VOP2_BIU 338
+#define SRST_H_VOP_BIU 339
+#define SRST_P_VOP_BIU 340
+#define SRST_H_VOP 341
+#define SRST_A_VOP 342
+#define SRST_D_VP0 343
+
+#define SRST_D_VP1 344
+#define SRST_D_VP2 345
+#define SRST_P_VOP2_BIU 346
+#define SRST_P_VOPGRF 347
+
+#define SRST_H_VO0_BIU 348
+#define SRST_P_VO0_BIU 349
+#define SRST_A_HDCP0_BIU 350
+#define SRST_P_VO0_GRF 351
+#define SRST_A_HDCP0 352
+#define SRST_H_HDCP0 353
+#define SRST_HDCP0 354
+
+#define SRST_P_DSIHOST0 355
+#define SRST_DSIHOST0 356
+#define SRST_P_HDMITX0 357
+#define SRST_HDMITX0_REF 358
+#define SRST_P_EDP0 359
+#define SRST_EDP0_24M 360
+
+#define SRST_M_SAI5_8CH 361
+#define SRST_H_SAI5_8CH 362
+#define SRST_M_SAI6_8CH 363
+#define SRST_H_SAI6_8CH 364
+#define SRST_H_SPDIF_TX2 365
+#define SRST_M_SPDIF_TX2 366
+#define SRST_H_SPDIF_RX2 367
+#define SRST_M_SPDIF_RX2 368
+
+#define SRST_H_SAI8_8CH 369
+#define SRST_M_SAI8_8CH 370
+
+#define SRST_H_VO1_BIU 371
+#define SRST_P_VO1_BIU 372
+#define SRST_M_SAI7_8CH 373
+#define SRST_H_SAI7_8CH 374
+#define SRST_H_SPDIF_TX3 375
+#define SRST_H_SPDIF_TX4 376
+#define SRST_H_SPDIF_TX5 377
+#define SRST_M_SPDIF_TX3 378
+
+#define SRST_DP0 379
+#define SRST_P_VO1_GRF 380
+#define SRST_A_HDCP1_BIU 381
+#define SRST_A_HDCP1 382
+#define SRST_H_HDCP1 383
+#define SRST_HDCP1 384
+#define SRST_H_SAI9_8CH 385
+#define SRST_M_SAI9_8CH 386
+#define SRST_M_SPDIF_TX4 387
+#define SRST_M_SPDIF_TX5 388
+
+#define SRST_GPU 389
+#define SRST_A_S_GPU_BIU 390
+#define SRST_A_M0_GPU_BIU 391
+#define SRST_P_GPU_BIU 392
+#define SRST_P_GPU_GRF 393
+#define SRST_GPU_PVTPLL 394
+#define SRST_P_PVTPLL_GPU 395
+
+#define SRST_A_CENTER_BIU 396
+#define SRST_A_DMA2DDR 397
+#define SRST_A_DDR_SHAREMEM 398
+#define SRST_A_DDR_SHAREMEM_BIU 399
+#define SRST_H_CENTER_BIU 400
+#define SRST_P_CENTER_GRF 401
+#define SRST_P_DMA2DDR 402
+#define SRST_P_SHAREMEM 403
+#define SRST_P_CENTER_BIU 404
+
+#define SRST_LINKSYM_HDMITXPHY0 405
+
+#define SRST_DP0_PIXELCLK 406
+#define SRST_PHY_DP0_TX 407
+#define SRST_DP1_PIXELCLK 408
+#define SRST_DP2_PIXELCLK 409
+
+#define SRST_H_VEPU1_BIU 410
+#define SRST_A_VEPU1_BIU 411
+#define SRST_H_VEPU1 412
+#define SRST_A_VEPU1 413
+#define SRST_VEPU1_CORE 414
+
+#define SRST_P_PHPPHY_CRU 415
+#define SRST_P_APB2ASB_SLV_CHIP_TOP 416
+#define SRST_P_PCIE2_COMBOPHY0 417
+#define SRST_P_PCIE2_COMBOPHY0_GRF 418
+#define SRST_P_PCIE2_COMBOPHY1 419
+#define SRST_P_PCIE2_COMBOPHY1_GRF 420
+
+#define SRST_PCIE0_PIPE_PHY 421
+#define SRST_PCIE1_PIPE_PHY 422
+
+#define SRST_H_CRYPTO_NS 423
+#define SRST_H_TRNG_NS 424
+#define SRST_P_OTPC_NS 425
+#define SRST_OTPC_NS 426
+
+#define SRST_P_HDPTX_GRF 427
+#define SRST_P_HDPTX_APB 428
+#define SRST_P_MIPI_DCPHY 429
+#define SRST_P_DCPHY_GRF 430
+#define SRST_P_BOT0_APB2ASB 431
+#define SRST_P_BOT1_APB2ASB 432
+#define SRST_USB2DEBUG 433
+#define SRST_P_CSIPHY_GRF 434
+#define SRST_P_CSIPHY 435
+#define SRST_P_USBPHY_GRF_0 436
+#define SRST_P_USBPHY_GRF_1 437
+#define SRST_P_USBDP_GRF 438
+#define SRST_P_USBDPPHY 439
+#define SRST_USBDP_COMBO_PHY_INIT 440
+
+#define SRST_USBDP_COMBO_PHY_CMN 441
+#define SRST_USBDP_COMBO_PHY_LANE 442
+#define SRST_USBDP_COMBO_PHY_PCS 443
+#define SRST_M_MIPI_DCPHY 444
+#define SRST_S_MIPI_DCPHY 445
+#define SRST_SCAN_CSIPHY 446
+#define SRST_P_VCCIO6_IOC 447
+#define SRST_OTGPHY_0 448
+#define SRST_OTGPHY_1 449
+#define SRST_HDPTX_INIT 450
+#define SRST_HDPTX_CMN 451
+#define SRST_HDPTX_LANE 452
+#define SRST_HDMITXHDP 453
+
+#define SRST_MPHY_INIT 454
+#define SRST_P_MPHY_GRF 455
+#define SRST_P_VCCIO7_IOC 456
+
+#define SRST_H_PMU1_BIU 457
+#define SRST_P_PMU1_NIU 458
+#define SRST_H_PMU_CM0_BIU 459
+#define SRST_PMU_CM0_CORE 460
+#define SRST_PMU_CM0_JTAG 461
+
+#define SRST_P_CRU_PMU1 462
+#define SRST_P_PMU1_GRF 463
+#define SRST_P_PMU1_IOC 464
+#define SRST_P_PMU1WDT 465
+#define SRST_T_PMU1WDT 466
+#define SRST_P_PMUTIMER 467
+#define SRST_PMUTIMER0 468
+#define SRST_PMUTIMER1 469
+#define SRST_P_PMU1PWM 470
+#define SRST_PMU1PWM 471
+
+#define SRST_P_I2C0 472
+#define SRST_I2C0 473
+#define SRST_S_UART1 474
+#define SRST_P_UART1 475
+#define SRST_PDM0 476
+#define SRST_H_PDM0 477
+
+#define SRST_M_PDM0 478
+#define SRST_H_VAD 479
+
+#define SRST_P_PMU0GRF 480
+#define SRST_P_PMU0IOC 481
+#define SRST_P_GPIO0 482
+#define SRST_DB_GPIO0 483
+
+#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 01/20] dt-bindings: clock, reset: Add support for rk3576
2024-11-21 14:27 ` [PATCH 01/20] dt-bindings: clock, reset: Add support for rk3576 Heiko Stuebner
@ 2025-01-03 3:07 ` Kever Yang
0 siblings, 0 replies; 44+ messages in thread
From: Kever Yang @ 2025-01-03 3:07 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, quentin.schulz, detlev.casanova, u-boot, sebastian.reichel,
Elaine Zhang, Sugar Zhang, Rob Herring
On 2024/11/21 22:27, Heiko Stuebner wrote:
> From: Detlev Casanova <detlev.casanova@collabora.com>
>
> Add clock and reset ID defines for rk3576.
>
> Compared to the downstream bindings written by Elaine, this uses
> continous gapless IDs starting at 0. Thus all numbers are
> different between downstream and upstream, but names are kept
> exactly the same.
>
> Also add documentation for the rk3576 CRU core.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Link: https://lore.kernel.org/r/0102019199a76766-f3a2b53f-d063-458b-b0d1-dfbc2ea1893c-000000@eu-west-1.amazonses.com
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>
> [ upstream commit: 49c04453db81fc806906e26ef9fc53bdb635ff39 ]
>
> (cherry picked from commit 6f1c891c492348ef3cc4595f66d7fd7a4a824199)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../Bindings/clock/rockchip,rk3576-cru.yaml | 56 ++
> .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++
> .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++
> 3 files changed, 1212 insertions(+)
> create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
>
> diff --git a/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml b/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> new file mode 100644
> index 00000000000..9c9b36049c7
> --- /dev/null
> +++ b/dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> @@ -0,0 +1,56 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip rk3576 Family Clock and Reset Control Module
> +
> +maintainers:
> + - Elaine Zhang <zhangqing@rock-chips.com>
> + - Heiko Stuebner <heiko@sntech.de>
> + - Detlev Casanova <detlev.casanova@collabora.com>
> +
> +description:
> + The RK3576 clock controller generates the clock and also implements a reset
> + controller for SoC peripherals. For example it provides SCLK_UART2 and
> + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
> + module.
> +
> +properties:
> + compatible:
> + const: rockchip,rk3576-cru
> +
> + reg:
> + maxItems: 1
> +
> + "#clock-cells":
> + const: 1
> +
> + "#reset-cells":
> + const: 1
> +
> + clocks:
> + maxItems: 2
> +
> + clock-names:
> + items:
> + - const: xin24m
> + - const: xin32k
> +
> +required:
> + - compatible
> + - reg
> + - "#clock-cells"
> + - "#reset-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@27200000 {
> + compatible = "rockchip,rk3576-cru";
> + reg = <0xfd7c0000 0x5c000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> new file mode 100644
> index 00000000000..a2933021be8
> --- /dev/null
> +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> @@ -0,0 +1,592 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> +* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> +* Copyright (c) 2024 Collabora Ltd.
> +*
> +* Author: Elaine Zhang <zhangqing@rock-chips.com>
> +* Author: Detlev Casanova <detlev.casanova@collabora.com>
> +*/
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> +
> +/* cru-clocks indices */
> +
> +/* cru plls */
> +#define PLL_BPLL 0
> +#define PLL_LPLL 1
> +#define PLL_VPLL 2
> +#define PLL_AUPLL 3
> +#define PLL_CPLL 4
> +#define PLL_GPLL 5
> +#define PLL_PPLL 6
> +#define ARMCLK_L 7
> +#define ARMCLK_B 8
> +
> +/* cru clocks */
> +#define CLK_CPLL_DIV20 9
> +#define CLK_CPLL_DIV10 10
> +#define CLK_GPLL_DIV8 11
> +#define CLK_GPLL_DIV6 12
> +#define CLK_CPLL_DIV4 13
> +#define CLK_GPLL_DIV4 14
> +#define CLK_SPLL_DIV2 15
> +#define CLK_GPLL_DIV3 16
> +#define CLK_CPLL_DIV2 17
> +#define CLK_GPLL_DIV2 18
> +#define CLK_SPLL_DIV1 19
> +#define PCLK_TOP_ROOT 20
> +#define ACLK_TOP 21
> +#define HCLK_TOP 22
> +#define CLK_AUDIO_FRAC_0 23
> +#define CLK_AUDIO_FRAC_1 24
> +#define CLK_AUDIO_FRAC_2 25
> +#define CLK_AUDIO_FRAC_3 26
> +#define CLK_UART_FRAC_0 27
> +#define CLK_UART_FRAC_1 28
> +#define CLK_UART_FRAC_2 29
> +#define CLK_UART1_SRC_TOP 30
> +#define CLK_AUDIO_INT_0 31
> +#define CLK_AUDIO_INT_1 32
> +#define CLK_AUDIO_INT_2 33
> +#define CLK_PDM0_SRC_TOP 34
> +#define CLK_PDM1_OUT 35
> +#define CLK_GMAC0_125M_SRC 36
> +#define CLK_GMAC1_125M_SRC 37
> +#define LCLK_ASRC_SRC_0 38
> +#define LCLK_ASRC_SRC_1 39
> +#define REF_CLK0_OUT_PLL 40
> +#define REF_CLK1_OUT_PLL 41
> +#define REF_CLK2_OUT_PLL 42
> +#define REFCLKO25M_GMAC0_OUT 43
> +#define REFCLKO25M_GMAC1_OUT 44
> +#define CLK_CIFOUT_OUT 45
> +#define CLK_GMAC0_RMII_CRU 46
> +#define CLK_GMAC1_RMII_CRU 47
> +#define CLK_OTPC_AUTO_RD_G 48
> +#define CLK_OTP_PHY_G 49
> +#define CLK_MIPI_CAMERAOUT_M0 50
> +#define CLK_MIPI_CAMERAOUT_M1 51
> +#define CLK_MIPI_CAMERAOUT_M2 52
> +#define MCLK_PDM0_SRC_TOP 53
> +#define HCLK_AUDIO_ROOT 54
> +#define HCLK_ASRC_2CH_0 55
> +#define HCLK_ASRC_2CH_1 56
> +#define HCLK_ASRC_4CH_0 57
> +#define HCLK_ASRC_4CH_1 58
> +#define CLK_ASRC_2CH_0 59
> +#define CLK_ASRC_2CH_1 60
> +#define CLK_ASRC_4CH_0 61
> +#define CLK_ASRC_4CH_1 62
> +#define MCLK_SAI0_8CH_SRC 63
> +#define MCLK_SAI0_8CH 64
> +#define HCLK_SAI0_8CH 65
> +#define HCLK_SPDIF_RX0 66
> +#define MCLK_SPDIF_RX0 67
> +#define HCLK_SPDIF_RX1 68
> +#define MCLK_SPDIF_RX1 69
> +#define MCLK_SAI1_8CH_SRC 70
> +#define MCLK_SAI1_8CH 71
> +#define HCLK_SAI1_8CH 72
> +#define MCLK_SAI2_2CH_SRC 73
> +#define MCLK_SAI2_2CH 74
> +#define HCLK_SAI2_2CH 75
> +#define MCLK_SAI3_2CH_SRC 76
> +#define MCLK_SAI3_2CH 77
> +#define HCLK_SAI3_2CH 78
> +#define MCLK_SAI4_2CH_SRC 79
> +#define MCLK_SAI4_2CH 80
> +#define HCLK_SAI4_2CH 81
> +#define HCLK_ACDCDIG_DSM 82
> +#define MCLK_ACDCDIG_DSM 83
> +#define CLK_PDM1 84
> +#define HCLK_PDM1 85
> +#define MCLK_PDM1 86
> +#define HCLK_SPDIF_TX0 87
> +#define MCLK_SPDIF_TX0 88
> +#define HCLK_SPDIF_TX1 89
> +#define MCLK_SPDIF_TX1 90
> +#define CLK_SAI1_MCLKOUT 91
> +#define CLK_SAI2_MCLKOUT 92
> +#define CLK_SAI3_MCLKOUT 93
> +#define CLK_SAI4_MCLKOUT 94
> +#define CLK_SAI0_MCLKOUT 95
> +#define HCLK_BUS_ROOT 96
> +#define PCLK_BUS_ROOT 97
> +#define ACLK_BUS_ROOT 98
> +#define HCLK_CAN0 99
> +#define CLK_CAN0 100
> +#define HCLK_CAN1 101
> +#define CLK_CAN1 102
> +#define CLK_KEY_SHIFT 103
> +#define PCLK_I2C1 104
> +#define PCLK_I2C2 105
> +#define PCLK_I2C3 106
> +#define PCLK_I2C4 107
> +#define PCLK_I2C5 108
> +#define PCLK_I2C6 109
> +#define PCLK_I2C7 110
> +#define PCLK_I2C8 111
> +#define PCLK_I2C9 112
> +#define PCLK_WDT_BUSMCU 113
> +#define TCLK_WDT_BUSMCU 114
> +#define ACLK_GIC 115
> +#define CLK_I2C1 116
> +#define CLK_I2C2 117
> +#define CLK_I2C3 118
> +#define CLK_I2C4 119
> +#define CLK_I2C5 120
> +#define CLK_I2C6 121
> +#define CLK_I2C7 122
> +#define CLK_I2C8 123
> +#define CLK_I2C9 124
> +#define PCLK_SARADC 125
> +#define CLK_SARADC 126
> +#define PCLK_TSADC 127
> +#define CLK_TSADC 128
> +#define PCLK_UART0 129
> +#define PCLK_UART2 130
> +#define PCLK_UART3 131
> +#define PCLK_UART4 132
> +#define PCLK_UART5 133
> +#define PCLK_UART6 134
> +#define PCLK_UART7 135
> +#define PCLK_UART8 136
> +#define PCLK_UART9 137
> +#define PCLK_UART10 138
> +#define PCLK_UART11 139
> +#define SCLK_UART0 140
> +#define SCLK_UART2 141
> +#define SCLK_UART3 142
> +#define SCLK_UART4 143
> +#define SCLK_UART5 144
> +#define SCLK_UART6 145
> +#define SCLK_UART7 146
> +#define SCLK_UART8 147
> +#define SCLK_UART9 148
> +#define SCLK_UART10 149
> +#define SCLK_UART11 150
> +#define PCLK_SPI0 151
> +#define PCLK_SPI1 152
> +#define PCLK_SPI2 153
> +#define PCLK_SPI3 154
> +#define PCLK_SPI4 155
> +#define CLK_SPI0 156
> +#define CLK_SPI1 157
> +#define CLK_SPI2 158
> +#define CLK_SPI3 159
> +#define CLK_SPI4 160
> +#define PCLK_WDT0 161
> +#define TCLK_WDT0 162
> +#define PCLK_PWM1 163
> +#define CLK_PWM1 164
> +#define CLK_OSC_PWM1 165
> +#define CLK_RC_PWM1 166
> +#define PCLK_BUSTIMER0 167
> +#define PCLK_BUSTIMER1 168
> +#define CLK_TIMER0_ROOT 169
> +#define CLK_TIMER0 170
> +#define CLK_TIMER1 171
> +#define CLK_TIMER2 172
> +#define CLK_TIMER3 173
> +#define CLK_TIMER4 174
> +#define CLK_TIMER5 175
> +#define PCLK_MAILBOX0 176
> +#define PCLK_GPIO1 177
> +#define DBCLK_GPIO1 178
> +#define PCLK_GPIO2 179
> +#define DBCLK_GPIO2 180
> +#define PCLK_GPIO3 181
> +#define DBCLK_GPIO3 182
> +#define PCLK_GPIO4 183
> +#define DBCLK_GPIO4 184
> +#define ACLK_DECOM 185
> +#define PCLK_DECOM 186
> +#define DCLK_DECOM 187
> +#define CLK_TIMER1_ROOT 188
> +#define CLK_TIMER6 189
> +#define CLK_TIMER7 190
> +#define CLK_TIMER8 191
> +#define CLK_TIMER9 192
> +#define CLK_TIMER10 193
> +#define CLK_TIMER11 194
> +#define ACLK_DMAC0 195
> +#define ACLK_DMAC1 196
> +#define ACLK_DMAC2 197
> +#define ACLK_SPINLOCK 198
> +#define HCLK_I3C0 199
> +#define HCLK_I3C1 200
> +#define HCLK_BUS_CM0_ROOT 201
> +#define FCLK_BUS_CM0_CORE 202
> +#define CLK_BUS_CM0_RTC 203
> +#define PCLK_PMU2 204
> +#define PCLK_PWM2 205
> +#define CLK_PWM2 206
> +#define CLK_RC_PWM2 207
> +#define CLK_OSC_PWM2 208
> +#define CLK_FREQ_PWM1 209
> +#define CLK_COUNTER_PWM1 210
> +#define SAI_SCLKIN_FREQ 211
> +#define SAI_SCLKIN_COUNTER 212
> +#define CLK_I3C0 213
> +#define CLK_I3C1 214
> +#define PCLK_CSIDPHY1 215
> +#define PCLK_DDR_ROOT 216
> +#define PCLK_DDR_MON_CH0 217
> +#define TMCLK_DDR_MON_CH0 218
> +#define ACLK_DDR_ROOT 219
> +#define HCLK_DDR_ROOT 220
> +#define FCLK_DDR_CM0_CORE 221
> +#define CLK_DDR_TIMER_ROOT 222
> +#define CLK_DDR_TIMER0 223
> +#define CLK_DDR_TIMER1 224
> +#define TCLK_WDT_DDR 225
> +#define PCLK_WDT 226
> +#define PCLK_TIMER 227
> +#define CLK_DDR_CM0_RTC 228
> +#define ACLK_RKNN0 229
> +#define ACLK_RKNN1 230
> +#define HCLK_RKNN_ROOT 231
> +#define CLK_RKNN_DSU0 232
> +#define PCLK_NPUTOP_ROOT 233
> +#define PCLK_NPU_TIMER 234
> +#define CLK_NPUTIMER_ROOT 235
> +#define CLK_NPUTIMER0 236
> +#define CLK_NPUTIMER1 237
> +#define PCLK_NPU_WDT 238
> +#define TCLK_NPU_WDT 239
> +#define ACLK_RKNN_CBUF 240
> +#define HCLK_NPU_CM0_ROOT 241
> +#define FCLK_NPU_CM0_CORE 242
> +#define CLK_NPU_CM0_RTC 243
> +#define HCLK_RKNN_CBUF 244
> +#define HCLK_NVM_ROOT 245
> +#define ACLK_NVM_ROOT 246
> +#define SCLK_FSPI_X2 247
> +#define HCLK_FSPI 248
> +#define CCLK_SRC_EMMC 249
> +#define HCLK_EMMC 250
> +#define ACLK_EMMC 251
> +#define BCLK_EMMC 252
> +#define TCLK_EMMC 253
> +#define PCLK_PHP_ROOT 254
> +#define ACLK_PHP_ROOT 255
> +#define PCLK_PCIE0 256
> +#define CLK_PCIE0_AUX 257
> +#define ACLK_PCIE0_MST 258
> +#define ACLK_PCIE0_SLV 259
> +#define ACLK_PCIE0_DBI 260
> +#define ACLK_USB3OTG1 261
> +#define CLK_REF_USB3OTG1 262
> +#define CLK_SUSPEND_USB3OTG1 263
> +#define ACLK_MMU0 264
> +#define ACLK_SLV_MMU0 265
> +#define ACLK_MMU1 266
> +#define ACLK_SLV_MMU1 267
> +#define PCLK_PCIE1 268
> +#define CLK_PCIE1_AUX 269
> +#define ACLK_PCIE1_MST 270
> +#define ACLK_PCIE1_SLV 271
> +#define ACLK_PCIE1_DBI 272
> +#define CLK_RXOOB0 273
> +#define CLK_RXOOB1 274
> +#define CLK_PMALIVE0 275
> +#define CLK_PMALIVE1 276
> +#define ACLK_SATA0 277
> +#define ACLK_SATA1 278
> +#define CLK_USB3OTG1_PIPE_PCLK 279
> +#define CLK_USB3OTG1_UTMI 280
> +#define CLK_USB3OTG0_PIPE_PCLK 281
> +#define CLK_USB3OTG0_UTMI 282
> +#define HCLK_SDGMAC_ROOT 283
> +#define ACLK_SDGMAC_ROOT 284
> +#define PCLK_SDGMAC_ROOT 285
> +#define ACLK_GMAC0 286
> +#define ACLK_GMAC1 287
> +#define PCLK_GMAC0 288
> +#define PCLK_GMAC1 289
> +#define CCLK_SRC_SDIO 290
> +#define HCLK_SDIO 291
> +#define CLK_GMAC1_PTP_REF 292
> +#define CLK_GMAC0_PTP_REF 293
> +#define CLK_GMAC1_PTP_REF_SRC 294
> +#define CLK_GMAC0_PTP_REF_SRC 295
> +#define CCLK_SRC_SDMMC0 296
> +#define HCLK_SDMMC0 297
> +#define SCLK_FSPI1_X2 298
> +#define HCLK_FSPI1 299
> +#define ACLK_DSMC_ROOT 300
> +#define ACLK_DSMC 301
> +#define PCLK_DSMC 302
> +#define CLK_DSMC_SYS 303
> +#define HCLK_HSGPIO 304
> +#define CLK_HSGPIO_TX 305
> +#define CLK_HSGPIO_RX 306
> +#define ACLK_HSGPIO 307
> +#define PCLK_PHPPHY_ROOT 308
> +#define PCLK_PCIE2_COMBOPHY0 309
> +#define PCLK_PCIE2_COMBOPHY1 310
> +#define CLK_PCIE_100M_SRC 311
> +#define CLK_PCIE_100M_NDUTY_SRC 312
> +#define CLK_REF_PCIE0_PHY 313
> +#define CLK_REF_PCIE1_PHY 314
> +#define CLK_REF_MPHY_26M 315
> +#define HCLK_RKVDEC_ROOT 316
> +#define ACLK_RKVDEC_ROOT 317
> +#define HCLK_RKVDEC 318
> +#define CLK_RKVDEC_HEVC_CA 319
> +#define CLK_RKVDEC_CORE 320
> +#define ACLK_UFS_ROOT 321
> +#define ACLK_USB_ROOT 322
> +#define PCLK_USB_ROOT 323
> +#define ACLK_USB3OTG0 324
> +#define CLK_REF_USB3OTG0 325
> +#define CLK_SUSPEND_USB3OTG0 326
> +#define ACLK_MMU2 327
> +#define ACLK_SLV_MMU2 328
> +#define ACLK_UFS_SYS 329
> +#define ACLK_VPU_ROOT 330
> +#define ACLK_VPU_MID_ROOT 331
> +#define HCLK_VPU_ROOT 332
> +#define ACLK_JPEG_ROOT 333
> +#define ACLK_VPU_LOW_ROOT 334
> +#define HCLK_RGA2E_0 335
> +#define ACLK_RGA2E_0 336
> +#define CLK_CORE_RGA2E_0 337
> +#define ACLK_JPEG 338
> +#define HCLK_JPEG 339
> +#define HCLK_VDPP 340
> +#define ACLK_VDPP 341
> +#define CLK_CORE_VDPP 342
> +#define HCLK_RGA2E_1 343
> +#define ACLK_RGA2E_1 344
> +#define CLK_CORE_RGA2E_1 345
> +#define DCLK_EBC_FRAC_SRC 346
> +#define HCLK_EBC 347
> +#define ACLK_EBC 348
> +#define DCLK_EBC 349
> +#define HCLK_VEPU0_ROOT 350
> +#define ACLK_VEPU0_ROOT 351
> +#define HCLK_VEPU0 352
> +#define ACLK_VEPU0 353
> +#define CLK_VEPU0_CORE 354
> +#define ACLK_VI_ROOT 355
> +#define HCLK_VI_ROOT 356
> +#define PCLK_VI_ROOT 357
> +#define DCLK_VICAP 358
> +#define ACLK_VICAP 359
> +#define HCLK_VICAP 360
> +#define CLK_ISP_CORE 361
> +#define CLK_ISP_CORE_MARVIN 362
> +#define CLK_ISP_CORE_VICAP 363
> +#define ACLK_ISP 364
> +#define HCLK_ISP 365
> +#define ACLK_VPSS 366
> +#define HCLK_VPSS 367
> +#define CLK_CORE_VPSS 368
> +#define PCLK_CSI_HOST_0 369
> +#define PCLK_CSI_HOST_1 370
> +#define PCLK_CSI_HOST_2 371
> +#define PCLK_CSI_HOST_3 372
> +#define PCLK_CSI_HOST_4 373
> +#define ICLK_CSIHOST01 374
> +#define ICLK_CSIHOST0 375
> +#define CLK_ISP_PVTPLL_SRC 376
> +#define ACLK_VI_ROOT_INTER 377
> +#define CLK_VICAP_I0CLK 378
> +#define CLK_VICAP_I1CLK 379
> +#define CLK_VICAP_I2CLK 380
> +#define CLK_VICAP_I3CLK 381
> +#define CLK_VICAP_I4CLK 382
> +#define ACLK_VOP_ROOT 383
> +#define HCLK_VOP_ROOT 384
> +#define PCLK_VOP_ROOT 385
> +#define HCLK_VOP 386
> +#define ACLK_VOP 387
> +#define DCLK_VP0_SRC 388
> +#define DCLK_VP1_SRC 389
> +#define DCLK_VP2_SRC 390
> +#define DCLK_VP0 391
> +#define DCLK_VP1 392
> +#define DCLK_VP2 393
> +#define PCLK_VOPGRF 394
> +#define ACLK_VO0_ROOT 395
> +#define HCLK_VO0_ROOT 396
> +#define PCLK_VO0_ROOT 397
> +#define PCLK_VO0_GRF 398
> +#define ACLK_HDCP0 399
> +#define HCLK_HDCP0 400
> +#define PCLK_HDCP0 401
> +#define CLK_TRNG0_SKP 402
> +#define PCLK_DSIHOST0 403
> +#define CLK_DSIHOST0 404
> +#define PCLK_HDMITX0 405
> +#define CLK_HDMITX0_EARC 406
> +#define CLK_HDMITX0_REF 407
> +#define PCLK_EDP0 408
> +#define CLK_EDP0_24M 409
> +#define CLK_EDP0_200M 410
> +#define MCLK_SAI5_8CH_SRC 411
> +#define MCLK_SAI5_8CH 412
> +#define HCLK_SAI5_8CH 413
> +#define MCLK_SAI6_8CH_SRC 414
> +#define MCLK_SAI6_8CH 415
> +#define HCLK_SAI6_8CH 416
> +#define HCLK_SPDIF_TX2 417
> +#define MCLK_SPDIF_TX2 418
> +#define HCLK_SPDIF_RX2 419
> +#define MCLK_SPDIF_RX2 420
> +#define HCLK_SAI8_8CH 421
> +#define MCLK_SAI8_8CH_SRC 422
> +#define MCLK_SAI8_8CH 423
> +#define ACLK_VO1_ROOT 424
> +#define HCLK_VO1_ROOT 425
> +#define PCLK_VO1_ROOT 426
> +#define MCLK_SAI7_8CH_SRC 427
> +#define MCLK_SAI7_8CH 428
> +#define HCLK_SAI7_8CH 429
> +#define HCLK_SPDIF_TX3 430
> +#define HCLK_SPDIF_TX4 431
> +#define HCLK_SPDIF_TX5 432
> +#define MCLK_SPDIF_TX3 433
> +#define CLK_AUX16MHZ_0 434
> +#define ACLK_DP0 435
> +#define PCLK_DP0 436
> +#define PCLK_VO1_GRF 437
> +#define ACLK_HDCP1 438
> +#define HCLK_HDCP1 439
> +#define PCLK_HDCP1 440
> +#define CLK_TRNG1_SKP 441
> +#define HCLK_SAI9_8CH 442
> +#define MCLK_SAI9_8CH_SRC 443
> +#define MCLK_SAI9_8CH 444
> +#define MCLK_SPDIF_TX4 445
> +#define MCLK_SPDIF_TX5 446
> +#define CLK_GPU_SRC_PRE 447
> +#define CLK_GPU 448
> +#define PCLK_GPU_ROOT 449
> +#define ACLK_CENTER_ROOT 450
> +#define ACLK_CENTER_LOW_ROOT 451
> +#define HCLK_CENTER_ROOT 452
> +#define PCLK_CENTER_ROOT 453
> +#define ACLK_DMA2DDR 454
> +#define ACLK_DDR_SHAREMEM 455
> +#define PCLK_DMA2DDR 456
> +#define PCLK_SHAREMEM 457
> +#define HCLK_VEPU1_ROOT 458
> +#define ACLK_VEPU1_ROOT 459
> +#define HCLK_VEPU1 460
> +#define ACLK_VEPU1 461
> +#define CLK_VEPU1_CORE 462
> +#define CLK_JDBCK_DAP 463
> +#define PCLK_MIPI_DCPHY 464
> +#define CLK_32K_USB2DEBUG 465
> +#define PCLK_CSIDPHY 466
> +#define PCLK_USBDPPHY 467
> +#define CLK_PMUPHY_REF_SRC 468
> +#define CLK_USBDP_COMBO_PHY_IMMORTAL 469
> +#define CLK_HDMITXHDP 470
> +#define PCLK_MPHY 471
> +#define CLK_REF_OSC_MPHY 472
> +#define CLK_REF_UFS_CLKOUT 473
> +#define HCLK_PMU1_ROOT 474
> +#define HCLK_PMU_CM0_ROOT 475
> +#define CLK_200M_PMU_SRC 476
> +#define CLK_100M_PMU_SRC 477
> +#define CLK_50M_PMU_SRC 478
> +#define FCLK_PMU_CM0_CORE 479
> +#define CLK_PMU_CM0_RTC 480
> +#define PCLK_PMU1 481
> +#define CLK_PMU1 482
> +#define PCLK_PMU1WDT 483
> +#define TCLK_PMU1WDT 484
> +#define PCLK_PMUTIMER 485
> +#define CLK_PMUTIMER_ROOT 486
> +#define CLK_PMUTIMER0 487
> +#define CLK_PMUTIMER1 488
> +#define PCLK_PMU1PWM 489
> +#define CLK_PMU1PWM 490
> +#define CLK_PMU1PWM_OSC 491
> +#define PCLK_PMUPHY_ROOT 492
> +#define PCLK_I2C0 493
> +#define CLK_I2C0 494
> +#define SCLK_UART1 495
> +#define PCLK_UART1 496
> +#define CLK_PMU1PWM_RC 497
> +#define CLK_PDM0 498
> +#define HCLK_PDM0 499
> +#define MCLK_PDM0 500
> +#define HCLK_VAD 501
> +#define CLK_OSCCHK_PVTM 502
> +#define CLK_PDM0_OUT 503
> +#define CLK_HPTIMER_SRC 504
> +#define PCLK_PMU0_ROOT 505
> +#define PCLK_PMU0 506
> +#define PCLK_GPIO0 507
> +#define DBCLK_GPIO0 508
> +#define CLK_OSC0_PMU1 509
> +#define PCLK_PMU1_ROOT 510
> +#define XIN_OSC0_DIV 511
> +#define ACLK_USB 512
> +#define ACLK_UFS 513
> +#define ACLK_SDGMAC 514
> +#define HCLK_SDGMAC 515
> +#define PCLK_SDGMAC 516
> +#define HCLK_VO1 517
> +#define HCLK_VO0 518
> +#define PCLK_CCI_ROOT 519
> +#define ACLK_CCI_ROOT 520
> +#define HCLK_VO0VOP_CHANNEL 521
> +#define ACLK_VO0VOP_CHANNEL 522
> +#define ACLK_TOP_MID 523
> +#define ACLK_SECURE_HIGH 524
> +#define CLK_USBPHY_REF_SRC 525
> +#define CLK_PHY_REF_SRC 526
> +#define CLK_CPLL_REF_SRC 527
> +#define CLK_AUPLL_REF_SRC 528
> +#define PCLK_SECURE_NS 529
> +#define HCLK_SECURE_NS 530
> +#define ACLK_SECURE_NS 531
> +#define PCLK_OTPC_NS 532
> +#define HCLK_CRYPTO_NS 533
> +#define HCLK_TRNG_NS 534
> +#define CLK_OTPC_NS 535
> +#define SCLK_DSU 536
> +#define SCLK_DDR 537
> +#define ACLK_CRYPTO_NS 538
> +#define CLK_PKA_CRYPTO_NS 539
> +#define ACLK_RKVDEC_ROOT_BAK 540
> +#define CLK_AUDIO_FRAC_0_SRC 541
> +#define CLK_AUDIO_FRAC_1_SRC 542
> +#define CLK_AUDIO_FRAC_2_SRC 543
> +#define CLK_AUDIO_FRAC_3_SRC 544
> +#define PCLK_HDPTX_APB 545
> +
> +/* secure clk */
> +#define CLK_STIMER0_ROOT 546
> +#define CLK_STIMER1_ROOT 547
> +#define PCLK_SECURE_S 548
> +#define HCLK_SECURE_S 549
> +#define ACLK_SECURE_S 550
> +#define CLK_PKA_CRYPTO_S 551
> +#define HCLK_VO1_S 552
> +#define PCLK_VO1_S 553
> +#define HCLK_VO0_S 554
> +#define PCLK_VO0_S 555
> +#define PCLK_KLAD 556
> +#define HCLK_CRYPTO_S 557
> +#define HCLK_KLAD 558
> +#define ACLK_CRYPTO_S 559
> +#define HCLK_TRNG_S 560
> +#define PCLK_OTPC_S 561
> +#define CLK_OTPC_S 562
> +#define PCLK_WDT_S 563
> +#define TCLK_WDT_S 564
> +#define PCLK_HDCP0_TRNG 565
> +#define PCLK_HDCP1_TRNG 566
> +#define HCLK_HDCP_KEY0 567
> +#define HCLK_HDCP_KEY1 568
> +#define PCLK_EDP_S 569
> +#define ACLK_KLAD 570
> +
> +#endif
> diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> new file mode 100644
> index 00000000000..291fec0ecba
> --- /dev/null
> +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> @@ -0,0 +1,564 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> +* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> +* Copyright (c) 2024 Collabora Ltd.
> +*
> +* Author: Elaine Zhang <zhangqing@rock-chips.com>
> +* Author: Detlev Casanova <detlev.casanova@collabora.com>
> +*/
> +
> +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
> +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
> +
> +#define SRST_A_TOP_BIU 0
> +#define SRST_P_TOP_BIU 1
> +#define SRST_A_TOP_MID_BIU 2
> +#define SRST_A_SECURE_HIGH_BIU 3
> +#define SRST_H_TOP_BIU 4
> +
> +#define SRST_H_VO0VOP_CHANNEL_BIU 5
> +#define SRST_A_VO0VOP_CHANNEL_BIU 6
> +
> +#define SRST_BISRINTF 7
> +
> +#define SRST_H_AUDIO_BIU 8
> +#define SRST_H_ASRC_2CH_0 9
> +#define SRST_H_ASRC_2CH_1 10
> +#define SRST_H_ASRC_4CH_0 11
> +#define SRST_H_ASRC_4CH_1 12
> +#define SRST_ASRC_2CH_0 13
> +#define SRST_ASRC_2CH_1 14
> +#define SRST_ASRC_4CH_0 15
> +#define SRST_ASRC_4CH_1 16
> +#define SRST_M_SAI0_8CH 17
> +#define SRST_H_SAI0_8CH 18
> +#define SRST_H_SPDIF_RX0 19
> +#define SRST_M_SPDIF_RX0 20
> +
> +#define SRST_H_SPDIF_RX1 21
> +#define SRST_M_SPDIF_RX1 22
> +#define SRST_M_SAI1_8CH 23
> +#define SRST_H_SAI1_8CH 24
> +#define SRST_M_SAI2_2CH 25
> +#define SRST_H_SAI2_2CH 26
> +#define SRST_M_SAI3_2CH 27
> +#define SRST_H_SAI3_2CH 28
> +
> +#define SRST_M_SAI4_2CH 29
> +#define SRST_H_SAI4_2CH 30
> +#define SRST_H_ACDCDIG_DSM 31
> +#define SRST_M_ACDCDIG_DSM 32
> +#define SRST_PDM1 33
> +#define SRST_H_PDM1 34
> +#define SRST_M_PDM1 35
> +#define SRST_H_SPDIF_TX0 36
> +#define SRST_M_SPDIF_TX0 37
> +#define SRST_H_SPDIF_TX1 38
> +#define SRST_M_SPDIF_TX1 39
> +
> +#define SRST_A_BUS_BIU 40
> +#define SRST_P_BUS_BIU 41
> +#define SRST_P_CRU 42
> +#define SRST_H_CAN0 43
> +#define SRST_CAN0 44
> +#define SRST_H_CAN1 45
> +#define SRST_CAN1 46
> +#define SRST_P_INTMUX2BUS 47
> +#define SRST_P_VCCIO_IOC 48
> +#define SRST_H_BUS_BIU 49
> +#define SRST_KEY_SHIFT 50
> +
> +#define SRST_P_I2C1 51
> +#define SRST_P_I2C2 52
> +#define SRST_P_I2C3 53
> +#define SRST_P_I2C4 54
> +#define SRST_P_I2C5 55
> +#define SRST_P_I2C6 56
> +#define SRST_P_I2C7 57
> +#define SRST_P_I2C8 58
> +#define SRST_P_I2C9 59
> +#define SRST_P_WDT_BUSMCU 60
> +#define SRST_T_WDT_BUSMCU 61
> +#define SRST_A_GIC 62
> +#define SRST_I2C1 63
> +#define SRST_I2C2 64
> +#define SRST_I2C3 65
> +#define SRST_I2C4 66
> +
> +#define SRST_I2C5 67
> +#define SRST_I2C6 68
> +#define SRST_I2C7 69
> +#define SRST_I2C8 70
> +#define SRST_I2C9 71
> +#define SRST_P_SARADC 72
> +#define SRST_SARADC 73
> +#define SRST_P_TSADC 74
> +#define SRST_TSADC 75
> +#define SRST_P_UART0 76
> +#define SRST_P_UART2 77
> +#define SRST_P_UART3 78
> +#define SRST_P_UART4 79
> +#define SRST_P_UART5 80
> +#define SRST_P_UART6 81
> +
> +#define SRST_P_UART7 82
> +#define SRST_P_UART8 83
> +#define SRST_P_UART9 84
> +#define SRST_P_UART10 85
> +#define SRST_P_UART11 86
> +#define SRST_S_UART0 87
> +#define SRST_S_UART2 88
> +#define SRST_S_UART3 89
> +#define SRST_S_UART4 90
> +#define SRST_S_UART5 91
> +
> +#define SRST_S_UART6 92
> +#define SRST_S_UART7 93
> +#define SRST_S_UART8 94
> +#define SRST_S_UART9 95
> +#define SRST_S_UART10 96
> +#define SRST_S_UART11 97
> +#define SRST_P_SPI0 98
> +#define SRST_P_SPI1 99
> +#define SRST_P_SPI2 100
> +
> +#define SRST_P_SPI3 101
> +#define SRST_P_SPI4 102
> +#define SRST_SPI0 103
> +#define SRST_SPI1 104
> +#define SRST_SPI2 105
> +#define SRST_SPI3 106
> +#define SRST_SPI4 107
> +#define SRST_P_WDT0 108
> +#define SRST_T_WDT0 109
> +#define SRST_P_SYS_GRF 110
> +#define SRST_P_PWM1 111
> +#define SRST_PWM1 112
> +
> +#define SRST_P_BUSTIMER0 113
> +#define SRST_P_BUSTIMER1 114
> +#define SRST_TIMER0 115
> +#define SRST_TIMER1 116
> +#define SRST_TIMER2 117
> +#define SRST_TIMER3 118
> +#define SRST_TIMER4 119
> +#define SRST_TIMER5 120
> +#define SRST_P_BUSIOC 121
> +#define SRST_P_MAILBOX0 122
> +#define SRST_P_GPIO1 123
> +
> +#define SRST_GPIO1 124
> +#define SRST_P_GPIO2 125
> +#define SRST_GPIO2 126
> +#define SRST_P_GPIO3 127
> +#define SRST_GPIO3 128
> +#define SRST_P_GPIO4 129
> +#define SRST_GPIO4 130
> +#define SRST_A_DECOM 131
> +#define SRST_P_DECOM 132
> +#define SRST_D_DECOM 133
> +#define SRST_TIMER6 134
> +#define SRST_TIMER7 135
> +#define SRST_TIMER8 136
> +#define SRST_TIMER9 137
> +#define SRST_TIMER10 138
> +
> +#define SRST_TIMER11 139
> +#define SRST_A_DMAC0 140
> +#define SRST_A_DMAC1 141
> +#define SRST_A_DMAC2 142
> +#define SRST_A_SPINLOCK 143
> +#define SRST_REF_PVTPLL_BUS 144
> +#define SRST_H_I3C0 145
> +#define SRST_H_I3C1 146
> +#define SRST_H_BUS_CM0_BIU 147
> +#define SRST_F_BUS_CM0_CORE 148
> +#define SRST_T_BUS_CM0_JTAG 149
> +
> +#define SRST_P_INTMUX2PMU 150
> +#define SRST_P_INTMUX2DDR 151
> +#define SRST_P_PVTPLL_BUS 152
> +#define SRST_P_PWM2 153
> +#define SRST_PWM2 154
> +#define SRST_FREQ_PWM1 155
> +#define SRST_COUNTER_PWM1 156
> +#define SRST_I3C0 157
> +#define SRST_I3C1 158
> +
> +#define SRST_P_DDR_MON_CH0 159
> +#define SRST_P_DDR_BIU 160
> +#define SRST_P_DDR_UPCTL_CH0 161
> +#define SRST_TM_DDR_MON_CH0 162
> +#define SRST_A_DDR_BIU 163
> +#define SRST_DFI_CH0 164
> +#define SRST_DDR_MON_CH0 165
> +#define SRST_P_DDR_HWLP_CH0 166
> +#define SRST_P_DDR_MON_CH1 167
> +#define SRST_P_DDR_HWLP_CH1 168
> +
> +#define SRST_P_DDR_UPCTL_CH1 169
> +#define SRST_TM_DDR_MON_CH1 170
> +#define SRST_DFI_CH1 171
> +#define SRST_A_DDR01_MSCH0 172
> +#define SRST_A_DDR01_MSCH1 173
> +#define SRST_DDR_MON_CH1 174
> +#define SRST_DDR_SCRAMBLE_CH0 175
> +#define SRST_DDR_SCRAMBLE_CH1 176
> +#define SRST_P_AHB2APB 177
> +#define SRST_H_AHB2APB 178
> +#define SRST_H_DDR_BIU 179
> +#define SRST_F_DDR_CM0_CORE 180
> +
> +#define SRST_P_DDR01_MSCH0 181
> +#define SRST_P_DDR01_MSCH1 182
> +#define SRST_DDR_TIMER0 183
> +#define SRST_DDR_TIMER1 184
> +#define SRST_T_WDT_DDR 185
> +#define SRST_P_WDT 186
> +#define SRST_P_TIMER 187
> +#define SRST_T_DDR_CM0_JTAG 188
> +#define SRST_P_DDR_GRF 189
> +
> +#define SRST_DDR_UPCTL_CH0 190
> +#define SRST_A_DDR_UPCTL_0_CH0 191
> +#define SRST_A_DDR_UPCTL_1_CH0 192
> +#define SRST_A_DDR_UPCTL_2_CH0 193
> +#define SRST_A_DDR_UPCTL_3_CH0 194
> +#define SRST_A_DDR_UPCTL_4_CH0 195
> +
> +#define SRST_DDR_UPCTL_CH1 196
> +#define SRST_A_DDR_UPCTL_0_CH1 197
> +#define SRST_A_DDR_UPCTL_1_CH1 198
> +#define SRST_A_DDR_UPCTL_2_CH1 199
> +#define SRST_A_DDR_UPCTL_3_CH1 200
> +#define SRST_A_DDR_UPCTL_4_CH1 201
> +
> +#define SRST_REF_PVTPLL_DDR 202
> +#define SRST_P_PVTPLL_DDR 203
> +
> +#define SRST_A_RKNN0 204
> +#define SRST_A_RKNN0_BIU 205
> +#define SRST_L_RKNN0_BIU 206
> +
> +#define SRST_A_RKNN1 207
> +#define SRST_A_RKNN1_BIU 208
> +#define SRST_L_RKNN1_BIU 209
> +
> +#define SRST_NPU_DAP 210
> +#define SRST_L_NPUSUBSYS_BIU 211
> +#define SRST_P_NPUTOP_BIU 212
> +#define SRST_P_NPU_TIMER 213
> +#define SRST_NPUTIMER0 214
> +#define SRST_NPUTIMER1 215
> +#define SRST_P_NPU_WDT 216
> +#define SRST_T_NPU_WDT 217
> +
> +#define SRST_A_RKNN_CBUF 218
> +#define SRST_A_RVCORE0 219
> +#define SRST_P_NPU_GRF 220
> +#define SRST_P_PVTPLL_NPU 221
> +#define SRST_NPU_PVTPLL 222
> +#define SRST_H_NPU_CM0_BIU 223
> +#define SRST_F_NPU_CM0_CORE 224
> +#define SRST_T_NPU_CM0_JTAG 225
> +#define SRST_A_RKNNTOP_BIU 226
> +#define SRST_H_RKNN_CBUF 227
> +#define SRST_H_RKNNTOP_BIU 228
> +
> +#define SRST_H_NVM_BIU 229
> +#define SRST_A_NVM_BIU 230
> +#define SRST_S_FSPI 231
> +#define SRST_H_FSPI 232
> +#define SRST_C_EMMC 233
> +#define SRST_H_EMMC 234
> +#define SRST_A_EMMC 235
> +#define SRST_B_EMMC 236
> +#define SRST_T_EMMC 237
> +
> +#define SRST_P_GRF 238
> +#define SRST_P_PHP_BIU 239
> +#define SRST_A_PHP_BIU 240
> +#define SRST_P_PCIE0 241
> +#define SRST_PCIE0_POWER_UP 242
> +
> +#define SRST_A_USB3OTG1 243
> +#define SRST_A_MMU0 244
> +#define SRST_A_SLV_MMU0 245
> +#define SRST_A_MMU1 246
> +
> +#define SRST_A_SLV_MMU1 247
> +#define SRST_P_PCIE1 248
> +#define SRST_PCIE1_POWER_UP 249
> +
> +#define SRST_RXOOB0 250
> +#define SRST_RXOOB1 251
> +#define SRST_PMALIVE0 252
> +#define SRST_PMALIVE1 253
> +#define SRST_A_SATA0 254
> +#define SRST_A_SATA1 255
> +#define SRST_ASIC1 256
> +#define SRST_ASIC0 257
> +
> +#define SRST_P_CSIDPHY1 258
> +#define SRST_SCAN_CSIDPHY1 259
> +
> +#define SRST_P_SDGMAC_GRF 260
> +#define SRST_P_SDGMAC_BIU 261
> +#define SRST_A_SDGMAC_BIU 262
> +#define SRST_H_SDGMAC_BIU 263
> +#define SRST_A_GMAC0 264
> +#define SRST_A_GMAC1 265
> +#define SRST_P_GMAC0 266
> +#define SRST_P_GMAC1 267
> +#define SRST_H_SDIO 268
> +
> +#define SRST_H_SDMMC0 269
> +#define SRST_S_FSPI1 270
> +#define SRST_H_FSPI1 271
> +#define SRST_A_DSMC_BIU 272
> +#define SRST_A_DSMC 273
> +#define SRST_P_DSMC 274
> +#define SRST_H_HSGPIO 275
> +#define SRST_HSGPIO 276
> +#define SRST_A_HSGPIO 277
> +
> +#define SRST_H_RKVDEC 278
> +#define SRST_H_RKVDEC_BIU 279
> +#define SRST_A_RKVDEC_BIU 280
> +#define SRST_RKVDEC_HEVC_CA 281
> +#define SRST_RKVDEC_CORE 282
> +
> +#define SRST_A_USB_BIU 283
> +#define SRST_P_USBUFS_BIU 284
> +#define SRST_A_USB3OTG0 285
> +#define SRST_A_UFS_BIU 286
> +#define SRST_A_MMU2 287
> +#define SRST_A_SLV_MMU2 288
> +#define SRST_A_UFS_SYS 289
> +
> +#define SRST_A_UFS 290
> +#define SRST_P_USBUFS_GRF 291
> +#define SRST_P_UFS_GRF 292
> +
> +#define SRST_H_VPU_BIU 293
> +#define SRST_A_JPEG_BIU 294
> +#define SRST_A_RGA_BIU 295
> +#define SRST_A_VDPP_BIU 296
> +#define SRST_A_EBC_BIU 297
> +#define SRST_H_RGA2E_0 298
> +#define SRST_A_RGA2E_0 299
> +#define SRST_CORE_RGA2E_0 300
> +
> +#define SRST_A_JPEG 301
> +#define SRST_H_JPEG 302
> +#define SRST_H_VDPP 303
> +#define SRST_A_VDPP 304
> +#define SRST_CORE_VDPP 305
> +#define SRST_H_RGA2E_1 306
> +#define SRST_A_RGA2E_1 307
> +#define SRST_CORE_RGA2E_1 308
> +#define SRST_H_EBC 309
> +#define SRST_A_EBC 310
> +#define SRST_D_EBC 311
> +
> +#define SRST_H_VEPU0_BIU 312
> +#define SRST_A_VEPU0_BIU 313
> +#define SRST_H_VEPU0 314
> +#define SRST_A_VEPU0 315
> +#define SRST_VEPU0_CORE 316
> +
> +#define SRST_A_VI_BIU 317
> +#define SRST_H_VI_BIU 318
> +#define SRST_P_VI_BIU 319
> +#define SRST_D_VICAP 320
> +#define SRST_A_VICAP 321
> +#define SRST_H_VICAP 322
> +#define SRST_ISP0 323
> +#define SRST_ISP0_VICAP 324
> +
> +#define SRST_CORE_VPSS 325
> +#define SRST_P_CSI_HOST_0 326
> +#define SRST_P_CSI_HOST_1 327
> +#define SRST_P_CSI_HOST_2 328
> +#define SRST_P_CSI_HOST_3 329
> +#define SRST_P_CSI_HOST_4 330
> +
> +#define SRST_CIFIN 331
> +#define SRST_VICAP_I0CLK 332
> +#define SRST_VICAP_I1CLK 333
> +#define SRST_VICAP_I2CLK 334
> +#define SRST_VICAP_I3CLK 335
> +#define SRST_VICAP_I4CLK 336
> +
> +#define SRST_A_VOP_BIU 337
> +#define SRST_A_VOP2_BIU 338
> +#define SRST_H_VOP_BIU 339
> +#define SRST_P_VOP_BIU 340
> +#define SRST_H_VOP 341
> +#define SRST_A_VOP 342
> +#define SRST_D_VP0 343
> +
> +#define SRST_D_VP1 344
> +#define SRST_D_VP2 345
> +#define SRST_P_VOP2_BIU 346
> +#define SRST_P_VOPGRF 347
> +
> +#define SRST_H_VO0_BIU 348
> +#define SRST_P_VO0_BIU 349
> +#define SRST_A_HDCP0_BIU 350
> +#define SRST_P_VO0_GRF 351
> +#define SRST_A_HDCP0 352
> +#define SRST_H_HDCP0 353
> +#define SRST_HDCP0 354
> +
> +#define SRST_P_DSIHOST0 355
> +#define SRST_DSIHOST0 356
> +#define SRST_P_HDMITX0 357
> +#define SRST_HDMITX0_REF 358
> +#define SRST_P_EDP0 359
> +#define SRST_EDP0_24M 360
> +
> +#define SRST_M_SAI5_8CH 361
> +#define SRST_H_SAI5_8CH 362
> +#define SRST_M_SAI6_8CH 363
> +#define SRST_H_SAI6_8CH 364
> +#define SRST_H_SPDIF_TX2 365
> +#define SRST_M_SPDIF_TX2 366
> +#define SRST_H_SPDIF_RX2 367
> +#define SRST_M_SPDIF_RX2 368
> +
> +#define SRST_H_SAI8_8CH 369
> +#define SRST_M_SAI8_8CH 370
> +
> +#define SRST_H_VO1_BIU 371
> +#define SRST_P_VO1_BIU 372
> +#define SRST_M_SAI7_8CH 373
> +#define SRST_H_SAI7_8CH 374
> +#define SRST_H_SPDIF_TX3 375
> +#define SRST_H_SPDIF_TX4 376
> +#define SRST_H_SPDIF_TX5 377
> +#define SRST_M_SPDIF_TX3 378
> +
> +#define SRST_DP0 379
> +#define SRST_P_VO1_GRF 380
> +#define SRST_A_HDCP1_BIU 381
> +#define SRST_A_HDCP1 382
> +#define SRST_H_HDCP1 383
> +#define SRST_HDCP1 384
> +#define SRST_H_SAI9_8CH 385
> +#define SRST_M_SAI9_8CH 386
> +#define SRST_M_SPDIF_TX4 387
> +#define SRST_M_SPDIF_TX5 388
> +
> +#define SRST_GPU 389
> +#define SRST_A_S_GPU_BIU 390
> +#define SRST_A_M0_GPU_BIU 391
> +#define SRST_P_GPU_BIU 392
> +#define SRST_P_GPU_GRF 393
> +#define SRST_GPU_PVTPLL 394
> +#define SRST_P_PVTPLL_GPU 395
> +
> +#define SRST_A_CENTER_BIU 396
> +#define SRST_A_DMA2DDR 397
> +#define SRST_A_DDR_SHAREMEM 398
> +#define SRST_A_DDR_SHAREMEM_BIU 399
> +#define SRST_H_CENTER_BIU 400
> +#define SRST_P_CENTER_GRF 401
> +#define SRST_P_DMA2DDR 402
> +#define SRST_P_SHAREMEM 403
> +#define SRST_P_CENTER_BIU 404
> +
> +#define SRST_LINKSYM_HDMITXPHY0 405
> +
> +#define SRST_DP0_PIXELCLK 406
> +#define SRST_PHY_DP0_TX 407
> +#define SRST_DP1_PIXELCLK 408
> +#define SRST_DP2_PIXELCLK 409
> +
> +#define SRST_H_VEPU1_BIU 410
> +#define SRST_A_VEPU1_BIU 411
> +#define SRST_H_VEPU1 412
> +#define SRST_A_VEPU1 413
> +#define SRST_VEPU1_CORE 414
> +
> +#define SRST_P_PHPPHY_CRU 415
> +#define SRST_P_APB2ASB_SLV_CHIP_TOP 416
> +#define SRST_P_PCIE2_COMBOPHY0 417
> +#define SRST_P_PCIE2_COMBOPHY0_GRF 418
> +#define SRST_P_PCIE2_COMBOPHY1 419
> +#define SRST_P_PCIE2_COMBOPHY1_GRF 420
> +
> +#define SRST_PCIE0_PIPE_PHY 421
> +#define SRST_PCIE1_PIPE_PHY 422
> +
> +#define SRST_H_CRYPTO_NS 423
> +#define SRST_H_TRNG_NS 424
> +#define SRST_P_OTPC_NS 425
> +#define SRST_OTPC_NS 426
> +
> +#define SRST_P_HDPTX_GRF 427
> +#define SRST_P_HDPTX_APB 428
> +#define SRST_P_MIPI_DCPHY 429
> +#define SRST_P_DCPHY_GRF 430
> +#define SRST_P_BOT0_APB2ASB 431
> +#define SRST_P_BOT1_APB2ASB 432
> +#define SRST_USB2DEBUG 433
> +#define SRST_P_CSIPHY_GRF 434
> +#define SRST_P_CSIPHY 435
> +#define SRST_P_USBPHY_GRF_0 436
> +#define SRST_P_USBPHY_GRF_1 437
> +#define SRST_P_USBDP_GRF 438
> +#define SRST_P_USBDPPHY 439
> +#define SRST_USBDP_COMBO_PHY_INIT 440
> +
> +#define SRST_USBDP_COMBO_PHY_CMN 441
> +#define SRST_USBDP_COMBO_PHY_LANE 442
> +#define SRST_USBDP_COMBO_PHY_PCS 443
> +#define SRST_M_MIPI_DCPHY 444
> +#define SRST_S_MIPI_DCPHY 445
> +#define SRST_SCAN_CSIPHY 446
> +#define SRST_P_VCCIO6_IOC 447
> +#define SRST_OTGPHY_0 448
> +#define SRST_OTGPHY_1 449
> +#define SRST_HDPTX_INIT 450
> +#define SRST_HDPTX_CMN 451
> +#define SRST_HDPTX_LANE 452
> +#define SRST_HDMITXHDP 453
> +
> +#define SRST_MPHY_INIT 454
> +#define SRST_P_MPHY_GRF 455
> +#define SRST_P_VCCIO7_IOC 456
> +
> +#define SRST_H_PMU1_BIU 457
> +#define SRST_P_PMU1_NIU 458
> +#define SRST_H_PMU_CM0_BIU 459
> +#define SRST_PMU_CM0_CORE 460
> +#define SRST_PMU_CM0_JTAG 461
> +
> +#define SRST_P_CRU_PMU1 462
> +#define SRST_P_PMU1_GRF 463
> +#define SRST_P_PMU1_IOC 464
> +#define SRST_P_PMU1WDT 465
> +#define SRST_T_PMU1WDT 466
> +#define SRST_P_PMUTIMER 467
> +#define SRST_PMUTIMER0 468
> +#define SRST_PMUTIMER1 469
> +#define SRST_P_PMU1PWM 470
> +#define SRST_PMU1PWM 471
> +
> +#define SRST_P_I2C0 472
> +#define SRST_I2C0 473
> +#define SRST_S_UART1 474
> +#define SRST_P_UART1 475
> +#define SRST_PDM0 476
> +#define SRST_H_PDM0 477
> +
> +#define SRST_M_PDM0 478
> +#define SRST_H_VAD 479
> +
> +#define SRST_P_PMU0GRF 480
> +#define SRST_P_PMU0IOC 481
> +#define SRST_P_GPIO0 482
> +#define SRST_DB_GPIO0 483
> +
> +#endif
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 02/20] dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
2024-11-21 14:27 ` [PATCH 01/20] dt-bindings: clock, reset: Add support for rk3576 Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-03 3:08 ` Kever Yang
2024-11-21 14:27 ` [PATCH 03/20] dt-bindings: power: Add support for RK3576 SoC Heiko Stuebner
` (19 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Stephen Boyd
Block comments should align the * on each line, as checkpatch rightfully
pointed out, so fix that style issue on the newly added rk3576 headers.
Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[ upstream commit: eb3b3f520518003cd363239fc160bdd7ed327319 ]
(cherry picked from commit 92b03f0021dfe4686d84fb75d52a5b4203c000a5)
---
.../include/dt-bindings/clock/rockchip,rk3576-cru.h | 12 ++++++------
.../include/dt-bindings/reset/rockchip,rk3576-cru.h | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
index a2933021be8..25aed298ac2 100644
--- a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
+++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
-* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
-* Copyright (c) 2024 Collabora Ltd.
-*
-* Author: Elaine Zhang <zhangqing@rock-chips.com>
-* Author: Detlev Casanova <detlev.casanova@collabora.com>
-*/
+ * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ */
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
index 291fec0ecba..ae856906f3a 100644
--- a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
+++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
-* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
-* Copyright (c) 2024 Collabora Ltd.
-*
-* Author: Elaine Zhang <zhangqing@rock-chips.com>
-* Author: Detlev Casanova <detlev.casanova@collabora.com>
-*/
+ * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ *
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ */
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 02/20] dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
2024-11-21 14:27 ` [PATCH 02/20] dt-bindings: clock, reset: fix top-comment indentation rk3576 headers Heiko Stuebner
@ 2025-01-03 3:08 ` Kever Yang
0 siblings, 0 replies; 44+ messages in thread
From: Kever Yang @ 2025-01-03 3:08 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, quentin.schulz, detlev.casanova, u-boot, sebastian.reichel,
Stephen Boyd
On 2024/11/21 22:27, Heiko Stuebner wrote:
> Block comments should align the * on each line, as checkpatch rightfully
> pointed out, so fix that style issue on the newly added rk3576 headers.
>
> Fixes: 49c04453db81 ("dt-bindings: clock, reset: Add support for rk3576")
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Link: https://lore.kernel.org/r/20240909223149.85364-1-heiko@sntech.de
> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
>
> [ upstream commit: eb3b3f520518003cd363239fc160bdd7ed327319 ]
>
> (cherry picked from commit 92b03f0021dfe4686d84fb75d52a5b4203c000a5)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../include/dt-bindings/clock/rockchip,rk3576-cru.h | 12 ++++++------
> .../include/dt-bindings/reset/rockchip,rk3576-cru.h | 12 ++++++------
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> index a2933021be8..25aed298ac2 100644
> --- a/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> +++ b/dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> @@ -1,11 +1,11 @@
> /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> /*
> -* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> -* Copyright (c) 2024 Collabora Ltd.
> -*
> -* Author: Elaine Zhang <zhangqing@rock-chips.com>
> -* Author: Detlev Casanova <detlev.casanova@collabora.com>
> -*/
> + * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> + * Copyright (c) 2024 Collabora Ltd.
> + *
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + * Author: Detlev Casanova <detlev.casanova@collabora.com>
> + */
>
> #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> diff --git a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> index 291fec0ecba..ae856906f3a 100644
> --- a/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> +++ b/dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> @@ -1,11 +1,11 @@
> /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> /*
> -* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> -* Copyright (c) 2024 Collabora Ltd.
> -*
> -* Author: Elaine Zhang <zhangqing@rock-chips.com>
> -* Author: Detlev Casanova <detlev.casanova@collabora.com>
> -*/
> + * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> + * Copyright (c) 2024 Collabora Ltd.
> + *
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + * Author: Detlev Casanova <detlev.casanova@collabora.com>
> + */
>
> #ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
> #define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 03/20] dt-bindings: power: Add support for RK3576 SoC
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
2024-11-21 14:27 ` [PATCH 01/20] dt-bindings: clock, reset: Add support for rk3576 Heiko Stuebner
2024-11-21 14:27 ` [PATCH 02/20] dt-bindings: clock, reset: fix top-comment indentation rk3576 headers Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-03 3:08 ` Kever Yang
2024-11-21 14:27 ` [PATCH 04/20] DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT Heiko Stuebner
` (18 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Finley Xiao, Conor Dooley, Ulf Hansson
From: Finley Xiao <finley.xiao@rock-chips.com>
Define power domain IDs as described in the TRM and add compatible for
rockchip,rk3576-power-controller
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Co-Developed-by: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240814222824.3170-2-detlev.casanova@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
[ upstream commit: 77c5e7b623032502ee49fe7e7868eaca6786d7ed ]
(cherry picked from commit 4f3821f3803953f291bbc957dc5a8aaa3f61e1d3)
---
.../power/rockchip,power-controller.yaml | 1 +
.../dt-bindings/power/rockchip,rk3576-power.h | 30 +++++++++++++++++++
2 files changed, 31 insertions(+)
create mode 100644 dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
diff --git a/dts/upstream/Bindings/power/rockchip,power-controller.yaml b/dts/upstream/Bindings/power/rockchip,power-controller.yaml
index 0d5e999a58f..650dc0aae6f 100644
--- a/dts/upstream/Bindings/power/rockchip,power-controller.yaml
+++ b/dts/upstream/Bindings/power/rockchip,power-controller.yaml
@@ -41,6 +41,7 @@ properties:
- rockchip,rk3368-power-controller
- rockchip,rk3399-power-controller
- rockchip,rk3568-power-controller
+ - rockchip,rk3576-power-controller
- rockchip,rk3588-power-controller
- rockchip,rv1126-power-controller
diff --git a/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h b/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
new file mode 100644
index 00000000000..324a056aa85
--- /dev/null
+++ b/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+#ifndef __DT_BINDINGS_POWER_RK3576_POWER_H__
+#define __DT_BINDINGS_POWER_RK3576_POWER_H__
+
+/* VD_NPU */
+#define RK3576_PD_NPU 0
+#define RK3576_PD_NPUTOP 1
+#define RK3576_PD_NPU0 2
+#define RK3576_PD_NPU1 3
+
+/* VD_GPU */
+#define RK3576_PD_GPU 4
+
+/* VD_LOGIC */
+#define RK3576_PD_NVM 5
+#define RK3576_PD_SDGMAC 6
+#define RK3576_PD_USB 7
+#define RK3576_PD_PHP 8
+#define RK3576_PD_SUBPHP 9
+#define RK3576_PD_AUDIO 10
+#define RK3576_PD_VEPU0 11
+#define RK3576_PD_VEPU1 12
+#define RK3576_PD_VPU 13
+#define RK3576_PD_VDEC 14
+#define RK3576_PD_VI 15
+#define RK3576_PD_VO0 16
+#define RK3576_PD_VO1 17
+#define RK3576_PD_VOP 18
+
+#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 03/20] dt-bindings: power: Add support for RK3576 SoC
2024-11-21 14:27 ` [PATCH 03/20] dt-bindings: power: Add support for RK3576 SoC Heiko Stuebner
@ 2025-01-03 3:08 ` Kever Yang
0 siblings, 0 replies; 44+ messages in thread
From: Kever Yang @ 2025-01-03 3:08 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, quentin.schulz, detlev.casanova, u-boot, sebastian.reichel,
Finley Xiao, Conor Dooley, Ulf Hansson
On 2024/11/21 22:27, Heiko Stuebner wrote:
> From: Finley Xiao <finley.xiao@rock-chips.com>
>
> Define power domain IDs as described in the TRM and add compatible for
> rockchip,rk3576-power-controller
>
> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
> Co-Developed-by: Detlev Casanova <detlev.casanova@collabora.com>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Link: https://lore.kernel.org/r/20240814222824.3170-2-detlev.casanova@collabora.com
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
>
> [ upstream commit: 77c5e7b623032502ee49fe7e7868eaca6786d7ed ]
>
> (cherry picked from commit 4f3821f3803953f291bbc957dc5a8aaa3f61e1d3)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thanks,
- Kever
> ---
> .../power/rockchip,power-controller.yaml | 1 +
> .../dt-bindings/power/rockchip,rk3576-power.h | 30 +++++++++++++++++++
> 2 files changed, 31 insertions(+)
> create mode 100644 dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
>
> diff --git a/dts/upstream/Bindings/power/rockchip,power-controller.yaml b/dts/upstream/Bindings/power/rockchip,power-controller.yaml
> index 0d5e999a58f..650dc0aae6f 100644
> --- a/dts/upstream/Bindings/power/rockchip,power-controller.yaml
> +++ b/dts/upstream/Bindings/power/rockchip,power-controller.yaml
> @@ -41,6 +41,7 @@ properties:
> - rockchip,rk3368-power-controller
> - rockchip,rk3399-power-controller
> - rockchip,rk3568-power-controller
> + - rockchip,rk3576-power-controller
> - rockchip,rk3588-power-controller
> - rockchip,rv1126-power-controller
>
> diff --git a/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h b/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
> new file mode 100644
> index 00000000000..324a056aa85
> --- /dev/null
> +++ b/dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +#ifndef __DT_BINDINGS_POWER_RK3576_POWER_H__
> +#define __DT_BINDINGS_POWER_RK3576_POWER_H__
> +
> +/* VD_NPU */
> +#define RK3576_PD_NPU 0
> +#define RK3576_PD_NPUTOP 1
> +#define RK3576_PD_NPU0 2
> +#define RK3576_PD_NPU1 3
> +
> +/* VD_GPU */
> +#define RK3576_PD_GPU 4
> +
> +/* VD_LOGIC */
> +#define RK3576_PD_NVM 5
> +#define RK3576_PD_SDGMAC 6
> +#define RK3576_PD_USB 7
> +#define RK3576_PD_PHP 8
> +#define RK3576_PD_SUBPHP 9
> +#define RK3576_PD_AUDIO 10
> +#define RK3576_PD_VEPU0 11
> +#define RK3576_PD_VEPU1 12
> +#define RK3576_PD_VPU 13
> +#define RK3576_PD_VDEC 14
> +#define RK3576_PD_VI 15
> +#define RK3576_PD_VO0 16
> +#define RK3576_PD_VO1 17
> +#define RK3576_PD_VOP 18
> +
> +#endif
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 04/20] DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (2 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 03/20] dt-bindings: power: Add support for RK3576 SoC Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 14:27 ` [PATCH 05/20] DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node Heiko Stuebner
` (17 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Liang Chen, Finley Xiao, Yifeng Zhao,
Elaine Zhang, Heiko Stuebner
From: Detlev Casanova <detlev.casanova@collabora.com>
This device tree contains all devices necessary for booting from network
or SD Card.
It supports CPU, CRU, PM domains, dma, interrupts, timers, UART, I2C
and SDHCI (everything necessary to boot Linux on this system on chip)
as well as Ethernet, SPI, GPU and RTC.
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Tested-by: Liang Chen <cl@rock-chips.com>
Link: https://lore.kernel.org/r/20240903152308.13565-9-detlev.casanova@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 57b1ce9039665c6cb6907aee4b517f43e1557d2f)
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
---
.../src/arm64/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++
dts/upstream/src/arm64/rockchip/rk3576.dtsi | 1678 +++++
2 files changed, 7453 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi
create mode 100644 dts/upstream/src/arm64/rockchip/rk3576.dtsi
diff --git a/dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi b/dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi
new file mode 100644
index 00000000000..0b0851a7e4e
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi
@@ -0,0 +1,5775 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ aupll_clk {
+ /omit-if-no-ref/
+ aupll_clkm0_pins: aupll_clkm0-pins {
+ rockchip,pins =
+ /* aupll_clk_in_m0 */
+ <0 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ aupll_clkm1_pins: aupll_clkm1-pins {
+ rockchip,pins =
+ /* aupll_clk_in_m1 */
+ <0 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ aupll_clkm2_pins: aupll_clkm2-pins {
+ rockchip,pins =
+ /* aupll_clk_in_m2 */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk0 {
+ /omit-if-no-ref/
+ cam_clk0m0_clk0: cam_clk0m0-clk0 {
+ rockchip,pins =
+ /* cam_clk0_out_m0 */
+ <3 RK_PD7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk0m1_clk0: cam_clk0m1-clk0 {
+ rockchip,pins =
+ /* cam_clk0_out_m1 */
+ <2 RK_PD2 1 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk1 {
+ /omit-if-no-ref/
+ cam_clk1m0_clk1: cam_clk1m0-clk1 {
+ rockchip,pins =
+ /* cam_clk1_out_m0 */
+ <4 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk1m1_clk1: cam_clk1m1-clk1 {
+ rockchip,pins =
+ /* cam_clk1_out_m1 */
+ <2 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ cam_clk2 {
+ /omit-if-no-ref/
+ cam_clk2m0_clk2: cam_clk2m0-clk2 {
+ rockchip,pins =
+ /* cam_clk2_out_m0 */
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clk2m1_clk2: cam_clk2m1-clk2 {
+ rockchip,pins =
+ /* cam_clk2_out_m1 */
+ <2 RK_PD7 1 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <2 RK_PA0 13 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <2 RK_PA1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <4 RK_PC3 12 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <4 RK_PC2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m2_pins: can0m2-pins {
+ rockchip,pins =
+ /* can0_rx_m2 */
+ <4 RK_PA6 13 &pcfg_pull_none>,
+ /* can0_tx_m2 */
+ <4 RK_PA4 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m3_pins: can0m3-pins {
+ rockchip,pins =
+ /* can0_rx_m3 */
+ <3 RK_PC1 12 &pcfg_pull_none>,
+ /* can0_tx_m3 */
+ <3 RK_PC4 12 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <2 RK_PA2 13 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <2 RK_PA3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <4 RK_PC7 13 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <4 RK_PC6 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m2_pins: can1m2-pins {
+ rockchip,pins =
+ /* can1_rx_m2 */
+ <4 RK_PB4 13 &pcfg_pull_none>,
+ /* can1_tx_m2 */
+ <4 RK_PB5 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m3_pins: can1m3-pins {
+ rockchip,pins =
+ /* can1_rx_m3 */
+ <3 RK_PA3 11 &pcfg_pull_none>,
+ /* can1_tx_m3 */
+ <3 RK_PA2 11 &pcfg_pull_none>;
+ };
+ };
+
+ clk0_32k {
+ /omit-if-no-ref/
+ clk0_32k_pins: clk0_32k-pins {
+ rockchip,pins =
+ /* clk0_32k_out */
+ <0 RK_PA2 10 &pcfg_pull_none>;
+ };
+ };
+
+ clk1_32k {
+ /omit-if-no-ref/
+ clk1_32k_pins: clk1_32k-pins {
+ rockchip,pins =
+ /* clk1_32k_out */
+ <1 RK_PD5 13 &pcfg_pull_none>;
+ };
+ };
+
+ clk_32k {
+ /omit-if-no-ref/
+ clk_32k_pins: clk_32k-pins {
+ rockchip,pins =
+ /* clk_32k_in */
+ <0 RK_PA2 9 &pcfg_pull_none>;
+ };
+ };
+
+ cpubig {
+ /omit-if-no-ref/
+ cpubig_pins: cpubig-pins {
+ rockchip,pins =
+ /* cpubig_avs */
+ <0 RK_PD2 11 &pcfg_pull_none>;
+ };
+ };
+
+ cpulit {
+ /omit-if-no-ref/
+ cpulit_pins: cpulit-pins {
+ rockchip,pins =
+ /* cpulit_avs */
+ <0 RK_PC0 11 &pcfg_pull_none>;
+ };
+ };
+
+ debug0_test {
+ /omit-if-no-ref/
+ debug0_test_pins: debug0_test-pins {
+ rockchip,pins =
+ /* debug0_test_out */
+ <1 RK_PC4 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug1_test {
+ /omit-if-no-ref/
+ debug1_test_pins: debug1_test-pins {
+ rockchip,pins =
+ /* debug1_test_out */
+ <1 RK_PC5 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug2_test {
+ /omit-if-no-ref/
+ debug2_test_pins: debug2_test-pins {
+ rockchip,pins =
+ /* debug2_test_out */
+ <1 RK_PC6 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug3_test {
+ /omit-if-no-ref/
+ debug3_test_pins: debug3_test-pins {
+ rockchip,pins =
+ /* debug3_test_out */
+ <1 RK_PC7 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug4_test {
+ /omit-if-no-ref/
+ debug4_test_pins: debug4_test-pins {
+ rockchip,pins =
+ /* debug4_test_out */
+ <1 RK_PD0 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug5_test {
+ /omit-if-no-ref/
+ debug5_test_pins: debug5_test-pins {
+ rockchip,pins =
+ /* debug5_test_out */
+ <1 RK_PD1 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug6_test {
+ /omit-if-no-ref/
+ debug6_test_pins: debug6_test-pins {
+ rockchip,pins =
+ /* debug6_test_out */
+ <1 RK_PD2 7 &pcfg_pull_none>;
+ };
+ };
+
+ debug7_test {
+ /omit-if-no-ref/
+ debug7_test_pins: debug7_test-pins {
+ rockchip,pins =
+ /* debug7_test_out */
+ <1 RK_PD3 7 &pcfg_pull_none>;
+ };
+ };
+
+ dp {
+ /omit-if-no-ref/
+ dpm0_pins: dpm0-pins {
+ rockchip,pins =
+ /* dp_hpdin_m0 */
+ <4 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dpm1_pins: dpm1-pins {
+ rockchip,pins =
+ /* dp_hpdin_m1 */
+ <0 RK_PC5 9 &pcfg_pull_none>;
+ };
+ };
+
+ dsm_aud {
+ /omit-if-no-ref/
+ dsm_audm0_ln: dsm_audm0-ln {
+ rockchip,pins =
+ /* dsm_aud_ln_m0 */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_lp: dsm_audm0-lp {
+ rockchip,pins =
+ /* dsm_aud_lp_m0 */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_rn: dsm_audm0-rn {
+ rockchip,pins =
+ /* dsm_aud_rn_m0 */
+ <2 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm0_rp: dsm_audm0-rp {
+ rockchip,pins =
+ /* dsm_aud_rp_m0 */
+ <2 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_ln: dsm_audm1-ln {
+ rockchip,pins =
+ /* dsm_aud_ln_m1 */
+ <4 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_lp: dsm_audm1-lp {
+ rockchip,pins =
+ /* dsm_aud_lp_m1 */
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_rn: dsm_audm1-rn {
+ rockchip,pins =
+ /* dsm_aud_rn_m1 */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ dsm_audm1_rp: dsm_audm1-rp {
+ rockchip,pins =
+ /* dsm_aud_rp_m1 */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ dsmc {
+ /omit-if-no-ref/
+ dsmc_clkn: dsmc-clkn {
+ rockchip,pins =
+ /* dsmc_clkn */
+ <3 RK_PD6 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_clkp: dsmc-clkp {
+ rockchip,pins =
+ /* dsmc_clkp */
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_csn0: dsmc-csn0 {
+ rockchip,pins =
+ /* dsmc_csn0 */
+ <3 RK_PD3 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_csn1: dsmc-csn1 {
+ rockchip,pins =
+ /* dsmc_csn1 */
+ <3 RK_PB0 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_csn2: dsmc-csn2 {
+ rockchip,pins =
+ /* dsmc_csn2 */
+ <3 RK_PD1 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_csn3: dsmc-csn3 {
+ rockchip,pins =
+ /* dsmc_csn3 */
+ <3 RK_PD2 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data0: dsmc-data0 {
+ rockchip,pins =
+ /* dsmc_data0 */
+ <3 RK_PD4 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data1: dsmc-data1 {
+ rockchip,pins =
+ /* dsmc_data1 */
+ <3 RK_PD0 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data2: dsmc-data2 {
+ rockchip,pins =
+ /* dsmc_data2 */
+ <3 RK_PC7 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data3: dsmc-data3 {
+ rockchip,pins =
+ /* dsmc_data3 */
+ <3 RK_PC6 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data4: dsmc-data4 {
+ rockchip,pins =
+ /* dsmc_data4 */
+ <3 RK_PC5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data5: dsmc-data5 {
+ rockchip,pins =
+ /* dsmc_data5 */
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data6: dsmc-data6 {
+ rockchip,pins =
+ /* dsmc_data6 */
+ <3 RK_PC1 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data7: dsmc-data7 {
+ rockchip,pins =
+ /* dsmc_data7 */
+ <3 RK_PC0 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data8: dsmc-data8 {
+ rockchip,pins =
+ /* dsmc_data8 */
+ <3 RK_PB5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data9: dsmc-data9 {
+ rockchip,pins =
+ /* dsmc_data9 */
+ <3 RK_PB4 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data10: dsmc-data10 {
+ rockchip,pins =
+ /* dsmc_data10 */
+ <3 RK_PB3 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data11: dsmc-data11 {
+ rockchip,pins =
+ /* dsmc_data11 */
+ <3 RK_PB2 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data12: dsmc-data12 {
+ rockchip,pins =
+ /* dsmc_data12 */
+ <3 RK_PB1 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data13: dsmc-data13 {
+ rockchip,pins =
+ /* dsmc_data13 */
+ <3 RK_PA7 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data14: dsmc-data14 {
+ rockchip,pins =
+ /* dsmc_data14 */
+ <3 RK_PA6 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_data15: dsmc-data15 {
+ rockchip,pins =
+ /* dsmc_data15 */
+ <3 RK_PA5 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_dqs0: dsmc-dqs0 {
+ rockchip,pins =
+ /* dsmc_dqs0 */
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_dqs1: dsmc-dqs1 {
+ rockchip,pins =
+ /* dsmc_dqs1 */
+ <3 RK_PB6 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_int0: dsmc-int0 {
+ rockchip,pins =
+ /* dsmc_int0 */
+ <4 RK_PA0 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_int1: dsmc-int1 {
+ rockchip,pins =
+ /* dsmc_int1 */
+ <3 RK_PC2 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_int2: dsmc-int2 {
+ rockchip,pins =
+ /* dsmc_int2 */
+ <4 RK_PA1 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_int3: dsmc-int3 {
+ rockchip,pins =
+ /* dsmc_int3 */
+ <3 RK_PC3 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_rdyn: dsmc-rdyn {
+ rockchip,pins =
+ /* dsmc_rdyn */
+ <3 RK_PA4 5 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ dsmc_resetn: dsmc-resetn {
+ rockchip,pins =
+ /* dsmc_resetn */
+ <3 RK_PD7 5 &pcfg_pull_none>;
+ };
+ };
+
+ dsmc_testclk {
+ /omit-if-no-ref/
+ dsmc_testclk_out: dsmc-testclk-out {
+ rockchip,pins =
+ /* dsmc_testclk_out */
+ <3 RK_PC2 7 &pcfg_pull_none>;
+ };
+ };
+
+ dsmc_testdata {
+ /omit-if-no-ref/
+ dsmc_testdata_out: dsmc-testdata-out {
+ rockchip,pins =
+ /* dsmc_testdata_out */
+ <3 RK_PC3 7 &pcfg_pull_none>;
+ };
+ };
+
+ edp_tx {
+ /omit-if-no-ref/
+ edp_txm0_pins: edp_txm0-pins {
+ rockchip,pins =
+ /* edp_tx_hpdin_m0 */
+ <4 RK_PC1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ edp_txm1_pins: edp_txm1-pins {
+ rockchip,pins =
+ /* edp_tx_hpdin_m1 */
+ <0 RK_PB6 10 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ emmc_testclk {
+ /omit-if-no-ref/
+ emmc_testclk_test: emmc_testclk-test {
+ rockchip,pins =
+ /* emmc_testclk_out */
+ <1 RK_PB3 6 &pcfg_pull_none>;
+ };
+ };
+
+ emmc_testdata {
+ /omit-if-no-ref/
+ emmc_testdata_test: emmc_testdata-test {
+ rockchip,pins =
+ /* emmc_testdata_out */
+ <1 RK_PB7 5 &pcfg_pull_none>;
+ };
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0m0_miim: eth0m0-miim {
+ rockchip,pins =
+ /* eth0_mdc_m0 */
+ <3 RK_PA6 3 &pcfg_pull_none>,
+ /* eth0_mdio_m0 */
+ <3 RK_PA5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m0_rx_bus2: eth0m0-rx_bus2 {
+ rockchip,pins =
+ /* eth0_rxctl_m0 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* eth0_rxd0_m0 */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* eth0_rxd1_m0 */
+ <3 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m0_tx_bus2: eth0m0-tx_bus2 {
+ rockchip,pins =
+ /* eth0_txctl_m0 */
+ <3 RK_PB3 3 &pcfg_pull_none>,
+ /* eth0_txd0_m0 */
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ /* eth0_txd1_m0 */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m0_rgmii_clk: eth0m0-rgmii_clk {
+ rockchip,pins =
+ /* eth0_rxclk_m0 */
+ <3 RK_PD1 3 &pcfg_pull_none>,
+ /* eth0_txclk_m0 */
+ <3 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m0_rgmii_bus: eth0m0-rgmii_bus {
+ rockchip,pins =
+ /* eth0_rxd2_m0 */
+ <3 RK_PD3 3 &pcfg_pull_none>,
+ /* eth0_rxd3_m0 */
+ <3 RK_PD2 3 &pcfg_pull_none>,
+ /* eth0_txd2_m0 */
+ <3 RK_PC3 3 &pcfg_pull_none>,
+ /* eth0_txd3_m0 */
+ <3 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m0_mclk: eth0m0-mclk {
+ rockchip,pins =
+ /* eth0m0_mclk */
+ <3 RK_PB0 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth0m0_ppsclk: eth0m0-ppsclk {
+ rockchip,pins =
+ /* eth0m0_ppsclk */
+ <3 RK_PC0 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth0m0_ppstrig: eth0m0-ppstrig {
+ rockchip,pins =
+ /* eth0m0_ppstrig */
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_miim: eth0m1-miim {
+ rockchip,pins =
+ /* eth0_mdc_m1 */
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ /* eth0_mdio_m1 */
+ <3 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_rx_bus2: eth0m1-rx_bus2 {
+ rockchip,pins =
+ /* eth0_rxctl_m1 */
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ /* eth0_rxd0_m1 */
+ <2 RK_PA6 3 &pcfg_pull_none>,
+ /* eth0_rxd1_m1 */
+ <3 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_tx_bus2: eth0m1-tx_bus2 {
+ rockchip,pins =
+ /* eth0_txctl_m1 */
+ <2 RK_PA7 3 &pcfg_pull_none>,
+ /* eth0_txd0_m1 */
+ <2 RK_PB1 3 &pcfg_pull_none>,
+ /* eth0_txd1_m1 */
+ <2 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_rgmii_clk: eth0m1-rgmii_clk {
+ rockchip,pins =
+ /* eth0_rxclk_m1 */
+ <2 RK_PB5 3 &pcfg_pull_none>,
+ /* eth0_txclk_m1 */
+ <2 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_rgmii_bus: eth0m1-rgmii_bus {
+ rockchip,pins =
+ /* eth0_rxd2_m1 */
+ <2 RK_PB7 3 &pcfg_pull_none>,
+ /* eth0_rxd3_m1 */
+ <2 RK_PB6 3 &pcfg_pull_none>,
+ /* eth0_txd2_m1 */
+ <2 RK_PB4 3 &pcfg_pull_none>,
+ /* eth0_txd3_m1 */
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_mclk: eth0m1-mclk {
+ rockchip,pins =
+ /* eth0m1_mclk */
+ <2 RK_PD6 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth0m1_ppsclk: eth0m1-ppsclk {
+ rockchip,pins =
+ /* eth0m1_ppsclk */
+ <2 RK_PC1 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth0m1_ppstrig: eth0m1-ppstrig {
+ rockchip,pins =
+ /* eth0m1_ppstrig */
+ <2 RK_PC2 3 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1m0_miim: eth1m0-miim {
+ rockchip,pins =
+ /* eth1_mdc_m0 */
+ <2 RK_PD4 2 &pcfg_pull_none>,
+ /* eth1_mdio_m0 */
+ <2 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rx_bus2: eth1m0-rx_bus2 {
+ rockchip,pins =
+ /* eth1_rxctl_m0 */
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ /* eth1_rxd0_m0 */
+ <2 RK_PD1 2 &pcfg_pull_none>,
+ /* eth1_rxd1_m0 */
+ <2 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_tx_bus2: eth1m0-tx_bus2 {
+ rockchip,pins =
+ /* eth1_txctl_m0 */
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ /* eth1_txd0_m0 */
+ <2 RK_PC6 2 &pcfg_pull_none>,
+ /* eth1_txd1_m0 */
+ <2 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rgmii_clk: eth1m0-rgmii_clk {
+ rockchip,pins =
+ /* eth1_rxclk_m0 */
+ <2 RK_PC2 2 &pcfg_pull_none>,
+ /* eth1_txclk_m0 */
+ <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_rgmii_bus: eth1m0-rgmii_bus {
+ rockchip,pins =
+ /* eth1_rxd2_m0 */
+ <2 RK_PC0 2 &pcfg_pull_none>,
+ /* eth1_rxd3_m0 */
+ <2 RK_PC1 2 &pcfg_pull_none>,
+ /* eth1_txd2_m0 */
+ <2 RK_PC3 2 &pcfg_pull_none>,
+ /* eth1_txd3_m0 */
+ <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m0_mclk: eth1m0-mclk {
+ rockchip,pins =
+ /* eth1m0_mclk */
+ <2 RK_PD7 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth1m0_ppsclk: eth1m0-ppsclk {
+ rockchip,pins =
+ /* eth1m0_ppsclk */
+ <3 RK_PA2 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth1m0_ppstrig: eth1m0-ppstrig {
+ rockchip,pins =
+ /* eth1m0_ppstrig */
+ <3 RK_PA1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_miim: eth1m1-miim {
+ rockchip,pins =
+ /* eth1_mdc_m1 */
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ /* eth1_mdio_m1 */
+ <1 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rx_bus2: eth1m1-rx_bus2 {
+ rockchip,pins =
+ /* eth1_rxctl_m1 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* eth1_rxd0_m1 */
+ <1 RK_PC7 1 &pcfg_pull_none>,
+ /* eth1_rxd1_m1 */
+ <1 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_tx_bus2: eth1m1-tx_bus2 {
+ rockchip,pins =
+ /* eth1_txctl_m1 */
+ <1 RK_PC6 1 &pcfg_pull_none>,
+ /* eth1_txd0_m1 */
+ <1 RK_PC4 1 &pcfg_pull_none>,
+ /* eth1_txd1_m1 */
+ <1 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rgmii_clk: eth1m1-rgmii_clk {
+ rockchip,pins =
+ /* eth1_rxclk_m1 */
+ <1 RK_PB6 1 &pcfg_pull_none>,
+ /* eth1_txclk_m1 */
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_rgmii_bus: eth1m1-rgmii_bus {
+ rockchip,pins =
+ /* eth1_rxd2_m1 */
+ <1 RK_PB4 1 &pcfg_pull_none>,
+ /* eth1_rxd3_m1 */
+ <1 RK_PB5 1 &pcfg_pull_none>,
+ /* eth1_txd2_m1 */
+ <1 RK_PB7 1 &pcfg_pull_none>,
+ /* eth1_txd3_m1 */
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_mclk: eth1m1-mclk {
+ rockchip,pins =
+ /* eth1m1_mclk */
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth1m1_ppsclk: eth1m1-ppsclk {
+ rockchip,pins =
+ /* eth1m1_ppsclk */
+ <1 RK_PC2 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ eth1m1_ppstrig: eth1m1-ppstrig {
+ rockchip,pins =
+ /* eth1m1_ppstrig */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth0_ptp {
+ /omit-if-no-ref/
+ eth0m0_ptp_refclk: eth0m0-ptp-refclk {
+ rockchip,pins =
+ /* eth0m0_ptp_refclk */
+ <3 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0m1_ptp_refclk: eth0m1-ptp-refclk {
+ rockchip,pins =
+ /* eth0m1_ptp_refclk */
+ <2 RK_PC0 3 &pcfg_pull_none>;
+ };
+ };
+
+ eth0_testrxclk {
+ /omit-if-no-ref/
+ eth0_testrxclkm0_test: eth0_testrxclkm0-test {
+ rockchip,pins =
+ /* eth0_testrxclk_out_m0 */
+ <3 RK_PC7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_testrxclkm1_test: eth0_testrxclkm1-test {
+ rockchip,pins =
+ /* eth0_testrxclk_out_m1 */
+ <2 RK_PC5 6 &pcfg_pull_none>;
+ };
+ };
+
+ eth0_testrxd {
+ /omit-if-no-ref/
+ eth0_testrxdm0_test: eth0_testrxdm0-test {
+ rockchip,pins =
+ /* eth0_testrxd_out_m0 */
+ <3 RK_PD0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth0_testrxdm1_test: eth0_testrxdm1-test {
+ rockchip,pins =
+ /* eth0_testrxd_out_m1 */
+ <2 RK_PC4 6 &pcfg_pull_none>;
+ };
+ };
+
+ eth1_ptp {
+ /omit-if-no-ref/
+ eth1m0_ptp_refclk: eth1m0-ptp-refclk {
+ rockchip,pins =
+ /* eth1m0_ptp_refclk */
+ <3 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_ptp_refclk: eth1m1-ptp-refclk {
+ rockchip,pins =
+ /* eth1m1_ptp_refclk */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+ };
+
+ eth1_testrxclk {
+ /omit-if-no-ref/
+ eth1_testrxclkm0_test: eth1_testrxclkm0-test {
+ rockchip,pins =
+ /* eth1_testrxclk_out_m0 */
+ <3 RK_PA1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1_testrxclkm1_test: eth1_testrxclkm1-test {
+ rockchip,pins =
+ /* eth1_testrxclk_out_m1 */
+ <1 RK_PC3 6 &pcfg_pull_none>;
+ };
+ };
+
+ eth1_testrxd {
+ /omit-if-no-ref/
+ eth1_testrxdm0_test: eth1_testrxdm0-test {
+ rockchip,pins =
+ /* eth1_testrxd_out_m0 */
+ <3 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1_testrxdm1_test: eth1_testrxdm1-test {
+ rockchip,pins =
+ /* eth1_testrxd_out_m1 */
+ <1 RK_PC2 6 &pcfg_pull_none>;
+ };
+ };
+
+ eth_clk0_25m {
+ /omit-if-no-ref/
+ ethm0_clk0_25m_out: ethm0-clk0-25m-out {
+ rockchip,pins =
+ /* ethm0_clk0_25m_out */
+ <3 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ethm1_clk0_25m_out: ethm1-clk0-25m-out {
+ rockchip,pins =
+ /* ethm1_clk0_25m_out */
+ <2 RK_PD7 3 &pcfg_pull_none>;
+ };
+ };
+
+ eth_clk1_25m {
+ /omit-if-no-ref/
+ ethm0_clk1_25m_out: ethm0-clk1-25m-out {
+ rockchip,pins =
+ /* ethm0_clk1_25m_out */
+ <2 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ethm1_clk1_25m_out: ethm1-clk1-25m-out {
+ rockchip,pins =
+ /* ethm1_clk1_25m_out */
+ <1 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus0 {
+ /omit-if-no-ref/
+ flexbus0m0_csn: flexbus0m0-csn {
+ rockchip,pins =
+ /* flexbus0_csn_m0 */
+ <3 RK_PA4 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m0_d13: flexbus0m0-d13 {
+ rockchip,pins =
+ /* flexbus0_d13_m0 */
+ <4 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m0_d14: flexbus0m0-d14 {
+ rockchip,pins =
+ /* flexbus0_d14_m0 */
+ <4 RK_PA1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m0_d15: flexbus0m0-d15 {
+ rockchip,pins =
+ /* flexbus0_d15_m0 */
+ <3 RK_PD7 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m1_csn: flexbus0m1-csn {
+ rockchip,pins =
+ /* flexbus0_csn_m1 */
+ <4 RK_PA1 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m1_d13: flexbus0m1-d13 {
+ rockchip,pins =
+ /* flexbus0_d13_m1 */
+ <4 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m1_d14: flexbus0m1-d14 {
+ rockchip,pins =
+ /* flexbus0_d14_m1 */
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m1_d15: flexbus0m1-d15 {
+ rockchip,pins =
+ /* flexbus0_d15_m1 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m2_csn: flexbus0m2-csn {
+ rockchip,pins =
+ /* flexbus0_csn_m2 */
+ <3 RK_PC3 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m3_csn: flexbus0m3-csn {
+ rockchip,pins =
+ /* flexbus0_csn_m3 */
+ <3 RK_PD2 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0m4_csn: flexbus0m4-csn {
+ rockchip,pins =
+ /* flexbus0_csn_m4 */
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_clk: flexbus0-clk {
+ rockchip,pins =
+ /* flexbus0_clk */
+ <3 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d10: flexbus0-d10 {
+ rockchip,pins =
+ /* flexbus0_d10 */
+ <3 RK_PC3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d11: flexbus0-d11 {
+ rockchip,pins =
+ /* flexbus0_d11 */
+ <3 RK_PD1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d12: flexbus0-d12 {
+ rockchip,pins =
+ /* flexbus0_d12 */
+ <3 RK_PD2 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d0: flexbus0-d0 {
+ rockchip,pins =
+ /* flexbus0_d0 */
+ <3 RK_PB5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d1: flexbus0-d1 {
+ rockchip,pins =
+ /* flexbus0_d1 */
+ <3 RK_PB4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d2: flexbus0-d2 {
+ rockchip,pins =
+ /* flexbus0_d2 */
+ <3 RK_PB3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d3: flexbus0-d3 {
+ rockchip,pins =
+ /* flexbus0_d3 */
+ <3 RK_PB2 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d4: flexbus0-d4 {
+ rockchip,pins =
+ /* flexbus0_d4 */
+ <3 RK_PB1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d5: flexbus0-d5 {
+ rockchip,pins =
+ /* flexbus0_d5 */
+ <3 RK_PA7 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d6: flexbus0-d6 {
+ rockchip,pins =
+ /* flexbus0_d6 */
+ <3 RK_PA6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d7: flexbus0-d7 {
+ rockchip,pins =
+ /* flexbus0_d7 */
+ <3 RK_PA5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d8: flexbus0-d8 {
+ rockchip,pins =
+ /* flexbus0_d8 */
+ <3 RK_PB0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus0_d9: flexbus0-d9 {
+ rockchip,pins =
+ /* flexbus0_d9 */
+ <3 RK_PC2 6 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus1 {
+ /omit-if-no-ref/
+ flexbus1m0_csn: flexbus1m0-csn {
+ rockchip,pins =
+ /* flexbus1_csn_m0 */
+ <3 RK_PB7 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m0_d12: flexbus1m0-d12 {
+ rockchip,pins =
+ /* flexbus1_d12_m0 */
+ <3 RK_PD7 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m0_d13: flexbus1m0-d13 {
+ rockchip,pins =
+ /* flexbus1_d13_m0 */
+ <4 RK_PA1 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m0_d14: flexbus1m0-d14 {
+ rockchip,pins =
+ /* flexbus1_d14_m0 */
+ <4 RK_PA0 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m0_d15: flexbus1m0-d15 {
+ rockchip,pins =
+ /* flexbus1_d15_m0 */
+ <3 RK_PD2 7 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m1_csn: flexbus1m1-csn {
+ rockchip,pins =
+ /* flexbus1_csn_m1 */
+ <3 RK_PD7 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m1_d12: flexbus1m1-d12 {
+ rockchip,pins =
+ /* flexbus1_d12_m1 */
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m1_d13: flexbus1m1-d13 {
+ rockchip,pins =
+ /* flexbus1_d13_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m1_d14: flexbus1m1-d14 {
+ rockchip,pins =
+ /* flexbus1_d14_m1 */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m1_d15: flexbus1m1-d15 {
+ rockchip,pins =
+ /* flexbus1_d15_m1 */
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m2_csn: flexbus1m2-csn {
+ rockchip,pins =
+ /* flexbus1_csn_m2 */
+ <3 RK_PD1 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m3_csn: flexbus1m3-csn {
+ rockchip,pins =
+ /* flexbus1_csn_m3 */
+ <4 RK_PA0 8 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1m4_csn: flexbus1m4-csn {
+ rockchip,pins =
+ /* flexbus1_csn_m4 */
+ <4 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_clk: flexbus1-clk {
+ rockchip,pins =
+ /* flexbus1_clk */
+ <3 RK_PD6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d10: flexbus1-d10 {
+ rockchip,pins =
+ /* flexbus1_d10 */
+ <3 RK_PB7 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d11: flexbus1-d11 {
+ rockchip,pins =
+ /* flexbus1_d11 */
+ <3 RK_PA4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d0: flexbus1-d0 {
+ rockchip,pins =
+ /* flexbus1_d0 */
+ <3 RK_PD5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d1: flexbus1-d1 {
+ rockchip,pins =
+ /* flexbus1_d1 */
+ <3 RK_PD4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d2: flexbus1-d2 {
+ rockchip,pins =
+ /* flexbus1_d2 */
+ <3 RK_PD3 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d3: flexbus1-d3 {
+ rockchip,pins =
+ /* flexbus1_d3 */
+ <3 RK_PD0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d4: flexbus1-d4 {
+ rockchip,pins =
+ /* flexbus1_d4 */
+ <3 RK_PC7 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d5: flexbus1-d5 {
+ rockchip,pins =
+ /* flexbus1_d5 */
+ <3 RK_PC6 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d6: flexbus1-d6 {
+ rockchip,pins =
+ /* flexbus1_d6 */
+ <3 RK_PC5 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d7: flexbus1-d7 {
+ rockchip,pins =
+ /* flexbus1_d7 */
+ <3 RK_PC4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d8: flexbus1-d8 {
+ rockchip,pins =
+ /* flexbus1_d8 */
+ <3 RK_PC1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ flexbus1_d9: flexbus1-d9 {
+ rockchip,pins =
+ /* flexbus1_d9 */
+ <3 RK_PC0 6 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus0_testclk {
+ /omit-if-no-ref/
+ flexbus0_testclk_testclk: flexbus0_testclk-testclk {
+ rockchip,pins =
+ /* flexbus0_testclk_out */
+ <2 RK_PA3 6 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus0_testdata {
+ /omit-if-no-ref/
+ flexbus0_testdata_testdata: flexbus0_testdata-testdata {
+ rockchip,pins =
+ /* flexbus0_testdata_out */
+ <2 RK_PA2 6 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus1_testclk {
+ /omit-if-no-ref/
+ flexbus1_testclk_testclk: flexbus1_testclk-testclk {
+ rockchip,pins =
+ /* flexbus1_testclk_out */
+ <2 RK_PA5 6 &pcfg_pull_none>;
+ };
+ };
+
+ flexbus1_testdata {
+ /omit-if-no-ref/
+ flexbus1_testdata_testdata: flexbus1_testdata-testdata {
+ rockchip,pins =
+ /* flexbus1_testdata_out */
+ <2 RK_PA4 6 &pcfg_pull_none>;
+ };
+ };
+
+ fspi0 {
+ /omit-if-no-ref/
+ fspi0_pins: fspi0-pins {
+ rockchip,pins =
+ /* fspi0_clk */
+ <1 RK_PB1 2 &pcfg_pull_none>,
+ /* fspi0_d0 */
+ <1 RK_PA0 2 &pcfg_pull_none>,
+ /* fspi0_d1 */
+ <1 RK_PA1 2 &pcfg_pull_none>,
+ /* fspi0_d2 */
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ /* fspi0_d3 */
+ <1 RK_PA3 2 &pcfg_pull_none>,
+ /* fspi0_d4 */
+ <1 RK_PA4 2 &pcfg_pull_none>,
+ /* fspi0_d5 */
+ <1 RK_PA5 2 &pcfg_pull_none>,
+ /* fspi0_d6 */
+ <1 RK_PA6 2 &pcfg_pull_none>,
+ /* fspi0_d7 */
+ <1 RK_PA7 2 &pcfg_pull_none>,
+ /* fspi0_dqs */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi0_csn0: fspi0-csn0 {
+ rockchip,pins =
+ /* fspi0_csn0 */
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ fspi0_csn1: fspi0-csn1 {
+ rockchip,pins =
+ /* fspi0_csn1 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ fspi1 {
+ /omit-if-no-ref/
+ fspi1m0_pins: fspi1m0-pins {
+ rockchip,pins =
+ /* fspi1_clk_m0 */
+ <2 RK_PA5 2 &pcfg_pull_none>,
+ /* fspi1_d0_m0 */
+ <2 RK_PA0 2 &pcfg_pull_none>,
+ /* fspi1_d1_m0 */
+ <2 RK_PA1 2 &pcfg_pull_none>,
+ /* fspi1_d2_m0 */
+ <2 RK_PA2 2 &pcfg_pull_none>,
+ /* fspi1_d3_m0 */
+ <2 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m0_csn0: fspi1m0-csn0 {
+ rockchip,pins =
+ /* fspi1m0_csn0 */
+ <2 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m1_pins: fspi1m1-pins {
+ rockchip,pins =
+ /* fspi1_clk_m1 */
+ <1 RK_PD5 3 &pcfg_pull_none>,
+ /* fspi1_d0_m1 */
+ <1 RK_PC4 3 &pcfg_pull_none>,
+ /* fspi1_d1_m1 */
+ <1 RK_PC5 3 &pcfg_pull_none>,
+ /* fspi1_d2_m1 */
+ <1 RK_PC6 3 &pcfg_pull_none>,
+ /* fspi1_d3_m1 */
+ <1 RK_PC7 3 &pcfg_pull_none>,
+ /* fspi1_d4_m1 */
+ <1 RK_PD0 3 &pcfg_pull_none>,
+ /* fspi1_d5_m1 */
+ <1 RK_PD1 3 &pcfg_pull_none>,
+ /* fspi1_d6_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none>,
+ /* fspi1_d7_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none>,
+ /* fspi1_dqs_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi1m1_csn0: fspi1m1-csn0 {
+ rockchip,pins =
+ /* fspi1m1_csn0 */
+ <1 RK_PC3 3 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ fspi1m1_csn1: fspi1m1-csn1 {
+ rockchip,pins =
+ /* fspi1m1_csn1 */
+ <1 RK_PC2 3 &pcfg_pull_none>;
+ };
+ };
+
+ fspi0_testclk {
+ /omit-if-no-ref/
+ fspi0_testclk_test: fspi0_testclk-test {
+ rockchip,pins =
+ /* fspi0_testclk_out */
+ <1 RK_PB0 6 &pcfg_pull_none>;
+ };
+ };
+
+ fspi0_testdata {
+ /omit-if-no-ref/
+ fspi0_testdata_test: fspi0_testdata-test {
+ rockchip,pins =
+ /* fspi0_testdata_out */
+ <1 RK_PB7 6 &pcfg_pull_none>;
+ };
+ };
+
+ fspi1_testclk {
+ /omit-if-no-ref/
+ fspi1_testclkm1_test: fspi1_testclkm1-test {
+ rockchip,pins =
+ /* fspi1_testclk_out_m1 */
+ <1 RK_PC1 7 &pcfg_pull_none>;
+ };
+ };
+
+ fspi1_testdata {
+ /omit-if-no-ref/
+ fspi1_testdatam1_test: fspi1_testdatam1-test {
+ rockchip,pins =
+ /* fspi1_testdata_out_m1 */
+ <1 RK_PB7 7 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PD3 11 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi_tx {
+ /omit-if-no-ref/
+ hdmi_txm0_pins: hdmi_txm0-pins {
+ rockchip,pins =
+ /* hdmi_tx_cec_m0 */
+ <4 RK_PC0 9 &pcfg_pull_none>,
+ /* hdmi_tx_hpdin_m0 */
+ <4 RK_PC1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_txm1_pins: hdmi_txm1-pins {
+ rockchip,pins =
+ /* hdmi_tx_cec_m1 */
+ <0 RK_PC3 9 &pcfg_pull_none>,
+ /* hdmi_tx_hpdin_m1 */
+ <0 RK_PB6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmi_tx_scl: hdmi-tx-scl {
+ rockchip,pins =
+ /* hdmi_tx_scl */
+ <4 RK_PC2 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ hdmi_tx_sda: hdmi-tx-sda {
+ rockchip,pins =
+ /* hdmi_tx_sda */
+ <4 RK_PC3 9 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <0 RK_PB0 11 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <0 RK_PB1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <0 RK_PC1 9 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <0 RK_PC2 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB2 11 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB3 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <0 RK_PB4 9 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <0 RK_PB5 9 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB7 9 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PC0 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <1 RK_PA0 10 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <1 RK_PA1 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m2_xfer: i2c2m2-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m2 */
+ <4 RK_PA3 11 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m2 */
+ <4 RK_PA5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m3_xfer: i2c2m3-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m3 */
+ <4 RK_PC2 11 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m3 */
+ <4 RK_PC3 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <4 RK_PB5 11 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <4 RK_PB4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <0 RK_PC6 9 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <0 RK_PC7 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m2_xfer: i2c3m2-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m2 */
+ <3 RK_PD4 11 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m2 */
+ <3 RK_PD5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m3_xfer: i2c3m3-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m3 */
+ <4 RK_PC4 11 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m3 */
+ <4 RK_PC5 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <0 RK_PD2 9 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <0 RK_PD3 9 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <4 RK_PA4 11 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <4 RK_PA6 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m2_xfer: i2c4m2-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m2 */
+ <2 RK_PA6 11 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m2 */
+ <2 RK_PA7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m3_xfer: i2c4m3-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m3 */
+ <3 RK_PC0 11 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m3 */
+ <3 RK_PB7 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <2 RK_PA5 11 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <2 RK_PA4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PD4 10 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD5 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m2_xfer: i2c5m2-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m2 */
+ <2 RK_PC6 11 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m2 */
+ <2 RK_PC7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m3_xfer: i2c5m3-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m3 */
+ <3 RK_PC4 11 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m3 */
+ <3 RK_PC1 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ /omit-if-no-ref/
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <0 RK_PA2 11 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <0 RK_PA5 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PC2 10 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PC3 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m2_xfer: i2c6m2-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m2 */
+ <2 RK_PD0 11 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m2 */
+ <2 RK_PD1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c6m3_xfer: i2c6m3-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m3 */
+ <4 RK_PC6 11 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m3 */
+ <4 RK_PC7 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ /omit-if-no-ref/
+ i2c7m0_xfer: i2c7m0-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m0 */
+ <1 RK_PB0 10 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m0 */
+ <1 RK_PB3 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m1_xfer: i2c7m1-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m1 */
+ <3 RK_PA0 11 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m1 */
+ <3 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m2_xfer: i2c7m2-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m2 */
+ <4 RK_PA0 11 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m2 */
+ <4 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c7m3_xfer: i2c7m3-xfer {
+ rockchip,pins =
+ /* i2c7_scl_m3 */
+ <4 RK_PC0 11 &pcfg_pull_none_smt>,
+ /* i2c7_sda_m3 */
+ <4 RK_PC1 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c8 {
+ /omit-if-no-ref/
+ i2c8m0_xfer: i2c8m0-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m0 */
+ <2 RK_PA0 11 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m0 */
+ <2 RK_PA1 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m1_xfer: i2c8m1-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m1 */
+ <1 RK_PC6 10 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m1 */
+ <1 RK_PC7 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m2_xfer: i2c8m2-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m2 */
+ <2 RK_PB6 11 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m2 */
+ <2 RK_PB7 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c8m3_xfer: i2c8m3-xfer {
+ rockchip,pins =
+ /* i2c8_scl_m3 */
+ <3 RK_PB3 11 &pcfg_pull_none_smt>,
+ /* i2c8_sda_m3 */
+ <3 RK_PB2 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c9 {
+ /omit-if-no-ref/
+ i2c9m0_xfer: i2c9m0-xfer {
+ rockchip,pins =
+ /* i2c9_scl_m0 */
+ <1 RK_PA5 10 &pcfg_pull_none_smt>,
+ /* i2c9_sda_m0 */
+ <1 RK_PA6 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m1_xfer: i2c9m1-xfer {
+ rockchip,pins =
+ /* i2c9_scl_m1 */
+ <1 RK_PB5 10 &pcfg_pull_none_smt>,
+ /* i2c9_sda_m1 */
+ <1 RK_PB4 10 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m2_xfer: i2c9m2-xfer {
+ rockchip,pins =
+ /* i2c9_scl_m2 */
+ <2 RK_PD5 11 &pcfg_pull_none_smt>,
+ /* i2c9_sda_m2 */
+ <2 RK_PD4 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c9m3_xfer: i2c9m3-xfer {
+ rockchip,pins =
+ /* i2c9_scl_m3 */
+ <3 RK_PC2 11 &pcfg_pull_none_smt>,
+ /* i2c9_sda_m3 */
+ <3 RK_PC3 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i3c0 {
+ /omit-if-no-ref/
+ i3c0m0_xfer: i3c0m0-xfer {
+ rockchip,pins =
+ /* i3c0_scl_m0 */
+ <0 RK_PC1 11 &pcfg_pull_none_smt>,
+ /* i3c0_sda_m0 */
+ <0 RK_PC2 11 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i3c0m1_xfer: i3c0m1-xfer {
+ rockchip,pins =
+ /* i3c0_scl_m1 */
+ <1 RK_PD2 10 &pcfg_pull_none_smt>,
+ /* i3c0_sda_m1 */
+ <1 RK_PD3 10 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i3c1 {
+ /omit-if-no-ref/
+ i3c1m0_xfer: i3c1m0-xfer {
+ rockchip,pins =
+ /* i3c1_scl_m0 */
+ <2 RK_PD2 12 &pcfg_pull_none_smt>,
+ /* i3c1_sda_m0 */
+ <2 RK_PD3 12 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i3c1m1_xfer: i3c1m1-xfer {
+ rockchip,pins =
+ /* i3c1_scl_m1 */
+ <2 RK_PA2 14 &pcfg_pull_none_smt>,
+ /* i3c1_sda_m1 */
+ <2 RK_PA3 14 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i3c1m2_xfer: i3c1m2-xfer {
+ rockchip,pins =
+ /* i3c1_scl_m2 */
+ <3 RK_PD3 11 &pcfg_pull_none_smt>,
+ /* i3c1_sda_m2 */
+ <3 RK_PD2 11 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i3c0_sda {
+ /omit-if-no-ref/
+ i3c0_sdam0_pu: i3c0_sdam0-pu {
+ rockchip,pins =
+ /* i3c0_sda_pu_m0 */
+ <0 RK_PC5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i3c0_sdam1_pu: i3c0_sdam1-pu {
+ rockchip,pins =
+ /* i3c0_sda_pu_m1 */
+ <1 RK_PD1 10 &pcfg_pull_none>;
+ };
+ };
+
+ i3c1_sda {
+ /omit-if-no-ref/
+ i3c1_sdam0_pu: i3c1_sdam0-pu {
+ rockchip,pins =
+ /* i3c1_sda_pu_m0 */
+ <2 RK_PD6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i3c1_sdam1_pu: i3c1_sdam1-pu {
+ rockchip,pins =
+ /* i3c1_sda_pu_m1 */
+ <2 RK_PA5 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i3c1_sdam2_pu: i3c1_sdam2-pu {
+ rockchip,pins =
+ /* i3c1_sda_pu_m2 */
+ <3 RK_PD1 11 &pcfg_pull_none>;
+ };
+ };
+
+ isp_flash {
+ /omit-if-no-ref/
+ isp_flashm0_pins: isp_flashm0-pins {
+ rockchip,pins =
+ /* isp_flash_trigout_m0 */
+ <2 RK_PD5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ isp_flashm1_pins: isp_flashm1-pins {
+ rockchip,pins =
+ /* isp_flash_trigout_m1 */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+ };
+
+ isp_prelight {
+ /omit-if-no-ref/
+ isp_prelightm0_pins: isp_prelightm0-pins {
+ rockchip,pins =
+ /* isp_prelight_trig_m0 */
+ <2 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ isp_prelightm1_pins: isp_prelightm1-pins {
+ rockchip,pins =
+ /* isp_prelight_trig_m1 */
+ <4 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_tck_m0 */
+ <2 RK_PA2 9 &pcfg_pull_none>,
+ /* jtag_tms_m0 */
+ <2 RK_PA3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_tck_m1 */
+ <0 RK_PD4 10 &pcfg_pull_none>,
+ /* jtag_tms_m1 */
+ <0 RK_PD5 10 &pcfg_pull_none>;
+ };
+ };
+
+ mipi {
+ /omit-if-no-ref/
+ mipim0_pins: mipim0-pins {
+ rockchip,pins =
+ /* mipi_te_m0 */
+ <4 RK_PB2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim1_pins: mipim1-pins {
+ rockchip,pins =
+ /* mipi_te_m1 */
+ <3 RK_PA2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim2_pins: mipim2-pins {
+ rockchip,pins =
+ /* mipi_te_m2 */
+ <4 RK_PA0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ mipim3_pins: mipim3-pins {
+ rockchip,pins =
+ /* mipi_te_m3 */
+ <1 RK_PB3 11 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PB7 11 &pcfg_pull_none>;
+ };
+ };
+
+ pcie0 {
+ /omit-if-no-ref/
+ pcie0m0_pins: pcie0m0-pins {
+ rockchip,pins =
+ /* pcie21_port0_clkreq_m0 */
+ <2 RK_PB2 11 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m1_pins: pcie0m1-pins {
+ rockchip,pins =
+ /* pcie0_clkreq_m1 */
+ <1 RK_PB6 12 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m2_pins: pcie0m2-pins {
+ rockchip,pins =
+ /* pcie0_clkreq_m2 */
+ <4 RK_PB5 12 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0m3_pins: pcie0m3-pins {
+ rockchip,pins =
+ /* pcie0_clkreq_m3 */
+ <4 RK_PC6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie0_buttonrst: pcie21-port0-buttonrst {
+ rockchip,pins =
+ /* pcie0_buttonrst */
+ <1 RK_PC4 12 &pcfg_pull_none>;
+ };
+ };
+
+ pcie1 {
+ /omit-if-no-ref/
+ pcie1m0_pins: pcie1m0-pins {
+ rockchip,pins =
+ /* pcie1_clkreq_m0 */
+ <2 RK_PB3 11 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m1_pins: pcie1m1-pins {
+ rockchip,pins =
+ /* pcie1_clkreq_m1 */
+ <1 RK_PB4 12 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m2_pins: pcie1m2-pins {
+ rockchip,pins =
+ /* pcie1_clkreq_m2 */
+ <4 RK_PA5 12 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1m3_pins: pcie1m3-pins {
+ rockchip,pins =
+ /* pcie1_clkreq_m3 */
+ <4 RK_PC1 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ pcie1_buttonrst: pcie21-port1-buttonrst {
+ rockchip,pins =
+ /* pcie1_buttonrst */
+ <1 RK_PC5 12 &pcfg_pull_none>;
+ };
+ };
+
+ pdm0 {
+ /omit-if-no-ref/
+ pdm0m0_clk0: pdm0m0-clk0 {
+ rockchip,pins =
+ /* pdm0_clk0_m0 */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_clk1: pdm0m0-clk1 {
+ rockchip,pins =
+ /* pdm0_clk1_m0 */
+ <0 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi0: pdm0m0-sdi0 {
+ rockchip,pins =
+ /* pdm0_sdi0_m0 */
+ <0 RK_PD0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi1: pdm0m0-sdi1 {
+ rockchip,pins =
+ /* pdm0_sdi1_m0 */
+ <0 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi2: pdm0m0-sdi2 {
+ rockchip,pins =
+ /* pdm0_sdi2_m0 */
+ <0 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m0_sdi3: pdm0m0-sdi3 {
+ rockchip,pins =
+ /* pdm0_sdi3_m0 */
+ <0 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_clk0: pdm0m1-clk0 {
+ rockchip,pins =
+ /* pdm0_clk0_m1 */
+ <1 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_clk1: pdm0m1-clk1 {
+ rockchip,pins =
+ /* pdm0_clk1_m1 */
+ <1 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi0: pdm0m1-sdi0 {
+ rockchip,pins =
+ /* pdm0_sdi0_m1 */
+ <1 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi1: pdm0m1-sdi1 {
+ rockchip,pins =
+ /* pdm0_sdi1_m1 */
+ <1 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi2: pdm0m1-sdi2 {
+ rockchip,pins =
+ /* pdm0_sdi2_m1 */
+ <1 RK_PA5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m1_sdi3: pdm0m1-sdi3 {
+ rockchip,pins =
+ /* pdm0_sdi3_m1 */
+ <1 RK_PA2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_clk0: pdm0m2-clk0 {
+ rockchip,pins =
+ /* pdm0_clk0_m2 */
+ <1 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_clk1: pdm0m2-clk1 {
+ rockchip,pins =
+ /* pdm0_clk1_m2 */
+ <1 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_sdi0: pdm0m2-sdi0 {
+ rockchip,pins =
+ /* pdm0_sdi0_m2 */
+ <1 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_sdi1: pdm0m2-sdi1 {
+ rockchip,pins =
+ /* pdm0_sdi1_m2 */
+ <1 RK_PC7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_sdi2: pdm0m2-sdi2 {
+ rockchip,pins =
+ /* pdm0_sdi2_m2 */
+ <1 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m2_sdi3: pdm0m2-sdi3 {
+ rockchip,pins =
+ /* pdm0_sdi3_m2 */
+ <1 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_clk0: pdm0m3-clk0 {
+ rockchip,pins =
+ /* pdm0_clk0_m3 */
+ <2 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_clk1: pdm0m3-clk1 {
+ rockchip,pins =
+ /* pdm0_clk1_m3 */
+ <2 RK_PB3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_sdi0: pdm0m3-sdi0 {
+ rockchip,pins =
+ /* pdm0_sdi0_m3 */
+ <2 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_sdi1: pdm0m3-sdi1 {
+ rockchip,pins =
+ /* pdm0_sdi1_m3 */
+ <2 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_sdi2: pdm0m3-sdi2 {
+ rockchip,pins =
+ /* pdm0_sdi2_m3 */
+ <2 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm0m3_sdi3: pdm0m3-sdi3 {
+ rockchip,pins =
+ /* pdm0_sdi3_m3 */
+ <2 RK_PB0 5 &pcfg_pull_none>;
+ };
+ };
+
+ pdm1 {
+ /omit-if-no-ref/
+ pdm1m0_clk0: pdm1m0-clk0 {
+ rockchip,pins =
+ /* pdm1_clk0_m0 */
+ <2 RK_PC5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_clk1: pdm1m0-clk1 {
+ rockchip,pins =
+ /* pdm1_clk1_m0 */
+ <2 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi0: pdm1m0-sdi0 {
+ rockchip,pins =
+ /* pdm1_sdi0_m0 */
+ <2 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi1: pdm1m0-sdi1 {
+ rockchip,pins =
+ /* pdm1_sdi1_m0 */
+ <2 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi2: pdm1m0-sdi2 {
+ rockchip,pins =
+ /* pdm1_sdi2_m0 */
+ <2 RK_PC2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m0_sdi3: pdm1m0-sdi3 {
+ rockchip,pins =
+ /* pdm1_sdi3_m0 */
+ <2 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_clk0: pdm1m1-clk0 {
+ rockchip,pins =
+ /* pdm1_clk0_m1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_clk1: pdm1m1-clk1 {
+ rockchip,pins =
+ /* pdm1_clk1_m1 */
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi0: pdm1m1-sdi0 {
+ rockchip,pins =
+ /* pdm1_sdi0_m1 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi1: pdm1m1-sdi1 {
+ rockchip,pins =
+ /* pdm1_sdi1_m1 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi2: pdm1m1-sdi2 {
+ rockchip,pins =
+ /* pdm1_sdi2_m1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m1_sdi3: pdm1m1-sdi3 {
+ rockchip,pins =
+ /* pdm1_sdi3_m1 */
+ <4 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_clk0: pdm1m2-clk0 {
+ rockchip,pins =
+ /* pdm1_clk0_m2 */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_clk1: pdm1m2-clk1 {
+ rockchip,pins =
+ /* pdm1_clk1_m2 */
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_sdi0: pdm1m2-sdi0 {
+ rockchip,pins =
+ /* pdm1_sdi0_m2 */
+ <3 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_sdi1: pdm1m2-sdi1 {
+ rockchip,pins =
+ /* pdm1_sdi1_m2 */
+ <3 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_sdi2: pdm1m2-sdi2 {
+ rockchip,pins =
+ /* pdm1_sdi2_m2 */
+ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdm1m2_sdi3: pdm1m2-sdi3 {
+ rockchip,pins =
+ /* pdm1_sdi3_m2 */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pmu_debug_test {
+ /omit-if-no-ref/
+ pmu_debug_test_pins: pmu_debug_test-pins {
+ rockchip,pins =
+ /* pmu_debug_test_out */
+ <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_ch0: pwm0m0-ch0 {
+ rockchip,pins =
+ /* pwm0_ch0_m0 */
+ <0 RK_PC4 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m0_ch1: pwm0m0-ch1 {
+ rockchip,pins =
+ /* pwm0_ch1_m0 */
+ <0 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_ch0: pwm0m1-ch0 {
+ rockchip,pins =
+ /* pwm0_ch0_m1 */
+ <1 RK_PC0 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_ch1: pwm0m1-ch1 {
+ rockchip,pins =
+ /* pwm0_ch1_m1 */
+ <4 RK_PC1 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_ch0: pwm0m2-ch0 {
+ rockchip,pins =
+ /* pwm0_ch0_m2 */
+ <2 RK_PC3 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m2_ch1: pwm0m2-ch1 {
+ rockchip,pins =
+ /* pwm0_ch1_m2 */
+ <2 RK_PC7 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m3_ch0: pwm0m3-ch0 {
+ rockchip,pins =
+ /* pwm0_ch0_m3 */
+ <3 RK_PB0 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m3_ch1: pwm0m3-ch1 {
+ rockchip,pins =
+ /* pwm0_ch1_m3 */
+ <3 RK_PB6 12 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_ch0: pwm1m0-ch0 {
+ rockchip,pins =
+ /* pwm1_ch0_m0 */
+ <0 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch1: pwm1m0-ch1 {
+ rockchip,pins =
+ /* pwm1_ch1_m0 */
+ <0 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch2: pwm1m0-ch2 {
+ rockchip,pins =
+ /* pwm1_ch2_m0 */
+ <0 RK_PB6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch3: pwm1m0-ch3 {
+ rockchip,pins =
+ /* pwm1_ch3_m0 */
+ <0 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch4: pwm1m0-ch4 {
+ rockchip,pins =
+ /* pwm1_ch4_m0 */
+ <0 RK_PB7 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m0_ch5: pwm1m0-ch5 {
+ rockchip,pins =
+ /* pwm1_ch5_m0 */
+ <0 RK_PD2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch0: pwm1m1-ch0 {
+ rockchip,pins =
+ /* pwm1_ch0_m1 */
+ <1 RK_PB4 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch1: pwm1m1-ch1 {
+ rockchip,pins =
+ /* pwm1_ch1_m1 */
+ <1 RK_PB5 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch2: pwm1m1-ch2 {
+ rockchip,pins =
+ /* pwm1_ch2_m1 */
+ <1 RK_PC2 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch3: pwm1m1-ch3 {
+ rockchip,pins =
+ /* pwm1_ch3_m1 */
+ <1 RK_PD2 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch4: pwm1m1-ch4 {
+ rockchip,pins =
+ /* pwm1_ch4_m1 */
+ <1 RK_PD3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_ch5: pwm1m1-ch5 {
+ rockchip,pins =
+ /* pwm1_ch5_m1 */
+ <4 RK_PC0 14 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch0: pwm1m2-ch0 {
+ rockchip,pins =
+ /* pwm1_ch0_m2 */
+ <2 RK_PC0 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch1: pwm1m2-ch1 {
+ rockchip,pins =
+ /* pwm1_ch1_m2 */
+ <2 RK_PC1 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch2: pwm1m2-ch2 {
+ rockchip,pins =
+ /* pwm1_ch2_m2 */
+ <2 RK_PC2 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch3: pwm1m2-ch3 {
+ rockchip,pins =
+ /* pwm1_ch3_m2 */
+ <2 RK_PC4 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch4: pwm1m2-ch4 {
+ rockchip,pins =
+ /* pwm1_ch4_m2 */
+ <2 RK_PC5 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m2_ch5: pwm1m2-ch5 {
+ rockchip,pins =
+ /* pwm1_ch5_m2 */
+ <2 RK_PC6 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch0: pwm1m3-ch0 {
+ rockchip,pins =
+ /* pwm1_ch0_m3 */
+ <3 RK_PA4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch1: pwm1m3-ch1 {
+ rockchip,pins =
+ /* pwm1_ch1_m3 */
+ <3 RK_PA5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch2: pwm1m3-ch2 {
+ rockchip,pins =
+ /* pwm1_ch2_m3 */
+ <3 RK_PA6 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch3: pwm1m3-ch3 {
+ rockchip,pins =
+ /* pwm1_ch3_m3 */
+ <3 RK_PB1 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch4: pwm1m3-ch4 {
+ rockchip,pins =
+ /* pwm1_ch4_m3 */
+ <3 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m3_ch5: pwm1m3-ch5 {
+ rockchip,pins =
+ /* pwm1_ch5_m3 */
+ <3 RK_PB5 12 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_ch0: pwm2m0-ch0 {
+ rockchip,pins =
+ /* pwm2_ch0_m0 */
+ <0 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch1: pwm2m0-ch1 {
+ rockchip,pins =
+ /* pwm2_ch1_m0 */
+ <1 RK_PB3 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch2: pwm2m0-ch2 {
+ rockchip,pins =
+ /* pwm2_ch2_m0 */
+ <2 RK_PA0 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch3: pwm2m0-ch3 {
+ rockchip,pins =
+ /* pwm2_ch3_m0 */
+ <2 RK_PA1 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch4: pwm2m0-ch4 {
+ rockchip,pins =
+ /* pwm2_ch4_m0 */
+ <2 RK_PA4 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch5: pwm2m0-ch5 {
+ rockchip,pins =
+ /* pwm2_ch5_m0 */
+ <4 RK_PA2 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch6: pwm2m0-ch6 {
+ rockchip,pins =
+ /* pwm2_ch6_m0 */
+ <4 RK_PA7 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m0_ch7: pwm2m0-ch7 {
+ rockchip,pins =
+ /* pwm2_ch7_m0 */
+ <4 RK_PB3 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch0: pwm2m1-ch0 {
+ rockchip,pins =
+ /* pwm2_ch0_m1 */
+ <4 RK_PC2 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch1: pwm2m1-ch1 {
+ rockchip,pins =
+ /* pwm2_ch1_m1 */
+ <4 RK_PC3 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch2: pwm2m1-ch2 {
+ rockchip,pins =
+ /* pwm2_ch2_m1 */
+ <4 RK_PC6 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch3: pwm2m1-ch3 {
+ rockchip,pins =
+ /* pwm2_ch3_m1 */
+ <4 RK_PC7 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch4: pwm2m1-ch4 {
+ rockchip,pins =
+ /* pwm2_ch4_m1 */
+ <4 RK_PA3 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch5: pwm2m1-ch5 {
+ rockchip,pins =
+ /* pwm2_ch5_m1 */
+ <4 RK_PC5 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch6: pwm2m1-ch6 {
+ rockchip,pins =
+ /* pwm2_ch6_m1 */
+ <4 RK_PC4 14 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_ch7: pwm2m1-ch7 {
+ rockchip,pins =
+ /* pwm2_ch7_m1 */
+ <1 RK_PB1 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch0: pwm2m2-ch0 {
+ rockchip,pins =
+ /* pwm2_ch0_m2 */
+ <2 RK_PD0 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch1: pwm2m2-ch1 {
+ rockchip,pins =
+ /* pwm2_ch1_m2 */
+ <2 RK_PD1 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch2: pwm2m2-ch2 {
+ rockchip,pins =
+ /* pwm2_ch2_m2 */
+ <2 RK_PD2 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch3: pwm2m2-ch3 {
+ rockchip,pins =
+ /* pwm2_ch3_m2 */
+ <2 RK_PD3 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch4: pwm2m2-ch4 {
+ rockchip,pins =
+ /* pwm2_ch4_m2 */
+ <2 RK_PD4 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch5: pwm2m2-ch5 {
+ rockchip,pins =
+ /* pwm2_ch5_m2 */
+ <2 RK_PD5 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch6: pwm2m2-ch6 {
+ rockchip,pins =
+ /* pwm2_ch6_m2 */
+ <2 RK_PD6 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m2_ch7: pwm2m2-ch7 {
+ rockchip,pins =
+ /* pwm2_ch7_m2 */
+ <2 RK_PD7 13 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch0: pwm2m3-ch0 {
+ rockchip,pins =
+ /* pwm2_ch0_m3 */
+ <3 RK_PC2 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch1: pwm2m3-ch1 {
+ rockchip,pins =
+ /* pwm2_ch1_m3 */
+ <3 RK_PC3 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch2: pwm2m3-ch2 {
+ rockchip,pins =
+ /* pwm2_ch2_m3 */
+ <3 RK_PC5 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch3: pwm2m3-ch3 {
+ rockchip,pins =
+ /* pwm2_ch3_m3 */
+ <3 RK_PD0 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch4: pwm2m3-ch4 {
+ rockchip,pins =
+ /* pwm2_ch4_m3 */
+ <3 RK_PD2 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch5: pwm2m3-ch5 {
+ rockchip,pins =
+ /* pwm2_ch5_m3 */
+ <3 RK_PD3 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch6: pwm2m3-ch6 {
+ rockchip,pins =
+ /* pwm2_ch6_m3 */
+ <3 RK_PD6 12 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m3_ch7: pwm2m3-ch7 {
+ rockchip,pins =
+ /* pwm2_ch7_m3 */
+ <3 RK_PD7 12 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ ref_clk0 {
+ /omit-if-no-ref/
+ ref_clk0_clk0: ref_clk0-clk0 {
+ rockchip,pins =
+ /* ref_clk0_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref_clk1 {
+ /omit-if-no-ref/
+ ref_clk1_clk1: ref_clk1-clk1 {
+ rockchip,pins =
+ /* ref_clk1_out */
+ <0 RK_PB4 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref_clk2 {
+ /omit-if-no-ref/
+ ref_clk2_clk2: ref_clk2-clk2 {
+ rockchip,pins =
+ /* ref_clk2_out */
+ <0 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sai0 {
+ /omit-if-no-ref/
+ sai0m0_lrck: sai0m0-lrck {
+ rockchip,pins =
+ /* sai0_lrck_m0 */
+ <2 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_mclk: sai0m0-mclk {
+ rockchip,pins =
+ /* sai0_mclk_m0 */
+ <2 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sclk: sai0m0-sclk {
+ rockchip,pins =
+ /* sai0_sclk_m0 */
+ <2 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi0: sai0m0-sdi0 {
+ rockchip,pins =
+ /* sai0_sdi0_m0 */
+ <2 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi1: sai0m0-sdi1 {
+ rockchip,pins =
+ /* sai0_sdi1_m0 */
+ <2 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi2: sai0m0-sdi2 {
+ rockchip,pins =
+ /* sai0_sdi2_m0 */
+ <2 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdi3: sai0m0-sdi3 {
+ rockchip,pins =
+ /* sai0_sdi3_m0 */
+ <2 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo0: sai0m0-sdo0 {
+ rockchip,pins =
+ /* sai0_sdo0_m0 */
+ <2 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo1: sai0m0-sdo1 {
+ rockchip,pins =
+ /* sai0_sdo1_m0 */
+ <2 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo2: sai0m0-sdo2 {
+ rockchip,pins =
+ /* sai0_sdo2_m0 */
+ <2 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m0_sdo3: sai0m0-sdo3 {
+ rockchip,pins =
+ /* sai0_sdo3_m0 */
+ <2 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_lrck: sai0m1-lrck {
+ rockchip,pins =
+ /* sai0_lrck_m1 */
+ <0 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_mclk: sai0m1-mclk {
+ rockchip,pins =
+ /* sai0_mclk_m1 */
+ <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sclk: sai0m1-sclk {
+ rockchip,pins =
+ /* sai0_sclk_m1 */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi0: sai0m1-sdi0 {
+ rockchip,pins =
+ /* sai0_sdi0_m1 */
+ <0 RK_PD0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi1: sai0m1-sdi1 {
+ rockchip,pins =
+ /* sai0_sdi1_m1 */
+ <0 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi2: sai0m1-sdi2 {
+ rockchip,pins =
+ /* sai0_sdi2_m1 */
+ <0 RK_PD2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdi3: sai0m1-sdi3 {
+ rockchip,pins =
+ /* sai0_sdi3_m1 */
+ <0 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo0: sai0m1-sdo0 {
+ rockchip,pins =
+ /* sai0_sdo0_m1 */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo1: sai0m1-sdo1 {
+ rockchip,pins =
+ /* sai0_sdo1_m1 */
+ <0 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo2: sai0m1-sdo2 {
+ rockchip,pins =
+ /* sai0_sdo2_m1 */
+ <0 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m1_sdo3: sai0m1-sdo3 {
+ rockchip,pins =
+ /* sai0_sdo3_m1 */
+ <0 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_lrck: sai0m2-lrck {
+ rockchip,pins =
+ /* sai0_lrck_m2 */
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_mclk: sai0m2-mclk {
+ rockchip,pins =
+ /* sai0_mclk_m2 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sclk: sai0m2-sclk {
+ rockchip,pins =
+ /* sai0_sclk_m2 */
+ <1 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi0: sai0m2-sdi0 {
+ rockchip,pins =
+ /* sai0_sdi0_m2 */
+ <1 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi1: sai0m2-sdi1 {
+ rockchip,pins =
+ /* sai0_sdi1_m2 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi2: sai0m2-sdi2 {
+ rockchip,pins =
+ /* sai0_sdi2_m2 */
+ <1 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdi3: sai0m2-sdi3 {
+ rockchip,pins =
+ /* sai0_sdi3_m2 */
+ <1 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdo0: sai0m2-sdo0 {
+ rockchip,pins =
+ /* sai0_sdo0_m2 */
+ <1 RK_PA7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdo1: sai0m2-sdo1 {
+ rockchip,pins =
+ /* sai0_sdo1_m2 */
+ <1 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdo2: sai0m2-sdo2 {
+ rockchip,pins =
+ /* sai0_sdo2_m2 */
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai0m2_sdo3: sai0m2-sdo3 {
+ rockchip,pins =
+ /* sai0_sdo3_m2 */
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+ };
+
+ sai1 {
+ /omit-if-no-ref/
+ sai1m0_lrck: sai1m0-lrck {
+ rockchip,pins =
+ /* sai1_lrck_m0 */
+ <4 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_mclk: sai1m0-mclk {
+ rockchip,pins =
+ /* sai1_mclk_m0 */
+ <4 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sclk: sai1m0-sclk {
+ rockchip,pins =
+ /* sai1_sclk_m0 */
+ <4 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi0: sai1m0-sdi0 {
+ rockchip,pins =
+ /* sai1_sdi0_m0 */
+ <4 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi1: sai1m0-sdi1 {
+ rockchip,pins =
+ /* sai1_sdi1_m0 */
+ <4 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi2: sai1m0-sdi2 {
+ rockchip,pins =
+ /* sai1_sdi2_m0 */
+ <4 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdi3: sai1m0-sdi3 {
+ rockchip,pins =
+ /* sai1_sdi3_m0 */
+ <4 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo0: sai1m0-sdo0 {
+ rockchip,pins =
+ /* sai1_sdo0_m0 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo1: sai1m0-sdo1 {
+ rockchip,pins =
+ /* sai1_sdo1_m0 */
+ <4 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo2: sai1m0-sdo2 {
+ rockchip,pins =
+ /* sai1_sdo2_m0 */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m0_sdo3: sai1m0-sdo3 {
+ rockchip,pins =
+ /* sai1_sdo3_m0 */
+ <4 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_lrck: sai1m1-lrck {
+ rockchip,pins =
+ /* sai1_lrck_m1 */
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_mclk: sai1m1-mclk {
+ rockchip,pins =
+ /* sai1_mclk_m1 */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sclk: sai1m1-sclk {
+ rockchip,pins =
+ /* sai1_sclk_m1 */
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi0: sai1m1-sdi0 {
+ rockchip,pins =
+ /* sai1_sdi0_m1 */
+ <3 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi1: sai1m1-sdi1 {
+ rockchip,pins =
+ /* sai1_sdi1_m1 */
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi2: sai1m1-sdi2 {
+ rockchip,pins =
+ /* sai1_sdi2_m1 */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdi3: sai1m1-sdi3 {
+ rockchip,pins =
+ /* sai1_sdi3_m1 */
+ <3 RK_PD6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo0: sai1m1-sdo0 {
+ rockchip,pins =
+ /* sai1_sdo0_m1 */
+ <3 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo1: sai1m1-sdo1 {
+ rockchip,pins =
+ /* sai1_sdo1_m1 */
+ <3 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo2: sai1m1-sdo2 {
+ rockchip,pins =
+ /* sai1_sdo2_m1 */
+ <3 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai1m1_sdo3: sai1m1-sdo3 {
+ rockchip,pins =
+ /* sai1_sdo3_m1 */
+ <3 RK_PC0 4 &pcfg_pull_none>;
+ };
+ };
+
+ sai2 {
+ /omit-if-no-ref/
+ sai2m0_lrck: sai2m0-lrck {
+ rockchip,pins =
+ /* sai2_lrck_m0 */
+ <1 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_mclk: sai2m0-mclk {
+ rockchip,pins =
+ /* sai2_mclk_m0 */
+ <1 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_sclk: sai2m0-sclk {
+ rockchip,pins =
+ /* sai2_sclk_m0 */
+ <1 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m0_sdi: sai2m0-sdi {
+ rockchip,pins =
+ /* sai2m0_sdi */
+ <1 RK_PD3 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai2m0_sdo: sai2m0-sdo {
+ rockchip,pins =
+ /* sai2m0_sdo */
+ <1 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_lrck: sai2m1-lrck {
+ rockchip,pins =
+ /* sai2_lrck_m1 */
+ <2 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_mclk: sai2m1-mclk {
+ rockchip,pins =
+ /* sai2_mclk_m1 */
+ <2 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_sclk: sai2m1-sclk {
+ rockchip,pins =
+ /* sai2_sclk_m1 */
+ <2 RK_PC2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m1_sdi: sai2m1-sdi {
+ rockchip,pins =
+ /* sai2m1_sdi */
+ <2 RK_PC5 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai2m1_sdo: sai2m1-sdo {
+ rockchip,pins =
+ /* sai2m1_sdo */
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m2_lrck: sai2m2-lrck {
+ rockchip,pins =
+ /* sai2_lrck_m2 */
+ <3 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m2_mclk: sai2m2-mclk {
+ rockchip,pins =
+ /* sai2_mclk_m2 */
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m2_sclk: sai2m2-sclk {
+ rockchip,pins =
+ /* sai2_sclk_m2 */
+ <3 RK_PC2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai2m2_sdi: sai2m2-sdi {
+ rockchip,pins =
+ /* sai2m2_sdi */
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai2m2_sdo: sai2m2-sdo {
+ rockchip,pins =
+ /* sai2m2_sdo */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+ };
+
+ sai3 {
+ /omit-if-no-ref/
+ sai3m0_lrck: sai3m0-lrck {
+ rockchip,pins =
+ /* sai3_lrck_m0 */
+ <1 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_mclk: sai3m0-mclk {
+ rockchip,pins =
+ /* sai3_mclk_m0 */
+ <1 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_sclk: sai3m0-sclk {
+ rockchip,pins =
+ /* sai3_sclk_m0 */
+ <1 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m0_sdi: sai3m0-sdi {
+ rockchip,pins =
+ /* sai3m0_sdi */
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai3m0_sdo: sai3m0-sdo {
+ rockchip,pins =
+ /* sai3m0_sdo */
+ <1 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_lrck: sai3m1-lrck {
+ rockchip,pins =
+ /* sai3_lrck_m1 */
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_mclk: sai3m1-mclk {
+ rockchip,pins =
+ /* sai3_mclk_m1 */
+ <1 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_sclk: sai3m1-sclk {
+ rockchip,pins =
+ /* sai3_sclk_m1 */
+ <1 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m1_sdi: sai3m1-sdi {
+ rockchip,pins =
+ /* sai3m1_sdi */
+ <1 RK_PB7 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai3m1_sdo: sai3m1-sdo {
+ rockchip,pins =
+ /* sai3m1_sdo */
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_lrck: sai3m2-lrck {
+ rockchip,pins =
+ /* sai3_lrck_m2 */
+ <3 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_mclk: sai3m2-mclk {
+ rockchip,pins =
+ /* sai3_mclk_m2 */
+ <2 RK_PD6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_sclk: sai3m2-sclk {
+ rockchip,pins =
+ /* sai3_sclk_m2 */
+ <3 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m2_sdi: sai3m2-sdi {
+ rockchip,pins =
+ /* sai3m2_sdi */
+ <3 RK_PA3 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai3m2_sdo: sai3m2-sdo {
+ rockchip,pins =
+ /* sai3m2_sdo */
+ <3 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m3_lrck: sai3m3-lrck {
+ rockchip,pins =
+ /* sai3_lrck_m3 */
+ <2 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m3_mclk: sai3m3-mclk {
+ rockchip,pins =
+ /* sai3_mclk_m3 */
+ <2 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m3_sclk: sai3m3-sclk {
+ rockchip,pins =
+ /* sai3_sclk_m3 */
+ <2 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai3m3_sdi: sai3m3-sdi {
+ rockchip,pins =
+ /* sai3m3_sdi */
+ <2 RK_PA3 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai3m3_sdo: sai3m3-sdo {
+ rockchip,pins =
+ /* sai3m3_sdo */
+ <2 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ sai4 {
+ /omit-if-no-ref/
+ sai4m0_lrck: sai4m0-lrck {
+ rockchip,pins =
+ /* sai4_lrck_m0 */
+ <4 RK_PA6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_mclk: sai4m0-mclk {
+ rockchip,pins =
+ /* sai4_mclk_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sclk: sai4m0-sclk {
+ rockchip,pins =
+ /* sai4_sclk_m0 */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m0_sdi: sai4m0-sdi {
+ rockchip,pins =
+ /* sai4m0_sdi */
+ <4 RK_PA7 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai4m0_sdo: sai4m0-sdo {
+ rockchip,pins =
+ /* sai4m0_sdo */
+ <4 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_lrck: sai4m1-lrck {
+ rockchip,pins =
+ /* sai4_lrck_m1 */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_mclk: sai4m1-mclk {
+ rockchip,pins =
+ /* sai4_mclk_m1 */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_sclk: sai4m1-sclk {
+ rockchip,pins =
+ /* sai4_sclk_m1 */
+ <3 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m1_sdi: sai4m1-sdi {
+ rockchip,pins =
+ /* sai4m1_sdi */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai4m1_sdo: sai4m1-sdo {
+ rockchip,pins =
+ /* sai4m1_sdo */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m2_lrck: sai4m2-lrck {
+ rockchip,pins =
+ /* sai4_lrck_m2 */
+ <4 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m2_mclk: sai4m2-mclk {
+ rockchip,pins =
+ /* sai4_mclk_m2 */
+ <4 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m2_sclk: sai4m2-sclk {
+ rockchip,pins =
+ /* sai4_sclk_m2 */
+ <4 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m2_sdi: sai4m2-sdi {
+ rockchip,pins =
+ /* sai4m2_sdi */
+ <4 RK_PC6 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai4m2_sdo: sai4m2-sdo {
+ rockchip,pins =
+ /* sai4m2_sdo */
+ <4 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m3_lrck: sai4m3-lrck {
+ rockchip,pins =
+ /* sai4_lrck_m3 */
+ <2 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m3_mclk: sai4m3-mclk {
+ rockchip,pins =
+ /* sai4_mclk_m3 */
+ <2 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m3_sclk: sai4m3-sclk {
+ rockchip,pins =
+ /* sai4_sclk_m3 */
+ <2 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sai4m3_sdi: sai4m3-sdi {
+ rockchip,pins =
+ /* sai4m3_sdi */
+ <2 RK_PD0 4 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sai4m3_sdo: sai4m3-sdo {
+ rockchip,pins =
+ /* sai4m3_sdo */
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+ sata30 {
+ /omit-if-no-ref/
+ sata30_sata: sata30-sata {
+ rockchip,pins =
+ /* sata30_cpdet */
+ <1 RK_PC7 12 &pcfg_pull_none>,
+ /* sata30_cppod */
+ <1 RK_PC6 12 &pcfg_pull_none>,
+ /* sata30_mpswit */
+ <1 RK_PD5 12 &pcfg_pull_none>;
+ };
+ };
+
+ sata30_port0 {
+ /omit-if-no-ref/
+ sata30_port0m0_port0: sata30_port0m0-port0 {
+ rockchip,pins =
+ /* sata30_port0_actled_m0 */
+ <2 RK_PB4 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata30_port0m1_port0: sata30_port0m1-port0 {
+ rockchip,pins =
+ /* sata30_port0_actled_m1 */
+ <4 RK_PC6 10 &pcfg_pull_none>;
+ };
+ };
+
+ sata30_port1 {
+ /omit-if-no-ref/
+ sata30_port1m0_port1: sata30_port1m0-port1 {
+ rockchip,pins =
+ /* sata30_port1_actled_m0 */
+ <2 RK_PB5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sata30_port1m1_port1: sata30_port1m1-port1 {
+ rockchip,pins =
+ /* sata30_port1_actled_m1 */
+ <4 RK_PC5 10 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_3>,
+ /* sdmmc0_d1 */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_3>,
+ /* sdmmc0_d2 */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_3>,
+ /* sdmmc0_d3 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_detn */
+ <0 RK_PA7 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_pwren: sdmmc0-pwren {
+ rockchip,pins =
+ /* sdmmc0_pwren */
+ <0 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1m0_bus4: sdmmc1m0-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0_m0 */
+ <1 RK_PB4 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1_m0 */
+ <1 RK_PB5 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2_m0 */
+ <1 RK_PB6 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3_m0 */
+ <1 RK_PB7 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m0_clk: sdmmc1m0-clk {
+ rockchip,pins =
+ /* sdmmc1_clk_m0 */
+ <1 RK_PC1 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m0_cmd: sdmmc1m0-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd_m0 */
+ <1 RK_PC0 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m0_det: sdmmc1m0-det {
+ rockchip,pins =
+ /* sdmmc1_detn_m0 */
+ <1 RK_PC3 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m0_pwren: sdmmc1m0-pwren {
+ rockchip,pins =
+ /* sdmmc1m0_pwren */
+ <1 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_bus4: sdmmc1m1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0_m1 */
+ <2 RK_PA6 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1_m1 */
+ <2 RK_PA7 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2_m1 */
+ <2 RK_PB0 2 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3_m1 */
+ <2 RK_PB1 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_clk: sdmmc1m1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk_m1 */
+ <2 RK_PB3 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_cmd: sdmmc1m1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd_m1 */
+ <2 RK_PB2 2 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_det: sdmmc1m1-det {
+ rockchip,pins =
+ /* sdmmc1_detn_m1 */
+ <2 RK_PB5 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m1_pwren: sdmmc1m1-pwren {
+ rockchip,pins =
+ /* sdmmc1m1_pwren */
+ <2 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1m2_det: sdmmc1m2-det {
+ rockchip,pins =
+ /* sdmmc1_detn_m2 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+
+ sdmmc0_testclk {
+ /omit-if-no-ref/
+ sdmmc0_testclk_test: sdmmc0_testclk-test {
+ rockchip,pins =
+ /* sdmmc0_testclk_out */
+ <1 RK_PC4 6 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0_testdata {
+ /omit-if-no-ref/
+ sdmmc0_testdata_test: sdmmc0_testdata-test {
+ rockchip,pins =
+ /* sdmmc0_testdata_out */
+ <1 RK_PC5 6 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1_testclk {
+ /omit-if-no-ref/
+ sdmmc1_testclkm0_test: sdmmc1_testclkm0-test {
+ rockchip,pins =
+ /* sdmmc1_testclk_out_m0 */
+ <1 RK_PC4 5 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1_testdata {
+ /omit-if-no-ref/
+ sdmmc1_testdatam0_test: sdmmc1_testdatam0-test {
+ rockchip,pins =
+ /* sdmmc1_testdata_out_m0 */
+ <1 RK_PC5 5 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_rx0: spdifm0-rx0 {
+ rockchip,pins =
+ /* spdif_rx0_m0 */
+ <4 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm0_rx1: spdifm0-rx1 {
+ rockchip,pins =
+ /* spdif_rx1_m0 */
+ <3 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm0_tx0: spdifm0-tx0 {
+ rockchip,pins =
+ /* spdif_tx0_m0 */
+ <4 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm0_tx1: spdifm0-tx1 {
+ rockchip,pins =
+ /* spdif_tx1_m0 */
+ <3 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_rx0: spdifm1-rx0 {
+ rockchip,pins =
+ /* spdif_rx0_m1 */
+ <4 RK_PA0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_rx1: spdifm1-rx1 {
+ rockchip,pins =
+ /* spdif_rx1_m1 */
+ <3 RK_PA2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx0: spdifm1-tx0 {
+ rockchip,pins =
+ /* spdif_tx0_m1 */
+ <4 RK_PA1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx1: spdifm1-tx1 {
+ rockchip,pins =
+ /* spdif_tx1_m1 */
+ <3 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_rx0: spdifm2-rx0 {
+ rockchip,pins =
+ /* spdif_rx0_m2 */
+ <2 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_rx1: spdifm2-rx1 {
+ rockchip,pins =
+ /* spdif_rx1_m2 */
+ <1 RK_PD4 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx0: spdifm2-tx0 {
+ rockchip,pins =
+ /* spdif_tx0_m2 */
+ <2 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx1: spdifm2-tx1 {
+ rockchip,pins =
+ /* spdif_tx1_m2 */
+ <1 RK_PD5 6 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <0 RK_PC7 11 &pcfg_pull_none>,
+ /* spi0_miso_m0 */
+ <0 RK_PD1 11 &pcfg_pull_none>,
+ /* spi0_mosi_m0 */
+ <0 RK_PD0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_csn0: spi0m0-csn0 {
+ rockchip,pins =
+ /* spi0m0_csn0 */
+ <0 RK_PC6 11 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi0m0_csn1: spi0m0-csn1 {
+ rockchip,pins =
+ /* spi0m0_csn1 */
+ <0 RK_PC3 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <2 RK_PA5 12 &pcfg_pull_none>,
+ /* spi0_miso_m1 */
+ <2 RK_PA1 12 &pcfg_pull_none>,
+ /* spi0_mosi_m1 */
+ <2 RK_PA0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_csn0: spi0m1-csn0 {
+ rockchip,pins =
+ /* spi0m1_csn0 */
+ <2 RK_PA4 12 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi0m1_csn1: spi0m1-csn1 {
+ rockchip,pins =
+ /* spi0m1_csn1 */
+ <2 RK_PA2 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_pins: spi0m2-pins {
+ rockchip,pins =
+ /* spi0_clk_m2 */
+ <1 RK_PA7 9 &pcfg_pull_none>,
+ /* spi0_miso_m2 */
+ <1 RK_PA6 9 &pcfg_pull_none>,
+ /* spi0_mosi_m2 */
+ <1 RK_PA5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m2_csn0: spi0m2-csn0 {
+ rockchip,pins =
+ /* spi0m2_csn0 */
+ <1 RK_PA4 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi0m2_csn1: spi0m2-csn1 {
+ rockchip,pins =
+ /* spi0m2_csn1 */
+ <1 RK_PB2 9 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clk_m0 */
+ <1 RK_PB4 11 &pcfg_pull_none>,
+ /* spi1_miso_m0 */
+ <1 RK_PB6 11 &pcfg_pull_none>,
+ /* spi1_mosi_m0 */
+ <1 RK_PB5 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_csn0: spi1m0-csn0 {
+ rockchip,pins =
+ /* spi1m0_csn0 */
+ <1 RK_PB7 11 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi1m0_csn1: spi1m0-csn1 {
+ rockchip,pins =
+ /* spi1m0_csn1 */
+ <1 RK_PC0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clk_m1 */
+ <2 RK_PC5 10 &pcfg_pull_none>,
+ /* spi1_miso_m1 */
+ <2 RK_PC3 10 &pcfg_pull_none>,
+ /* spi1_mosi_m1 */
+ <2 RK_PC2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_csn0: spi1m1-csn0 {
+ rockchip,pins =
+ /* spi1m1_csn0 */
+ <2 RK_PC4 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi1m1_csn1: spi1m1-csn1 {
+ rockchip,pins =
+ /* spi1m1_csn1 */
+ <2 RK_PC1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_pins: spi1m2-pins {
+ rockchip,pins =
+ /* spi1_clk_m2 */
+ <3 RK_PC7 10 &pcfg_pull_none>,
+ /* spi1_miso_m2 */
+ <3 RK_PC5 10 &pcfg_pull_none>,
+ /* spi1_mosi_m2 */
+ <3 RK_PC6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m2_csn0: spi1m2-csn0 {
+ rockchip,pins =
+ /* spi1m2_csn0 */
+ <3 RK_PD0 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi1m2_csn1: spi1m2-csn1 {
+ rockchip,pins =
+ /* spi1m2_csn1 */
+ <4 RK_PA0 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clk_m0 */
+ <0 RK_PB2 9 &pcfg_pull_none>,
+ /* spi2_miso_m0 */
+ <0 RK_PB1 9 &pcfg_pull_none>,
+ /* spi2_mosi_m0 */
+ <0 RK_PB3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_csn0: spi2m0-csn0 {
+ rockchip,pins =
+ /* spi2m0_csn0 */
+ <0 RK_PB0 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi2m0_csn1: spi2m0-csn1 {
+ rockchip,pins =
+ /* spi2m0_csn1 */
+ <0 RK_PA7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clk_m1 */
+ <1 RK_PD5 11 &pcfg_pull_none>,
+ /* spi2_miso_m1 */
+ <1 RK_PC5 11 &pcfg_pull_none>,
+ /* spi2_mosi_m1 */
+ <1 RK_PC4 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_csn0: spi2m1-csn0 {
+ rockchip,pins =
+ /* spi2m1_csn0 */
+ <1 RK_PC3 11 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi2m1_csn1: spi2m1-csn1 {
+ rockchip,pins =
+ /* spi2m1_csn1 */
+ <1 RK_PC2 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_pins: spi2m2-pins {
+ rockchip,pins =
+ /* spi2_clk_m2 */
+ <3 RK_PA4 10 &pcfg_pull_none>,
+ /* spi2_miso_m2 */
+ <3 RK_PC1 10 &pcfg_pull_none>,
+ /* spi2_mosi_m2 */
+ <3 RK_PB0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m2_csn0: spi2m2-csn0 {
+ rockchip,pins =
+ /* spi2m2_csn0 */
+ <3 RK_PC4 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi2m2_csn1: spi2m2-csn1 {
+ rockchip,pins =
+ /* spi2m2_csn1 */
+ <3 RK_PA5 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clk_m0 */
+ <3 RK_PA0 10 &pcfg_pull_none>,
+ /* spi3_miso_m0 */
+ <3 RK_PA2 10 &pcfg_pull_none>,
+ /* spi3_mosi_m0 */
+ <3 RK_PA1 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_csn0: spi3m0-csn0 {
+ rockchip,pins =
+ /* spi3m0_csn0 */
+ <3 RK_PA3 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi3m0_csn1: spi3m0-csn1 {
+ rockchip,pins =
+ /* spi3m0_csn1 */
+ <2 RK_PD7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clk_m1 */
+ <3 RK_PD4 10 &pcfg_pull_none>,
+ /* spi3_miso_m1 */
+ <3 RK_PD5 10 &pcfg_pull_none>,
+ /* spi3_mosi_m1 */
+ <3 RK_PD6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_csn0: spi3m1-csn0 {
+ rockchip,pins =
+ /* spi3m1_csn0 */
+ <3 RK_PB6 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi3m1_csn1: spi3m1-csn1 {
+ rockchip,pins =
+ /* spi3m1_csn1 */
+ <3 RK_PD7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_pins: spi3m2-pins {
+ rockchip,pins =
+ /* spi3_clk_m2 */
+ <4 RK_PA7 9 &pcfg_pull_none>,
+ /* spi3_miso_m2 */
+ <4 RK_PA6 9 &pcfg_pull_none>,
+ /* spi3_mosi_m2 */
+ <4 RK_PA4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m2_csn0: spi3m2-csn0 {
+ rockchip,pins =
+ /* spi3m2_csn0 */
+ <4 RK_PA3 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi3m2_csn1: spi3m2-csn1 {
+ rockchip,pins =
+ /* spi3m2_csn1 */
+ <4 RK_PB3 10 &pcfg_pull_none>;
+ };
+ };
+
+ spi4 {
+ /omit-if-no-ref/
+ spi4m0_pins: spi4m0-pins {
+ rockchip,pins =
+ /* spi4_clk_m0 */
+ <4 RK_PC7 12 &pcfg_pull_none>,
+ /* spi4_miso_m0 */
+ <4 RK_PC6 12 &pcfg_pull_none>,
+ /* spi4_mosi_m0 */
+ <4 RK_PC5 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m0_csn0: spi4m0-csn0 {
+ rockchip,pins =
+ /* spi4m0_csn0 */
+ <4 RK_PC4 12 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi4m0_csn1: spi4m0-csn1 {
+ rockchip,pins =
+ /* spi4m0_csn1 */
+ <4 RK_PC0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_pins: spi4m1-pins {
+ rockchip,pins =
+ /* spi4_clk_m1 */
+ <3 RK_PD1 10 &pcfg_pull_none>,
+ /* spi4_miso_m1 */
+ <3 RK_PC2 10 &pcfg_pull_none>,
+ /* spi4_mosi_m1 */
+ <3 RK_PC3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m1_csn0: spi4m1-csn0 {
+ rockchip,pins =
+ /* spi4m1_csn0 */
+ <3 RK_PB1 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi4m1_csn1: spi4m1-csn1 {
+ rockchip,pins =
+ /* spi4m1_csn1 */
+ <3 RK_PD2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_pins: spi4m2-pins {
+ rockchip,pins =
+ /* spi4_clk_m2 */
+ <4 RK_PB0 9 &pcfg_pull_none>,
+ /* spi4_miso_m2 */
+ <4 RK_PB2 9 &pcfg_pull_none>,
+ /* spi4_mosi_m2 */
+ <4 RK_PB1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m2_csn0: spi4m2-csn0 {
+ rockchip,pins =
+ /* spi4m2_csn0 */
+ <4 RK_PB3 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi4m2_csn1: spi4m2-csn1 {
+ rockchip,pins =
+ /* spi4m2_csn1 */
+ <4 RK_PA5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m3_pins: spi4m3-pins {
+ rockchip,pins =
+ /* spi4_clk_m3 */
+ <2 RK_PB3 10 &pcfg_pull_none>,
+ /* spi4_miso_m3 */
+ <2 RK_PB5 10 &pcfg_pull_none>,
+ /* spi4_mosi_m3 */
+ <2 RK_PB4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi4m3_csn0: spi4m3-csn0 {
+ rockchip,pins =
+ /* spi4m3_csn0 */
+ <2 RK_PB2 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ spi4m3_csn1: spi4m3-csn1 {
+ rockchip,pins =
+ /* spi4m3_csn1 */
+ <2 RK_PA6 10 &pcfg_pull_none>;
+ };
+ };
+
+ test_clk {
+ /omit-if-no-ref/
+ test_clk_pins: test_clk-pins {
+ rockchip,pins =
+ /* test_clk_out */
+ <2 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm0_pins: tsadcm0-pins {
+ rockchip,pins =
+ /* tsadc_ctrl_m0 */
+ <0 RK_PA1 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadcm1_pins: tsadcm1-pins {
+ rockchip,pins =
+ /* tsadc_ctrl_m1 */
+ <0 RK_PA3 10 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc_ctrl {
+ /omit-if-no-ref/
+ tsadc_ctrl_pins: tsadc_ctrl-pins {
+ rockchip,pins =
+ /* tsadc_ctrl_org */
+ <0 RK_PA1 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PD5 9 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PD4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <2 RK_PA0 9 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <2 RK_PA1 9 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PC0 10 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB7 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <0 RK_PD2 13 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <0 RK_PD3 13 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <2 RK_PB1 9 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <2 RK_PB0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <2 RK_PB2 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <2 RK_PB3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_xfer: uart1m2-xfer {
+ rockchip,pins =
+ /* uart1_rx_m2 */
+ <3 RK_PA6 9 &pcfg_pull_up>,
+ /* uart1_tx_m2 */
+ <3 RK_PA7 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m2_ctsn: uart1m2-ctsn {
+ rockchip,pins =
+ /* uart1m2_ctsn */
+ <3 RK_PA4 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart1m2_rtsn: uart1m2-rtsn {
+ rockchip,pins =
+ /* uart1m2_rtsn */
+ <3 RK_PA5 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <1 RK_PC7 9 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <1 RK_PC6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <1 RK_PC5 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <1 RK_PC4 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <4 RK_PB4 10 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <4 RK_PB5 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <4 RK_PB1 12 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <4 RK_PB0 12 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_xfer: uart2m2-xfer {
+ rockchip,pins =
+ /* uart2_rx_m2 */
+ <3 RK_PB7 9 &pcfg_pull_up>,
+ /* uart2_tx_m2 */
+ <3 RK_PC0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m2_ctsn: uart2m2-ctsn {
+ rockchip,pins =
+ /* uart2m2_ctsn */
+ <3 RK_PD3 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart2m2_rtsn: uart2m2-rtsn {
+ rockchip,pins =
+ /* uart2m2_rtsn */
+ <3 RK_PD2 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PA1 9 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PA0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_ctsn: uart3m0-ctsn {
+ rockchip,pins =
+ /* uart3m0_ctsn */
+ <3 RK_PA2 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3m0_rtsn: uart3m0-rtsn {
+ rockchip,pins =
+ /* uart3m0_rtsn */
+ <3 RK_PA3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <4 RK_PA1 9 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <4 RK_PA0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_ctsn: uart3m1-ctsn {
+ rockchip,pins =
+ /* uart3m1_ctsn */
+ <3 RK_PB7 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3m1_rtsn: uart3m1-rtsn {
+ rockchip,pins =
+ /* uart3m1_rtsn */
+ <3 RK_PC0 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_xfer: uart3m2-xfer {
+ rockchip,pins =
+ /* uart3_rx_m2 */
+ <1 RK_PC1 9 &pcfg_pull_up>,
+ /* uart3_tx_m2 */
+ <1 RK_PC0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m2_ctsn: uart3m2-ctsn {
+ rockchip,pins =
+ /* uart3m2_ctsn */
+ <1 RK_PB6 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart3m2_rtsn: uart3m2-rtsn {
+ rockchip,pins =
+ /* uart3m2_rtsn */
+ <1 RK_PB7 9 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <2 RK_PD1 9 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <2 RK_PD0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_ctsn: uart4m0-ctsn {
+ rockchip,pins =
+ /* uart4m0_ctsn */
+ <2 RK_PC6 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4m0_rtsn: uart4m0-rtsn {
+ rockchip,pins =
+ /* uart4m0_rtsn */
+ <2 RK_PC7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rx_m1 */
+ <1 RK_PC5 9 &pcfg_pull_up>,
+ /* uart4_tx_m1 */
+ <1 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_ctsn: uart4m1-ctsn {
+ rockchip,pins =
+ /* uart4m1_ctsn */
+ <1 RK_PC3 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart4m1_rtsn: uart4m1-rtsn {
+ rockchip,pins =
+ /* uart4m1_rtsn */
+ <1 RK_PC2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m2_xfer: uart4m2-xfer {
+ rockchip,pins =
+ /* uart4_rx_m2 */
+ <0 RK_PB5 10 &pcfg_pull_up>,
+ /* uart4_tx_m2 */
+ <0 RK_PB4 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PD4 9 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PD5 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <3 RK_PD6 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <3 RK_PD7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <4 RK_PB1 10 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <4 RK_PB0 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <4 RK_PA5 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <4 RK_PA3 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_xfer: uart5m2-xfer {
+ rockchip,pins =
+ /* uart5_rx_m2 */
+ <2 RK_PA4 9 &pcfg_pull_up>,
+ /* uart5_tx_m2 */
+ <2 RK_PA5 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m2_ctsn: uart5m2-ctsn {
+ rockchip,pins =
+ /* uart5m2_ctsn */
+ <2 RK_PA3 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart5m2_rtsn: uart5m2-rtsn {
+ rockchip,pins =
+ /* uart5m2_rtsn */
+ <2 RK_PA2 10 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <4 RK_PA6 10 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <4 RK_PA4 10 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <4 RK_PB1 11 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <4 RK_PB0 11 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <2 RK_PD3 9 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <2 RK_PD2 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_ctsn: uart6m1-ctsn {
+ rockchip,pins =
+ /* uart6m1_ctsn */
+ <2 RK_PD5 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6m1_rtsn: uart6m1-rtsn {
+ rockchip,pins =
+ /* uart6m1_rtsn */
+ <2 RK_PD4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_xfer: uart6m2-xfer {
+ rockchip,pins =
+ /* uart6_rx_m2 */
+ <1 RK_PB3 9 &pcfg_pull_up>,
+ /* uart6_tx_m2 */
+ <1 RK_PB0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m2_ctsn: uart6m2-ctsn {
+ rockchip,pins =
+ /* uart6m2_ctsn */
+ <1 RK_PA3 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart6m2_rtsn: uart6m2-rtsn {
+ rockchip,pins =
+ /* uart6m2_rtsn */
+ <1 RK_PA2 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m3_xfer: uart6m3-xfer {
+ rockchip,pins =
+ /* uart6_rx_m3 */
+ <4 RK_PC5 13 &pcfg_pull_up>,
+ /* uart6_tx_m3 */
+ <4 RK_PC4 13 &pcfg_pull_up>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <2 RK_PB7 9 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <2 RK_PB6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <2 RK_PB4 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <2 RK_PB5 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PA3 9 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PA2 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <1 RK_PA1 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <1 RK_PA0 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer: uart7m2-xfer {
+ rockchip,pins =
+ /* uart7_rx_m2 */
+ <2 RK_PA0 10 &pcfg_pull_up>,
+ /* uart7_tx_m2 */
+ <2 RK_PA1 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rx_m0 */
+ <3 RK_PC5 9 &pcfg_pull_up>,
+ /* uart8_tx_m0 */
+ <3 RK_PC6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <3 RK_PD0 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <3 RK_PC7 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rx_m1 */
+ <2 RK_PA7 9 &pcfg_pull_up>,
+ /* uart8_tx_m1 */
+ <2 RK_PA6 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_ctsn: uart8m1-ctsn {
+ rockchip,pins =
+ /* uart8m1_ctsn */
+ <2 RK_PB7 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart8m1_rtsn: uart8m1-rtsn {
+ rockchip,pins =
+ /* uart8m1_rtsn */
+ <2 RK_PB6 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m2_xfer: uart8m2-xfer {
+ rockchip,pins =
+ /* uart8_rx_m2 */
+ <0 RK_PC2 10 &pcfg_pull_up>,
+ /* uart8_tx_m2 */
+ <0 RK_PC1 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <2 RK_PC0 9 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <2 RK_PC1 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <2 RK_PD7 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <2 RK_PD6 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rx_m1 */
+ <3 RK_PB2 9 &pcfg_pull_up>,
+ /* uart9_tx_m1 */
+ <3 RK_PB3 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_ctsn: uart9m1-ctsn {
+ rockchip,pins =
+ /* uart9m1_ctsn */
+ <3 RK_PB5 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart9m1_rtsn: uart9m1-rtsn {
+ rockchip,pins =
+ /* uart9m1_rtsn */
+ <3 RK_PB4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer: uart9m2-xfer {
+ rockchip,pins =
+ /* uart9_rx_m2 */
+ <4 RK_PC3 13 &pcfg_pull_up>,
+ /* uart9_tx_m2 */
+ <4 RK_PC2 13 &pcfg_pull_up>;
+ };
+ };
+
+ uart10 {
+ /omit-if-no-ref/
+ uart10m0_xfer: uart10m0-xfer {
+ rockchip,pins =
+ /* uart10_rx_m0 */
+ <3 RK_PB0 9 &pcfg_pull_up>,
+ /* uart10_tx_m0 */
+ <3 RK_PB1 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart10m0_ctsn: uart10m0-ctsn {
+ rockchip,pins =
+ /* uart10m0_ctsn */
+ <3 RK_PA6 10 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart10m0_rtsn: uart10m0-rtsn {
+ rockchip,pins =
+ /* uart10m0_rtsn */
+ <3 RK_PA7 10 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m1_xfer: uart10m1-xfer {
+ rockchip,pins =
+ /* uart10_rx_m1 */
+ <1 RK_PD1 9 &pcfg_pull_up>,
+ /* uart10_tx_m1 */
+ <1 RK_PD0 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart10m1_ctsn: uart10m1-ctsn {
+ rockchip,pins =
+ /* uart10m1_ctsn */
+ <1 RK_PD5 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart10m1_rtsn: uart10m1-rtsn {
+ rockchip,pins =
+ /* uart10m1_rtsn */
+ <1 RK_PD4 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart10m2_xfer: uart10m2-xfer {
+ rockchip,pins =
+ /* uart10_rx_m2 */
+ <0 RK_PC5 10 &pcfg_pull_up>,
+ /* uart10_tx_m2 */
+ <0 RK_PC4 10 &pcfg_pull_up>;
+ };
+ };
+
+ uart11 {
+ /omit-if-no-ref/
+ uart11m0_xfer: uart11m0-xfer {
+ rockchip,pins =
+ /* uart11_rx_m0 */
+ <3 RK_PC1 9 &pcfg_pull_up>,
+ /* uart11_tx_m0 */
+ <3 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart11m0_ctsn: uart11m0-ctsn {
+ rockchip,pins =
+ /* uart11m0_ctsn */
+ <3 RK_PC3 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart11m0_rtsn: uart11m0-rtsn {
+ rockchip,pins =
+ /* uart11m0_rtsn */
+ <3 RK_PC2 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart11m1_xfer: uart11m1-xfer {
+ rockchip,pins =
+ /* uart11_rx_m1 */
+ <2 RK_PC5 9 &pcfg_pull_up>,
+ /* uart11_tx_m1 */
+ <2 RK_PC4 9 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart11m1_ctsn: uart11m1-ctsn {
+ rockchip,pins =
+ /* uart11m1_ctsn */
+ <2 RK_PC2 9 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart11m1_rtsn: uart11m1-rtsn {
+ rockchip,pins =
+ /* uart11m1_rtsn */
+ <2 RK_PC3 9 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart11m2_xfer: uart11m2-xfer {
+ rockchip,pins =
+ /* uart11_rx_m2 */
+ <4 RK_PC1 13 &pcfg_pull_up>,
+ /* uart11_tx_m2 */
+ <4 RK_PC0 13 &pcfg_pull_up>;
+ };
+ };
+
+ ufs {
+ /omit-if-no-ref/
+ ufs_refclk: ufs-refclk {
+ rockchip,pins =
+ /* ufs_refclk */
+ <4 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ufs_rst: ufs-rst {
+ rockchip,pins =
+ /* ufs_rstn */
+ <4 RK_PD0 1 &pcfg_pull_none>;
+ };
+ };
+
+ ufs_testdata0 {
+ /omit-if-no-ref/
+ ufs_testdata0_test: ufs_testdata0-test {
+ rockchip,pins =
+ /* ufs_testdata0_out */
+ <4 RK_PC4 4 &pcfg_pull_none>;
+ };
+ };
+
+ ufs_testdata1 {
+ /omit-if-no-ref/
+ ufs_testdata1_test: ufs_testdata1-test {
+ rockchip,pins =
+ /* ufs_testdata1_out */
+ <4 RK_PC5 4 &pcfg_pull_none>;
+ };
+ };
+
+ ufs_testdata2 {
+ /omit-if-no-ref/
+ ufs_testdata2_test: ufs_testdata2-test {
+ rockchip,pins =
+ /* ufs_testdata2_out */
+ <4 RK_PC6 4 &pcfg_pull_none>;
+ };
+ };
+
+ ufs_testdata3 {
+ /omit-if-no-ref/
+ ufs_testdata3_test: ufs_testdata3-test {
+ rockchip,pins =
+ /* ufs_testdata3_out */
+ <4 RK_PC7 4 &pcfg_pull_none>;
+ };
+ };
+
+ vi_cif {
+ /omit-if-no-ref/
+ vi_cif_pins: vi_cif-pins {
+ rockchip,pins =
+ /* vi_cif_clki */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* vi_cif_clko */
+ <3 RK_PA2 1 &pcfg_pull_none>,
+ /* vi_cif_d0 */
+ <2 RK_PC5 1 &pcfg_pull_none>,
+ /* vi_cif_d1 */
+ <2 RK_PC4 1 &pcfg_pull_none>,
+ /* vi_cif_d2 */
+ <2 RK_PC3 1 &pcfg_pull_none>,
+ /* vi_cif_d3 */
+ <2 RK_PC2 1 &pcfg_pull_none>,
+ /* vi_cif_d4 */
+ <2 RK_PC1 1 &pcfg_pull_none>,
+ /* vi_cif_d5 */
+ <2 RK_PC0 1 &pcfg_pull_none>,
+ /* vi_cif_d6 */
+ <2 RK_PB7 1 &pcfg_pull_none>,
+ /* vi_cif_d7 */
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ /* vi_cif_d8 */
+ <2 RK_PB5 1 &pcfg_pull_none>,
+ /* vi_cif_d9 */
+ <2 RK_PB4 1 &pcfg_pull_none>,
+ /* vi_cif_d10 */
+ <2 RK_PB3 1 &pcfg_pull_none>,
+ /* vi_cif_d11 */
+ <2 RK_PB2 1 &pcfg_pull_none>,
+ /* vi_cif_d12 */
+ <2 RK_PB1 1 &pcfg_pull_none>,
+ /* vi_cif_d13 */
+ <2 RK_PB0 1 &pcfg_pull_none>,
+ /* vi_cif_d14 */
+ <2 RK_PA7 1 &pcfg_pull_none>,
+ /* vi_cif_d15 */
+ <2 RK_PA6 1 &pcfg_pull_none>,
+ /* vi_cif_href */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* vi_cif_vsync */
+ <3 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ vo_lcdc {
+ /omit-if-no-ref/
+ vo_lcdc_pins: vo_lcdc-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d0 */
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d1 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d2 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d8 */
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d9 */
+ <3 RK_PC2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d16 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d17 */
+ <3 RK_PB2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d18 */
+ <3 RK_PB1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ vo_post {
+ /omit-if-no-ref/
+ vo_post_pins: vo_post-pins {
+ rockchip,pins =
+ /* vo_post_empty */
+ <4 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ vp0_sync {
+ /omit-if-no-ref/
+ vp0_sync_pins: vp0_sync-pins {
+ rockchip,pins =
+ /* vp0_sync_out */
+ <4 RK_PC5 3 &pcfg_pull_none>;
+ };
+ };
+
+ vp1_sync {
+ /omit-if-no-ref/
+ vp1_sync_pins: vp1_sync-pins {
+ rockchip,pins =
+ /* vp1_sync_out */
+ <4 RK_PC6 3 &pcfg_pull_none>;
+ };
+ };
+
+ vp2_sync {
+ /omit-if-no-ref/
+ vp2_sync_pins: vp2_sync-pins {
+ rockchip,pins =
+ /* vp2_sync_out */
+ <4 RK_PC7 3 &pcfg_pull_none>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ /* pmic_int */
+ <0 RK_PA6 9 &pcfg_pull_up>,
+ /* pmic_sleep */
+ <0 RK_PA4 9 &pcfg_pull_none>;
+ };
+ };
+
+ vo {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ bt656_pins: bt656-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m0: rgb3x8-pins-m0 {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb3x8_pins_m1: rgb3x8-pins-m1 {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb565_pins: rgb565-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb666_pins: rgb666-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d2 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d18 */
+ <3 RK_PB1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ rgb888_pins: rgb888-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d0 */
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d1 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d2 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d8 */
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d9 */
+ <3 RK_PC2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d16 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d17 */
+ <3 RK_PB2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d18 */
+ <3 RK_PB1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <3 RK_PD6 1 &pcfg_pull_none>;
+ };
+ };
+
+ vo_ebc {
+ /omit-if-no-ref/
+ vo_ebc_pins: vo_ebc-pins {
+ rockchip,pins =
+ /* vo_ebc_gdclk */
+ <3 RK_PD5 2 &pcfg_pull_none>,
+ /* vo_ebc_gdoe */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* vo_ebc_gdsp */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* vo_ebc_sdce0 */
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ /* vo_ebc_sdclk */
+ <3 RK_PD6 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo0 */
+ <3 RK_PD3 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo1 */
+ <3 RK_PD2 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo2 */
+ <3 RK_PD1 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo3 */
+ <3 RK_PD0 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo4 */
+ <3 RK_PC7 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo5 */
+ <3 RK_PC6 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo6 */
+ <3 RK_PC5 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo7 */
+ <3 RK_PC4 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo8 */
+ <3 RK_PC3 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo9 */
+ <3 RK_PC2 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo10 */
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo11 */
+ <3 RK_PC0 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo12 */
+ <3 RK_PB7 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo13 */
+ <3 RK_PB6 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo14 */
+ <3 RK_PB5 2 &pcfg_pull_none>,
+ /* vo_ebc_sddo15 */
+ <3 RK_PB4 2 &pcfg_pull_none>,
+ /* vo_ebc_sdle */
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ /* vo_ebc_sdoe */
+ <3 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ vo_ebc_extern: vo_ebc-extern {
+ rockchip,pins =
+ /* vo_ebc_sdce1 */
+ <3 RK_PB2 2 &pcfg_pull_none>,
+ /* vo_ebc_sdce2 */
+ <3 RK_PB1 2 &pcfg_pull_none>,
+ /* vo_ebc_sdce3 */
+ <3 RK_PB0 2 &pcfg_pull_none>,
+ /* vo_ebc_sdshr */
+ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* vo_ebc_vcom */
+ <3 RK_PA7 2 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
new file mode 100644
index 00000000000..436232ffe4d
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -0,0 +1,1678 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rk3576-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rockchip,rk3576-power.h>
+#include <dt-bindings/reset/rockchip,rk3576-cru.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ compatible = "rockchip,rk3576";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ serial10 = &uart10;
+ serial11 = &uart11;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ };
+
+ xin32k: clock-xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ #clock-cells = <0>;
+ };
+
+ xin24m: clock-xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ spll: clock-spll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <702000000>;
+ clock-output-names = "spll";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu_l0>;
+ };
+ core1 {
+ cpu = <&cpu_l1>;
+ };
+ core2 {
+ cpu = <&cpu_l2>;
+ };
+ core3 {
+ cpu = <&cpu_l3>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&cpu_b0>;
+ };
+ core1 {
+ cpu = <&cpu_b1>;
+ };
+ core2 {
+ cpu = <&cpu_b2>;
+ };
+ core3 {
+ cpu = <&cpu_b3>;
+ };
+ };
+ };
+
+ cpu_l0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+ clocks = <&scmi_clk ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <120>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_l1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+ clocks = <&scmi_clk ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_l2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+ clocks = <&scmi_clk ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_l3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <485>;
+ clocks = <&scmi_clk ARMCLK_L>;
+ operating-points-v2 = <&cluster0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_b0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ #cooling-cells = <2>;
+ dynamic-power-coefficient = <320>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_b1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_b2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ cpu_b3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ clocks = <&scmi_clk ARMCLK_B>;
+ operating-points-v2 = <&cluster1_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ local-timer-stop;
+ };
+ };
+ };
+
+ cluster0_opp_table: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <725000 725000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <750000 750000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <825000 825000 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <900000 900000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ cluster1_opp_table: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <700000 700000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <712500 712500 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <737500 737500 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <800000 800000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <862500 862500 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <925000 925000 950000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-2304000000 {
+ opp-hz = /bits/ 64 <2304000000>;
+ opp-microvolt = <950000 950000 950000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <700000 700000 850000>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <725000 725000 850000>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <775000 775000 850000>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <825000 825000 850000>;
+ };
+
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <850000 850000 850000>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ pmu_a53: pmu-a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>;
+ };
+
+ pmu_a72: pmu-a72 {
+ compatible = "arm,cortex-a72-pmu";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ sys_grf: syscon@2600a000 {
+ compatible = "rockchip,rk3576-sys-grf", "syscon";
+ reg = <0x0 0x2600a000 0x0 0x2000>;
+ };
+
+ bigcore_grf: syscon@2600c000 {
+ compatible = "rockchip,rk3576-bigcore-grf", "syscon";
+ reg = <0x0 0x2600c000 0x0 0x2000>;
+ };
+
+ litcore_grf: syscon@2600e000 {
+ compatible = "rockchip,rk3576-litcore-grf", "syscon";
+ reg = <0x0 0x2600e000 0x0 0x2000>;
+ };
+
+ cci_grf: syscon@26010000 {
+ compatible = "rockchip,rk3576-cci-grf", "syscon";
+ reg = <0x0 0x26010000 0x0 0x2000>;
+ };
+
+ gpu_grf: syscon@26016000 {
+ compatible = "rockchip,rk3576-gpu-grf", "syscon";
+ reg = <0x0 0x26016000 0x0 0x2000>;
+ };
+
+ npu_grf: syscon@26018000 {
+ compatible = "rockchip,rk3576-npu-grf", "syscon";
+ reg = <0x0 0x26018000 0x0 0x2000>;
+ };
+
+ vo0_grf: syscon@2601a000 {
+ compatible = "rockchip,rk3576-vo0-grf", "syscon";
+ reg = <0x0 0x2601a000 0x0 0x2000>;
+ };
+
+ usb_grf: syscon@2601e000 {
+ compatible = "rockchip,rk3576-usb-grf", "syscon";
+ reg = <0x0 0x2601e000 0x0 0x1000>;
+ };
+
+ php_grf: syscon@26020000 {
+ compatible = "rockchip,rk3576-php-grf", "syscon";
+ reg = <0x0 0x26020000 0x0 0x2000>;
+ };
+
+ pmu0_grf: syscon@26024000 {
+ compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd";
+ reg = <0x0 0x26024000 0x0 0x1000>;
+ };
+
+ pmu1_grf: syscon@26026000 {
+ compatible = "rockchip,rk3576-pmu1-grf", "syscon";
+ reg = <0x0 0x26026000 0x0 0x1000>;
+ };
+
+ pipe_phy0_grf: syscon@26028000 {
+ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
+ reg = <0x0 0x26028000 0x0 0x2000>;
+ };
+
+ pipe_phy1_grf: syscon@2602a000 {
+ compatible = "rockchip,rk3576-pipe-phy-grf", "syscon";
+ reg = <0x0 0x2602a000 0x0 0x2000>;
+ };
+
+ usbdpphy_grf: syscon@2602c000 {
+ compatible = "rockchip,rk3576-usbdpphy-grf", "syscon";
+ reg = <0x0 0x2602c000 0x0 0x2000>;
+ };
+
+ sdgmac_grf: syscon@26038000 {
+ compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
+ reg = <0x0 0x26038000 0x0 0x1000>;
+ };
+
+ ioc_grf: syscon@26040000 {
+ compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd";
+ reg = <0x0 0x26040000 0x0 0xc000>;
+ };
+
+ cru: clock-controller@27200000 {
+ compatible = "rockchip,rk3576-cru";
+ reg = <0x0 0x27200000 0x0 0x50000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ assigned-clocks =
+ <&cru CLK_AUDIO_FRAC_1_SRC>,
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>,
+ <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>,
+ <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>,
+ <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>,
+ <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>,
+ <&cru ACLK_PHP_ROOT>;
+ assigned-clock-parents = <&cru PLL_AUPLL>;
+ assigned-clock-rates =
+ <0>,
+ <1188000000>, <1000000000>,
+ <786432000>, <18432000>,
+ <96000000>, <128000000>,
+ <45158400>, <49152000>,
+ <500000000>, <250000000>,
+ <100000000>, <500000000>,
+ <250000000>;
+ };
+
+ i2c0: i2c@27300000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x27300000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart1: serial@27310000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x27310000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ status = "disabled";
+ };
+
+ pmu: power-management@27380000 {
+ compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0x27380000 0x0 0x800>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3576-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_NPU {
+ reg = <RK3576_PD_NPU>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_NPUTOP {
+ reg = <RK3576_PD_NPUTOP>;
+ clocks = <&cru ACLK_RKNN0>,
+ <&cru ACLK_RKNN1>,
+ <&cru ACLK_RKNN_CBUF>,
+ <&cru CLK_RKNN_DSU0>,
+ <&cru HCLK_RKNN_CBUF>,
+ <&cru HCLK_RKNN_ROOT>,
+ <&cru HCLK_NPU_CM0_ROOT>,
+ <&cru PCLK_NPUTOP_ROOT>;
+ pm_qos = <&qos_npu_mcu>,
+ <&qos_npu_nsp0>,
+ <&qos_npu_nsp1>,
+ <&qos_npu_m0ro>,
+ <&qos_npu_m1ro>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_NPU0 {
+ reg = <RK3576_PD_NPU0>;
+ clocks = <&cru HCLK_RKNN_ROOT>,
+ <&cru ACLK_RKNN0>;
+ pm_qos = <&qos_npu_m0>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3576_PD_NPU1 {
+ reg = <RK3576_PD_NPU1>;
+ clocks = <&cru HCLK_RKNN_ROOT>,
+ <&cru ACLK_RKNN1>;
+ pm_qos = <&qos_npu_m1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@RK3576_PD_GPU {
+ reg = <RK3576_PD_GPU>;
+ clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_NVM {
+ reg = <RK3576_PD_NVM>;
+ clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_fspi0>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_SDGMAC {
+ reg = <RK3576_PD_SDGMAC>;
+ clocks = <&cru ACLK_HSGPIO>,
+ <&cru ACLK_GMAC0>,
+ <&cru ACLK_GMAC1>,
+ <&cru CCLK_SRC_SDIO>,
+ <&cru CCLK_SRC_SDMMC0>,
+ <&cru HCLK_HSGPIO>,
+ <&cru HCLK_SDIO>,
+ <&cru HCLK_SDMMC0>,
+ <&cru PCLK_SDGMAC_ROOT>;
+ pm_qos = <&qos_fspi1>,
+ <&qos_gmac0>,
+ <&qos_gmac1>,
+ <&qos_sdio>,
+ <&qos_sdmmc>,
+ <&qos_flexbus>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@RK3576_PD_PHP {
+ reg = <RK3576_PD_PHP>;
+ clocks = <&cru ACLK_PHP_ROOT>,
+ <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_MMU0>,
+ <&cru ACLK_MMU1>;
+ pm_qos = <&qos_mmu0>,
+ <&qos_mmu1>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_SUBPHP {
+ reg = <RK3576_PD_SUBPHP>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@RK3576_PD_AUDIO {
+ reg = <RK3576_PD_AUDIO>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VEPU1 {
+ reg = <RK3576_PD_VEPU1>;
+ clocks = <&cru ACLK_VEPU1>,
+ <&cru HCLK_VEPU1>;
+ pm_qos = <&qos_vepu1>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VPU {
+ reg = <RK3576_PD_VPU>;
+ clocks = <&cru ACLK_EBC>,
+ <&cru HCLK_EBC>,
+ <&cru ACLK_JPEG>,
+ <&cru HCLK_JPEG>,
+ <&cru ACLK_RGA2E_0>,
+ <&cru HCLK_RGA2E_0>,
+ <&cru ACLK_RGA2E_1>,
+ <&cru HCLK_RGA2E_1>,
+ <&cru ACLK_VDPP>,
+ <&cru HCLK_VDPP>;
+ pm_qos = <&qos_ebc>,
+ <&qos_jpeg>,
+ <&qos_rga0>,
+ <&qos_rga1>,
+ <&qos_vdpp>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VDEC {
+ reg = <RK3576_PD_VDEC>;
+ clocks = <&cru ACLK_RKVDEC_ROOT>,
+ <&cru HCLK_RKVDEC>;
+ pm_qos = <&qos_rkvdec>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VI {
+ reg = <RK3576_PD_VI>;
+ clocks = <&cru ACLK_VICAP>,
+ <&cru HCLK_VICAP>,
+ <&cru DCLK_VICAP>,
+ <&cru ACLK_VI_ROOT>,
+ <&cru HCLK_VI_ROOT>,
+ <&cru PCLK_VI_ROOT>,
+ <&cru CLK_ISP_CORE>,
+ <&cru ACLK_ISP>,
+ <&cru HCLK_ISP>,
+ <&cru CLK_CORE_VPSS>,
+ <&cru ACLK_VPSS>,
+ <&cru HCLK_VPSS>;
+ pm_qos = <&qos_isp_mro>,
+ <&qos_isp_mwo>,
+ <&qos_vicap_m0>,
+ <&qos_vpss_mro>,
+ <&qos_vpss_mwo>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_VEPU0 {
+ reg = <RK3576_PD_VEPU0>;
+ clocks = <&cru ACLK_VEPU0>,
+ <&cru HCLK_VEPU0>;
+ pm_qos = <&qos_vepu0>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@RK3576_PD_VOP {
+ reg = <RK3576_PD_VOP>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru HCLK_VOP_ROOT>,
+ <&cru PCLK_VOP_ROOT>;
+ pm_qos = <&qos_vop_m0>,
+ <&qos_vop_m1ro>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3576_PD_USB {
+ reg = <RK3576_PD_USB>;
+ clocks = <&cru PCLK_PHP_ROOT>,
+ <&cru ACLK_USB_ROOT>,
+ <&cru ACLK_MMU2>,
+ <&cru ACLK_SLV_MMU2>,
+ <&cru ACLK_UFS_SYS>;
+ pm_qos = <&qos_mmu2>,
+ <&qos_ufshc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VO0 {
+ reg = <RK3576_PD_VO0>;
+ clocks = <&cru ACLK_HDCP0>,
+ <&cru HCLK_HDCP0>,
+ <&cru ACLK_VO0_ROOT>,
+ <&cru PCLK_VO0_ROOT>,
+ <&cru HCLK_VOP_ROOT>;
+ pm_qos = <&qos_hdcp0>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3576_PD_VO1 {
+ reg = <RK3576_PD_VO1>;
+ clocks = <&cru ACLK_HDCP1>,
+ <&cru HCLK_HDCP1>,
+ <&cru ACLK_VO1_ROOT>,
+ <&cru PCLK_VO1_ROOT>,
+ <&cru HCLK_VOP_ROOT>;
+ pm_qos = <&qos_hdcp1>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ gpu: gpu@27800000 {
+ compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
+ reg = <0x0 0x27800000 0x0 0x200000>;
+ assigned-clocks = <&scmi_clk CLK_GPU>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_GPU>;
+ clock-names = "core";
+ dynamic-power-coefficient = <1625>;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&power RK3576_PD_GPU>;
+ #cooling-cells = <2>;
+ status = "disabled";
+ };
+
+ qos_hdcp1: qos@27f02000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f02000 0x0 0x20>;
+ };
+
+ qos_fspi1: qos@27f04000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04000 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@27f04080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@27f04100 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04100 0x0 0x20>;
+ };
+
+ qos_sdio: qos@27f04180 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04180 0x0 0x20>;
+ };
+
+ qos_sdmmc: qos@27f04200 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04200 0x0 0x20>;
+ };
+
+ qos_flexbus: qos@27f04280 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f04280 0x0 0x20>;
+ };
+
+ qos_gpu: qos@27f05000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f05000 0x0 0x20>;
+ };
+
+ qos_vepu1: qos@27f06000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f06000 0x0 0x20>;
+ };
+
+ qos_npu_mcu: qos@27f08000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f08000 0x0 0x20>;
+ };
+
+ qos_npu_nsp0: qos@27f08080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f08080 0x0 0x20>;
+ };
+
+ qos_npu_nsp1: qos@27f08100 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f08100 0x0 0x20>;
+ };
+
+ qos_emmc: qos@27f09000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f09000 0x0 0x20>;
+ };
+
+ qos_fspi0: qos@27f09080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f09080 0x0 0x20>;
+ };
+
+ qos_mmu0: qos@27f0a000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0a000 0x0 0x20>;
+ };
+
+ qos_mmu1: qos@27f0a080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0a080 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@27f0c000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0c000 0x0 0x20>;
+ };
+
+ qos_crypto: qos@27f0d000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0d000 0x0 0x20>;
+ };
+
+ qos_mmu2: qos@27f0e000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0e000 0x0 0x20>;
+ };
+
+ qos_ufshc: qos@27f0e080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0e080 0x0 0x20>;
+ };
+
+ qos_vepu0: qos@27f0f000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f0f000 0x0 0x20>;
+ };
+
+ qos_isp_mro: qos@27f10000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f10000 0x0 0x20>;
+ };
+
+ qos_isp_mwo: qos@27f10080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f10080 0x0 0x20>;
+ };
+
+ qos_vicap_m0: qos@27f10100 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f10100 0x0 0x20>;
+ };
+
+ qos_vpss_mro: qos@27f10180 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f10180 0x0 0x20>;
+ };
+
+ qos_vpss_mwo: qos@27f10200 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f10200 0x0 0x20>;
+ };
+
+ qos_hdcp0: qos@27f11000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f11000 0x0 0x20>;
+ };
+
+ qos_vop_m0: qos@27f12800 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f12800 0x0 0x20>;
+ };
+
+ qos_vop_m1ro: qos@27f12880 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f12880 0x0 0x20>;
+ };
+
+ qos_ebc: qos@27f13000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f13000 0x0 0x20>;
+ };
+
+ qos_rga0: qos@27f13080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f13080 0x0 0x20>;
+ };
+
+ qos_rga1: qos@27f13100 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f13100 0x0 0x20>;
+ };
+
+ qos_jpeg: qos@27f13180 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f13180 0x0 0x20>;
+ };
+
+ qos_vdpp: qos@27f13200 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f13200 0x0 0x20>;
+ };
+
+ qos_npu_m0: qos@27f20000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f20000 0x0 0x20>;
+ };
+
+ qos_npu_m1: qos@27f21000 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f21000 0x0 0x20>;
+ };
+
+ qos_npu_m0ro: qos@27f22080 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f22080 0x0 0x20>;
+ };
+
+ qos_npu_m1ro: qos@27f22100 {
+ compatible = "rockchip,rk3576-qos", "syscon";
+ reg = <0x0 0x27f22100 0x0 0x20>;
+ };
+
+ gmac0: ethernet@2a220000 {
+ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x2a220000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>,
+ <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
+ <&cru CLK_GMAC0_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3576_PD_SDGMAC>;
+ resets = <&cru SRST_A_GMAC0>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&sdgmac_grf>;
+ rockchip,php-grf = <&ioc_grf>;
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ gmac1: ethernet@2a230000 {
+ compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0x2a230000 0x0 0x10000>;
+ clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>,
+ <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
+ <&cru CLK_GMAC1_PTP_REF>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac",
+ "ptp_ref";
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ power-domains = <&power RK3576_PD_SDGMAC>;
+ resets = <&cru SRST_A_GMAC1>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&sdgmac_grf>;
+ rockchip,php-grf = <&ioc_grf>;
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mixed-burst;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+ snps,tso;
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,blen = <0 0 0 0 16 8 4>;
+ snps,rd_osr_lmt = <8>;
+ snps,wr_osr_lmt = <4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ sdmmc: mmc@2a310000 {
+ compatible = "rockchip,rk3576-dw-mshc";
+ reg = <0x0 0x2a310000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>;
+ power-domains = <&power RK3576_PD_SDGMAC>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdhci: mmc@2a330000 {
+ compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc";
+ reg = <0x0 0x2a330000 0x0 0x10000>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
+ <&emmc_cmd>, <&emmc_strb>;
+ pinctrl-names = "default";
+ power-domains = <&power RK3576_PD_NVM>;
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ supports-cqe;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@2a701000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0x2a701000 0 0x10000>,
+ <0x0 0x2a702000 0 0x10000>,
+ <0x0 0x2a704000 0 0x10000>,
+ <0x0 0x2a706000 0 0x10000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ };
+
+ dmac0: dma-controller@2ab90000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x2ab90000 0x0 0x4000>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC0>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
+
+ dmac1: dma-controller@2abb0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x2abb0000 0x0 0x4000>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC1>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
+
+ dmac2: dma-controller@2abd0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0x2abd0000 0x0 0x4000>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC2>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@2ac40000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac40000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2ac50000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac50000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@2ac60000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac60000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@2ac70000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac70000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@2ac80000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+
+ i2c6: i2c@2ac90000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ac90000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@2aca0000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2aca0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c8: i2c@2acb0000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2acb0000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c8m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ timer0: timer@2acc0000 {
+ compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0x2acc0000 0x0 0x20>;
+ clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ wdt: watchdog@2ace0000 {
+ compatible = "rockchip,rk3576-wdt", "snps,dw-wdt";
+ reg = <0x0 0x2ace0000 0x0 0x100>;
+ clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ spi0: spi@2acf0000 {
+ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0x2acf0000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi1: spi@2ad00000 {
+ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0x2ad00000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi2: spi@2ad10000 {
+ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0x2ad10000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 15>, <&dmac1 16>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi3: spi@2ad20000 {
+ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0x2ad20000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac1 17>, <&dmac1 18>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spi4: spi@2ad30000 {
+ compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0x2ad30000 0x0 0x1000>;
+ clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac2 12>, <&dmac2 13>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@2ad40000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad40000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart0m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart2: serial@2ad50000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad50000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart3: serial@2ad60000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad60000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart3m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart4: serial@2ad70000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad70000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 9>, <&dmac1 10>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart4m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart5: serial@2ad80000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad80000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 11>, <&dmac1 12>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart5m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart6: serial@2ad90000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ad90000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac1 13>, <&dmac1 14>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart7: serial@2ada0000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2ada0000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 6>, <&dmac2 7>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart7m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart8: serial@2adb0000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2adb0000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 8>, <&dmac2 9>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart8m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ uart9: serial@2adc0000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2adc0000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 10>, <&dmac2 11>;
+ dma-names = "tx", "rx";
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
+ saradc: adc@2ae00000 {
+ compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
+ reg = <0x0 0x2ae00000 0x0 0x10000>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ i2c9: i2c@2ae80000 {
+ compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0x2ae80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c9m0_xfer>;
+ resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>;
+ reset-names = "i2c", "apb";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart10: serial@2afc0000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2afc0000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 21>, <&dmac2 22>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart10m0_xfer>;
+ status = "disabled";
+ };
+
+ uart11: serial@2afd0000 {
+ compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart";
+ reg = <0x0 0x2afd0000 0x0 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac2 23>, <&dmac2 24>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart11m0_xfer>;
+ status = "disabled";
+ };
+
+ sram: sram@3ff88000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x3ff88000 0x0 0x78000>;
+ ranges = <0x0 0x0 0x3ff88000 0x78000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* start address and size should be 4k align */
+ rkvdec_sram: rkvdec-sram@0 {
+ reg = <0x0 0x78000>;
+ };
+ };
+
+ scmi_shmem: scmi-shmem@4010f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x4010f000 0x0 0x100>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3576-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@27320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x27320000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2ae10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae10000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2ae20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae20000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@2ae30000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae30000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@2ae40000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0x2ae40000 0x0 0x200>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+};
+
+#include "rk3576-pinctrl.dtsi"
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 05/20] DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (3 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 04/20] DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 14:27 ` [PATCH 06/20] DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding Heiko Stuebner
` (16 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
This adds the otp node to the rk3576 soc devicetree including the
individual fields we know about.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
dts/upstream/src/arm64/rockchip/rk3576.dtsi | 39 +++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/dts/upstream/src/arm64/rockchip/rk3576.dtsi b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
index 436232ffe4d..c70c9dcfad8 100644
--- a/dts/upstream/src/arm64/rockchip/rk3576.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3576.dtsi
@@ -1149,6 +1149,45 @@
status = "disabled";
};
+ otp: otp@2a580000 {
+ compatible = "rockchip,rk3576-otp";
+ reg = <0x0 0x2a580000 0x0 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
+ <&cru CLK_OTP_PHY_G>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>;
+ reset-names = "otp", "apb";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ otp_cpu_version: cpu-version@5 {
+ reg = <0x05 0x1>;
+ bits = <3 3>;
+ };
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+ cpub_leakage: cpub-leakage@1e {
+ reg = <0x1e 0x1>;
+ };
+ cpul_leakage: cpul-leakage@1f {
+ reg = <0x1f 0x1>;
+ };
+ npu_leakage: npu-leakage@20 {
+ reg = <0x20 0x1>;
+ };
+ gpu_leakage: gpu-leakage@21 {
+ reg = <0x21 0x1>;
+ };
+ log_leakage: log-leakage@22 {
+ reg = <0x22 0x1>;
+ };
+ };
+
gic: interrupt-controller@2a701000 {
compatible = "arm,gic-400";
reg = <0x0 0x2a701000 0 0x10000>,
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 06/20] DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (4 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 05/20] DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 14:27 ` [PATCH 07/20] DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC Heiko Stuebner
` (15 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Add devicetree binding for the ROC-RK3576-PC SBC.
The board is based on the RK3576 SoC (4*Cortex-A72 + 4*Cortex-A53).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
dts/upstream/Bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/dts/upstream/Bindings/arm/rockchip.yaml b/dts/upstream/Bindings/arm/rockchip.yaml
index 1ef09fbfdfa..9536f3b7070 100644
--- a/dts/upstream/Bindings/arm/rockchip.yaml
+++ b/dts/upstream/Bindings/arm/rockchip.yaml
@@ -193,6 +193,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly ROC-RK3576-PC
+ items:
+ - const: firefly,roc-rk3576-pc
+ - const: rockchip,rk3576
+
- description: Firefly Station M2
items:
- const: firefly,rk3566-roc-pc
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 07/20] DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (5 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 06/20] DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 14:27 ` [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions Heiko Stuebner
` (14 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
As the name implies, it is built around the RK3576 SoC with 4x Cortex-A72
cores, four Cortex-A53 cores and Mali-G52 MC3 GPU.
Storage options are EMMC, SD-Card, a 2242 M.2 slot and the possibility to
use UFS 2.0 storage.
Video Output options are a HDMI port, a DSI connector as well as Display-
Port via the TypeC connector (all of them not yet supported).
Networking options are a Low-profile Gigabit Ethernet RJ45 port with
Motorcomm YT8531 PHY as well as WiFi via an AMPAK AP6256 module.
USB ports on the board are 1x USB 3.0 port, 1x USB 2.0 port, 1x USB Type-C
and it comes with 40-pin GPIO header
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../src/arm64/rockchip/rk3576-roc-pc.dts | 736 ++++++++++++++++++
1 file changed, 736 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
diff --git a/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
new file mode 100644
index 00000000000..ce069a58ba5
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Firefly Technology Co. Ltd
+ * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
+#include "rk3576.dtsi"
+
+/ {
+ model = "Firefly ROC-RK3576-PC";
+ compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576";
+
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = "serial0:1500000n8";
+ };
+
+ adc-keys-0 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-maskrom {
+ label = "Maskrom";
+ linux,code = <KEY_SETUP>;
+ press-threshold-microvolt = <17000>;
+ };
+ };
+
+ adc-keys-1 {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ poll-interval = <100>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <17000>;
+ };
+ };
+
+ vbus5v0_typec: regulator-vbus5v0-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_otg0_pwren_h>;
+ regulator-name = "vbus5v0_typec";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_device_s0>;
+ };
+
+ vcc12v_dcin: regulator-vcc12v-dcin {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v2_ufs_vccq_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc1v8_ufs_vccq2_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc3v3_pcie: regulator-vcc3v3-pcie {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pwren_h>;
+ regulator-name = "vcc3v3_pcie";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <5000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_rtc_s5";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc5v0_device_s0: regulator-vcc5v0-device-s0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5vd_en>;
+ regulator-name = "vcc5v0_device";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+
+ vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb3_host_pwren_h>;
+ regulator-name = "vcc5v0_host1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_device_s0>;
+ };
+
+ vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v1_nldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc_1v8_s0: regulator-vcc-1v8-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_1v8_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_1v8_s3>;
+ };
+
+ vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_2v0_pldo_s3";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <2000000>;
+ regulator-max-microvolt = <2000000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+
+ vcc_3v3_s0: regulator-vcc-3v3-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_3v3_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_3v3_s3>;
+ };
+
+ vcc_ufs_s0: regulator-vcc-ufs-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_ufs_s0";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys_s5>;
+ };
+};
+
+&cpu_l0 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l1 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l2 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_l3 {
+ cpu-supply = <&vdd_cpu_lit_s0>;
+};
+
+&cpu_b0 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b1 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b2 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&cpu_b3 {
+ cpu-supply = <&vdd_cpu_big_s0>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu_s0>;
+ status = "okay";
+};
+
+&gmac0 {
+ clock_in_out = "output";
+ pinctrl-names = "default";
+ pinctrl-0 = <ð0m0_miim
+ ð0m0_tx_bus2
+ ð0m0_rx_bus2
+ ð0m0_rgmii_clk
+ ð0m0_rgmii_bus
+ ðm0_clk0_25m_out>;
+ /* Use rgmii-rxid mode to disable rx delay inside Soc */
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&rgmii_phy0>;
+ snps,reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x21>;
+ status = "okay";
+};
+
+&mdio0 {
+ status = "okay";
+
+ rgmii_phy0: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ clocks = <&cru REFCLKO25M_GMAC0_OUT>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+
+ pmic@23 {
+ compatible = "rockchip,rk806";
+ reg = <0x23>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
+ <&rk806_dvs2_null>, <&rk806_dvs3_null>;
+ system-power-controller;
+
+ vcc1-supply = <&vcc5v0_sys_s5>;
+ vcc2-supply = <&vcc5v0_sys_s5>;
+ vcc3-supply = <&vcc5v0_sys_s5>;
+ vcc4-supply = <&vcc5v0_sys_s5>;
+ vcc5-supply = <&vcc5v0_sys_s5>;
+ vcc6-supply = <&vcc5v0_sys_s5>;
+ vcc7-supply = <&vcc5v0_sys_s5>;
+ vcc8-supply = <&vcc5v0_sys_s5>;
+ vcc9-supply = <&vcc5v0_sys_s5>;
+ vcc10-supply = <&vcc5v0_sys_s5>;
+ vcc11-supply = <&vcc_2v0_pldo_s3>;
+ vcc12-supply = <&vcc5v0_sys_s5>;
+ vcc13-supply = <&vcc_1v1_nldo_s3>;
+ vcc14-supply = <&vcc_1v1_nldo_s3>;
+ vcca-supply = <&vcc5v0_sys_s5>;
+
+ rk806_dvs1_null: dvs1-null-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs2_null: dvs2-null-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs3_null: dvs3-null-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun0";
+ };
+
+ rk806_dvs1_slp: dvs1-slp-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs1_rst: dvs1-rst-pins {
+ pins = "gpio_pwrctrl1";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_slp: dvs2-slp-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs2_rst: dvs2-rst-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs2_dvs: dvs2-dvs-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs2_gpio: dvs2-gpio-pins {
+ pins = "gpio_pwrctrl2";
+ function = "pin_fun5";
+ };
+
+ rk806_dvs3_slp: dvs3-slp-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun1";
+ };
+
+ rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun2";
+ };
+
+ rk806_dvs3_rst: dvs3-rst-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun3";
+ };
+
+ rk806_dvs3_dvs: dvs3-dvs-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun4";
+ };
+
+ rk806_dvs3_gpio: dvs3-gpio-pins {
+ pins = "gpio_pwrctrl3";
+ function = "pin_fun5";
+ };
+
+ regulators {
+ vdd_cpu_big_s0: dcdc-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_big_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_npu_s0: dcdc-reg2 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_npu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_cpu_lit_s0: dcdc-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_cpu_lit_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vcc_3v3_s3: dcdc-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd_gpu_s0: dcdc-reg5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <900000>;
+ regulator-ramp-delay = <12500>;
+ regulator-name = "vdd_gpu_s0";
+ regulator-enable-ramp-delay = <400>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <850000>;
+ };
+ };
+
+ vddq_ddr_s0: dcdc-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vddq_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic_s0: dcdc-reg7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vdd_logic_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8_s3: dcdc-reg8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd2_ddr_s3: dcdc-reg9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vdd2_ddr_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_ddr_s0: dcdc-reg10 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd_ddr_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_1v8_s0: pldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo2_s0: pldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_1v2_s0: pldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdda_1v2_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca_3v3_s0: pldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcca_3v3_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd_s0: pldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pldo6_s3: pldo-reg6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pldo6_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_0v75_s3: nldo-reg1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdd_0v75_s3";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <750000>;
+ };
+ };
+
+ vdda_ddr_pll_s0: nldo-reg2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_ddr_pll_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v75_hdmi_s0: nldo-reg3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <837500>;
+ regulator-max-microvolt = <837500>;
+ regulator-name = "vdda0v75_hdmi_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v85_s0: nldo-reg4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-name = "vdda_0v85_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v75_s0: nldo-reg5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <750000>;
+ regulator-name = "vdda_0v75_s0";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+
+ /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */
+
+ /* hnyetek,husb311 typec-portc@4e */
+
+ hym8563: rtc@51 {
+ compatible = "haoyu,hym8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ clock-output-names = "hym8563";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rtc_int_l>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
+ wakeup-source;
+ };
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8_s0>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ no-sdio;
+ no-sd;
+ non-removable;
+ max-frequency = <200000000>;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ full-pwr-cycle-in-suspend;
+ status = "okay";
+};
+
+&sdmmc {
+ max-frequency = <200000000>;
+ no-sdio;
+ no-mmc;
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ disable-wp;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd_s0>;
+ status = "okay";
+};
+
+&pinctrl {
+ hym8563 {
+ rtc_int_l: rtc-int-l {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ power {
+ vcc5vd_en: vcc5vd-en {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ pcie_pwren_h: pcie-pwren-h {
+ rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ hub_reset_h: hub-reset-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb3_host_pwren_h: usb3-host-pwren-h {
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usb_otg0_pwren_h: usb-otg0-pwren-h {
+ rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ usbc0_int_l: usbc0-int-l {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ watchdog {
+ wd_en: wd-en {
+ rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0m0_xfer>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>;
+ status = "okay";
+};
+
+/* On the extension pin header */
+&uart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m3_xfer>;
+ status = "okay";
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (6 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 07/20] DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-26 16:13 ` Quentin Schulz
2025-01-30 22:23 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 09/20] rockchip: mkimage: Add rk3576 support Heiko Stuebner
` (13 subsequent siblings)
21 siblings, 2 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Currently the sdram code for arm64 expects CFG_SYS_SDRAM_BASE to be 0.
The ram being in front and the device-area behind it.
The upcoming RK3576 uses a different layout, with the device area
in front the ram, which then also extends past the 4G mark.
Adapt both the generic zone definitions as well as the ATAG parser
to be usable on devices where CFG_SYS_SDRAM_BASE is not 0.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/mach-rockchip/sdram.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 1fb01e1c4b1..4e2af55d6e1 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -181,9 +181,9 @@ static int rockchip_dram_init_banksize(void)
* BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
* have it, so force this space as reserved.
*/
- if (start_addr < SZ_2M) {
- size -= SZ_2M - start_addr;
- start_addr = SZ_2M;
+ if (start_addr < SZ_2M + CFG_SYS_SDRAM_BASE) {
+ size -= SZ_2M - (start_addr - CFG_SYS_SDRAM_BASE);
+ start_addr = SZ_2M + CFG_SYS_SDRAM_BASE;
}
/*
@@ -228,7 +228,7 @@ static int rockchip_dram_init_banksize(void)
return -EINVAL;
}
- size -= rsrv_end - start_addr;
+ size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
start_addr = rsrv_end;
break;
}
@@ -302,7 +302,7 @@ int dram_init_banksize(void)
ret);
/* Reserve 0x200000 for ATF bl31 */
- gd->bd->bi_dram[0].start = 0x200000;
+ gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + 0x200000;
gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
/* Add usable memory beyond the blob of space for peripheral near 4GB */
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
2024-11-21 14:27 ` [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions Heiko Stuebner
@ 2024-11-26 16:13 ` Quentin Schulz
2025-01-30 22:23 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Quentin Schulz @ 2024-11-26 16:13 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 11/21/24 3:27 PM, Heiko Stuebner wrote:
> Currently the sdram code for arm64 expects CFG_SYS_SDRAM_BASE to be 0.
> The ram being in front and the device-area behind it.
>
> The upcoming RK3576 uses a different layout, with the device area
> in front the ram, which then also extends past the 4G mark.
>
> Adapt both the generic zone definitions as well as the ATAG parser
> to be usable on devices where CFG_SYS_SDRAM_BASE is not 0.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/mach-rockchip/sdram.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 1fb01e1c4b1..4e2af55d6e1 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -181,9 +181,9 @@ static int rockchip_dram_init_banksize(void)
> * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
> * have it, so force this space as reserved.
> */
> - if (start_addr < SZ_2M) {
> - size -= SZ_2M - start_addr;
> - start_addr = SZ_2M;
> + if (start_addr < SZ_2M + CFG_SYS_SDRAM_BASE) {
> + size -= SZ_2M - (start_addr - CFG_SYS_SDRAM_BASE);
> + start_addr = SZ_2M + CFG_SYS_SDRAM_BASE;
I would just put CFG_SYS_SDRAM_BASE on the left side of SZ_2M.
I would also do
size -= CFG_SYS_SDRAM_BASE + SZ_2M - start_addr;
But those nitpicks are just a matter of taste, therefore
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Thanks!
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
2024-11-21 14:27 ` [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions Heiko Stuebner
2024-11-26 16:13 ` Quentin Schulz
@ 2025-01-30 22:23 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 22:23 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg@chromium.org, philipp.tomsich@vrull.eu,
kever.yang@rock-chips.com, lukma@denx.de, seanga2@gmail.com,
peng.fan@nxp.com, jh80.chung@samsung.com, joe.hershberger@ni.com,
rfried.dev@gmail.com, quentin.schulz@cherry.de,
detlev.casanova@collabora.com, u-boot@lists.denx.de,
sebastian.reichel@collabora.com
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> Currently the sdram code for arm64 expects CFG_SYS_SDRAM_BASE to be 0.
> The ram being in front and the device-area behind it.
>
> The upcoming RK3576 uses a different layout, with the device area
> in front the ram, which then also extends past the 4G mark.
>
> Adapt both the generic zone definitions as well as the ATAG parser
> to be usable on devices where CFG_SYS_SDRAM_BASE is not 0.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/mach-rockchip/sdram.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 1fb01e1c4b1..4e2af55d6e1 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -181,9 +181,9 @@ static int rockchip_dram_init_banksize(void)
> * BL31 (TF-A) reserves the first 2MB but DDR_MEM tag may not
> * have it, so force this space as reserved.
> */
> - if (start_addr < SZ_2M) {
> - size -= SZ_2M - start_addr;
> - start_addr = SZ_2M;
> + if (start_addr < SZ_2M + CFG_SYS_SDRAM_BASE) {
> + size -= SZ_2M - (start_addr - CFG_SYS_SDRAM_BASE);
> + start_addr = SZ_2M + CFG_SYS_SDRAM_BASE;
For consistency these should be changed to CFG_SYS_SDRAM_BASE + SZ_2M.
> }
>
> /*
> @@ -228,7 +228,7 @@ static int rockchip_dram_init_banksize(void)
> return -EINVAL;
> }
>
> - size -= rsrv_end - start_addr;
> + size -= rsrv_end - (start_addr - CFG_SYS_SDRAM_BASE);
> start_addr = rsrv_end;
> break;
> }
> @@ -302,7 +302,7 @@ int dram_init_banksize(void)
> ret);
>
> /* Reserve 0x200000 for ATF bl31 */
> - gd->bd->bi_dram[0].start = 0x200000;
> + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE + 0x200000;
This can be changed to SZ_2M instead of 0x200000 and 2M in the comment.
> gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start;
>
> /* Add usable memory beyond the blob of space for peripheral near 4GB */
Beside above nitpicks this is
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Regards,
Jonas
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 09/20] rockchip: mkimage: Add rk3576 support
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (7 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 08/20] rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-26 16:53 ` Quentin Schulz
2024-11-21 14:27 ` [PATCH 10/20] arm: rockchip: add RK3576-specific syscon ids Heiko Stuebner
` (12 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Xuhui Lin
From: Xuhui Lin <xuhui.lin@rock-chips.com>
Add support for rk3576 package header in mkimage tool.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 3e52236b15a..d89c7d3afea 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -135,6 +135,7 @@ static struct spl_info spl_infos[] = {
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 09/20] rockchip: mkimage: Add rk3576 support
2024-11-21 14:27 ` [PATCH 09/20] rockchip: mkimage: Add rk3576 support Heiko Stuebner
@ 2024-11-26 16:53 ` Quentin Schulz
2025-01-10 0:54 ` Kever Yang
0 siblings, 1 reply; 44+ messages in thread
From: Quentin Schulz @ 2024-11-26 16:53 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel, Xuhui Lin
Hi Heiko,
On 11/21/24 3:27 PM, Heiko Stuebner wrote:
> From: Xuhui Lin <xuhui.lin@rock-chips.com>
>
> Add support for rk3576 package header in mkimage tool.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> tools/rkcommon.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
> index 3e52236b15a..d89c7d3afea 100644
> --- a/tools/rkcommon.c
> +++ b/tools/rkcommon.c
> @@ -135,6 +135,7 @@ static struct spl_info spl_infos[] = {
> { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
> { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
> { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
> + { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
I don't understand why we remove 0x1000 here from the size of the SRAM.
If I go back in git history, I found
915e09814a83128fee8b87b2ee2e5f4a17e04a01 which states it's total SRAM -
size used by BootROM.
Can anyone provide feedback on how one is supposed to find this out? I
think it's not the first time I'm confused by this and I'm not sure
anyone's answered me before, but in any case, documenting this would be
much welcome :)
The RK3576 does have 512KiB of SRAM so the base value before subtracting
is fine :)
Cheers,
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 09/20] rockchip: mkimage: Add rk3576 support
2024-11-26 16:53 ` Quentin Schulz
@ 2025-01-10 0:54 ` Kever Yang
2025-01-14 16:43 ` Quentin Schulz
0 siblings, 1 reply; 44+ messages in thread
From: Kever Yang @ 2025-01-10 0:54 UTC (permalink / raw)
To: Quentin Schulz, Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel, Xuhui Lin
Hi Quentin,
On 2024/11/27 00:53, Quentin Schulz wrote:
> Hi Heiko,
>
> On 11/21/24 3:27 PM, Heiko Stuebner wrote:
>> From: Xuhui Lin <xuhui.lin@rock-chips.com>
>>
>> Add support for rk3576 package header in mkimage tool.
>>
>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>> ---
>> tools/rkcommon.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
>> index 3e52236b15a..d89c7d3afea 100644
>> --- a/tools/rkcommon.c
>> +++ b/tools/rkcommon.c
>> @@ -135,6 +135,7 @@ static struct spl_info spl_infos[] = {
>> { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
>> { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
>> { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
>> + { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
>
> I don't understand why we remove 0x1000 here from the size of the SRAM.
>
> If I go back in git history, I found
> 915e09814a83128fee8b87b2ee2e5f4a17e04a01 which states it's total SRAM
> - size used by BootROM.
>
> Can anyone provide feedback on how one is supposed to find this out? I
> think it's not the first time I'm confused by this and I'm not sure
> anyone's answered me before, but in any case, documenting this would
> be much welcome :)
If you look this change at vendor U-Boot, you can find below commit msg:
"Sram total size is 512KB and 4KB is used as bootrom stack."
This size limit is for the first blob binary which is TPL/DDR init, and
after running the DDR init,
we need to back to bootROM, so we should not touch the bootRom stack to
keep the bootRom
available.
Thanks,
- Kever
>
> The RK3576 does have 512KiB of SRAM so the base value before
> subtracting is fine :)
>
> Cheers,
> Quentin
>
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 09/20] rockchip: mkimage: Add rk3576 support
2025-01-10 0:54 ` Kever Yang
@ 2025-01-14 16:43 ` Quentin Schulz
0 siblings, 0 replies; 44+ messages in thread
From: Quentin Schulz @ 2025-01-14 16:43 UTC (permalink / raw)
To: Kever Yang, Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel, Xuhui Lin
Hi Kever,
On 1/10/25 1:54 AM, Kever Yang wrote:
> Hi Quentin,
>
> On 2024/11/27 00:53, Quentin Schulz wrote:
>> Hi Heiko,
>>
>> On 11/21/24 3:27 PM, Heiko Stuebner wrote:
>>> From: Xuhui Lin <xuhui.lin@rock-chips.com>
>>>
>>> Add support for rk3576 package header in mkimage tool.
>>>
>>> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
>>> ---
>>> tools/rkcommon.c | 1 +
>>> 1 file changed, 1 insertion(+)
>>>
>>> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
>>> index 3e52236b15a..d89c7d3afea 100644
>>> --- a/tools/rkcommon.c
>>> +++ b/tools/rkcommon.c
>>> @@ -135,6 +135,7 @@ static struct spl_info spl_infos[] = {
>>> { "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
>>> { "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
>>> { "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
>>> + { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
>>
>> I don't understand why we remove 0x1000 here from the size of the SRAM.
>>
>> If I go back in git history, I found
>> 915e09814a83128fee8b87b2ee2e5f4a17e04a01 which states it's total SRAM
>> - size used by BootROM.
>>
>> Can anyone provide feedback on how one is supposed to find this out? I
>> think it's not the first time I'm confused by this and I'm not sure
>> anyone's answered me before, but in any case, documenting this would
>> be much welcome :)
> If you look this change at vendor U-Boot, you can find below commit msg:
> "Sram total size is 512KB and 4KB is used as bootrom stack."
Somehow this value changed for a couple of SoCs in vendor U-Boot so I'm
not really trusting it ;)
> This size limit is for the first blob binary which is TPL/DDR init, and
> after running the DDR init,
> we need to back to bootROM, so we should not touch the bootRom stack to
> keep the bootRom
> available.
>
Considering we don't have access to the source code of the BootROM, I
assume we're in the case of "trust us the BootROM needs that much for
its stack" and there's nothing we can do to verify it?
Cheers,
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 10/20] arm: rockchip: add RK3576-specific syscon ids
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (8 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 09/20] rockchip: mkimage: Add rk3576 support Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-26 17:12 ` Quentin Schulz
2024-11-21 14:27 ` [PATCH 11/20] arm: rockchip: Add RK3576 arch core support Heiko Stuebner
` (11 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
From: Detlev Casanova <detlev.casanova@collabora.com>
The rk3576 defines some more different syscons, namely the IOC-syscon
holding io-controller registers and sdgmac holding settings for the
gmac controller.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/include/asm/arch-rockchip/clock.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 73e5283108b..82305ef17ae 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -32,6 +32,8 @@ enum {
ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
ROCKCHIP_SYSCON_VOP_GRF,
ROCKCHIP_SYSCON_VO_GRF,
+ ROCKCHIP_SYSCON_IOC,
+ ROCKCHIP_SYSCON_SDGMAC,
};
/* Standard Rockchip clock numbers */
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 10/20] arm: rockchip: add RK3576-specific syscon ids
2024-11-21 14:27 ` [PATCH 10/20] arm: rockchip: add RK3576-specific syscon ids Heiko Stuebner
@ 2024-11-26 17:12 ` Quentin Schulz
0 siblings, 0 replies; 44+ messages in thread
From: Quentin Schulz @ 2024-11-26 17:12 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 11/21/24 3:27 PM, Heiko Stuebner wrote:
> From: Detlev Casanova <detlev.casanova@collabora.com>
>
> The rk3576 defines some more different syscons, namely the IOC-syscon
> holding io-controller registers and sdgmac holding settings for the
> gmac controller.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/include/asm/arch-rockchip/clock.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
> index 73e5283108b..82305ef17ae 100644
> --- a/arch/arm/include/asm/arch-rockchip/clock.h
> +++ b/arch/arm/include/asm/arch-rockchip/clock.h
> @@ -32,6 +32,8 @@ enum {
> ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
> ROCKCHIP_SYSCON_VOP_GRF,
> ROCKCHIP_SYSCON_VO_GRF,
> + ROCKCHIP_SYSCON_IOC,
> + ROCKCHIP_SYSCON_SDGMAC,
We should really start migrating away from this.
I would hope that the generic syscon would be enough for us. The issue
would be to migrate all
syscon_get_first_range(ROCKCHIP_SYSCON_*);
we use in the code by checking the DT instead, e.g. rockchip,grf
property for ROCKCHIP_SYSCON_GRF. For DT-less driver (e.g. SDRAM), I
guess just using a hardcoded address would do just fine? Like, I don't
understand what this brings us.
Anyway, a topic for another patch series :)
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Thanks!
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 11/20] arm: rockchip: Add RK3576 arch core support
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (9 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 10/20] arm: rockchip: add RK3576-specific syscon ids Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-26 18:07 ` Quentin Schulz
2025-01-30 23:07 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 12/20] pinctrl: rockchip: support rk3576 pinctrl Heiko Stuebner
` (10 subsequent siblings)
21 siblings, 2 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Xuhui Lin
From: Xuhui Lin <xuhui.lin@rock-chips.com>
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A72
and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out,
DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS,
USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C,
UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
[adapted for mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/dts/rk3576-u-boot.dtsi | 119 +++++++++
arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
.../include/asm/arch-rockchip/grf_rk3576.h | 225 ++++++++++++++++
.../include/asm/arch-rockchip/ioc_rk3576.h | 244 ++++++++++++++++++
arch/arm/mach-rockchip/Kconfig | 46 +++-
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3576/Kconfig | 48 ++++
arch/arm/mach-rockchip/rk3576/Makefile | 9 +
arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +++
arch/arm/mach-rockchip/rk3576/rk3576.c | 169 ++++++++++++
arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 ++
arch/arm/mach-rockchip/sdram.c | 1 +
doc/board/rockchip/rockchip.rst | 9 +
include/configs/rk3576_common.h | 42 +++
15 files changed, 992 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
create mode 100644 include/configs/rk3576_common.h
diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
new file mode 100644
index 00000000000..1399faf47df
--- /dev/null
+++ b/arch/arm/dts/rk3576-u-boot.dtsi
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include "rockchip-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
+ };
+
+ dmc {
+ compatible = "rockchip,rk3576-dmc";
+ bootph-all;
+ };
+};
+
+&cru {
+ bootph-all;
+};
+
+&emmc_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&emmc_strb {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&pcfg_pull_down {
+ bootph-all;
+};
+
+&pcfg_pull_none {
+ bootph-all;
+};
+
+&pcfg_pull_up {
+ bootph-all;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&php_grf {
+ bootph-all;
+};
+
+&pinctrl {
+ bootph-all;
+};
+
+&pmu1_grf {
+ bootph-all;
+};
+
+&sdhci {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc {
+ bootph-pre-ram;
+ bootph-some-ram;
+ u-boot,spl-fifo-mode;
+};
+
+&sdmmc0_bus4 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sdmmc0_det {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+&sys_grf {
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+ clock-frequency = <24000000>;
+};
+
+&uart0m0_xfer {
+ bootph-all;
+};
+
+&xin24m {
+ bootph-all;
+};
diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h
new file mode 100644
index 00000000000..dea2b20252d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3576/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h
new file mode 100644
index 00000000000..b48c0a5cf84
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3576/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3576.h b/arch/arm/include/asm/arch-rockchip/grf_rk3576.h
new file mode 100644
index 00000000000..0db7f5277f5
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3576.h
@@ -0,0 +1,225 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_GRF_RK3576_H
+#define _ASM_ARCH_GRF_RK3576_H
+
+/* usb2phy_grf register structure define */
+struct rk3576_usb2phygrf {
+ unsigned int con[6]; /* address offset: 0x0000 */
+ unsigned int reserved0018[2]; /* address offset: 0x0018 */
+ unsigned int ls_con; /* address offset: 0x0020 */
+ unsigned int dis_con; /* address offset: 0x0024 */
+ unsigned int bvalid_con; /* address offset: 0x0028 */
+ unsigned int id_con; /* address offset: 0x002c */
+ unsigned int vbusvalid_con; /* address offset: 0x0030 */
+ unsigned int reserved0034[3]; /* address offset: 0x0034 */
+ unsigned int dbg_con[1]; /* address offset: 0x0040 */
+ unsigned int linest_timeout; /* address offset: 0x0044 */
+ unsigned int linest_deb; /* address offset: 0x0048 */
+ unsigned int rx_timeout; /* address offset: 0x004c */
+ unsigned int seq_limt; /* address offset: 0x0050 */
+ unsigned int linest_cnt_st; /* address offset: 0x0054 */
+ unsigned int dbg_st; /* address offset: 0x0058 */
+ unsigned int rx_cnt_st; /* address offset: 0x005c */
+ unsigned int reserved0060[8]; /* address offset: 0x0060 */
+ unsigned int st[1]; /* address offset: 0x0080 */
+ unsigned int reserved0084[15]; /* address offset: 0x0084 */
+ unsigned int int_en; /* address offset: 0x00c0 */
+ unsigned int int_st; /* address offset: 0x00c4 */
+ unsigned int int_st_clr; /* address offset: 0x00c8 */
+ unsigned int reserved00cc; /* address offset: 0x00cc */
+ unsigned int detclk_sel; /* address offset: 0x00d0 */
+};
+
+check_member(rk3576_usb2phygrf, detclk_sel, 0x00d0);
+
+/* php_grf register structure define */
+struct rk3576_phpgrf {
+ unsigned int mmubp_st; /* address offset: 0x0000 */
+ unsigned int mmubp_con[1]; /* address offset: 0x0004 */
+ unsigned int mmu0_con; /* address offset: 0x0008 */
+ unsigned int mmu1_con; /* address offset: 0x000c */
+ unsigned int mem_con[3]; /* address offset: 0x0010 */
+ unsigned int sata0_con; /* address offset: 0x001c */
+ unsigned int sata1_con; /* address offset: 0x0020 */
+ unsigned int usb3otg1_status_lat[2]; /* address offset: 0x0024 */
+ unsigned int usb3otg1_status_cb; /* address offset: 0x002c */
+ unsigned int usb3otg1_status; /* address offset: 0x0030 */
+ unsigned int usb3otg1_con[2]; /* address offset: 0x0034 */
+ unsigned int reserved003c[3]; /* address offset: 0x003c */
+ unsigned int pciepipe_con[1]; /* address offset: 0x0048 */
+ unsigned int reserved004c[2]; /* address offset: 0x004c */
+ unsigned int pcie_clkreq_st; /* address offset: 0x0054 */
+ unsigned int reserved0058; /* address offset: 0x0058 */
+ unsigned int mmu0_st[5]; /* address offset: 0x005c */
+ unsigned int mmu1_st[5]; /* address offset: 0x0070 */
+};
+
+check_member(rk3576_phpgrf, mmu1_st, 0x0070);
+
+/* pmu0_grf register structure define */
+struct rk3576_pmu0grf {
+ unsigned int soc_con[7]; /* address offset: 0x0000 */
+ unsigned int reserved001c; /* address offset: 0x001c */
+ unsigned int io_ret_con[2]; /* address offset: 0x0020 */
+ unsigned int reserved0028[2]; /* address offset: 0x0028 */
+ unsigned int mem_con; /* address offset: 0x0030 */
+ unsigned int reserved0034[3]; /* address offset: 0x0034 */
+ unsigned int os_reg[8]; /* address offset: 0x0040 */
+};
+
+check_member(rk3576_pmu0grf, os_reg, 0x0040);
+
+/* pmu0_sgrf register structure define */
+struct rk3576_pmu0sgrf {
+ unsigned int soc_con[3]; /* address offset: 0x0000 */
+ unsigned int reserved000c[13]; /* address offset: 0x000c */
+ unsigned int dcie_con[8]; /* address offset: 0x0040 */
+ unsigned int dcie_wlock; /* address offset: 0x0060 */
+};
+
+check_member(rk3576_pmu0sgrf, dcie_wlock, 0x0060);
+
+/* pmu1_grf register structure define */
+struct rk3576_pmu1grf {
+ unsigned int soc_con[8]; /* address offset: 0x0000 */
+ unsigned int reserved0020[12]; /* address offset: 0x0020 */
+ unsigned int biu_con; /* address offset: 0x0050 */
+ unsigned int biu_status; /* address offset: 0x0054 */
+ unsigned int reserved0058[2]; /* address offset: 0x0058 */
+ unsigned int soc_status; /* address offset: 0x0060 */
+ unsigned int reserved0064[7]; /* address offset: 0x0064 */
+ unsigned int mem_con[2]; /* address offset: 0x0080 */
+ unsigned int reserved0088[30]; /* address offset: 0x0088 */
+ unsigned int func_rst_status; /* address offset: 0x0100 */
+ unsigned int func_rst_clr; /* address offset: 0x0104 */
+ unsigned int reserved0108[2]; /* address offset: 0x0108 */
+ unsigned int sd_detect_con; /* address offset: 0x0110 */
+ unsigned int sd_detect_sts; /* address offset: 0x0114 */
+ unsigned int sd_detect_clr; /* address offset: 0x0118 */
+ unsigned int sd_detect_cnt; /* address offset: 0x011c */
+ unsigned int reserved0120[56]; /* address offset: 0x0120 */
+ unsigned int os_reg[16]; /* address offset: 0x0200 */
+};
+
+check_member(rk3576_pmu1grf, os_reg, 0x0200);
+
+/* pmu1_sgrf register structure define */
+struct rk3576_pmu1sgrf {
+ unsigned int soc_con[18]; /* address offset: 0x0000 */
+};
+
+check_member(rk3576_pmu1sgrf, soc_con, 0x0000);
+
+/* sdgmac_grf register structure define */
+struct rk3576_sdgmacgrf {
+ unsigned int mem_con[5]; /* address offset: 0x0000 */
+ unsigned int reserved0014[2]; /* address offset: 0x0014 */
+ unsigned int gmac_st[1]; /* address offset: 0x001c */
+ unsigned int gmac0_con; /* address offset: 0x0020 */
+ unsigned int gmac1_con; /* address offset: 0x0024 */
+ unsigned int gmac0_tp[2]; /* address offset: 0x0028 */
+ unsigned int gmac1_tp[2]; /* address offset: 0x0030 */
+ unsigned int gmac0_cmd; /* address offset: 0x0038 */
+ unsigned int gmac1_cmd; /* address offset: 0x003c */
+ unsigned int reserved0040[2]; /* address offset: 0x0040 */
+ unsigned int mem_gate_con; /* address offset: 0x0048 */
+};
+
+check_member(rk3576_sdgmacgrf, mem_gate_con, 0x0048);
+
+/* sys_grf register structure define */
+struct rk3576_sysgrf {
+ unsigned int soc_con[13]; /* address offset: 0x0000 */
+ unsigned int reserved0034[3]; /* address offset: 0x0034 */
+ unsigned int biu_con[6]; /* address offset: 0x0040 */
+ unsigned int reserved0058[2]; /* address offset: 0x0058 */
+ unsigned int biu_status[8]; /* address offset: 0x0060 */
+ unsigned int mem_con[19]; /* address offset: 0x0080 */
+ unsigned int reserved00cc[29]; /* address offset: 0x00cc */
+ unsigned int soc_status[2]; /* address offset: 0x0140 */
+ unsigned int memfault_status[2]; /* address offset: 0x0148 */
+ unsigned int reserved0150[12]; /* address offset: 0x0150 */
+ unsigned int soc_code; /* address offset: 0x0180 */
+ unsigned int reserved0184[3]; /* address offset: 0x0184 */
+ unsigned int soc_version; /* address offset: 0x0190 */
+ unsigned int reserved0194[3]; /* address offset: 0x0194 */
+ unsigned int chip_id; /* address offset: 0x01a0 */
+ unsigned int reserved01a4[3]; /* address offset: 0x01a4 */
+ unsigned int chip_version; /* address offset: 0x01b0 */
+};
+
+check_member(rk3576_sysgrf, chip_version, 0x01b0);
+
+/* sys_sgrf register structure define */
+struct rk3576_syssgrf {
+ unsigned int ddr_bank_hash_ctrl; /* address offset: 0x0000 */
+ unsigned int ddr_bank_mask[4]; /* address offset: 0x0004 */
+ unsigned int ddr_rank_mask[1]; /* address offset: 0x0014 */
+ unsigned int reserved0018[2]; /* address offset: 0x0018 */
+ unsigned int soc_con[21]; /* address offset: 0x0020 */
+ unsigned int reserved0074[3]; /* address offset: 0x0074 */
+ unsigned int dmac0_con[10]; /* address offset: 0x0080 */
+ unsigned int reserved00a8[22]; /* address offset: 0x00a8 */
+ unsigned int dmac1_con[10]; /* address offset: 0x0100 */
+ unsigned int reserved0128[22]; /* address offset: 0x0128 */
+ unsigned int dmac2_con[10]; /* address offset: 0x0180 */
+ unsigned int reserved01a8[22]; /* address offset: 0x01a8 */
+ unsigned int key_con[2]; /* address offset: 0x0200 */
+ unsigned int key_wlock; /* address offset: 0x0208 */
+ unsigned int reserved020c[13]; /* address offset: 0x020c */
+ unsigned int soc_status; /* address offset: 0x0240 */
+ unsigned int reserved0244[47]; /* address offset: 0x0244 */
+ unsigned int ip_info_con; /* address offset: 0x0300 */
+};
+
+check_member(rk3576_syssgrf, ip_info_con, 0x0300);
+
+/* ufs_grf register structure define */
+struct rk3576_ufsgrf {
+ unsigned int clk_ctrl; /* address offset: 0x0000 */
+ unsigned int uic_src_sel; /* address offset: 0x0004 */
+ unsigned int ufs_state_ie; /* address offset: 0x0008 */
+ unsigned int ufs_state_is; /* address offset: 0x000c */
+ unsigned int ufs_state; /* address offset: 0x0010 */
+ unsigned int reserved0014[13]; /* address offset: 0x0014 */
+};
+
+check_member(rk3576_ufsgrf, reserved0014, 0x0014);
+
+/* usbdpphy_grf register structure define */
+struct rk3576_usbdpphygrf {
+ unsigned int reserved0000; /* address offset: 0x0000 */
+ unsigned int con[3]; /* address offset: 0x0004 */
+ unsigned int reserved0010[29]; /* address offset: 0x0010 */
+ unsigned int status[1]; /* address offset: 0x0084 */
+ unsigned int reserved0088[14]; /* address offset: 0x0088 */
+ unsigned int lfps_det_con; /* address offset: 0x00c0 */
+ unsigned int int_en; /* address offset: 0x00c4 */
+ unsigned int int_status; /* address offset: 0x00c8 */
+};
+
+check_member(rk3576_usbdpphygrf, int_status, 0x00c8);
+
+/* usb_grf register structure define */
+struct rk3576_usbgrf {
+ unsigned int mmubp_st; /* address offset: 0x0000 */
+ unsigned int mmubp_con; /* address offset: 0x0004 */
+ unsigned int mmu2_con; /* address offset: 0x0008 */
+ unsigned int mem_con0; /* address offset: 0x000c */
+ unsigned int mem_con1; /* address offset: 0x0010 */
+ unsigned int reserved0014[2]; /* address offset: 0x0014 */
+ unsigned int usb3otg0_status_lat[2]; /* address offset: 0x001c */
+ unsigned int usb3otg0_status_cb; /* address offset: 0x0024 */
+ unsigned int usb3otg0_status; /* address offset: 0x0028 */
+ unsigned int usb3otg0_con[2]; /* address offset: 0x002c */
+ unsigned int reserved0034[4]; /* address offset: 0x0034 */
+ unsigned int mmu2_st[5]; /* address offset: 0x0044 */
+ unsigned int mem_con[1]; /* address offset: 0x0058 */
+};
+
+check_member(rk3576_usbgrf, mem_con, 0x0058);
+
+#endif /* _ASM_ARCH_GRF_RK3576_H */
diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
new file mode 100644
index 00000000000..9fd24b502bb
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+#ifndef _ASM_ARCH_IOC_RK3576_H
+#define _ASM_ARCH_IOC_RK3576_H
+
+/* pmu0_ioc register structure define */
+struct rk3576_pmu0_ioc_reg {
+ unsigned int gpio0a_iomux_sel_l; /* address offset: 0x0000 */
+ unsigned int gpio0a_iomux_sel_h; /* address offset: 0x0004 */
+ unsigned int gpio0b_iomux_sel_l; /* address offset: 0x0008 */
+ unsigned int reserved000c; /* address offset: 0x000c */
+ unsigned int gpio0a_ds_l; /* address offset: 0x0010 */
+ unsigned int gpio0a_ds_h; /* address offset: 0x0014 */
+ unsigned int gpio0b_ds_l; /* address offset: 0x0018 */
+ unsigned int reserved001c; /* address offset: 0x001c */
+ unsigned int gpio0a_pull; /* address offset: 0x0020 */
+ unsigned int gpio0b_pull_l; /* address offset: 0x0024 */
+ unsigned int gpio0a_ie; /* address offset: 0x0028 */
+ unsigned int gpio0b_ie_l; /* address offset: 0x002c */
+ unsigned int gpio0a_smt; /* address offset: 0x0030 */
+ unsigned int gpio0b_smt_l; /* address offset: 0x0034 */
+ unsigned int gpio0a_pdis; /* address offset: 0x0038 */
+ unsigned int gpio0b_pdis_l; /* address offset: 0x003c */
+ unsigned int osc_con; /* address offset: 0x0040 */
+};
+
+check_member(rk3576_pmu0_ioc_reg, osc_con, 0x0040);
+
+/* pmu1_ioc register structure define */
+struct rk3576_pmu1_ioc_reg {
+ unsigned int gpio0b_iomux_sel_h; /* address offset: 0x0000 */
+ unsigned int gpio0c_iomux_sel_l; /* address offset: 0x0004 */
+ unsigned int gpio0c_iomux_sel_h; /* address offset: 0x0008 */
+ unsigned int gpio0d_iomux_sel_l; /* address offset: 0x000c */
+ unsigned int gpio0d_iomux_sel_h; /* address offset: 0x0010 */
+ unsigned int gpio0b_ds_h; /* address offset: 0x0014 */
+ unsigned int gpio0c_ds_l; /* address offset: 0x0018 */
+ unsigned int gpio0c_ds_h; /* address offset: 0x001c */
+ unsigned int gpio0d_ds_l; /* address offset: 0x0020 */
+ unsigned int gpio0d_ds_h; /* address offset: 0x0024 */
+ unsigned int gpio0b_pull_h; /* address offset: 0x0028 */
+ unsigned int gpio0c_pull; /* address offset: 0x002c */
+ unsigned int gpio0d_pull; /* address offset: 0x0030 */
+ unsigned int gpio0b_ie_h; /* address offset: 0x0034 */
+ unsigned int gpio0c_ie; /* address offset: 0x0038 */
+ unsigned int gpio0d_ie; /* address offset: 0x003c */
+ unsigned int gpio0b_smt_h; /* address offset: 0x0040 */
+ unsigned int gpio0c_smt; /* address offset: 0x0044 */
+ unsigned int gpio0d_smt; /* address offset: 0x0048 */
+ unsigned int gpio0b_pdis_h; /* address offset: 0x004c */
+ unsigned int gpio0c_pdis; /* address offset: 0x0050 */
+ unsigned int gpio0d_pdis; /* address offset: 0x0054 */
+};
+
+check_member(rk3576_pmu1_ioc_reg, gpio0d_pdis, 0x0054);
+
+/* top_ioc register structure define */
+struct rk3576_top_ioc_reg {
+ unsigned int reserved0000[2]; /* address offset: 0x0000 */
+ unsigned int gpio0b_iomux_sel_l; /* address offset: 0x0008 */
+ unsigned int gpio0b_iomux_sel_h; /* address offset: 0x000c */
+ unsigned int gpio0c_iomux_sel_l; /* address offset: 0x0010 */
+ unsigned int gpio0c_iomux_sel_h; /* address offset: 0x0014 */
+ unsigned int gpio0d_iomux_sel_l; /* address offset: 0x0018 */
+ unsigned int gpio0d_iomux_sel_h; /* address offset: 0x001c */
+ unsigned int gpio1a_iomux_sel_l; /* address offset: 0x0020 */
+ unsigned int gpio1a_iomux_sel_h; /* address offset: 0x0024 */
+ unsigned int gpio1b_iomux_sel_l; /* address offset: 0x0028 */
+ unsigned int gpio1b_iomux_sel_h; /* address offset: 0x002c */
+ unsigned int gpio1c_iomux_sel_l; /* address offset: 0x0030 */
+ unsigned int gpio1c_iomux_sel_h; /* address offset: 0x0034 */
+ unsigned int gpio1d_iomux_sel_l; /* address offset: 0x0038 */
+ unsigned int gpio1d_iomux_sel_h; /* address offset: 0x003c */
+ unsigned int gpio2a_iomux_sel_l; /* address offset: 0x0040 */
+ unsigned int gpio2a_iomux_sel_h; /* address offset: 0x0044 */
+ unsigned int gpio2b_iomux_sel_l; /* address offset: 0x0048 */
+ unsigned int gpio2b_iomux_sel_h; /* address offset: 0x004c */
+ unsigned int gpio2c_iomux_sel_l; /* address offset: 0x0050 */
+ unsigned int gpio2c_iomux_sel_h; /* address offset: 0x0054 */
+ unsigned int gpio2d_iomux_sel_l; /* address offset: 0x0058 */
+ unsigned int gpio2d_iomux_sel_h; /* address offset: 0x005c */
+ unsigned int gpio3a_iomux_sel_l; /* address offset: 0x0060 */
+ unsigned int gpio3a_iomux_sel_h; /* address offset: 0x0064 */
+ unsigned int gpio3b_iomux_sel_l; /* address offset: 0x0068 */
+ unsigned int gpio3b_iomux_sel_h; /* address offset: 0x006c */
+ unsigned int gpio3c_iomux_sel_l; /* address offset: 0x0070 */
+ unsigned int gpio3c_iomux_sel_h; /* address offset: 0x0074 */
+ unsigned int gpio3d_iomux_sel_l; /* address offset: 0x0078 */
+ unsigned int gpio3d_iomux_sel_h; /* address offset: 0x007c */
+ unsigned int gpio4a_iomux_sel_l; /* address offset: 0x0080 */
+ unsigned int gpio4a_iomux_sel_h; /* address offset: 0x0084 */
+ unsigned int gpio4b_iomux_sel_l; /* address offset: 0x0088 */
+ unsigned int gpio4b_iomux_sel_h; /* address offset: 0x008c */
+ unsigned int reserved0090[24]; /* address offset: 0x0090 */
+ unsigned int ioc_misc_con; /* address offset: 0x00f0 */
+ unsigned int sdmmc_detn_flt; /* address offset: 0x00f4 */
+};
+
+check_member(rk3576_top_ioc_reg, sdmmc_detn_flt, 0x00f4);
+
+/* vccio_ioc register structure define */
+struct rk3576_vccio_ioc_reg {
+ unsigned int reserved0000[8]; /* address offset: 0x0000 */
+ unsigned int gpio1a_ds_l; /* address offset: 0x0020 */
+ unsigned int gpio1a_ds_h; /* address offset: 0x0024 */
+ unsigned int gpio1b_ds_l; /* address offset: 0x0028 */
+ unsigned int gpio1b_ds_h; /* address offset: 0x002c */
+ unsigned int gpio1c_ds_l; /* address offset: 0x0030 */
+ unsigned int gpio1c_ds_h; /* address offset: 0x0034 */
+ unsigned int gpio1d_ds_l; /* address offset: 0x0038 */
+ unsigned int gpio1d_ds_h; /* address offset: 0x003c */
+ unsigned int gpio2a_ds_l; /* address offset: 0x0040 */
+ unsigned int gpio2a_ds_h; /* address offset: 0x0044 */
+ unsigned int gpio2b_ds_l; /* address offset: 0x0048 */
+ unsigned int gpio2b_ds_h; /* address offset: 0x004c */
+ unsigned int gpio2c_ds_l; /* address offset: 0x0050 */
+ unsigned int gpio2c_ds_h; /* address offset: 0x0054 */
+ unsigned int gpio2d_ds_l; /* address offset: 0x0058 */
+ unsigned int gpio2d_ds_h; /* address offset: 0x005c */
+ unsigned int gpio3a_ds_l; /* address offset: 0x0060 */
+ unsigned int gpio3a_ds_h; /* address offset: 0x0064 */
+ unsigned int gpio3b_ds_l; /* address offset: 0x0068 */
+ unsigned int gpio3b_ds_h; /* address offset: 0x006c */
+ unsigned int gpio3c_ds_l; /* address offset: 0x0070 */
+ unsigned int gpio3c_ds_h; /* address offset: 0x0074 */
+ unsigned int gpio3d_ds_l; /* address offset: 0x0078 */
+ unsigned int gpio3d_ds_h; /* address offset: 0x007c */
+ unsigned int gpio4a_ds_l; /* address offset: 0x0080 */
+ unsigned int gpio4a_ds_h; /* address offset: 0x0084 */
+ unsigned int gpio4b_ds_l; /* address offset: 0x0088 */
+ unsigned int gpio4b_ds_h; /* address offset: 0x008c */
+ unsigned int reserved0090[32]; /* address offset: 0x0090 */
+ unsigned int gpio1a_pull; /* address offset: 0x0110 */
+ unsigned int gpio1b_pull; /* address offset: 0x0114 */
+ unsigned int gpio1c_pull; /* address offset: 0x0118 */
+ unsigned int gpio1d_pull; /* address offset: 0x011c */
+ unsigned int gpio2a_pull; /* address offset: 0x0120 */
+ unsigned int gpio2b_pull; /* address offset: 0x0124 */
+ unsigned int gpio2c_pull; /* address offset: 0x0128 */
+ unsigned int gpio2d_pull; /* address offset: 0x012c */
+ unsigned int gpio3a_pull; /* address offset: 0x0130 */
+ unsigned int gpio3b_pull; /* address offset: 0x0134 */
+ unsigned int gpio3c_pull; /* address offset: 0x0138 */
+ unsigned int gpio3d_pull; /* address offset: 0x013c */
+ unsigned int gpio4a_pull; /* address offset: 0x0140 */
+ unsigned int gpio4b_pull; /* address offset: 0x0144 */
+ unsigned int reserved0148[14]; /* address offset: 0x0148 */
+ unsigned int gpio1a_ie; /* address offset: 0x0180 */
+ unsigned int gpio1b_ie; /* address offset: 0x0184 */
+ unsigned int gpio1c_ie; /* address offset: 0x0188 */
+ unsigned int gpio1d_ie; /* address offset: 0x018c */
+ unsigned int gpio2a_ie; /* address offset: 0x0190 */
+ unsigned int gpio2b_ie; /* address offset: 0x0194 */
+ unsigned int gpio2c_ie; /* address offset: 0x0198 */
+ unsigned int gpio2d_ie; /* address offset: 0x019c */
+ unsigned int gpio3a_ie; /* address offset: 0x01a0 */
+ unsigned int gpio3b_ie; /* address offset: 0x01a4 */
+ unsigned int gpio3c_ie; /* address offset: 0x01a8 */
+ unsigned int gpio3d_ie; /* address offset: 0x01ac */
+ unsigned int gpio4a_ie; /* address offset: 0x01b0 */
+ unsigned int gpio4b_ie; /* address offset: 0x01b4 */
+ unsigned int reserved01b8[22]; /* address offset: 0x01b8 */
+ unsigned int gpio1a_smt; /* address offset: 0x0210 */
+ unsigned int gpio1b_smt; /* address offset: 0x0214 */
+ unsigned int gpio1c_smt; /* address offset: 0x0218 */
+ unsigned int gpio1d_smt; /* address offset: 0x021c */
+ unsigned int gpio2a_smt; /* address offset: 0x0220 */
+ unsigned int gpio2b_smt; /* address offset: 0x0224 */
+ unsigned int gpio2c_smt; /* address offset: 0x0228 */
+ unsigned int gpio2d_smt; /* address offset: 0x022c */
+ unsigned int gpio3a_smt; /* address offset: 0x0230 */
+ unsigned int gpio3b_smt; /* address offset: 0x0234 */
+ unsigned int gpio3c_smt; /* address offset: 0x0238 */
+ unsigned int gpio3d_smt; /* address offset: 0x023c */
+ unsigned int gpio4a_smt; /* address offset: 0x0240 */
+ unsigned int gpio4b_smt; /* address offset: 0x0244 */
+ unsigned int reserved0248[14]; /* address offset: 0x0248 */
+ unsigned int gpio1a_pdis; /* address offset: 0x0280 */
+ unsigned int gpio1b_pdis; /* address offset: 0x0284 */
+ unsigned int gpio1c_pdis; /* address offset: 0x0288 */
+ unsigned int gpio1d_pdis; /* address offset: 0x028c */
+ unsigned int gpio2a_pdis; /* address offset: 0x0290 */
+ unsigned int gpio2b_pdis; /* address offset: 0x0294 */
+ unsigned int gpio2c_pdis; /* address offset: 0x0298 */
+ unsigned int gpio2d_pdis; /* address offset: 0x029c */
+ unsigned int gpio3a_pdis; /* address offset: 0x02a0 */
+ unsigned int gpio3b_pdis; /* address offset: 0x02a4 */
+ unsigned int gpio3c_pdis; /* address offset: 0x02a8 */
+ unsigned int gpio3d_pdis; /* address offset: 0x02ac */
+ unsigned int gpio4a_pdis; /* address offset: 0x02b0 */
+ unsigned int gpio4b_pdis; /* address offset: 0x02b4 */
+ unsigned int reserved02b8[82]; /* address offset: 0x02b8 */
+ unsigned int misc_con[9]; /* address offset: 0x0400 */
+};
+
+check_member(rk3576_vccio_ioc_reg, misc_con, 0x0400);
+
+/* vccio6_ioc register structure define */
+struct rk3576_vccio6_ioc_reg {
+ unsigned int reserved0000[36]; /* address offset: 0x0000 */
+ unsigned int gpio4c_ds_l; /* address offset: 0x0090 */
+ unsigned int gpio4c_ds_h; /* address offset: 0x0094 */
+ unsigned int reserved0098[44]; /* address offset: 0x0098 */
+ unsigned int gpio4c_pull; /* address offset: 0x0148 */
+ unsigned int reserved014c[27]; /* address offset: 0x014c */
+ unsigned int gpio4c_ie; /* address offset: 0x01b8 */
+ unsigned int reserved01bc[35]; /* address offset: 0x01bc */
+ unsigned int gpio4c_smt; /* address offset: 0x0248 */
+ unsigned int reserved024c[27]; /* address offset: 0x024c */
+ unsigned int gpio4c_pdis; /* address offset: 0x02b8 */
+ unsigned int reserved02bc[53]; /* address offset: 0x02bc */
+ unsigned int gpio4c_iomux_sel_l; /* address offset: 0x0390 */
+ unsigned int gpio4c_iomux_sel_h; /* address offset: 0x0394 */
+ unsigned int reserved0398[26]; /* address offset: 0x0398 */
+ unsigned int misc_con[2]; /* address offset: 0x0400 */
+ unsigned int reserved0408[14]; /* address offset: 0x0408 */
+ unsigned int hdmitx_hpd_status; /* address offset: 0x0440 */
+};
+
+check_member(rk3576_vccio6_ioc_reg, hdmitx_hpd_status, 0x0440);
+
+/* vccio7_ioc register structure define */
+struct rk3576_vccio7_ioc_reg {
+ unsigned int reserved0000[38]; /* address offset: 0x0000 */
+ unsigned int gpio4d_ds_l; /* address offset: 0x0098 */
+ unsigned int reserved009c[44]; /* address offset: 0x009c */
+ unsigned int gpio4d_pull; /* address offset: 0x014c */
+ unsigned int reserved0150[27]; /* address offset: 0x0150 */
+ unsigned int gpio4d_ie; /* address offset: 0x01bc */
+ unsigned int reserved01c0[35]; /* address offset: 0x01c0 */
+ unsigned int gpio4d_smt; /* address offset: 0x024c */
+ unsigned int reserved0250[27]; /* address offset: 0x0250 */
+ unsigned int gpio4d_pdis; /* address offset: 0x02bc */
+ unsigned int reserved02c0[54]; /* address offset: 0x02c0 */
+ unsigned int gpio4d_iomux_sel_l; /* address offset: 0x0398 */
+ unsigned int reserved039c[25]; /* address offset: 0x039c */
+ unsigned int xin_ufs_con; /* address offset: 0x0400 */
+};
+
+check_member(rk3576_vccio7_ioc_reg, xin_ufs_con, 0x0400);
+
+#endif /* _ASM_ARCH_IOC_RK3576_H */
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 269c219a6f8..568ce7389ed 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -341,6 +341,49 @@ config ROCKCHIP_RK3568
and video codec support. Peripherals include Gigabit Ethernet,
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+config ROCKCHIP_RK3576
+ bool "Support Rockchip RK3576"
+ select ARM64
+ select SUPPORT_SPL
+ select SPL
+ select CLK
+ select PINCTRL
+ select RAM
+ select REGMAP
+ select SYSCON
+ select BOARD_LATE_INIT
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ imply BOOTSTD_FULL
+ imply CLK_SCMI
+ imply DM_RNG
+ imply MISC_INIT_R
+ imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
+ imply OF_LIBFDT_OVERLAY
+ imply OF_UPSTREAM
+ imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
+ imply RNG_ROCKCHIP
+ imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_OTP
+ imply SCMI_FIRMWARE
+ imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
+ imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
+ select HAS_CUSTOM_SYS_INIT_SP_ADDR
+ imply SPL_LIBCOMMON_SUPPORT if SPL
+ imply SPL_LIBGENERIC_SUPPORT if SPL
+ imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SYS_MALLOC_F if SPL
+ imply SPL_SYS_MALLOC_SIMPLE if SPL
+ imply TPL_LIBCOMMON_SUPPORT if TPL
+ imply TPL_LIBGENERIC_SUPPORT if TPL
+ imply TPL_ROCKCHIP_COMMON_BOARD if TPL
+ imply TPL_SYS_MALLOC_F if TPL
+ imply TPL_SYS_MALLOC_SIMPLE if TPL
+
+ help
+ The Rockchip RK3576 is a ARM-based SoC with a quad-core Cortex-A53
+ and a quad-core Cortex-A72.
+
config ROCKCHIP_RK3588
bool "Support Rockchip RK3588"
select ARM64
@@ -490,7 +533,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
config ROCKCHIP_EXTERNAL_TPL
bool "Use external TPL binary"
- default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
+ default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3576 || ROCKCHIP_RK3588
help
Some Rockchip SoCs require an external TPL to initialize DRAM.
Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
@@ -627,6 +670,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
+source "arch/arm/mach-rockchip/rk3576/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
source "arch/arm/mach-rockchip/rv1126/Kconfig"
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
index 5e7edc99cdc..52464b01f4e 100644
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
+obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
new file mode 100644
index 00000000000..2e46b2b90d2
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/Kconfig
@@ -0,0 +1,48 @@
+if ROCKCHIP_RK3576
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0x26024040
+
+config ROCKCHIP_STIMER_BASE
+ default 0x27400000
+
+config SYS_SOC
+ default "rk3576"
+
+config CUSTOM_SYS_INIT_SP_ADDR
+ default 0x43f00000
+
+config SYS_MALLOC_F_LEN
+ default 0x10000
+
+config SPL_SYS_MALLOC_F_LEN
+ default 0x8000
+
+config TPL_SYS_MALLOC_F_LEN
+ default 0x4000
+
+config TEXT_BASE
+ default 0x40200000
+
+config SPL_TEXT_BASE
+ default 0x40000000
+
+config SPL_HAS_BSS_LINKER_SECTION
+ default y if ARM64
+
+config SPL_BSS_START_ADDR
+ default 0x43f80000
+
+config SPL_BSS_MAX_SIZE
+ default 0x8000
+
+config SPL_STACK_R
+ default y
+
+config SPL_STACK_R_ADDR
+ default 0x43e00000
+
+config SPL_STACK_R_MALLOC_SIMPLE_LEN
+ default 0x200000
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3576/Makefile b/arch/arm/mach-rockchip/rk3576/Makefile
new file mode 100644
index 00000000000..cbc58257deb
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rk3576.o
+obj-y += clk_rk3576.o
+obj-y += syscon_rk3576.o
diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
new file mode 100644
index 00000000000..cc580b33e9c
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rk3576.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rk3576_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rk3576_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
new file mode 100644
index 00000000000..a0fe1803e37
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <spl.h>
+#include <asm/armv8/mmu.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/grf_rk3576.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/ioc_rk3576.h>
+
+#define SYS_GRF_BASE 0x2600A000
+#define SYS_GRF_SOC_CON2 0x0008
+#define SYS_GRF_SOC_CON7 0x001c
+#define SYS_GRF_SOC_CON11 0x002c
+#define SYS_GRF_SOC_CON12 0x0030
+
+#define GPIO0_IOC_BASE 0x26040000
+#define GPIO0B_PULL_L 0x0024
+#define GPIO0B_IE_L 0x002C
+
+#define SYS_SGRF_BASE 0x26004000
+#define SYS_SGRF_SOC_CON14 0x0058
+#define SYS_SGRF_SOC_CON15 0x005C
+#define SYS_SGRF_SOC_CON20 0x0070
+
+#define FW_SYS_SGRF_BASE 0x26005000
+#define SGRF_DOMAIN_CON1 0x4
+#define SGRF_DOMAIN_CON2 0x8
+#define SGRF_DOMAIN_CON3 0xc
+#define SGRF_DOMAIN_CON4 0x10
+#define SGRF_DOMAIN_CON5 0x14
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
+ [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
+};
+
+static struct mm_region rk3576_mem_map[] = {
+ {
+ /*
+ * sdhci_send_command sets the start_addr to 0, while
+ * sdhci_transfer_data calls dma_unmap_single on that
+ * address when the transfer is done, which in turn calls
+ * invalidate_dcache_range on that memory block.
+ * Map the Bootrom that sits in that memory area, to just
+ * let the invalidate_dcache_range call pass.
+ */
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x00008000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O area */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0xb080000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PMU_SRAM, CBUF, SYSTEM_SRAM */
+ .virt = 0x3fe70000UL,
+ .phys = 0x3fe70000UL,
+ .size = 0x190000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* MSCH_DDR_PORT */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* PCIe 0+1 */
+ .virt = 0x900000000UL,
+ .phys = 0x900000000UL,
+ .size = 0x100800000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3576_mem_map;
+
+void board_debug_uart_init(void)
+{
+}
+
+#ifdef CONFIG_XPL_BUILD
+void rockchip_stimer_init(void)
+{
+ u32 reg;
+
+ /* If Timer already enabled, don't re-init it */
+ reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+ if (reg & 0x1)
+ return;
+
+ asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
+ writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
+}
+#endif
+
+#ifndef CONFIG_TPL_BUILD
+int arch_cpu_init(void)
+{
+#ifdef CONFIG_XPL_BUILD
+ u32 val;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+ writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
+
+ /* Set the sdmmc0 to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+ writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
+
+ /* Set the UFS to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+ writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
+
+ /* Set the fspi0 and fspi1 to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+ writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
+
+ /* Set the decom to access ddr memory */
+ val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+ writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
+
+ /*
+ * Set the GPIO0B0~B3 pull up and input enable.
+ * Keep consistent with other IO.
+ */
+ writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
+ writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
+
+ /*
+ * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
+ * keep consistent with other pwm.
+ */
+ writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
+
+ /* Enable noc slave response timeout */
+ writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
+ writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
+
+ /*
+ * Enable cci channels for below module AXI R/W
+ * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
+ */
+ writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
+#endif
+
+ return 0;
+}
+#endif
+
diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
new file mode 100644
index 00000000000..7c15df97d28
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rk3576_syscon_ids[] = {
+ { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3576-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
+ { .compatible = "rockchip,rk3576-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
+ { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3576-sdgmac-grf", .data = ROCKCHIP_SYSCON_SDGMAC },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3576) = {
+ .name = "rk3576_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3576_syscon_ids,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
index 4e2af55d6e1..8d6a1261bfa 100644
--- a/arch/arm/mach-rockchip/sdram.c
+++ b/arch/arm/mach-rockchip/sdram.c
@@ -110,6 +110,7 @@ static int rockchip_dram_init_banksize(void)
u8 i, j;
if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
+ !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
!IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
return -ENOTSUPP;
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 9bab86d2347..6b544e957b2 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -265,6 +265,15 @@ To build rk3568 boards:
make evb-rk3568_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
+To build rk3576 boards:
+
+.. code-block:: bash
+
+ export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf
+ export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin
+ make roc-pc-rk3576_defconfig
+ make CROSS_COMPILE=aarch64-linux-gnu-
+
To build rk3588 boards:
.. code-block:: bash
diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h
new file mode 100644
index 00000000000..d52a0c18da2
--- /dev/null
+++ b/include/configs/rk3576_common.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIG_RK3576_COMMON_H
+#define __CONFIG_RK3576_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CFG_IRAM_BASE 0x3ff80000
+
+#define CFG_SYS_SDRAM_BASE 0x40000000
+
+/*
+ * 16G according to the TRM memory map, but things like efi_memory
+ * handling (efi_loader) choke on a main block going out side the
+ * 4G area.
+ */
+//#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE)
+#define SDRAM_MAX_SIZE 0x400000000UL
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x40c00000\0" \
+ "script_offset_f=0xffe000\0" \
+ "script_size_f=0x2000\0" \
+ "pxefile_addr_r=0x40e00000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "kernel_comp_addr_r=0x4a000000\0" \
+ "fdt_addr_r=0x52000000\0" \
+ "fdtoverlay_addr_r=0x52100000\0" \
+ "ramdisk_addr_r=0x52180000\0" \
+ "kernel_comp_size=0x8000000\0"
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ "boot_targets=" BOOT_TARGETS "\0"
+
+#endif /* __CONFIG_RK3576_COMMON_H */
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 11/20] arm: rockchip: Add RK3576 arch core support
2024-11-21 14:27 ` [PATCH 11/20] arm: rockchip: Add RK3576 arch core support Heiko Stuebner
@ 2024-11-26 18:07 ` Quentin Schulz
2025-01-30 23:07 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Quentin Schulz @ 2024-11-26 18:07 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel, Xuhui Lin
Hi Heiko,
On 11/21/24 3:27 PM, Heiko Stuebner wrote:
> From: Xuhui Lin <xuhui.lin@rock-chips.com>
>
> The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A72
Probably rather RK3576 :)
> and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out,
> DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS,
> USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C,
> UART, SPI, GPIO and PWM.
>
> Add arch core support for it.
>
> Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
> [adapted for mainline u-boot]
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/dts/rk3576-u-boot.dtsi | 119 +++++++++
> arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
> .../include/asm/arch-rockchip/grf_rk3576.h | 225 ++++++++++++++++
> .../include/asm/arch-rockchip/ioc_rk3576.h | 244 ++++++++++++++++++
> arch/arm/mach-rockchip/Kconfig | 46 +++-
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3576/Kconfig | 48 ++++
> arch/arm/mach-rockchip/rk3576/Makefile | 9 +
> arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +++
> arch/arm/mach-rockchip/rk3576/rk3576.c | 169 ++++++++++++
> arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 ++
> arch/arm/mach-rockchip/sdram.c | 1 +
> doc/board/rockchip/rockchip.rst | 9 +
> include/configs/rk3576_common.h | 42 +++
> 15 files changed, 992 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
> create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> create mode 100644 include/configs/rk3576_common.h
>
> diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
> new file mode 100644
> index 00000000000..1399faf47df
> --- /dev/null
> +++ b/arch/arm/dts/rk3576-u-boot.dtsi
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
Not sure this is the appropriate copyright holder here.
> + */
> +
> +#include "rockchip-u-boot.dtsi"
> +
> +/ {
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
> + };
> +
> + dmc {
> + compatible = "rockchip,rk3576-dmc";
> + bootph-all;
> + };
> +};
> +
> +&cru {
> + bootph-all;
> +};
> +
> +&emmc_bus8 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_strb {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&pcfg_pull_down {
> + bootph-all;
> +};
> +
> +&pcfg_pull_none {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up_drv_level_2 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&php_grf {
> + bootph-all;
> +};
> +
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pmu1_grf {
> + bootph-all;
> +};
> +
> +&sdhci {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc0_bus4 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_det {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sys_grf {
> + bootph-all;
> +};
> +
> +&uart0 {
> + bootph-all;
> + clock-frequency = <24000000>;
> +};
> +
> +&uart0m0_xfer {
> + bootph-all;
> +};
> +
> +&xin24m {
> + bootph-all;
> +};
> diff --git a/arch/arm/include/asm/arch-rk3576/boot0.h b/arch/arm/include/asm/arch-rk3576/boot0.h
> new file mode 100644
> index 00000000000..dea2b20252d
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3576/boot0.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_BOOT0_H__
> +#define __ASM_ARCH_BOOT0_H__
> +
> +#include <asm/arch-rockchip/boot0.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rk3576/gpio.h b/arch/arm/include/asm/arch-rk3576/gpio.h
> new file mode 100644
> index 00000000000..b48c0a5cf84
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rk3576/gpio.h
> @@ -0,0 +1,11 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __ASM_ARCH_GPIO_H__
> +#define __ASM_ARCH_GPIO_H__
> +
> +#include <asm/arch-rockchip/gpio.h>
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3576.h b/arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> new file mode 100644
> index 00000000000..0db7f5277f5
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> @@ -0,0 +1,225 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
> + */
> +#ifndef _ASM_ARCH_GRF_RK3576_H
> +#define _ASM_ARCH_GRF_RK3576_H
> +
> +/* usb2phy_grf register structure define */
> +struct rk3576_usb2phygrf {
> + unsigned int con[6]; /* address offset: 0x0000 */
> + unsigned int reserved0018[2]; /* address offset: 0x0018 */
> + unsigned int ls_con; /* address offset: 0x0020 */
> + unsigned int dis_con; /* address offset: 0x0024 */
> + unsigned int bvalid_con; /* address offset: 0x0028 */
> + unsigned int id_con; /* address offset: 0x002c */
> + unsigned int vbusvalid_con; /* address offset: 0x0030 */
> + unsigned int reserved0034[3]; /* address offset: 0x0034 */
> + unsigned int dbg_con[1]; /* address offset: 0x0040 */
> + unsigned int linest_timeout; /* address offset: 0x0044 */
> + unsigned int linest_deb; /* address offset: 0x0048 */
> + unsigned int rx_timeout; /* address offset: 0x004c */
> + unsigned int seq_limt; /* address offset: 0x0050 */
> + unsigned int linest_cnt_st; /* address offset: 0x0054 */
> + unsigned int dbg_st; /* address offset: 0x0058 */
> + unsigned int rx_cnt_st; /* address offset: 0x005c */
> + unsigned int reserved0060[8]; /* address offset: 0x0060 */
> + unsigned int st[1]; /* address offset: 0x0080 */
> + unsigned int reserved0084[15]; /* address offset: 0x0084 */
> + unsigned int int_en; /* address offset: 0x00c0 */
> + unsigned int int_st; /* address offset: 0x00c4 */
> + unsigned int int_st_clr; /* address offset: 0x00c8 */
> + unsigned int reserved00cc; /* address offset: 0x00cc */
> + unsigned int detclk_sel; /* address offset: 0x00d0 */
> +};
> +
> +check_member(rk3576_usb2phygrf, detclk_sel, 0x00d0);
> +
> +/* php_grf register structure define */
> +struct rk3576_phpgrf {
> + unsigned int mmubp_st; /* address offset: 0x0000 */
> + unsigned int mmubp_con[1]; /* address offset: 0x0004 */
> + unsigned int mmu0_con; /* address offset: 0x0008 */
> + unsigned int mmu1_con; /* address offset: 0x000c */
> + unsigned int mem_con[3]; /* address offset: 0x0010 */
> + unsigned int sata0_con; /* address offset: 0x001c */
> + unsigned int sata1_con; /* address offset: 0x0020 */
> + unsigned int usb3otg1_status_lat[2]; /* address offset: 0x0024 */
> + unsigned int usb3otg1_status_cb; /* address offset: 0x002c */
> + unsigned int usb3otg1_status; /* address offset: 0x0030 */
> + unsigned int usb3otg1_con[2]; /* address offset: 0x0034 */
> + unsigned int reserved003c[3]; /* address offset: 0x003c */
> + unsigned int pciepipe_con[1]; /* address offset: 0x0048 */
> + unsigned int reserved004c[2]; /* address offset: 0x004c */
> + unsigned int pcie_clkreq_st; /* address offset: 0x0054 */
> + unsigned int reserved0058; /* address offset: 0x0058 */
> + unsigned int mmu0_st[5]; /* address offset: 0x005c */
> + unsigned int mmu1_st[5]; /* address offset: 0x0070 */
> +};
> +
> +check_member(rk3576_phpgrf, mmu1_st, 0x0070);
> +
> +/* pmu0_grf register structure define */
> +struct rk3576_pmu0grf {
> + unsigned int soc_con[7]; /* address offset: 0x0000 */
> + unsigned int reserved001c; /* address offset: 0x001c */
> + unsigned int io_ret_con[2]; /* address offset: 0x0020 */
> + unsigned int reserved0028[2]; /* address offset: 0x0028 */
> + unsigned int mem_con; /* address offset: 0x0030 */
> + unsigned int reserved0034[3]; /* address offset: 0x0034 */
> + unsigned int os_reg[8]; /* address offset: 0x0040 */
> +};
> +
> +check_member(rk3576_pmu0grf, os_reg, 0x0040);
> +
> +/* pmu0_sgrf register structure define */
> +struct rk3576_pmu0sgrf {
> + unsigned int soc_con[3]; /* address offset: 0x0000 */
> + unsigned int reserved000c[13]; /* address offset: 0x000c */
> + unsigned int dcie_con[8]; /* address offset: 0x0040 */
> + unsigned int dcie_wlock; /* address offset: 0x0060 */
> +};
> +
> +check_member(rk3576_pmu0sgrf, dcie_wlock, 0x0060);
> +
> +/* pmu1_grf register structure define */
> +struct rk3576_pmu1grf {
> + unsigned int soc_con[8]; /* address offset: 0x0000 */
> + unsigned int reserved0020[12]; /* address offset: 0x0020 */
> + unsigned int biu_con; /* address offset: 0x0050 */
> + unsigned int biu_status; /* address offset: 0x0054 */
> + unsigned int reserved0058[2]; /* address offset: 0x0058 */
> + unsigned int soc_status; /* address offset: 0x0060 */
> + unsigned int reserved0064[7]; /* address offset: 0x0064 */
> + unsigned int mem_con[2]; /* address offset: 0x0080 */
> + unsigned int reserved0088[30]; /* address offset: 0x0088 */
> + unsigned int func_rst_status; /* address offset: 0x0100 */
> + unsigned int func_rst_clr; /* address offset: 0x0104 */
> + unsigned int reserved0108[2]; /* address offset: 0x0108 */
> + unsigned int sd_detect_con; /* address offset: 0x0110 */
> + unsigned int sd_detect_sts; /* address offset: 0x0114 */
> + unsigned int sd_detect_clr; /* address offset: 0x0118 */
> + unsigned int sd_detect_cnt; /* address offset: 0x011c */
> + unsigned int reserved0120[56]; /* address offset: 0x0120 */
> + unsigned int os_reg[16]; /* address offset: 0x0200 */
> +};
> +
> +check_member(rk3576_pmu1grf, os_reg, 0x0200);
> +
> +/* pmu1_sgrf register structure define */
> +struct rk3576_pmu1sgrf {
> + unsigned int soc_con[18]; /* address offset: 0x0000 */
> +};
> +
> +check_member(rk3576_pmu1sgrf, soc_con, 0x0000);
> +
> +/* sdgmac_grf register structure define */
> +struct rk3576_sdgmacgrf {
> + unsigned int mem_con[5]; /* address offset: 0x0000 */
> + unsigned int reserved0014[2]; /* address offset: 0x0014 */
> + unsigned int gmac_st[1]; /* address offset: 0x001c */
> + unsigned int gmac0_con; /* address offset: 0x0020 */
> + unsigned int gmac1_con; /* address offset: 0x0024 */
> + unsigned int gmac0_tp[2]; /* address offset: 0x0028 */
> + unsigned int gmac1_tp[2]; /* address offset: 0x0030 */
> + unsigned int gmac0_cmd; /* address offset: 0x0038 */
> + unsigned int gmac1_cmd; /* address offset: 0x003c */
> + unsigned int reserved0040[2]; /* address offset: 0x0040 */
> + unsigned int mem_gate_con; /* address offset: 0x0048 */
> +};
> +
> +check_member(rk3576_sdgmacgrf, mem_gate_con, 0x0048);
> +
> +/* sys_grf register structure define */
> +struct rk3576_sysgrf {
> + unsigned int soc_con[13]; /* address offset: 0x0000 */
> + unsigned int reserved0034[3]; /* address offset: 0x0034 */
> + unsigned int biu_con[6]; /* address offset: 0x0040 */
> + unsigned int reserved0058[2]; /* address offset: 0x0058 */
> + unsigned int biu_status[8]; /* address offset: 0x0060 */
> + unsigned int mem_con[19]; /* address offset: 0x0080 */
> + unsigned int reserved00cc[29]; /* address offset: 0x00cc */
> + unsigned int soc_status[2]; /* address offset: 0x0140 */
> + unsigned int memfault_status[2]; /* address offset: 0x0148 */
> + unsigned int reserved0150[12]; /* address offset: 0x0150 */
> + unsigned int soc_code; /* address offset: 0x0180 */
> + unsigned int reserved0184[3]; /* address offset: 0x0184 */
> + unsigned int soc_version; /* address offset: 0x0190 */
> + unsigned int reserved0194[3]; /* address offset: 0x0194 */
> + unsigned int chip_id; /* address offset: 0x01a0 */
> + unsigned int reserved01a4[3]; /* address offset: 0x01a4 */
> + unsigned int chip_version; /* address offset: 0x01b0 */
> +};
> +
> +check_member(rk3576_sysgrf, chip_version, 0x01b0);
> +
> +/* sys_sgrf register structure define */
> +struct rk3576_syssgrf {
> + unsigned int ddr_bank_hash_ctrl; /* address offset: 0x0000 */
> + unsigned int ddr_bank_mask[4]; /* address offset: 0x0004 */
> + unsigned int ddr_rank_mask[1]; /* address offset: 0x0014 */
> + unsigned int reserved0018[2]; /* address offset: 0x0018 */
> + unsigned int soc_con[21]; /* address offset: 0x0020 */
> + unsigned int reserved0074[3]; /* address offset: 0x0074 */
> + unsigned int dmac0_con[10]; /* address offset: 0x0080 */
> + unsigned int reserved00a8[22]; /* address offset: 0x00a8 */
> + unsigned int dmac1_con[10]; /* address offset: 0x0100 */
> + unsigned int reserved0128[22]; /* address offset: 0x0128 */
> + unsigned int dmac2_con[10]; /* address offset: 0x0180 */
> + unsigned int reserved01a8[22]; /* address offset: 0x01a8 */
> + unsigned int key_con[2]; /* address offset: 0x0200 */
> + unsigned int key_wlock; /* address offset: 0x0208 */
> + unsigned int reserved020c[13]; /* address offset: 0x020c */
> + unsigned int soc_status; /* address offset: 0x0240 */
> + unsigned int reserved0244[47]; /* address offset: 0x0244 */
> + unsigned int ip_info_con; /* address offset: 0x0300 */
> +};
> +
> +check_member(rk3576_syssgrf, ip_info_con, 0x0300);
> +
> +/* ufs_grf register structure define */
> +struct rk3576_ufsgrf {
> + unsigned int clk_ctrl; /* address offset: 0x0000 */
> + unsigned int uic_src_sel; /* address offset: 0x0004 */
> + unsigned int ufs_state_ie; /* address offset: 0x0008 */
> + unsigned int ufs_state_is; /* address offset: 0x000c */
> + unsigned int ufs_state; /* address offset: 0x0010 */
> + unsigned int reserved0014[13]; /* address offset: 0x0014 */
> +};
> +
> +check_member(rk3576_ufsgrf, reserved0014, 0x0014);
> +
> +/* usbdpphy_grf register structure define */
> +struct rk3576_usbdpphygrf {
> + unsigned int reserved0000; /* address offset: 0x0000 */
> + unsigned int con[3]; /* address offset: 0x0004 */
> + unsigned int reserved0010[29]; /* address offset: 0x0010 */
> + unsigned int status[1]; /* address offset: 0x0084 */
> + unsigned int reserved0088[14]; /* address offset: 0x0088 */
> + unsigned int lfps_det_con; /* address offset: 0x00c0 */
> + unsigned int int_en; /* address offset: 0x00c4 */
> + unsigned int int_status; /* address offset: 0x00c8 */
> +};
> +
> +check_member(rk3576_usbdpphygrf, int_status, 0x00c8);
> +
> +/* usb_grf register structure define */
> +struct rk3576_usbgrf {
> + unsigned int mmubp_st; /* address offset: 0x0000 */
> + unsigned int mmubp_con; /* address offset: 0x0004 */
> + unsigned int mmu2_con; /* address offset: 0x0008 */
> + unsigned int mem_con0; /* address offset: 0x000c */
> + unsigned int mem_con1; /* address offset: 0x0010 */
> + unsigned int reserved0014[2]; /* address offset: 0x0014 */
> + unsigned int usb3otg0_status_lat[2]; /* address offset: 0x001c */
> + unsigned int usb3otg0_status_cb; /* address offset: 0x0024 */
> + unsigned int usb3otg0_status; /* address offset: 0x0028 */
> + unsigned int usb3otg0_con[2]; /* address offset: 0x002c */
> + unsigned int reserved0034[4]; /* address offset: 0x0034 */
> + unsigned int mmu2_st[5]; /* address offset: 0x0044 */
> + unsigned int mem_con[1]; /* address offset: 0x0058 */
> +};
> +
> +check_member(rk3576_usbgrf, mem_con, 0x0058);
> +
> +#endif /* _ASM_ARCH_GRF_RK3576_H */
> diff --git a/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h b/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> new file mode 100644
> index 00000000000..9fd24b502bb
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> @@ -0,0 +1,244 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
> + */
> +#ifndef _ASM_ARCH_IOC_RK3576_H
> +#define _ASM_ARCH_IOC_RK3576_H
> +
> +/* pmu0_ioc register structure define */
> +struct rk3576_pmu0_ioc_reg {
> + unsigned int gpio0a_iomux_sel_l; /* address offset: 0x0000 */
> + unsigned int gpio0a_iomux_sel_h; /* address offset: 0x0004 */
> + unsigned int gpio0b_iomux_sel_l; /* address offset: 0x0008 */
> + unsigned int reserved000c; /* address offset: 0x000c */
> + unsigned int gpio0a_ds_l; /* address offset: 0x0010 */
> + unsigned int gpio0a_ds_h; /* address offset: 0x0014 */
> + unsigned int gpio0b_ds_l; /* address offset: 0x0018 */
> + unsigned int reserved001c; /* address offset: 0x001c */
> + unsigned int gpio0a_pull; /* address offset: 0x0020 */
> + unsigned int gpio0b_pull_l; /* address offset: 0x0024 */
> + unsigned int gpio0a_ie; /* address offset: 0x0028 */
> + unsigned int gpio0b_ie_l; /* address offset: 0x002c */
> + unsigned int gpio0a_smt; /* address offset: 0x0030 */
> + unsigned int gpio0b_smt_l; /* address offset: 0x0034 */
> + unsigned int gpio0a_pdis; /* address offset: 0x0038 */
> + unsigned int gpio0b_pdis_l; /* address offset: 0x003c */
> + unsigned int osc_con; /* address offset: 0x0040 */
> +};
> +
> +check_member(rk3576_pmu0_ioc_reg, osc_con, 0x0040);
> +
> +/* pmu1_ioc register structure define */
> +struct rk3576_pmu1_ioc_reg {
> + unsigned int gpio0b_iomux_sel_h; /* address offset: 0x0000 */
> + unsigned int gpio0c_iomux_sel_l; /* address offset: 0x0004 */
> + unsigned int gpio0c_iomux_sel_h; /* address offset: 0x0008 */
> + unsigned int gpio0d_iomux_sel_l; /* address offset: 0x000c */
> + unsigned int gpio0d_iomux_sel_h; /* address offset: 0x0010 */
> + unsigned int gpio0b_ds_h; /* address offset: 0x0014 */
> + unsigned int gpio0c_ds_l; /* address offset: 0x0018 */
> + unsigned int gpio0c_ds_h; /* address offset: 0x001c */
> + unsigned int gpio0d_ds_l; /* address offset: 0x0020 */
> + unsigned int gpio0d_ds_h; /* address offset: 0x0024 */
> + unsigned int gpio0b_pull_h; /* address offset: 0x0028 */
> + unsigned int gpio0c_pull; /* address offset: 0x002c */
> + unsigned int gpio0d_pull; /* address offset: 0x0030 */
> + unsigned int gpio0b_ie_h; /* address offset: 0x0034 */
> + unsigned int gpio0c_ie; /* address offset: 0x0038 */
> + unsigned int gpio0d_ie; /* address offset: 0x003c */
> + unsigned int gpio0b_smt_h; /* address offset: 0x0040 */
> + unsigned int gpio0c_smt; /* address offset: 0x0044 */
> + unsigned int gpio0d_smt; /* address offset: 0x0048 */
> + unsigned int gpio0b_pdis_h; /* address offset: 0x004c */
> + unsigned int gpio0c_pdis; /* address offset: 0x0050 */
> + unsigned int gpio0d_pdis; /* address offset: 0x0054 */
> +};
> +
> +check_member(rk3576_pmu1_ioc_reg, gpio0d_pdis, 0x0054);
> +
> +/* top_ioc register structure define */
> +struct rk3576_top_ioc_reg {
> + unsigned int reserved0000[2]; /* address offset: 0x0000 */
> + unsigned int gpio0b_iomux_sel_l; /* address offset: 0x0008 */
> + unsigned int gpio0b_iomux_sel_h; /* address offset: 0x000c */
> + unsigned int gpio0c_iomux_sel_l; /* address offset: 0x0010 */
> + unsigned int gpio0c_iomux_sel_h; /* address offset: 0x0014 */
> + unsigned int gpio0d_iomux_sel_l; /* address offset: 0x0018 */
> + unsigned int gpio0d_iomux_sel_h; /* address offset: 0x001c */
> + unsigned int gpio1a_iomux_sel_l; /* address offset: 0x0020 */
> + unsigned int gpio1a_iomux_sel_h; /* address offset: 0x0024 */
> + unsigned int gpio1b_iomux_sel_l; /* address offset: 0x0028 */
> + unsigned int gpio1b_iomux_sel_h; /* address offset: 0x002c */
> + unsigned int gpio1c_iomux_sel_l; /* address offset: 0x0030 */
> + unsigned int gpio1c_iomux_sel_h; /* address offset: 0x0034 */
> + unsigned int gpio1d_iomux_sel_l; /* address offset: 0x0038 */
> + unsigned int gpio1d_iomux_sel_h; /* address offset: 0x003c */
> + unsigned int gpio2a_iomux_sel_l; /* address offset: 0x0040 */
> + unsigned int gpio2a_iomux_sel_h; /* address offset: 0x0044 */
> + unsigned int gpio2b_iomux_sel_l; /* address offset: 0x0048 */
> + unsigned int gpio2b_iomux_sel_h; /* address offset: 0x004c */
> + unsigned int gpio2c_iomux_sel_l; /* address offset: 0x0050 */
> + unsigned int gpio2c_iomux_sel_h; /* address offset: 0x0054 */
> + unsigned int gpio2d_iomux_sel_l; /* address offset: 0x0058 */
> + unsigned int gpio2d_iomux_sel_h; /* address offset: 0x005c */
> + unsigned int gpio3a_iomux_sel_l; /* address offset: 0x0060 */
> + unsigned int gpio3a_iomux_sel_h; /* address offset: 0x0064 */
> + unsigned int gpio3b_iomux_sel_l; /* address offset: 0x0068 */
> + unsigned int gpio3b_iomux_sel_h; /* address offset: 0x006c */
> + unsigned int gpio3c_iomux_sel_l; /* address offset: 0x0070 */
> + unsigned int gpio3c_iomux_sel_h; /* address offset: 0x0074 */
> + unsigned int gpio3d_iomux_sel_l; /* address offset: 0x0078 */
> + unsigned int gpio3d_iomux_sel_h; /* address offset: 0x007c */
> + unsigned int gpio4a_iomux_sel_l; /* address offset: 0x0080 */
> + unsigned int gpio4a_iomux_sel_h; /* address offset: 0x0084 */
> + unsigned int gpio4b_iomux_sel_l; /* address offset: 0x0088 */
> + unsigned int gpio4b_iomux_sel_h; /* address offset: 0x008c */
> + unsigned int reserved0090[24]; /* address offset: 0x0090 */
> + unsigned int ioc_misc_con; /* address offset: 0x00f0 */
> + unsigned int sdmmc_detn_flt; /* address offset: 0x00f4 */
> +};
> +
> +check_member(rk3576_top_ioc_reg, sdmmc_detn_flt, 0x00f4);
> +
> +/* vccio_ioc register structure define */
> +struct rk3576_vccio_ioc_reg {
> + unsigned int reserved0000[8]; /* address offset: 0x0000 */
> + unsigned int gpio1a_ds_l; /* address offset: 0x0020 */
> + unsigned int gpio1a_ds_h; /* address offset: 0x0024 */
> + unsigned int gpio1b_ds_l; /* address offset: 0x0028 */
> + unsigned int gpio1b_ds_h; /* address offset: 0x002c */
> + unsigned int gpio1c_ds_l; /* address offset: 0x0030 */
> + unsigned int gpio1c_ds_h; /* address offset: 0x0034 */
> + unsigned int gpio1d_ds_l; /* address offset: 0x0038 */
> + unsigned int gpio1d_ds_h; /* address offset: 0x003c */
> + unsigned int gpio2a_ds_l; /* address offset: 0x0040 */
> + unsigned int gpio2a_ds_h; /* address offset: 0x0044 */
> + unsigned int gpio2b_ds_l; /* address offset: 0x0048 */
> + unsigned int gpio2b_ds_h; /* address offset: 0x004c */
> + unsigned int gpio2c_ds_l; /* address offset: 0x0050 */
> + unsigned int gpio2c_ds_h; /* address offset: 0x0054 */
> + unsigned int gpio2d_ds_l; /* address offset: 0x0058 */
> + unsigned int gpio2d_ds_h; /* address offset: 0x005c */
> + unsigned int gpio3a_ds_l; /* address offset: 0x0060 */
> + unsigned int gpio3a_ds_h; /* address offset: 0x0064 */
> + unsigned int gpio3b_ds_l; /* address offset: 0x0068 */
> + unsigned int gpio3b_ds_h; /* address offset: 0x006c */
> + unsigned int gpio3c_ds_l; /* address offset: 0x0070 */
> + unsigned int gpio3c_ds_h; /* address offset: 0x0074 */
> + unsigned int gpio3d_ds_l; /* address offset: 0x0078 */
> + unsigned int gpio3d_ds_h; /* address offset: 0x007c */
> + unsigned int gpio4a_ds_l; /* address offset: 0x0080 */
> + unsigned int gpio4a_ds_h; /* address offset: 0x0084 */
> + unsigned int gpio4b_ds_l; /* address offset: 0x0088 */
> + unsigned int gpio4b_ds_h; /* address offset: 0x008c */
> + unsigned int reserved0090[32]; /* address offset: 0x0090 */
> + unsigned int gpio1a_pull; /* address offset: 0x0110 */
> + unsigned int gpio1b_pull; /* address offset: 0x0114 */
> + unsigned int gpio1c_pull; /* address offset: 0x0118 */
> + unsigned int gpio1d_pull; /* address offset: 0x011c */
> + unsigned int gpio2a_pull; /* address offset: 0x0120 */
> + unsigned int gpio2b_pull; /* address offset: 0x0124 */
> + unsigned int gpio2c_pull; /* address offset: 0x0128 */
> + unsigned int gpio2d_pull; /* address offset: 0x012c */
> + unsigned int gpio3a_pull; /* address offset: 0x0130 */
> + unsigned int gpio3b_pull; /* address offset: 0x0134 */
> + unsigned int gpio3c_pull; /* address offset: 0x0138 */
> + unsigned int gpio3d_pull; /* address offset: 0x013c */
> + unsigned int gpio4a_pull; /* address offset: 0x0140 */
> + unsigned int gpio4b_pull; /* address offset: 0x0144 */
> + unsigned int reserved0148[14]; /* address offset: 0x0148 */
> + unsigned int gpio1a_ie; /* address offset: 0x0180 */
> + unsigned int gpio1b_ie; /* address offset: 0x0184 */
> + unsigned int gpio1c_ie; /* address offset: 0x0188 */
> + unsigned int gpio1d_ie; /* address offset: 0x018c */
> + unsigned int gpio2a_ie; /* address offset: 0x0190 */
> + unsigned int gpio2b_ie; /* address offset: 0x0194 */
> + unsigned int gpio2c_ie; /* address offset: 0x0198 */
> + unsigned int gpio2d_ie; /* address offset: 0x019c */
> + unsigned int gpio3a_ie; /* address offset: 0x01a0 */
> + unsigned int gpio3b_ie; /* address offset: 0x01a4 */
> + unsigned int gpio3c_ie; /* address offset: 0x01a8 */
> + unsigned int gpio3d_ie; /* address offset: 0x01ac */
> + unsigned int gpio4a_ie; /* address offset: 0x01b0 */
> + unsigned int gpio4b_ie; /* address offset: 0x01b4 */
> + unsigned int reserved01b8[22]; /* address offset: 0x01b8 */
> + unsigned int gpio1a_smt; /* address offset: 0x0210 */
> + unsigned int gpio1b_smt; /* address offset: 0x0214 */
> + unsigned int gpio1c_smt; /* address offset: 0x0218 */
> + unsigned int gpio1d_smt; /* address offset: 0x021c */
> + unsigned int gpio2a_smt; /* address offset: 0x0220 */
> + unsigned int gpio2b_smt; /* address offset: 0x0224 */
> + unsigned int gpio2c_smt; /* address offset: 0x0228 */
> + unsigned int gpio2d_smt; /* address offset: 0x022c */
> + unsigned int gpio3a_smt; /* address offset: 0x0230 */
> + unsigned int gpio3b_smt; /* address offset: 0x0234 */
> + unsigned int gpio3c_smt; /* address offset: 0x0238 */
> + unsigned int gpio3d_smt; /* address offset: 0x023c */
> + unsigned int gpio4a_smt; /* address offset: 0x0240 */
> + unsigned int gpio4b_smt; /* address offset: 0x0244 */
> + unsigned int reserved0248[14]; /* address offset: 0x0248 */
> + unsigned int gpio1a_pdis; /* address offset: 0x0280 */
> + unsigned int gpio1b_pdis; /* address offset: 0x0284 */
> + unsigned int gpio1c_pdis; /* address offset: 0x0288 */
> + unsigned int gpio1d_pdis; /* address offset: 0x028c */
> + unsigned int gpio2a_pdis; /* address offset: 0x0290 */
> + unsigned int gpio2b_pdis; /* address offset: 0x0294 */
> + unsigned int gpio2c_pdis; /* address offset: 0x0298 */
> + unsigned int gpio2d_pdis; /* address offset: 0x029c */
> + unsigned int gpio3a_pdis; /* address offset: 0x02a0 */
> + unsigned int gpio3b_pdis; /* address offset: 0x02a4 */
> + unsigned int gpio3c_pdis; /* address offset: 0x02a8 */
> + unsigned int gpio3d_pdis; /* address offset: 0x02ac */
> + unsigned int gpio4a_pdis; /* address offset: 0x02b0 */
> + unsigned int gpio4b_pdis; /* address offset: 0x02b4 */
> + unsigned int reserved02b8[82]; /* address offset: 0x02b8 */
> + unsigned int misc_con[9]; /* address offset: 0x0400 */
> +};
> +
> +check_member(rk3576_vccio_ioc_reg, misc_con, 0x0400);
> +
> +/* vccio6_ioc register structure define */
> +struct rk3576_vccio6_ioc_reg {
> + unsigned int reserved0000[36]; /* address offset: 0x0000 */
> + unsigned int gpio4c_ds_l; /* address offset: 0x0090 */
> + unsigned int gpio4c_ds_h; /* address offset: 0x0094 */
> + unsigned int reserved0098[44]; /* address offset: 0x0098 */
> + unsigned int gpio4c_pull; /* address offset: 0x0148 */
> + unsigned int reserved014c[27]; /* address offset: 0x014c */
> + unsigned int gpio4c_ie; /* address offset: 0x01b8 */
> + unsigned int reserved01bc[35]; /* address offset: 0x01bc */
> + unsigned int gpio4c_smt; /* address offset: 0x0248 */
> + unsigned int reserved024c[27]; /* address offset: 0x024c */
> + unsigned int gpio4c_pdis; /* address offset: 0x02b8 */
> + unsigned int reserved02bc[53]; /* address offset: 0x02bc */
> + unsigned int gpio4c_iomux_sel_l; /* address offset: 0x0390 */
> + unsigned int gpio4c_iomux_sel_h; /* address offset: 0x0394 */
> + unsigned int reserved0398[26]; /* address offset: 0x0398 */
> + unsigned int misc_con[2]; /* address offset: 0x0400 */
> + unsigned int reserved0408[14]; /* address offset: 0x0408 */
> + unsigned int hdmitx_hpd_status; /* address offset: 0x0440 */
> +};
> +
> +check_member(rk3576_vccio6_ioc_reg, hdmitx_hpd_status, 0x0440);
> +
> +/* vccio7_ioc register structure define */
> +struct rk3576_vccio7_ioc_reg {
> + unsigned int reserved0000[38]; /* address offset: 0x0000 */
> + unsigned int gpio4d_ds_l; /* address offset: 0x0098 */
> + unsigned int reserved009c[44]; /* address offset: 0x009c */
> + unsigned int gpio4d_pull; /* address offset: 0x014c */
> + unsigned int reserved0150[27]; /* address offset: 0x0150 */
> + unsigned int gpio4d_ie; /* address offset: 0x01bc */
> + unsigned int reserved01c0[35]; /* address offset: 0x01c0 */
> + unsigned int gpio4d_smt; /* address offset: 0x024c */
> + unsigned int reserved0250[27]; /* address offset: 0x0250 */
> + unsigned int gpio4d_pdis; /* address offset: 0x02bc */
> + unsigned int reserved02c0[54]; /* address offset: 0x02c0 */
> + unsigned int gpio4d_iomux_sel_l; /* address offset: 0x0398 */
> + unsigned int reserved039c[25]; /* address offset: 0x039c */
> + unsigned int xin_ufs_con; /* address offset: 0x0400 */
> +};
> +
> +check_member(rk3576_vccio7_ioc_reg, xin_ufs_con, 0x0400);
> +
> +#endif /* _ASM_ARCH_IOC_RK3576_H */
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 269c219a6f8..568ce7389ed 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -341,6 +341,49 @@ config ROCKCHIP_RK3568
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3576
> + bool "Support Rockchip RK3576"
> + select ARM64
> + select SUPPORT_SPL
> + select SPL
> + select CLK
> + select PINCTRL
> + select RAM
> + select REGMAP
> + select SYSCON
> + select BOARD_LATE_INIT
> + select DM_REGULATOR_FIXED
> + select DM_RESET
> + imply BOOTSTD_FULL
> + imply CLK_SCMI
> + imply DM_RNG
> + imply MISC_INIT_R
> + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
> + imply OF_LIBFDT_OVERLAY
> + imply OF_UPSTREAM
> + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
> + imply RNG_ROCKCHIP
> + imply ROCKCHIP_COMMON_BOARD
> + imply ROCKCHIP_OTP
> + imply SCMI_FIRMWARE
> + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
> + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
> + select HAS_CUSTOM_SYS_INIT_SP_ADDR
Can you move this one with the other "select"?
> + imply SPL_LIBCOMMON_SUPPORT if SPL
> + imply SPL_LIBGENERIC_SUPPORT if SPL
> + imply SPL_ROCKCHIP_COMMON_BOARD
> + imply SPL_SYS_MALLOC_F if SPL
> + imply SPL_SYS_MALLOC_SIMPLE if SPL
> + imply TPL_LIBCOMMON_SUPPORT if TPL
> + imply TPL_LIBGENERIC_SUPPORT if TPL
> + imply TPL_ROCKCHIP_COMMON_BOARD if TPL
> + imply TPL_SYS_MALLOC_F if TPL
> + imply TPL_SYS_MALLOC_SIMPLE if TPL
> +
> + help
> + The Rockchip RK3576 is a ARM-based SoC with a quad-core Cortex-A53
> + and a quad-core Cortex-A72.
> +
> config ROCKCHIP_RK3588
> bool "Support Rockchip RK3588"
> select ARM64
> @@ -490,7 +533,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
>
> config ROCKCHIP_EXTERNAL_TPL
> bool "Use external TPL binary"
> - default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
> + default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3576 || ROCKCHIP_RK3588
> help
> Some Rockchip SoCs require an external TPL to initialize DRAM.
> Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
> @@ -627,6 +670,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
> source "arch/arm/mach-rockchip/rk3368/Kconfig"
> source "arch/arm/mach-rockchip/rk3399/Kconfig"
> source "arch/arm/mach-rockchip/rk3568/Kconfig"
> +source "arch/arm/mach-rockchip/rk3576/Kconfig"
> source "arch/arm/mach-rockchip/rk3588/Kconfig"
> source "arch/arm/mach-rockchip/rv1108/Kconfig"
> source "arch/arm/mach-rockchip/rv1126/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 5e7edc99cdc..52464b01f4e 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
> +obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
> obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
> obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
> obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
> diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
> new file mode 100644
> index 00000000000..2e46b2b90d2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/Kconfig
> @@ -0,0 +1,48 @@
> +if ROCKCHIP_RK3576
> +
> +config ROCKCHIP_BOOT_MODE_REG
> + default 0x26024040
> +
> +config ROCKCHIP_STIMER_BASE
> + default 0x27400000
> +
> +config SYS_SOC
> + default "rk3576"
> +
> +config CUSTOM_SYS_INIT_SP_ADDR
> + default 0x43f00000
> +
> +config SYS_MALLOC_F_LEN
> + default 0x10000
> +
> +config SPL_SYS_MALLOC_F_LEN
> + default 0x8000
> +
> +config TPL_SYS_MALLOC_F_LEN
> + default 0x4000
> +
> +config TEXT_BASE
> + default 0x40200000
> +
> +config SPL_TEXT_BASE
> + default 0x40000000
> +
> +config SPL_HAS_BSS_LINKER_SECTION
> + default y if ARM64
> +
> +config SPL_BSS_START_ADDR
> + default 0x43f80000
> +
> +config SPL_BSS_MAX_SIZE
> + default 0x8000
> +
> +config SPL_STACK_R
> + default y
> +
> +config SPL_STACK_R_ADDR
> + default 0x43e00000
> +
> +config SPL_STACK_R_MALLOC_SIMPLE_LEN
> + default 0x200000
> +
> +endif
> diff --git a/arch/arm/mach-rockchip/rk3576/Makefile b/arch/arm/mach-rockchip/rk3576/Makefile
> new file mode 100644
> index 00000000000..cbc58257deb
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/Makefile
> @@ -0,0 +1,9 @@
> +#
> +# (C) Copyright 2023 Rockchip Electronics Co., Ltd
> +#
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +
> +obj-y += rk3576.o
> +obj-y += clk_rk3576.o
> +obj-y += syscon_rk3576.o
> diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> new file mode 100644
> index 00000000000..cc580b33e9c
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru_rk3576.h>
> +#include <linux/err.h>
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(rockchip_rk3576_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3576_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
> +}
> +
> diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
> new file mode 100644
> index 00000000000..a0fe1803e37
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <spl.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/arch-rockchip/bootrom.h>
> +#include <asm/arch-rockchip/grf_rk3576.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/arch-rockchip/ioc_rk3576.h>
> +
> +#define SYS_GRF_BASE 0x2600A000
> +#define SYS_GRF_SOC_CON2 0x0008
> +#define SYS_GRF_SOC_CON7 0x001c
> +#define SYS_GRF_SOC_CON11 0x002c
> +#define SYS_GRF_SOC_CON12 0x0030
> +
> +#define GPIO0_IOC_BASE 0x26040000
> +#define GPIO0B_PULL_L 0x0024
> +#define GPIO0B_IE_L 0x002C
> +
> +#define SYS_SGRF_BASE 0x26004000
> +#define SYS_SGRF_SOC_CON14 0x0058
> +#define SYS_SGRF_SOC_CON15 0x005C
> +#define SYS_SGRF_SOC_CON20 0x0070
> +
> +#define FW_SYS_SGRF_BASE 0x26005000
> +#define SGRF_DOMAIN_CON1 0x4
> +#define SGRF_DOMAIN_CON2 0x8
> +#define SGRF_DOMAIN_CON3 0xc
> +#define SGRF_DOMAIN_CON4 0x10
> +#define SGRF_DOMAIN_CON5 0x14
> +
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
> + [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
> +};
> +
> +static struct mm_region rk3576_mem_map[] = {
> + {
> + /*
> + * sdhci_send_command sets the start_addr to 0, while
> + * sdhci_transfer_data calls dma_unmap_single on that
> + * address when the transfer is done, which in turn calls
> + * invalidate_dcache_range on that memory block.
> + * Map the Bootrom that sits in that memory area, to just
> + * let the invalidate_dcache_range call pass.
> + */
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0x00008000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* I/O area */
> + .virt = 0x20000000UL,
> + .phys = 0x20000000UL,
> + .size = 0xb080000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* PMU_SRAM, CBUF, SYSTEM_SRAM */
> + .virt = 0x3fe70000UL,
> + .phys = 0x3fe70000UL,
> + .size = 0x190000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* MSCH_DDR_PORT */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x400000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + /* PCIe 0+1 */
> + .virt = 0x900000000UL,
> + .phys = 0x900000000UL,
> + .size = 0x100800000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = rk3576_mem_map;
> +
> +void board_debug_uart_init(void)
> +{
> +}
We need to surround this with #ifdef DEBUG_UART_BOARD_INIT otherwise
disabling the symbol (it's only implied at vendor level) will have
duplicate implementation for the function (one is provided if the symbol
isn't defined).
> +
> +#ifdef CONFIG_XPL_BUILD
> +void rockchip_stimer_init(void)
> +{
> + u32 reg;
> +
> + /* If Timer already enabled, don't re-init it */
> + reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
> + if (reg & 0x1)
> + return;
> +
> + asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
> + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
> + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
> + writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
> +}
> +#endif
> +
> +#ifndef CONFIG_TPL_BUILD
> +int arch_cpu_init(void)
> +{
> +#ifdef CONFIG_XPL_BUILD
> + u32 val;
> +
> + /* Set the emmc to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
> + writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
> +
> + /* Set the sdmmc0 to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
> + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
> +
> + /* Set the UFS to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
> + writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
> +
> + /* Set the fspi0 and fspi1 to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
> + writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
> +
> + /* Set the decom to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
> + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
> +
> + /*
> + * Set the GPIO0B0~B3 pull up and input enable.
> + * Keep consistent with other IO.
> + */
> + writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
> + writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
> +
Mmmmm... do we really want that? Shouldn't we rather let the user define
what they want in the DT and handle that whenever a device requests
those pins in the gpio function?
> + /*
> + * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
> + * keep consistent with other pwm.
> + */
> + writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
> +
This one is odd too, but this wouldn't be using pinmuxing I guess.
> + /* Enable noc slave response timeout */
> + writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
This is usb0_slv_timeout_ena in the TRM, shouldn't that be handled at
the USB controller/PHY level?
> + writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
> +
Same here? Timeout enabling for some but not all IPs there.
> + /*
> + * Enable cci channels for below module AXI R/W
> + * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
> + */
> + writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
> +#endif
> +
> + return 0;
> +}
> +#endif
> +
> diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> new file mode 100644
> index 00000000000..7c15df97d28
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2023 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +
> +static const struct udevice_id rk3576_syscon_ids[] = {
> + { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3576-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
> + { .compatible = "rockchip,rk3576-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
> + { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
> + { .compatible = "rockchip,rk3576-sdgmac-grf", .data = ROCKCHIP_SYSCON_SDGMAC },
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3576) = {
> + .name = "rk3576_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3576_syscon_ids,
> +#if CONFIG_IS_ENABLED(OF_REAL)
> + .bind = dm_scan_fdt_dev,
> +#endif
> +};
> diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c
> index 4e2af55d6e1..8d6a1261bfa 100644
> --- a/arch/arm/mach-rockchip/sdram.c
> +++ b/arch/arm/mach-rockchip/sdram.c
> @@ -110,6 +110,7 @@ static int rockchip_dram_init_banksize(void)
> u8 i, j;
>
> if (!IS_ENABLED(CONFIG_ROCKCHIP_RK3588) &&
> + !IS_ENABLED(CONFIG_ROCKCHIP_RK3576) &&
> !IS_ENABLED(CONFIG_ROCKCHIP_RK3568))
> return -ENOTSUPP;
>
Maybe we should add a new symbol for that which we enable on SoC Kconfig
level instead of having to update this file every time we add a new SoC
without open DRAM init :) Not necessary for this patch series though.
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 9bab86d2347..6b544e957b2 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -265,6 +265,15 @@ To build rk3568 boards:
> make evb-rk3568_defconfig
> make CROSS_COMPILE=aarch64-linux-gnu-
>
> +To build rk3576 boards:
> +
> +.. code-block:: bash
> +
> + export BL31=../rkbin/bin/rk35/rk3576_bl31_v1.04.elf
> + export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3576_ddr_lp4_2112MHz_lp5_2736MHz_v1.03.bin
> + make roc-pc-rk3576_defconfig
> + make CROSS_COMPILE=aarch64-linux-gnu-
> +
> To build rk3588 boards:
>
> .. code-block:: bash
> diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h
> new file mode 100644
> index 00000000000..d52a0c18da2
> --- /dev/null
> +++ b/include/configs/rk3576_common.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __CONFIG_RK3576_COMMON_H
> +#define __CONFIG_RK3576_COMMON_H
> +
> +#include "rockchip-common.h"
> +
> +#define CFG_IRAM_BASE 0x3ff80000
> +
> +#define CFG_SYS_SDRAM_BASE 0x40000000
> +
> +/*
> + * 16G according to the TRM memory map, but things like efi_memory
> + * handling (efi_loader) choke on a main block going out side the
> + * 4G area.
> + */
I believe you fixed that? Also the variable is set to 16GiB now, so I
guess this really isn't an issue anymore?
Cheers,
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 11/20] arm: rockchip: Add RK3576 arch core support
2024-11-21 14:27 ` [PATCH 11/20] arm: rockchip: Add RK3576 arch core support Heiko Stuebner
2024-11-26 18:07 ` Quentin Schulz
@ 2025-01-30 23:07 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:07 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg@chromium.org, philipp.tomsich@vrull.eu,
kever.yang@rock-chips.com, lukma@denx.de, seanga2@gmail.com,
peng.fan@nxp.com, jh80.chung@samsung.com, joe.hershberger@ni.com,
rfried.dev@gmail.com, quentin.schulz@cherry.de,
detlev.casanova@collabora.com, u-boot@lists.denx.de,
sebastian.reichel@collabora.com, Xuhui Lin
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> From: Xuhui Lin <xuhui.lin@rock-chips.com>
>
> The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A72
> and quad-core Cortex-A53 including 6TOPS NPU, Mali-G52 MC3, HDMI Out,
> DP, eDP, MIPI DSI, MIPI CSI2, LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, UFS,
> USB OTG 3.0, Type-C, USB 2.0, PCIe 2.1, SATA 3, Ethernet, SDIO3.0, I2C,
> UART, SPI, GPIO and PWM.
>
> Add arch core support for it.
>
> Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
> [adapted for mainline u-boot]
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/dts/rk3576-u-boot.dtsi | 119 +++++++++
> arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
> .../include/asm/arch-rockchip/grf_rk3576.h | 225 ++++++++++++++++
> .../include/asm/arch-rockchip/ioc_rk3576.h | 244 ++++++++++++++++++
> arch/arm/mach-rockchip/Kconfig | 46 +++-
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3576/Kconfig | 48 ++++
> arch/arm/mach-rockchip/rk3576/Makefile | 9 +
> arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +++
> arch/arm/mach-rockchip/rk3576/rk3576.c | 169 ++++++++++++
> arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 ++
> arch/arm/mach-rockchip/sdram.c | 1 +
> doc/board/rockchip/rockchip.rst | 9 +
> include/configs/rk3576_common.h | 42 +++
> 15 files changed, 992 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
> create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> create mode 100644 include/configs/rk3576_common.h
>
> diff --git a/arch/arm/dts/rk3576-u-boot.dtsi b/arch/arm/dts/rk3576-u-boot.dtsi
> new file mode 100644
> index 00000000000..1399faf47df
> --- /dev/null
> +++ b/arch/arm/dts/rk3576-u-boot.dtsi
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +#include "rockchip-u-boot.dtsi"
> +
> +/ {
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &sdhci;
> + };
> +
> + dmc {
> + compatible = "rockchip,rk3576-dmc";
> + bootph-all;
> + };
> +};
> +
> +&cru {
> + bootph-all;
> +};
> +
> +&emmc_bus8 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&emmc_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
This is missing:
&emmc_rstnout {
bootph-pre-ram;
bootph-some-ram;
};
> +
> +&emmc_strb {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
And to use pinctrl in SPL we need:
&ioc_grf {
bootph-all;
};
> +
> +&pcfg_pull_down {
> + bootph-all;
> +};
pcfg_pull_down is not used and can be dropped.
> +
> +&pcfg_pull_none {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up {
> + bootph-all;
> +};
> +
> +&pcfg_pull_up_drv_level_2 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
For sdmmc0 we need:
&pcfg_pull_up_drv_level_3 {
bootph-pre-ram;
bootph-some-ram;
};
> +
> +&php_grf {
> + bootph-all;
> +};
Nothing use php_grf and this can be dropped.
> +
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pmu1_grf {
> + bootph-all;
> +};
> +
> +&sdhci {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc {
> + bootph-pre-ram;
> + bootph-some-ram;
> + u-boot,spl-fifo-mode;
> +};
> +
> +&sdmmc0_bus4 {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_clk {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_cmd {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +&sdmmc0_det {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
This is missing:
&sdmmc0_pwren {
bootph-pre-ram;
bootph-some-ram;
};
> +
> +&sys_grf {
> + bootph-all;
> +};
> +
> +&uart0 {
> + bootph-all;
> + clock-frequency = <24000000>;
> +};
> +
> +&uart0m0_xfer {
> + bootph-all;
> +};
> +
> +&xin24m {
> + bootph-all;
> +};
[snip]
> diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
> index 269c219a6f8..568ce7389ed 100644
> --- a/arch/arm/mach-rockchip/Kconfig
> +++ b/arch/arm/mach-rockchip/Kconfig
> @@ -341,6 +341,49 @@ config ROCKCHIP_RK3568
> and video codec support. Peripherals include Gigabit Ethernet,
> USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
>
> +config ROCKCHIP_RK3576
> + bool "Support Rockchip RK3576"
> + select ARM64
> + select SUPPORT_SPL
> + select SPL
> + select CLK
> + select PINCTRL
> + select RAM
> + select REGMAP
> + select SYSCON
> + select BOARD_LATE_INIT
> + select DM_REGULATOR_FIXED
> + select DM_RESET
Please add:
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
> + imply BOOTSTD_FULL
> + imply CLK_SCMI
SCMI clk is not used, please drop.
> + imply DM_RNG
Please add:
imply FIT
imply LEGACY_IMAGE_FORMAT
imply MISC
> + imply MISC_INIT_R
> + imply MMC_HS200_SUPPORT if MMC_SDHCI_ROCKCHIP
> + imply OF_LIBFDT_OVERLAY
Please add:
imply OF_LIVE
> + imply OF_UPSTREAM
> + imply PHY_GIGE if DWC_ETH_QOS_ROCKCHIP
> + imply RNG_ROCKCHIP
> + imply ROCKCHIP_COMMON_BOARD
Please add:
imply ROCKCHIP_COMMON_STACK_ADDR
imply ROCKCHIP_EXTERNAL_TPL
> + imply ROCKCHIP_OTP
> + imply SCMI_FIRMWARE
SCMI firmware is not used, please drop.
Please add:
imply SPL_ATF
> + imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
Please add:
imply SPL_CLK
imply SPL_DM_SEQ_ALIAS
imply SPL_FIT_SIGNATURE
imply SPL_LOAD_FIT
> + imply SPL_MMC_HS200_SUPPORT if SPL_MMC && MMC_HS200_SUPPORT
Please add:
imply SPL_OF_CONTROL
imply SPL_PINCTRL
imply SPL_RAM
imply SPL_REGMAP
imply SPL_SERIAL
imply SPL_SYSCON
imply SYS_RELOC_GD_ENV_ADDR
imply SYSRESET
With all the extra imply rk3576 board defconfigs will have much less SPL
related option to enable.
The below select and imply can be dropped with [1]
[1] https://patchwork.ozlabs.org/patch/2039045/
> + select HAS_CUSTOM_SYS_INIT_SP_ADDR
> + imply SPL_LIBCOMMON_SUPPORT if SPL
> + imply SPL_LIBGENERIC_SUPPORT if SPL
> + imply SPL_ROCKCHIP_COMMON_BOARD
> + imply SPL_SYS_MALLOC_F if SPL
> + imply SPL_SYS_MALLOC_SIMPLE if SPL
> + imply TPL_LIBCOMMON_SUPPORT if TPL
> + imply TPL_LIBGENERIC_SUPPORT if TPL
> + imply TPL_ROCKCHIP_COMMON_BOARD if TPL
> + imply TPL_SYS_MALLOC_F if TPL
> + imply TPL_SYS_MALLOC_SIMPLE if TPL
> +
> + help
> + The Rockchip RK3576 is a ARM-based SoC with a quad-core Cortex-A53
> + and a quad-core Cortex-A72.
> +
> config ROCKCHIP_RK3588
> bool "Support Rockchip RK3588"
> select ARM64
> @@ -490,7 +533,7 @@ config TPL_ROCKCHIP_COMMON_BOARD
>
> config ROCKCHIP_EXTERNAL_TPL
> bool "Use external TPL binary"
> - default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3588
> + default y if ROCKCHIP_RK3308 || ROCKCHIP_RK3568 || ROCKCHIP_RK3576 || ROCKCHIP_RK3588
This should be moved to an imply under ROCKCHIP_RK3576.
> help
> Some Rockchip SoCs require an external TPL to initialize DRAM.
> Enable this option and build with ROCKCHIP_TPL=/path/to/ddr.bin to
> @@ -627,6 +670,7 @@ source "arch/arm/mach-rockchip/rk3328/Kconfig"
> source "arch/arm/mach-rockchip/rk3368/Kconfig"
> source "arch/arm/mach-rockchip/rk3399/Kconfig"
> source "arch/arm/mach-rockchip/rk3568/Kconfig"
> +source "arch/arm/mach-rockchip/rk3576/Kconfig"
> source "arch/arm/mach-rockchip/rk3588/Kconfig"
> source "arch/arm/mach-rockchip/rv1108/Kconfig"
> source "arch/arm/mach-rockchip/rv1126/Kconfig"
> diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
> index 5e7edc99cdc..52464b01f4e 100644
> --- a/arch/arm/mach-rockchip/Makefile
> +++ b/arch/arm/mach-rockchip/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
> obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
> obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
> obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
> +obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/
> obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
> obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
> obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
> diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
> new file mode 100644
> index 00000000000..2e46b2b90d2
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/Kconfig
> @@ -0,0 +1,48 @@
> +if ROCKCHIP_RK3576
> +
> +config ROCKCHIP_BOOT_MODE_REG
> + default 0x26024040
> +
> +config ROCKCHIP_STIMER_BASE
> + default 0x27400000
> +
> +config SYS_SOC
> + default "rk3576"
Please add following to simplify adding a board defconfig without
requiring a new TARGET_ symbol.
config SYS_CONFIG_NAME
default "rk3576_common"
The below defaults can be dropped with [1].
> +
> +config CUSTOM_SYS_INIT_SP_ADDR
> + default 0x43f00000
> +
> +config SYS_MALLOC_F_LEN
> + default 0x10000
> +
> +config SPL_SYS_MALLOC_F_LEN
> + default 0x8000
> +
> +config TPL_SYS_MALLOC_F_LEN
> + default 0x4000
> +
> +config TEXT_BASE
> + default 0x40200000
> +
> +config SPL_TEXT_BASE
> + default 0x40000000
> +
> +config SPL_HAS_BSS_LINKER_SECTION
> + default y if ARM64
> +
> +config SPL_BSS_START_ADDR
> + default 0x43f80000
> +
> +config SPL_BSS_MAX_SIZE
> + default 0x8000
> +
> +config SPL_STACK_R
> + default y
> +
> +config SPL_STACK_R_ADDR
> + default 0x43e00000
> +
> +config SPL_STACK_R_MALLOC_SIMPLE_LEN
> + default 0x200000
[1] https://patchwork.ozlabs.org/patch/2039045/
> +
> +endif
[snip]
> diff --git a/arch/arm/mach-rockchip/rk3576/clk_rk3576.c b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> new file mode 100644
> index 00000000000..cc580b33e9c
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <dm.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/cru_rk3576.h>
> +#include <linux/err.h>
With the suggested change below following includes can be removed:
- syscon.h
- asm/arch-rockchip/clock.h
- linux/err.h
> +
> +int rockchip_get_clk(struct udevice **devp)
> +{
> + return uclass_get_device_by_driver(UCLASS_CLK,
> + DM_DRIVER_GET(rockchip_rk3576_cru), devp);
> +}
> +
> +void *rockchip_get_cru(void)
> +{
> + struct rk3576_clk_priv *priv;
> + struct udevice *dev;
> + int ret;
> +
> + ret = rockchip_get_clk(&dev);
> + if (ret)
> + return ERR_PTR(ret);
> +
> + priv = dev_get_priv(dev);
> +
> + return priv->cru;
This entire function can be simplified to just:
return (void *)RK3576_CRU_BASE;
This will save a few ms of boot time.
> +}
> +
> diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c
> new file mode 100644
> index 00000000000..a0fe1803e37
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <spl.h>
> +#include <asm/armv8/mmu.h>
> +#include <asm/arch-rockchip/bootrom.h>
> +#include <asm/arch-rockchip/grf_rk3576.h>
> +#include <asm/arch-rockchip/hardware.h>
> +#include <asm/arch-rockchip/ioc_rk3576.h>
Following includes can be removed:
- spl.h
- asm/arch-rockchip/grf_rk3576.h
- asm/arch-rockchip/ioc_rk3576.h
> +
> +#define SYS_GRF_BASE 0x2600A000
> +#define SYS_GRF_SOC_CON2 0x0008
> +#define SYS_GRF_SOC_CON7 0x001c
> +#define SYS_GRF_SOC_CON11 0x002c
> +#define SYS_GRF_SOC_CON12 0x0030
> +
> +#define GPIO0_IOC_BASE 0x26040000
> +#define GPIO0B_PULL_L 0x0024
> +#define GPIO0B_IE_L 0x002C
> +
> +#define SYS_SGRF_BASE 0x26004000
> +#define SYS_SGRF_SOC_CON14 0x0058
> +#define SYS_SGRF_SOC_CON15 0x005C
> +#define SYS_SGRF_SOC_CON20 0x0070
> +
> +#define FW_SYS_SGRF_BASE 0x26005000
> +#define SGRF_DOMAIN_CON1 0x4
> +#define SGRF_DOMAIN_CON2 0x8
> +#define SGRF_DOMAIN_CON3 0xc
> +#define SGRF_DOMAIN_CON4 0x10
> +#define SGRF_DOMAIN_CON5 0x14
> +
> +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
> + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@2a330000",
> + [BROM_BOOTSOURCE_SD] = "/soc/mmc@2a310000",
> +};
> +
> +static struct mm_region rk3576_mem_map[] = {
> + {
> + /*
> + * sdhci_send_command sets the start_addr to 0, while
> + * sdhci_transfer_data calls dma_unmap_single on that
> + * address when the transfer is done, which in turn calls
> + * invalidate_dcache_range on that memory block.
> + * Map the Bootrom that sits in that memory area, to just
> + * let the invalidate_dcache_range call pass.
> + */
> + .virt = 0x0UL,
> + .phys = 0x0UL,
> + .size = 0x00008000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
Above workaround should not be needed with [2] and [3], please drop.
[2] https://patchwork.ozlabs.org/patch/2038102/
[3] https://patchwork.ozlabs.org/patch/2039037/
> + /* I/O area */
> + .virt = 0x20000000UL,
> + .phys = 0x20000000UL,
> + .size = 0xb080000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* PMU_SRAM, CBUF, SYSTEM_SRAM */
> + .virt = 0x3fe70000UL,
> + .phys = 0x3fe70000UL,
> + .size = 0x190000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* MSCH_DDR_PORT */
> + .virt = 0x40000000UL,
> + .phys = 0x40000000UL,
> + .size = 0x400000000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> + PTE_BLOCK_INNER_SHARE
> + }, {
> + /* PCIe 0+1 */
> + .virt = 0x900000000UL,
> + .phys = 0x900000000UL,
> + .size = 0x100800000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = rk3576_mem_map;
> +
> +void board_debug_uart_init(void)
> +{
> +}
> +
> +#ifdef CONFIG_XPL_BUILD
> +void rockchip_stimer_init(void)
> +{
> + u32 reg;
> +
> + /* If Timer already enabled, don't re-init it */
> + reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
> + if (reg & 0x1)
> + return;
> +
> + asm volatile("msr CNTFRQ_EL0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY));
> + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
> + writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
> + writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
These magic constans could be replaced with constants. See the commit
"fixup: arm: rockchip: Add RK3576 arch core support - rk3576.c" at [4]
for a possible option.
[4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3576-2025.04-wip/
> +}
> +#endif
> +
> +#ifndef CONFIG_TPL_BUILD
> +int arch_cpu_init(void)
> +{
> +#ifdef CONFIG_XPL_BUILD
Above ifndef CONFIG_TPL_BUILD and ifdef CONFIG_XPL_BUILD combo can be
replaced with a single ifdef CONFIG_SPL_BUILD.
> + u32 val;
> +
> + /* Set the emmc to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
> + writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
> +
> + /* Set the sdmmc0 to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
> + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
> +
> + /* Set the UFS to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
> + writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
> +
> + /* Set the fspi0 and fspi1 to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
> + writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
> +
> + /* Set the decom to access ddr memory */
> + val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
> + writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
> +
> + /*
> + * Set the GPIO0B0~B3 pull up and input enable.
> + * Keep consistent with other IO.
> + */
> + writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
> + writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
> +
> + /*
> + * Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
> + * keep consistent with other pwm.
> + */
> + writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
> +
> + /* Enable noc slave response timeout */
> + writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
> + writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
> +
> + /*
> + * Enable cci channels for below module AXI R/W
> + * Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
> + */
> + writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
> +#endif
> +
> + return 0;
> +}
> +#endif
> +
> diff --git a/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> new file mode 100644
> index 00000000000..7c15df97d28
> --- /dev/null
> +++ b/arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * (C) Copyright 2023 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <dm.h>
> +#include <syscon.h>
syscon.h is not needed and can be removed.
> +#include <asm/arch-rockchip/clock.h>
> +
> +static const struct udevice_id rk3576_syscon_ids[] = {
> + { .compatible = "rockchip,rk3576-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
> + { .compatible = "rockchip,rk3576-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
> + { .compatible = "rockchip,rk3576-php-grf", .data = ROCKCHIP_SYSCON_PHP_GRF },
> + { .compatible = "rockchip,rk3576-pmu1-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
> + { .compatible = "rockchip,rk3576-sdgmac-grf", .data = ROCKCHIP_SYSCON_SDGMAC },
None of these should be needed, suggest you only keep SYSCON_GRF and
SYSCON_PMUGRF.
> + { }
> +};
> +
> +U_BOOT_DRIVER(syscon_rk3576) = {
> + .name = "rk3576_syscon",
> + .id = UCLASS_SYSCON,
> + .of_match = rk3576_syscon_ids,
> +#if CONFIG_IS_ENABLED(OF_REAL)
> + .bind = dm_scan_fdt_dev,
> +#endif
> +};
[snip]
> diff --git a/include/configs/rk3576_common.h b/include/configs/rk3576_common.h
> new file mode 100644
> index 00000000000..d52a0c18da2
> --- /dev/null
> +++ b/include/configs/rk3576_common.h
> @@ -0,0 +1,42 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * (C) Copyright 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#ifndef __CONFIG_RK3576_COMMON_H
> +#define __CONFIG_RK3576_COMMON_H
RK3576 has cpu-id at 0xa in otp so we need:
#define CFG_CPUID_OFFSET 0xa
> +
> +#include "rockchip-common.h"
> +
> +#define CFG_IRAM_BASE 0x3ff80000
> +
> +#define CFG_SYS_SDRAM_BASE 0x40000000
> +
> +/*
> + * 16G according to the TRM memory map, but things like efi_memory
> + * handling (efi_loader) choke on a main block going out side the
> + * 4G area.
> + */
> +//#define SDRAM_MAX_SIZE (SZ_4G - CFG_SYS_SDRAM_BASE)
> +#define SDRAM_MAX_SIZE 0x400000000UL
Typically SDRAM_MAX_SIZE has been used for space below the 4G address
boundary. With the patch at [5] this no longer matter, but for
consistency with all other rockchip targets I suggest you change to use
the commented out version, SZ_4G - CFG_SYS_SDRAM_BASE.
[5] https://patchwork.ozlabs.org/patch/2040760/
Suggest we add following to make it possible to used this header as-is
as SYS_CONFIG_NAME="rk3576_common".
#ifndef ROCKCHIP_DEVICE_SETTINGS
#define ROCKCHIP_DEVICE_SETTINGS
#endif
> +
> +#define ENV_MEM_LAYOUT_SETTINGS \
> + "scriptaddr=0x40c00000\0" \
> + "script_offset_f=0xffe000\0" \
> + "script_size_f=0x2000\0" \
> + "pxefile_addr_r=0x40e00000\0" \
> + "kernel_addr_r=0x42000000\0" \
> + "kernel_comp_addr_r=0x4a000000\0" \
> + "fdt_addr_r=0x52000000\0" \
> + "fdtoverlay_addr_r=0x52100000\0" \
> + "ramdisk_addr_r=0x52180000\0" \
> + "kernel_comp_size=0x8000000\0"
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
> + "partitions=" PARTS_DEFAULT \
I suggest we remove this partitions env var, it include legacy
partitioning that has never been that useful.
> + ENV_MEM_LAYOUT_SETTINGS \
> + ROCKCHIP_DEVICE_SETTINGS \
> + "boot_targets=" BOOT_TARGETS "\0"
> +
> +#endif /* __CONFIG_RK3576_COMMON_H */
I have created a few fixup commits at [4] that include my suggested
changes, please feel free to squash any changes you feel is relevant :-)
[4] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3576-2025.04-wip/
Regards,
Jonas
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 12/20] pinctrl: rockchip: support rk3576 pinctrl
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (10 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 11/20] arm: rockchip: Add RK3576 arch core support Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-30 23:23 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 13/20] clk: rockchip: Add rk3576 clk support Heiko Stuebner
` (9 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Steven Liu
From: Steven Liu <steven.liu@rock-chips.com>
Add support for the rk3576 variant of pinctrl.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3576.c | 287 ++++++++++++++++++++
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 3 +
3 files changed, 291 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3576.c
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
index c91f650b043..468840913dd 100644
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3576.c b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
new file mode 100644
index 00000000000..9399540ed4a
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
@@ -0,0 +1,287 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd
+ */
+
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+#include <dt-bindings/pinctrl/rockchip.h>
+
+static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+
+ if (bank->bank_num == 0 && pin >= RK_PB4 && pin <= RK_PB7)
+ reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
+
+ debug("iomux write reg = %x data = %x\n", reg, data);
+
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3576_DRV_BITS_PER_PIN 4
+#define RK3576_DRV_PINS_PER_REG 4
+#define RK3576_DRV_GPIO0_AL_OFFSET 0x10
+#define RK3576_DRV_GPIO0_BH_OFFSET 0x2014
+#define RK3576_DRV_GPIO1_OFFSET 0x6020
+#define RK3576_DRV_GPIO2_OFFSET 0x6040
+#define RK3576_DRV_GPIO3_OFFSET 0x6060
+#define RK3576_DRV_GPIO4_AL_OFFSET 0x6080
+#define RK3576_DRV_GPIO4_CL_OFFSET 0xA090
+#define RK3576_DRV_GPIO4_DL_OFFSET 0xB098
+
+static void rk3576_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_DRV_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_DRV_GPIO0_BH_OFFSET - 0xc;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_DRV_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_DRV_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_DRV_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_DRV_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_DRV_GPIO4_CL_OFFSET - 0x10;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_DRV_GPIO4_DL_OFFSET - 0x18;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_DRV_PINS_PER_REG;
+ *bit *= RK3576_DRV_BITS_PER_PIN;
+}
+
+static int rk3576_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int drv = ((strength & BIT(2)) >> 2) | ((strength & BIT(0)) << 2) | (strength & BIT(1));
+
+ rk3576_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3576_PULL_BITS_PER_PIN 2
+#define RK3576_PULL_PINS_PER_REG 8
+#define RK3576_PULL_GPIO0_AL_OFFSET 0x20
+#define RK3576_PULL_GPIO0_BH_OFFSET 0x2028
+#define RK3576_PULL_GPIO1_OFFSET 0x6110
+#define RK3576_PULL_GPIO2_OFFSET 0x6120
+#define RK3576_PULL_GPIO3_OFFSET 0x6130
+#define RK3576_PULL_GPIO4_AL_OFFSET 0x6140
+#define RK3576_PULL_GPIO4_CL_OFFSET 0xA148
+#define RK3576_PULL_GPIO4_DL_OFFSET 0xB14C
+
+static void rk3576_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_PULL_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_PULL_GPIO0_BH_OFFSET - 0x4;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_PULL_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_PULL_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_PULL_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_PULL_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_PULL_GPIO4_CL_OFFSET - 0x8;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_PULL_GPIO4_DL_OFFSET - 0xc;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_PULL_PINS_PER_REG;
+ *bit *= RK3576_PULL_BITS_PER_PIN;
+}
+
+static int rk3576_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -EOPNOTSUPP;
+
+ rk3576_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = 1; /* FIXME: was always set to 1 in vendor kernel */
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3576_SMT_BITS_PER_PIN 1
+#define RK3576_SMT_PINS_PER_REG 8
+#define RK3576_SMT_GPIO0_AL_OFFSET 0x30
+#define RK3576_SMT_GPIO0_BH_OFFSET 0x2040
+#define RK3576_SMT_GPIO1_OFFSET 0x6210
+#define RK3576_SMT_GPIO2_OFFSET 0x6220
+#define RK3576_SMT_GPIO3_OFFSET 0x6230
+#define RK3576_SMT_GPIO4_AL_OFFSET 0x6240
+#define RK3576_SMT_GPIO4_CL_OFFSET 0xA248
+#define RK3576_SMT_GPIO4_DL_OFFSET 0xB24C
+
+static int rk3576_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ if (bank->bank_num == 0 && pin_num < 12) {
+ *reg = RK3576_SMT_GPIO0_AL_OFFSET;
+ } else if (bank->bank_num == 0) {
+ *reg = RK3576_SMT_GPIO0_BH_OFFSET - 0x4;
+ } else if (bank->bank_num == 1) {
+ *reg = RK3576_SMT_GPIO1_OFFSET;
+ } else if (bank->bank_num == 2) {
+ *reg = RK3576_SMT_GPIO2_OFFSET;
+ } else if (bank->bank_num == 3) {
+ *reg = RK3576_SMT_GPIO3_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 16) {
+ *reg = RK3576_SMT_GPIO4_AL_OFFSET;
+ } else if (bank->bank_num == 4 && pin_num < 24) {
+ *reg = RK3576_SMT_GPIO4_CL_OFFSET - 0x8;
+ } else if (bank->bank_num == 4) {
+ *reg = RK3576_SMT_GPIO4_DL_OFFSET - 0xc;
+ } else {
+ *reg = 0;
+ debug("unsupported bank_num %d\n", bank->bank_num);
+ }
+
+ *reg += ((pin_num / RK3576_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3576_SMT_PINS_PER_REG;
+ *bit *= RK3576_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3576_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+
+ rk3576_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3576_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_pin_bank rk3576_pin_banks[] = {
+ RK3576_PIN_BANK_FLAGS(0, 32, "gpio0", IOMUX_WIDTH_4BIT,
+ 0, 0x8, 0x2004, 0x200C),
+ RK3576_PIN_BANK_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ 0x4020, 0x4028, 0x4030, 0x4038),
+ RK3576_PIN_BANK_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ 0x4040, 0x4048, 0x4050, 0x4058),
+ RK3576_PIN_BANK_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ 0x4060, 0x4068, 0x4070, 0x4078),
+ RK3576_PIN_BANK_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ 0x4080, 0x4088, 0xA390, 0xB398),
+};
+
+static const struct rockchip_pin_ctrl rk3576_pin_ctrl = {
+ .pin_banks = rk3576_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3576_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3576_set_mux,
+ .set_pull = rk3576_set_pull,
+ .set_drive = rk3576_set_drive,
+ .set_schmitt = rk3576_set_schmitt,
+};
+
+static const struct udevice_id rk3576_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3576-pinctrl",
+ .data = (ulong)&rk3576_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3576) = {
+ .name = "rockchip_rk3576_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3576_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if CONFIG_IS_ENABLED(OF_REAL)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
index df7bc684d29..5e3c9c90760 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -458,6 +458,9 @@ struct rockchip_pin_bank {
#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
+#define RK3576_PIN_BANK_FLAGS(ID, PIN, LABEL, M, O1, O2, O3, O4) \
+ PIN_BANK_IOMUX_FLAGS_OFFSET(ID, PIN, LABEL, M, M, M, M, O1, O2, O3, O4)
+
#define RK3588_PIN_BANK_FLAGS(ID, PIN, LABEL, M, P) \
PIN_BANK_IOMUX_FLAGS_PULL_FLAGS(ID, PIN, LABEL, M, M, M, M, P, P, P, P)
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 12/20] pinctrl: rockchip: support rk3576 pinctrl
2024-11-21 14:27 ` [PATCH 12/20] pinctrl: rockchip: support rk3576 pinctrl Heiko Stuebner
@ 2025-01-30 23:23 ` Jonas Karlman
0 siblings, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:23 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg@chromium.org, philipp.tomsich@vrull.eu,
kever.yang@rock-chips.com, lukma@denx.de, seanga2@gmail.com,
peng.fan@nxp.com, jh80.chung@samsung.com, joe.hershberger@ni.com,
rfried.dev@gmail.com, quentin.schulz@cherry.de,
detlev.casanova@collabora.com, u-boot@lists.denx.de,
sebastian.reichel@collabora.com, Steven Liu
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> From: Steven Liu <steven.liu@rock-chips.com>
>
> Add support for the rk3576 variant of pinctrl.
>
> Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
> [adapted to mainline u-boot]
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3576.c | 287 ++++++++++++++++++++
> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 3 +
> 3 files changed, 291 insertions(+)
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3576.c
>
> diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile
> index c91f650b043..468840913dd 100644
> --- a/drivers/pinctrl/rockchip/Makefile
> +++ b/drivers/pinctrl/rockchip/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
> +obj-$(CONFIG_ROCKCHIP_RK3576) += pinctrl-rk3576.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o
> diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3576.c b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
> new file mode 100644
> index 00000000000..9399540ed4a
> --- /dev/null
> +++ b/drivers/pinctrl/rockchip/pinctrl-rk3576.c
> @@ -0,0 +1,287 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2024 Rockchip Electronics Co., Ltd
> + */
> +
> +#include <dm.h>
> +#include <dm/pinctrl.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +
> +#include "pinctrl-rockchip.h"
> +#include <dt-bindings/pinctrl/rockchip.h>
> +
> +static int rk3576_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
> +{
> + struct rockchip_pinctrl_priv *priv = bank->priv;
> + int iomux_num = (pin / 8);
> + struct regmap *regmap;
> + int reg, ret, mask;
> + u8 bit;
> + u32 data;
> +
> + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
This and the debug() below is not really needed, pinctrl-rockchip-core.c
already has similar debug() calls.
> +
> + regmap = priv->regmap_base;
> + reg = bank->iomux[iomux_num].offset;
> + if ((pin % 8) >= 4)
> + reg += 0x4;
> + bit = (pin % 4) * 4;
> + mask = 0xf;
> +
> + data = (mask << (bit + 16));
> + data |= (mux & mask) << bit;
> +
> + if (bank->bank_num == 0 && pin >= RK_PB4 && pin <= RK_PB7)
> + reg += 0x1FF4; /* GPIO0_IOC_GPIO0B_IOMUX_SEL_H */
> +
> + debug("iomux write reg = %x data = %x\n", reg, data);
> +
> + ret = regmap_write(regmap, reg, data);
We should use regmap_update_bits() similar to Linux kernel.
Please feel free to squash "fixup: pinctrl: rockchip: support rk3576
pinctrl" at [1] if you agree.
[1] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3576-2025.04-wip/
Regards,
Jonas
> +
> + return ret;
> +}
[snip]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 13/20] clk: rockchip: Add rk3576 clk support
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (11 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 12/20] pinctrl: rockchip: support rk3576 pinctrl Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-30 23:18 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 14/20] reset: rockchip: implement rk3576 lookup table Heiko Stuebner
` (8 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Elaine Zhang
From: Elaine Zhang <zhangqing@rock-chips.com>
Add clock driver support for Rockchip RK3576 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted to mainline u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
.../include/asm/arch-rockchip/cru_rk3576.h | 486 ++++
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk_rk3576.c | 2517 +++++++++++++++++
3 files changed, 3004 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3576.h
create mode 100644 drivers/clk/rockchip/clk_rk3576.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
new file mode 100644
index 00000000000..893d92ff5f7
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
@@ -0,0 +1,486 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3576_H
+#define _ASM_ARCH_CRU_RK3576_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1008 * MHz)
+#define LPLL_HZ (816 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (1000 * MHz)
+#define PPLL_HZ (1100 * MHz)
+#define GMAC0_PTP_REFCLK_IN (24 * MHz)
+#define GMAC1_PTP_REFCLK_IN (24 * MHz)
+
+/* RK3576 pll id */
+enum rk3576_pll_id {
+ BPLL,
+ LPLL,
+ DPLL,
+ CPLL,
+ GPLL,
+ VPLL,
+ AUPLL,
+ SPLL,
+ PPLL,
+ PLL_COUNT,
+};
+
+struct rk3576_clk_info {
+ unsigned long id;
+ char *name;
+ bool is_cru;
+};
+
+struct rk3576_clk_priv {
+ struct rk3576_cru *cru;
+ struct rk3576_grf *grf;
+ ulong ppll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong vpll_hz;
+ ulong aupll_hz;
+ ulong spll_hz;
+ ulong lpll_hz;
+ ulong bpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3576_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3576_cru {
+ struct rk3576_pll pll[18];
+ unsigned int reserved0[16];/* Address Offset: 0x0240 */
+ unsigned int mode_con00;/* Address Offset: 0x0280 */
+ unsigned int reserved1[31];/* Address Offset: 0x0284 */
+ unsigned int clksel_con[181]; /* Address Offset: 0x0300 */
+ unsigned int reserved2[139];/* Address Offset: 0x05d4 */
+ unsigned int clkgate_con[80];/* Address Offset: 0x0800 */
+ unsigned int reserved3[48];/* Address Offset: 0x0938 */
+ unsigned int softrst_con[80];/* Address Offset: 0x0400 */
+ unsigned int reserved4[48];/* Address Offset: 0x0b38 */
+ unsigned int glb_cnt_th;/* Address Offset: 0x0c00 */
+ unsigned int glb_rst_st;/* Address Offset: 0x0c04 */
+ unsigned int glb_srst_fst;/* Address Offset: 0x0c08 */
+ unsigned int glb_srsr_snd; /* Address Offset: 0x0c0c */
+ unsigned int glb_rst_con;/* Address Offset: 0x0c10 */
+ unsigned int reserved5[43];/* Address Offset: 0x0c14 */
+ unsigned int smoth_divfree_con[3];/* Address Offset: 0x0cc0 */
+ unsigned int fracdiv_high_con[4];/* Address Offset: 0x0ccc */
+ unsigned int reserved8[32137];/* Address Offset: 0x0c38 */
+ unsigned int pmuclksel_con[22]; /* Address Offset: 0x20300 */
+ unsigned int reserved9[298];/* Address Offset: 0x20358 */
+ unsigned int pmuclkgate_con[8]; /* Address Offset: 0x20800 */
+ unsigned int reserved10[32440];/* Address Offset: 0x20820 */
+ unsigned int litclksel_con[4]; /* Address Offset: 0x40300 */
+};
+
+check_member(rk3576_cru, mode_con00, 0x280);
+check_member(rk3576_cru, pmuclksel_con[1], 0x20304);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int m;
+ unsigned int p;
+ unsigned int s;
+ unsigned int k;
+};
+
+#define RK3576_PHP_CRU_BASE 0x8000
+#define RK3576_PMU_CRU_BASE 0x20000
+#define RK3576_BIGCORE_CRU_BASE 0x38000
+#define RK3576_LITCORE_CRU_BASE 0x40000
+#define RK3576_CCI_CRU_BASE 0x48000
+#define RK3576_CRU_BASE 0x27200000
+#define RK3576_SCRU_BASE 0x27214000
+
+#define RK3576_BIGCORE_GRF_BASE 0x2600C000
+#define RK3576_LITCORE_GRF_BASE 0x2600E000
+#define RK3576_CCI_GRF_BASE 0x26010000
+
+#define RK3576_PLL_CON(x) ((x) * 0x4)
+#define RK3576_MODE_CON0 0x280
+#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280)
+#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280)
+#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280)
+#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
+#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
+#define RK3576_GLB_CNT_TH 0xc00
+#define RK3576_GLB_SRST_FST 0xc08
+#define RK3576_GLB_SRST_SND 0xc0c
+#define RK3576_GLB_RST_CON 0xc10
+#define RK3576_GLB_RST_ST 0xc04
+#define RK3576_SDIO_CON0 0xC24
+#define RK3576_SDIO_CON1 0xC28
+#define RK3576_SDMMC_CON0 0xC30
+#define RK3576_SDMMC_CON1 0xC34
+
+#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300)
+#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800)
+#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00)
+
+#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE)
+#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300)
+#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800)
+#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00)
+
+#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300)
+#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800)
+#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00)
+
+#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE)
+#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300)
+#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800)
+#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00)
+#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE)
+#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300)
+#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800)
+#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00)
+
+enum {
+ /* CRU_CLK_SEL8_CON */
+ PCLK_TOP_SEL_SHIFT = 7,
+ PCLK_TOP_SEL_MASK = 3 << PCLK_TOP_SEL_SHIFT,
+ PCLK_TOP_SEL_100M = 0,
+ PCLK_TOP_SEL_50M,
+ PCLK_TOP_SEL_OSC,
+
+ /* CRU_CLK_SEL9_CON */
+ ACLK_TOP_SEL_SHIFT = 5,
+ ACLK_TOP_SEL_MASK = 3 << ACLK_TOP_SEL_SHIFT,
+ ACLK_TOP_SEL_GPLL = 0,
+ ACLK_TOP_SEL_CPLL,
+ ACLK_TOP_SEL_AUPLL,
+ ACLK_TOP_DIV_SHIFT = 0,
+ ACLK_TOP_DIV_MASK = 0x1f << ACLK_TOP_DIV_SHIFT,
+
+ /* CRU_CLK_SEL10_CON */
+ ACLK_TOP_MID_SEL_SHIFT = 5,
+ ACLK_TOP_MID_SEL_MASK = 1 << ACLK_TOP_MID_SEL_SHIFT,
+ ACLK_TOP_MID_SEL_GPLL = 0,
+ ACLK_TOP_MID_SEL_CPLL,
+ ACLK_TOP_MID_DIV_SHIFT = 0,
+ ACLK_TOP_MID_DIV_MASK = 0x1f << ACLK_TOP_MID_DIV_SHIFT,
+
+ /* CRU_CLK_SEL19_CON */
+ HCLK_TOP_SEL_SHIFT = 2,
+ HCLK_TOP_SEL_MASK = 3 << HCLK_TOP_SEL_SHIFT,
+ HCLK_TOP_SEL_200M = 0,
+ HCLK_TOP_SEL_100M,
+ HCLK_TOP_SEL_50M,
+ HCLK_TOP_SEL_OSC,
+
+ /* CRU_CLK_SEL25_CON */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
+
+ /* CRU_CLK_SEL26_CON */
+ CLK_UART_SRC_SEL_SHIFT = 0,
+ CLK_UART_SRC_SEL_MASK = 0x3 << CLK_UART_SRC_SEL_SHIFT,
+ CLK_UART_SRC_SEL_GPLL = 0,
+ CLK_UART_SRC_SEL_CPLL,
+ CLK_UART_SRC_SEL_AUPLL,
+ CLK_UART_SRC_SEL_OSC,
+
+ /* CRU_CLK_SEL27_CON */
+ CLK_UART1_SRC_SEL_SHIFT = 13,
+ CLK_UART1_SRC_SEL_MASK = 0x7 << CLK_UART1_SRC_SEL_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 5,
+ CLK_UART1_SRC_DIV_MASK = 0xff << CLK_UART1_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL30_CON */
+ CLK_GMAC0_125M_DIV_SHIFT = 10,
+ CLK_GMAC0_125M_DIV_MASK = 0x1f << CLK_GMAC0_125M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL31_CON */
+ CLK_GMAC1_125M_DIV_SHIFT = 0,
+ CLK_GMAC1_125M_DIV_MASK = 0x1f << CLK_GMAC1_125M_DIV_SHIFT,
+
+ /* CRU_CLK_SEL55_CON */
+ ACLK_BUS_ROOT_SEL_SHIFT = 9,
+ ACLK_BUS_ROOT_SEL_MASK = 1 << ACLK_BUS_ROOT_SEL_SHIFT,
+ ACLK_BUS_ROOT_SEL_GPLL = 0,
+ ACLK_BUS_ROOT_SEL_CPLL,
+ ACLK_BUS_ROOT_DIV_SHIFT = 4,
+ ACLK_BUS_ROOT_DIV_MASK = 0x1f << ACLK_BUS_ROOT_DIV_SHIFT,
+ PCLK_BUS_ROOT_SEL_SHIFT = 2,
+ PCLK_BUS_ROOT_SEL_MASK = 3 << PCLK_BUS_ROOT_SEL_SHIFT,
+ PCLK_BUS_ROOT_SEL_100M = 0,
+ PCLK_BUS_ROOT_SEL_50M,
+ PCLK_BUS_ROOT_SEL_OSC,
+ HCLK_BUS_ROOT_SEL_SHIFT = 0,
+ HCLK_BUS_ROOT_SEL_MASK = 3 << HCLK_BUS_ROOT_SEL_SHIFT,
+ HCLK_BUS_ROOT_SEL_200M = 0,
+ HCLK_BUS_ROOT_SEL_100M,
+ HCLK_BUS_ROOT_SEL_50M,
+ HCLK_BUS_ROOT_SEL_OSC,
+
+ /* CRU_CLK_SEL57_CON */
+ CLK_I2C8_SEL_SHIFT = 14,
+ CLK_I2C8_SEL_MASK = 3 << CLK_I2C8_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 12,
+ CLK_I2C7_SEL_MASK = 3 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C6_SEL_SHIFT = 10,
+ CLK_I2C6_SEL_MASK = 3 << CLK_I2C6_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 8,
+ CLK_I2C5_SEL_MASK = 3 << CLK_I2C5_SEL_SHIFT,
+ CLK_I2C4_SEL_SHIFT = 6,
+ CLK_I2C4_SEL_MASK = 3 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C3_SEL_SHIFT = 4,
+ CLK_I2C3_SEL_MASK = 3 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C2_SEL_SHIFT = 2,
+ CLK_I2C2_SEL_MASK = 3 << CLK_I2C2_SEL_SHIFT,
+ CLK_I2C1_SEL_SHIFT = 0,
+ CLK_I2C1_SEL_MASK = 3 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C_SEL_200M = 0,
+ CLK_I2C_SEL_100M,
+ CLK_I2C_SEL_50M,
+ CLK_I2C_SEL_OSC,
+
+ /* CRU_CLK_SEL58_CON */
+ CLK_SARADC_SEL_SHIFT = 12,
+ CLK_SARADC_SEL_MASK = 0x1 << CLK_SARADC_SEL_SHIFT,
+ CLK_SARADC_SEL_GPLL = 0,
+ CLK_SARADC_SEL_OSC,
+ CLK_SARADC_DIV_SHIFT = 4,
+ CLK_SARADC_DIV_MASK = 0xff << CLK_SARADC_DIV_SHIFT,
+ CLK_I2C9_SEL_SHIFT = 0,
+ CLK_I2C9_SEL_MASK = 3 << CLK_I2C9_SEL_SHIFT,
+
+ /* CRU_CLK_SEL59_CON */
+ CLK_TSADC_DIV_SHIFT = 0,
+ CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL60_CON */
+ CLK_UART_SEL_SHIFT = 8,
+ CLK_UART_SEL_MASK = 7 << CLK_UART_SEL_SHIFT,
+ CLK_UART_SEL_GPLL = 0,
+ CLK_UART_SEL_CPLL,
+ CLK_UART_SEL_AUPLL,
+ CLK_UART_SEL_OSC,
+ CLK_UART_SEL_FRAC0,
+ CLK_UART_SEL_FRAC1,
+ CLK_UART_SEL_FRAC2,
+ CLK_UART_DIV_SHIFT = 0,
+ CLK_UART_DIV_MASK = 0xff << CLK_UART_DIV_SHIFT,
+
+ /* CRU_CLK_SEL70_CON */
+ CLK_SPI0_SEL_SHIFT = 13,
+ CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
+ CLK_SPI_SEL_200M = 0,
+ CLK_SPI_SEL_100M,
+ CLK_SPI_SEL_50M,
+ CLK_SPI_SEL_OSC,
+
+ /* CRU_CLK_SEL71_CON */
+ CLK_PWM1_SEL_SHIFT = 8,
+ CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
+ CLK_SPI4_SEL_SHIFT = 6,
+ CLK_SPI4_SEL_MASK = 3 << CLK_SPI4_SEL_SHIFT,
+ CLK_SPI3_SEL_SHIFT = 4,
+ CLK_SPI3_SEL_MASK = 3 << CLK_SPI3_SEL_SHIFT,
+ CLK_SPI2_SEL_SHIFT = 2,
+ CLK_SPI2_SEL_MASK = 3 << CLK_SPI2_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 0,
+ CLK_SPI1_SEL_MASK = 3 << CLK_SPI1_SEL_SHIFT,
+ CLK_PWM_SEL_100M = 0,
+ CLK_PWM_SEL_50M,
+ CLK_PWM_SEL_OSC,
+
+ /* CRU_CLK_SEL72_CON */
+ DCLK_DECOM_SEL_SHIFT = 5,
+ DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT,
+ DCLK_DECOM_SEL_GPLL = 0,
+ DCLK_DECOM_SEL_SPLL,
+ DCLK_DECOM_DIV_SHIFT = 0,
+ DCLK_DECOM_DIV_MASK = 0x1f << DCLK_DECOM_DIV_SHIFT,
+
+ /* CRU_CLK_SEL74_CON */
+ CLK_PWM2_SEL_SHIFT = 6,
+ CLK_PWM2_SEL_MASK = 3 << CLK_PWM2_SEL_SHIFT,
+
+ /* CRU_CLK_SEL89_CON */
+ CCLK_EMMC_SEL_SHIFT = 14,
+ CCLK_EMMC_SEL_MASK = 3 << CCLK_EMMC_SEL_SHIFT,
+ CCLK_EMMC_SEL_GPLL = 0,
+ CCLK_EMMC_SEL_CPLL,
+ CCLK_EMMC_SEL_OSC,
+ CCLK_EMMC_DIV_SHIFT = 8,
+ CCLK_EMMC_DIV_MASK = 0x3f << CCLK_EMMC_DIV_SHIFT,
+ SCLK_FSPI_SEL_SHIFT = 6,
+ SCLK_FSPI_SEL_MASK = 3 << SCLK_FSPI_SEL_SHIFT,
+ SCLK_FSPI_SEL_GPLL = 0,
+ SCLK_FSPI_SEL_CPLL,
+ SCLK_FSPI_SEL_OSC,
+ SCLK_FSPI_DIV_SHIFT = 0,
+ SCLK_FSPI_DIV_MASK = 0x3f << SCLK_FSPI_DIV_SHIFT,
+
+ /* CRU_CLK_SEL90_CON */
+ BCLK_EMMC_SEL_SHIFT = 0,
+ BCLK_EMMC_SEL_MASK = 3 << BCLK_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_200M = 0,
+ BCLK_EMMC_SEL_100M,
+ BCLK_EMMC_SEL_50M,
+ BCLK_EMMC_SEL_OSC,
+
+ /* CRU_CLK_SEL104_CON */
+ CLK_GMAC1_PTP_SEL_SHIFT = 13,
+ CLK_GMAC1_PTP_SEL_MASK = 3 << CLK_GMAC1_PTP_SEL_SHIFT,
+ CLK_GMAC1_PTP_SEL_GPLL = 0,
+ CLK_GMAC1_PTP_SEL_CPLL,
+ CLK_GMAC1_PTP_SEL_REFIN,
+ CLK_GMAC1_PTP_DIV_SHIFT = 8,
+ CLK_GMAC1_PTP_DIV_MASK = 0x1f << CLK_GMAC1_PTP_DIV_SHIFT,
+ CCLK_SDIO_SRC_SEL_SHIFT = 6,
+ CCLK_SDIO_SRC_SEL_MASK = 3 << CCLK_SDIO_SRC_SEL_SHIFT,
+ CCLK_SDIO_SRC_SEL_GPLL = 0,
+ CCLK_SDIO_SRC_SEL_CPLL,
+ CCLK_SDIO_SRC_SEL_OSC,
+ CCLK_SDIO_SRC_DIV_SHIFT = 0,
+ CCLK_SDIO_SRC_DIV_MASK = 0x3f << CCLK_SDIO_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL105_CON */
+ CCLK_SDMMC0_SRC_SEL_SHIFT = 13,
+ CCLK_SDMMC0_SRC_SEL_MASK = 3 << CCLK_SDMMC0_SRC_SEL_SHIFT,
+ CCLK_SDMMC0_SRC_SEL_GPLL = 0,
+ CCLK_SDMMC0_SRC_SEL_CPLL,
+ CCLK_SDMMC0_SRC_SEL_OSC,
+ CCLK_SDMMC0_SRC_DIV_SHIFT = 7,
+ CCLK_SDMMC0_SRC_DIV_MASK = 0x3f << CCLK_SDMMC0_SRC_DIV_SHIFT,
+ CLK_GMAC0_PTP_SEL_SHIFT = 5,
+ CLK_GMAC0_PTP_SEL_MASK = 3 << CLK_GMAC0_PTP_SEL_SHIFT,
+ CLK_GMAC0_PTP_SEL_GPLL = 0,
+ CLK_GMAC0_PTP_SEL_CPLL,
+ CLK_GMAC0_PTP_SEL_REFIN,
+ CLK_GMAC0_PTP_DIV_SHIFT = 0,
+ CLK_GMAC0_PTP_DIV_MASK = 0x1f << CLK_GMAC0_PTP_DIV_SHIFT,
+
+ /* CRU_CLK_SEL123_CON */
+ DCLK_EBC_SEL_SHIFT = 12,
+ DCLK_EBC_SEL_MASK = 7 << DCLK_EBC_SEL_SHIFT,
+ DCLK_EBC_SEL_GPLL = 0,
+ DCLK_EBC_SEL_CPLL,
+ DCLK_EBC_SEL_VPLL,
+ DCLK_EBC_SEL_AUPLL,
+ DCLK_EBC_SEL_LPLL,
+ DCLK_EBC_SEL_FRAC_SRC,
+ DCLK_EBC_SEL_OSC,
+ DCLK_EBC_DIV_SHIFT = 3,
+ DCLK_EBC_DIV_MASK = 0x1ff << DCLK_EBC_DIV_SHIFT,
+ DCLK_EBC_FRAC_SRC_SEL_SHIFT = 0,
+ DCLK_EBC_FRAC_SRC_SEL_MASK = 7 << DCLK_EBC_FRAC_SRC_SEL_SHIFT,
+ DCLK_EBC_FRAC_SRC_SEL_GPLL = 0,
+ DCLK_EBC_FRAC_SRC_SEL_CPLL,
+ DCLK_EBC_FRAC_SRC_SEL_VPLL,
+ DCLK_EBC_FRAC_SRC_SEL_AUPLL,
+ DCLK_EBC_FRAC_SRC_SEL_OSC,
+
+ /* CRU_CLK_SEL144_CON */
+ PCLK_VOP_ROOT_SEL_SHIFT = 12,
+ PCLK_VOP_ROOT_SEL_MASK = 3 << PCLK_VOP_ROOT_SEL_SHIFT,
+ PCLK_VOP_ROOT_SEL_100M = 0,
+ PCLK_VOP_ROOT_SEL_50M,
+ PCLK_VOP_ROOT_SEL_OSC,
+ HCLK_VOP_ROOT_SEL_SHIFT = 10,
+ HCLK_VOP_ROOT_SEL_MASK = 3 << HCLK_VOP_ROOT_SEL_SHIFT,
+ HCLK_VOP_ROOT_SEL_200M = 0,
+ HCLK_VOP_ROOT_SEL_100M,
+ HCLK_VOP_ROOT_SEL_50M,
+ HCLK_VOP_ROOT_SEL_OSC,
+ ACLK_VOP_ROOT_SEL_SHIFT = 5,
+ ACLK_VOP_ROOT_SEL_MASK = 7 << ACLK_VOP_ROOT_SEL_SHIFT,
+ ACLK_VOP_ROOT_SEL_GPLL = 0,
+ ACLK_VOP_ROOT_SEL_CPLL,
+ ACLK_VOP_ROOT_SEL_AUPLL,
+ ACLK_VOP_ROOT_SEL_SPLL,
+ ACLK_VOP_ROOT_SEL_LPLL,
+ ACLK_VOP_ROOT_DIV_SHIFT = 0,
+ ACLK_VOP_ROOT_DIV_MASK = 0x1f << ACLK_VOP_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL145_CON */
+ DCLK0_VOP_SRC_SEL_SHIFT = 8,
+ DCLK0_VOP_SRC_SEL_MASK = 7 << DCLK0_VOP_SRC_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_GPLL = 0,
+ DCLK_VOP_SRC_SEL_CPLL,
+ DCLK_VOP_SRC_SEL_VPLL,
+ DCLK_VOP_SRC_SEL_BPLL,
+ DCLK_VOP_SRC_SEL_LPLL,
+ DCLK0_VOP_SRC_DIV_SHIFT = 0,
+ DCLK0_VOP_SRC_DIV_MASK = 0xff << DCLK0_VOP_SRC_DIV_SHIFT,
+
+ /* CRU_CLK_SEL147_CON */
+ DCLK2_VOP_SEL_SHIFT = 13,
+ DCLK2_VOP_SEL_MASK = 1 << DCLK2_VOP_SEL_SHIFT,
+ DCLK1_VOP_SEL_SHIFT = 12,
+ DCLK1_VOP_SEL_MASK = 1 << DCLK1_VOP_SEL_SHIFT,
+ DCLK0_VOP_SEL_SHIFT = 11,
+ DCLK0_VOP_SEL_MASK = 1 << DCLK0_VOP_SEL_SHIFT,
+
+ /* CRU_CLK_SEL149_CON */
+ ACLK_VO0_ROOT_SEL_SHIFT = 5,
+ ACLK_VO0_ROOT_SEL_MASK = 3 << ACLK_VO0_ROOT_SEL_SHIFT,
+ ACLK_VO0_ROOT_SEL_GPLL = 0,
+ ACLK_VO0_ROOT_SEL_CPLL,
+ ACLK_VO0_ROOT_SEL_LPLL,
+ ACLK_VO0_ROOT_SEL_BPLL,
+ ACLK_VO0_ROOT_DIV_SHIFT = 0,
+ ACLK_VO0_ROOT_DIV_MASK = 0x1f << ACLK_VO0_ROOT_DIV_SHIFT,
+
+ /* CRU_CLK_SEL151_CON */
+ CLK_DSIHOST0_SEL_SHIFT = 7,
+ CLK_DSIHOST0_SEL_MASK = 7 << CLK_DSIHOST0_SEL_SHIFT,
+ CLK_DSIHOST0_SEL_GPLL = 0,
+ CLK_DSIHOST0_SEL_CPLL,
+ CLK_DSIHOST0_SEL_SPLL,
+ CLK_DSIHOST0_SEL_VPLL,
+ CLK_DSIHOST0_SEL_BPLL,
+ CLK_DSIHOST0_SEL_LPLL,
+ CLK_DSIHOST0_DIV_SHIFT = 0,
+ CLK_DSIHOST0_DIV_MASK = 0x7f << CLK_DSIHOST0_DIV_SHIFT,
+
+ /* PMUCRU_CLK_SEL5_CON */
+ CLK_PMU1PWM_SEL_SHIFT = 2,
+ CLK_PMU1PWM_SEL_MASK = 3 << CLK_PMU1PWM_SEL_SHIFT,
+
+ /* PMUCRU_CLK_SEL6_CON */
+ CLK_I2C0_SEL_SHIFT = 7,
+ CLK_I2C0_SEL_MASK = 3 << CLK_I2C0_SEL_SHIFT,
+
+ /* PMUCRU_CLK_SEL8_CON */
+ CLK_UART1_SEL_SHIFT = 0,
+ CLK_UART1_SEL_MASK = 1 << CLK_UART1_SEL_SHIFT,
+ CLK_UART1_SEL_TOP = 0,
+ CLK_UART1_SEL_OSC,
+
+ /* LITCRU_CLK_SEL0_CON */
+ CLK_LITCORE_SEL_SHIFT = 12,
+ CLK_LITCORE_SEL_MASK = 3 << CLK_LITCORE_SEL_SHIFT,
+ CLK_LITCORE_SEL_LPLL = 0,
+ CLK_LITCORE_SEL_GPLL,
+ CLK_LITCORE_SEL_PVTPLL,
+ CLK_LITCORE_DIV_SHIFT = 7,
+ CLK_LITCORE_DIV_MASK = 0x1f << CLK_LITCORE_DIV_SHIFT,
+
+};
+#endif
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index 9e379cc2e3b..855bf318de7 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
new file mode 100644
index 00000000000..c11dd594a72
--- /dev/null
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -0,0 +1,2517 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ */
+
+#include <bitfield.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/cru_rk3576.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rockchip,rk3576-cru.h>
+#include <linux/delay.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = {
+ /* _mhz, _p, _m, _s, _k */
+ RK3588_PLL_RATE(1500000000, 2, 250, 1, 0),
+ RK3588_PLL_RATE(1200000000, 1, 100, 1, 0),
+ RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
+ RK3588_PLL_RATE(1150000000, 3, 575, 2, 0),
+ RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
+ RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
+ RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
+ RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
+ RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
+ RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
+ RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
+ RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
+ RK3588_PLL_RATE(742500000, 4, 495, 2, 0),
+ RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
+ RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
+ RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
+ RK3588_PLL_RATE(200000000, 3, 400, 4, 0),
+ RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3576_pll_clks[] = {
+ [BPLL] = PLL(pll_rk3588, PLL_BPLL, RK3576_PLL_CON(0),
+ RK3576_BPLL_MODE_CON0, 0, 15, 0,
+ rk3576_24m_pll_rates),
+ [LPLL] = PLL(pll_rk3588, PLL_LPLL, RK3576_LPLL_CON(16),
+ RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_24m_pll_rates),
+ [VPLL] = PLL(pll_rk3588, PLL_VPLL, RK3576_PLL_CON(88),
+ RK3576_LPLL_MODE_CON0, 4, 15, 0, rk3576_24m_pll_rates),
+ [AUPLL] = PLL(pll_rk3588, PLL_AUPLL, RK3576_PLL_CON(96),
+ RK3576_MODE_CON0, 6, 15, 0, rk3576_24m_pll_rates),
+ [CPLL] = PLL(pll_rk3588, PLL_CPLL, RK3576_PLL_CON(104),
+ RK3576_MODE_CON0, 8, 15, 0, rk3576_24m_pll_rates),
+ [GPLL] = PLL(pll_rk3588, PLL_GPLL, RK3576_PLL_CON(112),
+ RK3576_MODE_CON0, 2, 15, 0, rk3576_24m_pll_rates),
+ [PPLL] = PLL(pll_rk3588, PLL_PPLL, RK3576_PMU_PLL_CON(128),
+ RK3576_MODE_CON0, 10, 15, 0, rk3576_24m_pll_rates),
+};
+
+#ifdef CONFIG_SPL_BUILD
+#ifndef BITS_WITH_WMASK
+#define BITS_WITH_WMASK(bits, msk, shift) \
+ ((bits) << (shift)) | ((msk) << ((shift) + 16))
+#endif
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+#endif
+
+static ulong rk3576_bus_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, sel, div, rate;
+
+ switch (clk_id) {
+ case ACLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & ACLK_BUS_ROOT_SEL_MASK) >>
+ ACLK_BUS_ROOT_SEL_SHIFT;
+ div = (con & ACLK_BUS_ROOT_DIV_MASK) >>
+ ACLK_BUS_ROOT_DIV_SHIFT;
+ if (sel == ACLK_BUS_ROOT_SEL_CPLL)
+ rate = DIV_TO_RATE(priv->cpll_hz, div);
+ else
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
+ break;
+ case HCLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & HCLK_BUS_ROOT_SEL_MASK) >>
+ HCLK_BUS_ROOT_SEL_SHIFT;
+ if (sel == HCLK_BUS_ROOT_SEL_200M)
+ rate = 198 * MHz;
+ else if (sel == HCLK_BUS_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == HCLK_BUS_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case PCLK_BUS_ROOT:
+ con = readl(&cru->clksel_con[55]);
+ sel = (con & PCLK_BUS_ROOT_SEL_MASK) >>
+ PCLK_BUS_ROOT_SEL_SHIFT;
+ if (sel == PCLK_BUS_ROOT_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_BUS_ROOT_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3576_bus_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, src_clk_div;
+
+ switch (clk_id) {
+ case ACLK_BUS_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_BUS_ROOT_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_BUS_ROOT_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[55],
+ ACLK_BUS_ROOT_SEL_MASK,
+ src_clk << ACLK_BUS_ROOT_SEL_SHIFT);
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[55],
+ ACLK_BUS_ROOT_DIV_MASK |
+ ACLK_BUS_ROOT_SEL_MASK,
+ (src_clk <<
+ ACLK_BUS_ROOT_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_BUS_ROOT_DIV_SHIFT);
+ break;
+ case HCLK_BUS_ROOT:
+ if (rate >= 198 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = HCLK_BUS_ROOT_SEL_50M;
+ else
+ src_clk = HCLK_BUS_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[55],
+ HCLK_BUS_ROOT_SEL_MASK,
+ src_clk << HCLK_BUS_ROOT_SEL_SHIFT);
+ break;
+ case PCLK_BUS_ROOT:
+ if (rate >= 99 * MHz)
+ src_clk = PCLK_BUS_ROOT_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = PCLK_BUS_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_BUS_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[55],
+ PCLK_BUS_ROOT_SEL_MASK,
+ src_clk << PCLK_BUS_ROOT_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this center freq\n");
+ return -EINVAL;
+ }
+
+ return rk3576_bus_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_top_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, sel, div, rate, prate;
+
+ switch (clk_id) {
+ case ACLK_TOP:
+ con = readl(&cru->clksel_con[9]);
+ div = (con & ACLK_TOP_DIV_MASK) >>
+ ACLK_TOP_DIV_SHIFT;
+ sel = (con & ACLK_TOP_SEL_MASK) >>
+ ACLK_TOP_SEL_SHIFT;
+ if (sel == ACLK_TOP_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else if (sel == ACLK_TOP_SEL_AUPLL)
+ prate = priv->aupll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case ACLK_TOP_MID:
+ con = readl(&cru->clksel_con[10]);
+ div = (con & ACLK_TOP_MID_DIV_MASK) >>
+ ACLK_TOP_MID_DIV_SHIFT;
+ sel = (con & ACLK_TOP_MID_SEL_MASK) >>
+ ACLK_TOP_MID_SEL_SHIFT;
+ if (sel == ACLK_TOP_MID_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case PCLK_TOP_ROOT:
+ con = readl(&cru->clksel_con[8]);
+ sel = (con & PCLK_TOP_SEL_MASK) >> PCLK_TOP_SEL_SHIFT;
+ if (sel == PCLK_TOP_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == PCLK_TOP_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case HCLK_TOP:
+ con = readl(&cru->clksel_con[19]);
+ sel = (con & HCLK_TOP_SEL_MASK) >> HCLK_TOP_SEL_SHIFT;
+ if (sel == HCLK_TOP_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == HCLK_TOP_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == HCLK_TOP_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3576_top_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, src_clk_div;
+
+ switch (clk_id) {
+ case ACLK_TOP:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ assert(src_clk_div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[9],
+ ACLK_TOP_DIV_MASK |
+ ACLK_TOP_SEL_MASK,
+ (src_clk <<
+ ACLK_TOP_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_TOP_SEL_SHIFT);
+ break;
+ case ACLK_TOP_MID:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_MID_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_MID_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[10],
+ ACLK_TOP_MID_DIV_MASK |
+ ACLK_TOP_MID_SEL_MASK,
+ (ACLK_TOP_MID_SEL_GPLL <<
+ ACLK_TOP_MID_SEL_SHIFT) |
+ (src_clk_div - 1) << ACLK_TOP_MID_DIV_SHIFT);
+ break;
+ case PCLK_TOP_ROOT:
+ if (rate >= 99 * MHz)
+ src_clk = PCLK_TOP_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = PCLK_TOP_SEL_50M;
+ else
+ src_clk = PCLK_TOP_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[8],
+ PCLK_TOP_SEL_MASK,
+ src_clk << PCLK_TOP_SEL_SHIFT);
+ break;
+ case HCLK_TOP:
+ if (rate >= 198 * MHz)
+ src_clk = HCLK_TOP_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = HCLK_TOP_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = HCLK_TOP_SEL_50M;
+ else
+ src_clk = HCLK_TOP_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[19],
+ HCLK_TOP_SEL_MASK,
+ src_clk << HCLK_TOP_SEL_SHIFT);
+ break;
+ default:
+ printf("do not support this top freq\n");
+ return -EINVAL;
+ }
+
+ return rk3576_top_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_i2c_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ con = readl(&cru->pmuclksel_con[6]);
+ sel = (con & CLK_I2C0_SEL_MASK) >> CLK_I2C0_SEL_SHIFT;
+ break;
+ case CLK_I2C1:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C1_SEL_MASK) >> CLK_I2C1_SEL_SHIFT;
+ break;
+ case CLK_I2C2:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C2_SEL_MASK) >> CLK_I2C2_SEL_SHIFT;
+ break;
+ case CLK_I2C3:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C3_SEL_MASK) >> CLK_I2C3_SEL_SHIFT;
+ break;
+ case CLK_I2C4:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C4_SEL_MASK) >> CLK_I2C4_SEL_SHIFT;
+ break;
+ case CLK_I2C5:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C5_SEL_MASK) >> CLK_I2C5_SEL_SHIFT;
+ break;
+ case CLK_I2C6:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C6_SEL_MASK) >> CLK_I2C6_SEL_SHIFT;
+ break;
+ case CLK_I2C7:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C7_SEL_MASK) >> CLK_I2C7_SEL_SHIFT;
+ break;
+ case CLK_I2C8:
+ con = readl(&cru->clksel_con[57]);
+ sel = (con & CLK_I2C8_SEL_MASK) >> CLK_I2C8_SEL_SHIFT;
+ break;
+ case CLK_I2C9:
+ con = readl(&cru->clksel_con[58]);
+ sel = (con & CLK_I2C9_SEL_MASK) >> CLK_I2C9_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+ if (sel == CLK_I2C_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3576_i2c_set_clk(struct rk3576_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_I2C_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = CLK_I2C_SEL_100M;
+ if (rate >= 50 * MHz)
+ src_clk = CLK_I2C_SEL_50M;
+ else
+ src_clk = CLK_I2C_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ rk_clrsetreg(&cru->pmuclksel_con[6], CLK_I2C0_SEL_MASK,
+ src_clk << CLK_I2C0_SEL_SHIFT);
+ break;
+ case CLK_I2C1:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C1_SEL_MASK,
+ src_clk << CLK_I2C1_SEL_SHIFT);
+ break;
+ case CLK_I2C2:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C2_SEL_MASK,
+ src_clk << CLK_I2C2_SEL_SHIFT);
+ break;
+ case CLK_I2C3:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C3_SEL_MASK,
+ src_clk << CLK_I2C3_SEL_SHIFT);
+ break;
+ case CLK_I2C4:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C4_SEL_MASK,
+ src_clk << CLK_I2C4_SEL_SHIFT);
+ break;
+ case CLK_I2C5:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C5_SEL_MASK,
+ src_clk << CLK_I2C5_SEL_SHIFT);
+ break;
+ case CLK_I2C6:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C6_SEL_MASK,
+ src_clk << CLK_I2C6_SEL_SHIFT);
+ break;
+ case CLK_I2C7:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C7_SEL_MASK,
+ src_clk << CLK_I2C7_SEL_SHIFT);
+ break;
+ case CLK_I2C8:
+ rk_clrsetreg(&cru->clksel_con[57], CLK_I2C8_SEL_MASK,
+ src_clk << CLK_I2C8_SEL_SHIFT);
+ case CLK_I2C9:
+ rk_clrsetreg(&cru->clksel_con[58], CLK_I2C9_SEL_MASK,
+ src_clk << CLK_I2C9_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_spi_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ con = readl(&cru->clksel_con[70]);
+ sel = (con & CLK_SPI0_SEL_MASK) >> CLK_SPI0_SEL_SHIFT;
+ break;
+ case CLK_SPI1:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI1_SEL_MASK) >> CLK_SPI1_SEL_SHIFT;
+ break;
+ case CLK_SPI2:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI2_SEL_MASK) >> CLK_SPI2_SEL_SHIFT;
+ break;
+ case CLK_SPI3:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI3_SEL_MASK) >> CLK_SPI3_SEL_SHIFT;
+ break;
+ case CLK_SPI4:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_SPI4_SEL_MASK) >> CLK_SPI4_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_SPI_SEL_200M:
+ return 200 * MHz;
+ case CLK_SPI_SEL_100M:
+ return 100 * MHz;
+ case CLK_SPI_SEL_50M:
+ return 50 * MHz;
+ case CLK_SPI_SEL_OSC:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_spi_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 198 * MHz)
+ src_clk = CLK_SPI_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = CLK_SPI_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = CLK_SPI_SEL_50M;
+ else
+ src_clk = CLK_SPI_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ rk_clrsetreg(&cru->clksel_con[70],
+ CLK_SPI0_SEL_MASK,
+ src_clk << CLK_SPI0_SEL_SHIFT);
+ break;
+ case CLK_SPI1:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI1_SEL_MASK,
+ src_clk << CLK_SPI1_SEL_SHIFT);
+ break;
+ case CLK_SPI2:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI2_SEL_MASK,
+ src_clk << CLK_SPI2_SEL_SHIFT);
+ break;
+ case CLK_SPI3:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI3_SEL_MASK,
+ src_clk << CLK_SPI3_SEL_SHIFT);
+ break;
+ case CLK_SPI4:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_SPI4_SEL_MASK,
+ src_clk << CLK_SPI4_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_pwm_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ con = readl(&cru->clksel_con[71]);
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
+ break;
+ case CLK_PWM2:
+ con = readl(&cru->clksel_con[74]);
+ sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
+ break;
+ case CLK_PMU1PWM:
+ con = readl(&cru->pmuclksel_con[5]);
+ sel = (con & CLK_PMU1PWM_SEL_MASK) >> CLK_PMU1PWM_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (sel) {
+ case CLK_PWM_SEL_100M:
+ return 100 * MHz;
+ case CLK_PWM_SEL_50M:
+ return 50 * MHz;
+ case CLK_PWM_SEL_OSC:
+ return OSC_HZ;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_pwm_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk;
+
+ if (rate >= 99 * MHz)
+ src_clk = CLK_PWM_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = CLK_PWM_SEL_50M;
+ else
+ src_clk = CLK_PWM_SEL_OSC;
+
+ switch (clk_id) {
+ case CLK_PWM1:
+ rk_clrsetreg(&cru->clksel_con[71],
+ CLK_PWM1_SEL_MASK,
+ src_clk << CLK_PWM1_SEL_SHIFT);
+ break;
+ case CLK_PWM2:
+ rk_clrsetreg(&cru->clksel_con[74],
+ CLK_PWM2_SEL_MASK,
+ src_clk << CLK_PWM2_SEL_SHIFT);
+ break;
+ case CLK_PMU1PWM:
+ rk_clrsetreg(&cru->pmuclksel_con[5],
+ CLK_PMU1PWM_SEL_MASK,
+ src_clk << CLK_PMU1PWM_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_adc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, prate;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ con = readl(&cru->clksel_con[58]);
+ div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
+ sel = (con & CLK_SARADC_SEL_MASK) >>
+ CLK_SARADC_SEL_SHIFT;
+ if (sel == CLK_SARADC_SEL_OSC)
+ prate = OSC_HZ;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+ case CLK_TSADC:
+ con = readl(&cru->clksel_con[59]);
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_adc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk_div;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ if (!(OSC_HZ % rate)) {
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[58],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_OSC <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ } else {
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[59],
+ CLK_SARADC_SEL_MASK |
+ CLK_SARADC_DIV_MASK,
+ (CLK_SARADC_SEL_GPLL <<
+ CLK_SARADC_SEL_SHIFT) |
+ (src_clk_div - 1) <<
+ CLK_SARADC_DIV_SHIFT);
+ }
+ break;
+ case CLK_TSADC:
+ src_clk_div = DIV_ROUND_UP(OSC_HZ, rate);
+ assert(src_clk_div - 1 <= 255);
+ rk_clrsetreg(&cru->clksel_con[58],
+ CLK_TSADC_DIV_MASK,
+ (src_clk_div - 1) <<
+ CLK_TSADC_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rk3576_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_mmc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel, con, prate, div = 0;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case HCLK_SDIO:
+ con = readl(&cru->clksel_con[104]);
+ div = (con & CCLK_SDIO_SRC_DIV_MASK) >> CCLK_SDIO_SRC_DIV_SHIFT;
+ sel = (con & CCLK_SDIO_SRC_SEL_MASK) >>
+ CCLK_SDIO_SRC_SEL_SHIFT;
+ if (sel == CCLK_SDIO_SRC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDIO_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_SRC_SDMMC0:
+ case HCLK_SDMMC0:
+ con = readl(&cru->clksel_con[105]);
+ div = (con & CCLK_SDMMC0_SRC_DIV_MASK) >> CCLK_SDMMC0_SRC_DIV_SHIFT;
+ sel = (con & CCLK_SDMMC0_SRC_SEL_MASK) >>
+ CCLK_SDMMC0_SRC_SEL_SHIFT;
+ if (sel == CCLK_SDMMC0_SRC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDMMC0_SRC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case CCLK_SRC_EMMC:
+ case HCLK_EMMC:
+ con = readl(&cru->clksel_con[89]);
+ div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_EMMC_SEL_MASK) >>
+ CCLK_EMMC_SEL_SHIFT;
+ if (sel == CCLK_EMMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_EMMC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case BCLK_EMMC:
+ con = readl(&cru->clksel_con[90]);
+ sel = (con & BCLK_EMMC_SEL_MASK) >>
+ BCLK_EMMC_SEL_SHIFT;
+ if (sel == BCLK_EMMC_SEL_200M)
+ prate = 200 * MHz;
+ else if (sel == BCLK_EMMC_SEL_100M)
+ prate = 100 * MHz;
+ else if (sel == BCLK_EMMC_SEL_50M)
+ prate = 50 * MHz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_FSPI_X2:
+ con = readl(&cru->clksel_con[89]);
+ div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;
+ sel = (con & SCLK_FSPI_SEL_MASK) >>
+ SCLK_FSPI_SEL_SHIFT;
+ if (sel == SCLK_FSPI_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == SCLK_FSPI_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case SCLK_FSPI1_X2:
+ con = readl(&cru->clksel_con[106]);
+ div = (con & SCLK_FSPI_DIV_MASK) >> SCLK_FSPI_DIV_SHIFT;
+ sel = (con & SCLK_FSPI_SEL_MASK) >>
+ SCLK_FSPI_SEL_SHIFT;
+ if (sel == SCLK_FSPI_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == SCLK_FSPI_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+ return DIV_TO_RATE(prate, div);
+ case DCLK_DECOM:
+ con = readl(&cru->clksel_con[72]);
+ div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT;
+ sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT;
+ if (sel == DCLK_DECOM_SEL_SPLL)
+ prate = priv->spll_hz;
+ else
+ prate = priv->gpll_hz;
+ return DIV_TO_RATE(prate, div);
+
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_mmc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, div = 0;
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ if (!(OSC_HZ % rate)) {
+ src_clk = SCLK_FSPI_SEL_OSC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = SCLK_FSPI_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = SCLK_FSPI_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ case BCLK_EMMC:
+ if (rate >= 198 * MHz)
+ src_clk = BCLK_EMMC_SEL_200M;
+ else if (rate >= 99 * MHz)
+ src_clk = BCLK_EMMC_SEL_100M;
+ else if (rate >= 50 * MHz)
+ src_clk = BCLK_EMMC_SEL_50M;
+ else
+ src_clk = BCLK_EMMC_SEL_OSC;
+ break;
+ case DCLK_DECOM:
+ if (!(priv->spll_hz % rate)) {
+ src_clk = DCLK_DECOM_SEL_SPLL;
+ div = DIV_ROUND_UP(priv->spll_hz, rate);
+ } else {
+ src_clk = DCLK_DECOM_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ switch (clk_id) {
+ case CCLK_SRC_SDIO:
+ case HCLK_SDIO:
+ rk_clrsetreg(&cru->clksel_con[104],
+ CCLK_SDIO_SRC_SEL_MASK |
+ CCLK_SDIO_SRC_DIV_MASK,
+ (src_clk << CCLK_SDIO_SRC_SEL_SHIFT) |
+ (div - 1) << CCLK_SDIO_SRC_DIV_SHIFT);
+ break;
+ case CCLK_SRC_SDMMC0:
+ case HCLK_SDMMC0:
+ rk_clrsetreg(&cru->clksel_con[105],
+ CCLK_SDMMC0_SRC_SEL_MASK |
+ CCLK_SDMMC0_SRC_DIV_MASK,
+ (src_clk << CCLK_SDMMC0_SRC_SEL_SHIFT) |
+ (div - 1) << CCLK_SDMMC0_SRC_DIV_SHIFT);
+ break;
+ case CCLK_SRC_EMMC:
+ case HCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[89],
+ CCLK_EMMC_DIV_MASK |
+ CCLK_EMMC_SEL_MASK,
+ (src_clk << CCLK_EMMC_SEL_SHIFT) |
+ (div - 1) << CCLK_EMMC_DIV_SHIFT);
+ break;
+ case SCLK_FSPI_X2:
+ rk_clrsetreg(&cru->clksel_con[89],
+ SCLK_FSPI_DIV_MASK |
+ SCLK_FSPI_SEL_MASK,
+ (src_clk << SCLK_FSPI_SEL_SHIFT) |
+ (div - 1) << SCLK_FSPI_DIV_SHIFT);
+ break;
+ case SCLK_FSPI1_X2:
+ rk_clrsetreg(&cru->clksel_con[106],
+ SCLK_FSPI_DIV_MASK |
+ SCLK_FSPI_SEL_MASK,
+ (src_clk << SCLK_FSPI_SEL_SHIFT) |
+ (div - 1) << SCLK_FSPI_DIV_SHIFT);
+ break;
+ case BCLK_EMMC:
+ rk_clrsetreg(&cru->clksel_con[90],
+ BCLK_EMMC_SEL_MASK,
+ src_clk << BCLK_EMMC_SEL_SHIFT);
+ break;
+ case DCLK_DECOM:
+ rk_clrsetreg(&cru->clksel_con[72],
+ DCLK_DECOM_DIV_MASK |
+ DCLK_DECOM_SEL_MASK,
+ (src_clk << DCLK_DECOM_SEL_SHIFT) |
+ (div - 1) << DCLK_DECOM_DIV_SHIFT);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_mmc_get_clk(priv, clk_id);
+}
+
+#ifndef CONFIG_SPL_BUILD
+
+static ulong rk3576_aclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent = 0;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ con = readl(&cru->clksel_con[144]);
+ div = (con & ACLK_VOP_ROOT_DIV_MASK) >> ACLK_VOP_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VOP_ROOT_SEL_MASK) >> ACLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VOP_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_SPLL)
+ parent = priv->spll_hz;
+ else if (sel == ACLK_VOP_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ return DIV_TO_RATE(parent, div);
+ case ACLK_VO0_ROOT:
+ con = readl(&cru->clksel_con[149]);
+ div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VO0_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == ACLK_VO0_ROOT_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ return DIV_TO_RATE(parent, div);
+ case ACLK_VO1_ROOT:
+ con = readl(&cru->clksel_con[158]);
+ div = (con & ACLK_VO0_ROOT_DIV_MASK) >> ACLK_VO0_ROOT_DIV_SHIFT;
+ sel = (con & ACLK_VO0_ROOT_SEL_MASK) >> ACLK_VO0_ROOT_SEL_SHIFT;
+ if (sel == ACLK_VO0_ROOT_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == ACLK_VO0_ROOT_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == ACLK_VO0_ROOT_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ return DIV_TO_RATE(parent, div);
+ case HCLK_VOP_ROOT:
+ con = readl(&cru->clksel_con[144]);
+ sel = (con & HCLK_VOP_ROOT_SEL_MASK) >> HCLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == HCLK_VOP_ROOT_SEL_200M)
+ return 200 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_100M)
+ return 100 * MHz;
+ else if (sel == HCLK_VOP_ROOT_SEL_50M)
+ return 50 * MHz;
+ else
+ return OSC_HZ;
+ case PCLK_VOP_ROOT:
+ con = readl(&cru->clksel_con[144]);
+ sel = (con & PCLK_VOP_ROOT_SEL_MASK) >> PCLK_VOP_ROOT_SEL_SHIFT;
+ if (sel == PCLK_VOP_ROOT_SEL_100M)
+ return 100 * MHz;
+ else if (sel == PCLK_VOP_ROOT_SEL_50M)
+ return 50 * MHz;
+ else
+ return OSC_HZ;
+
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_aclk_vop_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int src_clk, div;
+
+ switch (clk_id) {
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ if (rate == 700 * MHz) {
+ src_clk = ACLK_VOP_ROOT_SEL_SPLL;
+ div = 1;
+ } else if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VOP_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VOP_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[144],
+ ACLK_VOP_ROOT_DIV_MASK |
+ ACLK_VOP_ROOT_SEL_MASK,
+ (src_clk << ACLK_VOP_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VOP_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_VO0_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VO0_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VO0_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[149],
+ ACLK_VO0_ROOT_DIV_MASK |
+ ACLK_VO0_ROOT_SEL_MASK,
+ (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);
+ break;
+ case ACLK_VO1_ROOT:
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_VO0_ROOT_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_VO0_ROOT_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+ rk_clrsetreg(&cru->clksel_con[158],
+ ACLK_VO0_ROOT_DIV_MASK |
+ ACLK_VO0_ROOT_SEL_MASK,
+ (src_clk << ACLK_VO0_ROOT_SEL_SHIFT) |
+ (div - 1) << ACLK_VO0_ROOT_DIV_SHIFT);
+ break;
+ case HCLK_VOP_ROOT:
+ if (rate == 200 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_200M;
+ else if (rate == 100 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = HCLK_VOP_ROOT_SEL_50M;
+ else
+ src_clk = HCLK_VOP_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[144],
+ HCLK_VOP_ROOT_SEL_MASK,
+ src_clk << HCLK_VOP_ROOT_SEL_SHIFT);
+ break;
+ case PCLK_VOP_ROOT:
+ if (rate == 100 * MHz)
+ src_clk = PCLK_VOP_ROOT_SEL_100M;
+ else if (rate == 50 * MHz)
+ src_clk = PCLK_VOP_ROOT_SEL_50M;
+ else
+ src_clk = PCLK_VOP_ROOT_SEL_OSC;
+ rk_clrsetreg(&cru->clksel_con[144],
+ PCLK_VOP_ROOT_SEL_MASK,
+ src_clk << PCLK_VOP_ROOT_SEL_SHIFT);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_aclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_dclk_vop_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ con = readl(&cru->clksel_con[145]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ con = readl(&cru->clksel_con[146]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ con = readl(&cru->clksel_con[147]);
+ div = (con & DCLK0_VOP_SRC_DIV_MASK) >> DCLK0_VOP_SRC_DIV_SHIFT;
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_VOP_SRC_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ else if (sel == DCLK_VOP_SRC_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == DCLK_VOP_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else
+ parent = priv->cpll_hz;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+#define RK3576_VOP_PLL_LIMIT_FREQ 600000000
+
+static ulong rk3576_dclk_vop_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, conid, con, sel, div, best_div = 0, best_sel = 0;
+ u32 mask, div_shift, sel_shift;
+
+ switch (clk_id) {
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ conid = 145;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ conid = 146;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ conid = 147;
+ con = readl(&cru->clksel_con[conid]);
+ sel = (con & DCLK0_VOP_SRC_SEL_MASK) >> DCLK0_VOP_SRC_SEL_SHIFT;
+ mask = DCLK0_VOP_SRC_SEL_MASK | DCLK0_VOP_SRC_DIV_MASK;
+ div_shift = DCLK0_VOP_SRC_DIV_SHIFT;
+ sel_shift = DCLK0_VOP_SRC_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SRC_SEL_VPLL) {
+ pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_VPLL << sel_shift |
+ ((div - 1) << div_shift));
+ } else {
+ div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ, rate);
+ if (div % 2)
+ div = div + 1;
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_VPLL << sel_shift |
+ ((div - 1) << div_shift));
+ rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL, div * rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ }
+ } else {
+ for (i = 0; i <= DCLK_VOP_SRC_SEL_LPLL; i++) {
+ switch (i) {
+ case DCLK_VOP_SRC_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case DCLK_VOP_SRC_SEL_BPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_VOP_SRC_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_VOP_SRC_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ best_sel << sel_shift |
+ (best_div - 1) << div_shift);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+ }
+
+ return rk3576_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_clk_csihost_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case CLK_DSIHOST0:
+ con = readl(&cru->clksel_con[151]);
+ div = (con & CLK_DSIHOST0_DIV_MASK) >> CLK_DSIHOST0_DIV_SHIFT;
+ sel = (con & CLK_DSIHOST0_SEL_MASK) >> CLK_DSIHOST0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == CLK_DSIHOST0_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == CLK_DSIHOST0_SEL_BPLL)
+ parent = priv->bpll_hz / 4;
+ else if (sel == CLK_DSIHOST0_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == CLK_DSIHOST0_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == CLK_DSIHOST0_SEL_SPLL)
+ parent = priv->spll_hz;
+ else
+ parent = priv->cpll_hz;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3576_clk_csihost_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, con, div, best_div = 0, best_sel = 0;
+ u32 mask, div_shift, sel_shift;
+
+ switch (clk_id) {
+ case CLK_DSIHOST0:
+ con = 151;
+ mask = CLK_DSIHOST0_SEL_MASK | CLK_DSIHOST0_DIV_MASK;
+ div_shift = CLK_DSIHOST0_DIV_SHIFT;
+ sel_shift = CLK_DSIHOST0_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+ for (i = 0; i <= CLK_DSIHOST0_SEL_LPLL; i++) {
+ switch (i) {
+ case CLK_DSIHOST0_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case CLK_DSIHOST0_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case CLK_DSIHOST0_SEL_BPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ case CLK_DSIHOST0_SEL_SPLL:
+ pll_rate = priv->spll_hz;
+ break;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[con],
+ mask,
+ best_sel << sel_shift |
+ (best_div - 1) << div_shift);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+
+ return rk3576_clk_csihost_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_dclk_ebc_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+ unsigned long m = 0, n = 0;
+
+ switch (clk_id) {
+ case DCLK_EBC:
+ con = readl(&cru->clksel_con[123]);
+ div = (con & DCLK_EBC_DIV_MASK) >> DCLK_EBC_DIV_SHIFT;
+ sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
+ if (sel == DCLK_EBC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == DCLK_EBC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_EBC_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else if (sel == DCLK_EBC_SEL_LPLL)
+ parent = priv->lpll_hz / 2;
+ else if (sel == DCLK_EBC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == DCLK_EBC_SEL_FRAC_SRC)
+ parent = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC);
+ else
+ parent = OSC_HZ;
+ return DIV_TO_RATE(parent, div);
+ case DCLK_EBC_FRAC_SRC:
+ con = readl(&cru->clksel_con[123]);
+ div = readl(&cru->clksel_con[122]);
+ sel = (con & DCLK_EBC_FRAC_SRC_SEL_MASK) >> DCLK_EBC_FRAC_SRC_SEL_SHIFT;
+ if (sel == DCLK_EBC_FRAC_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_VPLL)
+ parent = priv->vpll_hz;
+ else if (sel == DCLK_EBC_FRAC_SRC_SEL_AUPLL)
+ parent = priv->aupll_hz;
+ else
+ parent = OSC_HZ;
+
+ n = div & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = div & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return parent * n / m;
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_dclk_ebc_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ ulong pll_rate, now, best_rate = 0;
+ u32 i, con, sel, div, best_div = 0, best_sel = 0;
+ unsigned long m = 0, n = 0, val;
+
+ switch (clk_id) {
+ case DCLK_EBC:
+ con = readl(&cru->clksel_con[123]);
+ sel = (con & DCLK_EBC_SEL_MASK) >> DCLK_EBC_SEL_SHIFT;
+ if (sel == DCLK_EBC_SEL_VPLL) {
+ pll_rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ if (pll_rate >= RK3576_VOP_PLL_LIMIT_FREQ &&
+ pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ } else {
+ div = DIV_ROUND_UP(RK3576_VOP_PLL_LIMIT_FREQ,
+ rate);
+ if (div % 2)
+ div = div + 1;
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ rockchip_pll_set_rate(&rk3576_pll_clks[VPLL],
+ priv->cru,
+ VPLL, div * rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru,
+ VPLL);
+ }
+ } else if (sel == DCLK_EBC_SEL_FRAC_SRC) {
+ rk3576_dclk_ebc_set_clk(priv, DCLK_EBC_FRAC_SRC, rate);
+ div = rk3576_dclk_ebc_get_clk(priv, DCLK_EBC_FRAC_SRC) / rate;
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK,
+ (div - 1) << DCLK_EBC_DIV_SHIFT);
+ } else {
+ for (i = 0; i <= DCLK_EBC_SEL_LPLL; i++) {
+ switch (i) {
+ case DCLK_EBC_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_EBC_SEL_CPLL:
+ pll_rate = priv->cpll_hz;
+ break;
+ case DCLK_EBC_SEL_VPLL:
+ pll_rate = 0;
+ break;
+ case DCLK_EBC_SEL_AUPLL:
+ pll_rate = priv->aupll_hz;
+ break;
+ case DCLK_EBC_SEL_LPLL:
+ pll_rate = 0;
+ break;
+ default:
+ printf("not support ebc pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ }
+
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_DIV_MASK |
+ DCLK_EBC_SEL_MASK,
+ best_sel <<
+ DCLK_EBC_SEL_SHIFT |
+ (best_div - 1) <<
+ DCLK_EBC_DIV_SHIFT);
+ } else {
+ printf("do not support this vop freq %lu\n",
+ rate);
+ return -EINVAL;
+ }
+ }
+ break;
+ case DCLK_EBC_FRAC_SRC:
+ sel = DCLK_EBC_FRAC_SRC_SEL_GPLL;
+ div = 1;
+ rational_best_approximation(rate, priv->gpll_hz,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &m, &n);
+
+ if (m < 4 && m != 0) {
+ if (n % 2 == 0)
+ val = 1;
+ else
+ val = DIV_ROUND_UP(4, m);
+
+ n *= val;
+ m *= val;
+ if (n > 0xffff)
+ n = 0xffff;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[123],
+ DCLK_EBC_FRAC_SRC_SEL_MASK,
+ (sel << DCLK_EBC_FRAC_SRC_SEL_SHIFT));
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[122]);
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+ return rk3576_dclk_ebc_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_gmac_get_clk(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, div, src, p_rate;
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ con = readl(&cru->clksel_con[105]);
+ div = (con & CLK_GMAC0_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
+ src = (con & CLK_GMAC0_PTP_SEL_MASK) >> CLK_GMAC0_PTP_SEL_SHIFT;
+ if (src == CLK_GMAC0_PTP_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_GMAC0_PTP_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = GMAC0_PTP_REFCLK_IN;
+ return DIV_TO_RATE(p_rate, div);
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF:
+ con = readl(&cru->clksel_con[104]);
+ div = (con & CLK_GMAC1_PTP_DIV_MASK) >> CLK_GMAC0_PTP_DIV_SHIFT;
+ src = (con & CLK_GMAC1_PTP_SEL_MASK) >> CLK_GMAC1_PTP_SEL_SHIFT;
+ if (src == CLK_GMAC1_PTP_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_GMAC1_PTP_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else
+ p_rate = GMAC1_PTP_REFCLK_IN;
+ return DIV_TO_RATE(p_rate, div);
+ case CLK_GMAC0_125M_SRC:
+ con = readl(&cru->clksel_con[30]);
+ div = (con & CLK_GMAC0_125M_DIV_MASK) >> CLK_GMAC0_125M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ case CLK_GMAC1_125M_SRC:
+ con = readl(&cru->clksel_con[31]);
+ div = (con & CLK_GMAC1_125M_DIV_MASK) >> CLK_GMAC1_125M_DIV_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ default:
+ return -ENOENT;
+ }
+}
+
+static ulong rk3576_gmac_set_clk(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ int div, src;
+
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+
+ switch (clk_id) {
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ if (rate == GMAC0_PTP_REFCLK_IN) {
+ src = CLK_GMAC0_PTP_SEL_REFIN;
+ div = 1;
+ } else if (!(priv->gpll_hz % rate)) {
+ src = CLK_GMAC0_PTP_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_GMAC0_PTP_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[105],
+ CLK_GMAC0_PTP_DIV_MASK | CLK_GMAC0_PTP_SEL_MASK,
+ src << CLK_GMAC0_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC0_PTP_DIV_SHIFT);
+ break;
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF:
+ if (rate == GMAC1_PTP_REFCLK_IN) {
+ src = CLK_GMAC1_PTP_SEL_REFIN;
+ div = 1;
+ } else if (!(priv->gpll_hz % rate)) {
+ src = CLK_GMAC1_PTP_SEL_GPLL;
+ div = priv->gpll_hz / rate;
+ } else {
+ src = CLK_GMAC1_PTP_SEL_CPLL;
+ div = priv->cpll_hz / rate;
+ }
+ rk_clrsetreg(&cru->clksel_con[104],
+ CLK_GMAC1_PTP_DIV_MASK | CLK_GMAC1_PTP_SEL_MASK,
+ src << CLK_GMAC1_PTP_SEL_SHIFT |
+ (div - 1) << CLK_GMAC1_PTP_DIV_SHIFT);
+ break;
+
+ case CLK_GMAC0_125M_SRC:
+ rk_clrsetreg(&cru->clksel_con[30],
+ CLK_GMAC0_125M_DIV_MASK,
+ (div - 1) << CLK_GMAC0_125M_DIV_SHIFT);
+ break;
+ case CLK_GMAC1_125M_SRC:
+ rk_clrsetreg(&cru->clksel_con[31],
+ CLK_GMAC1_125M_DIV_MASK,
+ (div - 1) << CLK_GMAC1_125M_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3576_gmac_get_clk(priv, clk_id);
+}
+
+static ulong rk3576_uart_frac_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, con, fracdiv, p_src, p_rate;
+ unsigned long m, n;
+
+ switch (clk_id) {
+ case CLK_UART_FRAC_0:
+ reg = 21;
+ break;
+ case CLK_UART_FRAC_1:
+ reg = 23;
+ break;
+ case CLK_UART_FRAC_2:
+ reg = 25;
+ break;
+ default:
+ return -ENOENT;
+ }
+ con = readl(&cru->clksel_con[reg + 1]);
+ p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
+ if (p_src == CLK_UART_SRC_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (p_src == CLK_UART_SRC_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else if (p_src == CLK_UART_SRC_SEL_AUPLL)
+ p_rate = priv->aupll_hz;
+ else
+ p_rate = OSC_HZ;
+
+ fracdiv = readl(&cru->clksel_con[reg]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return p_rate * n / m;
+}
+
+static ulong rk3576_uart_frac_set_rate(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, clk_src, p_rate;
+ unsigned long m = 0, n = 0, val;
+
+ if (priv->cpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_CPLL;
+ p_rate = priv->cpll_hz;
+ } else if (rate == OSC_HZ) {
+ clk_src = CLK_UART_SRC_SEL_OSC;
+ p_rate = OSC_HZ;
+ } else {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ p_rate = priv->cpll_hz;
+ }
+
+ rational_best_approximation(rate, p_rate, GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0), &m, &n);
+
+ if (m < 4 && m != 0) {
+ if (n % 2 == 0)
+ val = 1;
+ else
+ val = DIV_ROUND_UP(4, m);
+
+ n *= val;
+ m *= val;
+ if (n > 0xffff)
+ n = 0xffff;
+ }
+
+ switch (clk_id) {
+ case CLK_UART_FRAC_0:
+ reg = 21;
+ break;
+ case CLK_UART_FRAC_1:
+ reg = 23;
+ break;
+ case CLK_UART_FRAC_2:
+ reg = 25;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[reg + 1],
+ CLK_UART_SRC_SEL_MASK,
+ (clk_src << CLK_UART_SRC_SEL_SHIFT));
+ if (m && n) {
+ val = m << CLK_UART_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, &cru->clksel_con[reg]);
+ }
+
+ return rk3576_uart_frac_get_rate(priv, clk_id);
+}
+
+static ulong rk3576_uart_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 con, div, src, p_rate;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ con = readl(&cru->clksel_con[60]);
+ break;
+ case SCLK_UART1:
+ con = readl(&cru->pmuclksel_con[8]);
+ src = (con & CLK_UART1_SEL_MASK) >> CLK_UART1_SEL_SHIFT;
+ if (src == CLK_UART1_SEL_OSC)
+ return OSC_HZ;
+ con = readl(&cru->clksel_con[27]);
+ break;
+ case SCLK_UART2:
+ con = readl(&cru->clksel_con[61]);
+ break;
+ case SCLK_UART3:
+ con = readl(&cru->clksel_con[62]);
+ break;
+ case SCLK_UART4:
+ con = readl(&cru->clksel_con[63]);
+ break;
+ case SCLK_UART5:
+ con = readl(&cru->clksel_con[64]);
+ break;
+ case SCLK_UART6:
+ con = readl(&cru->clksel_con[65]);
+ break;
+ case SCLK_UART7:
+ con = readl(&cru->clksel_con[66]);
+ break;
+ case SCLK_UART8:
+ con = readl(&cru->clksel_con[67]);
+ break;
+ case SCLK_UART9:
+ con = readl(&cru->clksel_con[68]);
+ break;
+ case SCLK_UART10:
+ con = readl(&cru->clksel_con[69]);
+ break;
+ case SCLK_UART11:
+ con = readl(&cru->clksel_con[70]);
+ break;
+ default:
+ return -ENOENT;
+ }
+ if (clk_id == SCLK_UART1) {
+ src = (con & CLK_UART1_SRC_SEL_SHIFT) >> CLK_UART1_SRC_SEL_SHIFT;
+ div = (con & CLK_UART1_SRC_DIV_MASK) >> CLK_UART1_SRC_DIV_SHIFT;
+ } else {
+ src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
+ div = (con & CLK_UART_DIV_MASK) >> CLK_UART_DIV_SHIFT;
+ }
+ if (src == CLK_UART_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else if (src == CLK_UART_SEL_CPLL)
+ p_rate = priv->cpll_hz;
+ else if (src == CLK_UART_SEL_AUPLL)
+ p_rate = priv->aupll_hz;
+ else if (src == CLK_UART_SEL_FRAC0)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0);
+ else if (src == CLK_UART_SEL_FRAC1)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1);
+ else if (src == CLK_UART_SEL_FRAC2)
+ p_rate = rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2);
+ else
+ p_rate = OSC_HZ;
+
+ return DIV_TO_RATE(p_rate, div);
+}
+
+static ulong rk3576_uart_set_rate(struct rk3576_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 reg, clk_src = 0, div = 0;
+
+ if (!(priv->gpll_hz % rate)) {
+ clk_src = CLK_UART_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (!(priv->cpll_hz % rate)) {
+ clk_src = CLK_UART_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC0;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_0), rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC1;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_1), rate);
+ } else if (!(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2) % rate)) {
+ clk_src = CLK_UART_SEL_FRAC2;
+ div = DIV_ROUND_UP(rk3576_uart_frac_get_rate(priv, CLK_UART_FRAC_2), rate);
+ } else if (!(OSC_HZ % rate)) {
+ clk_src = CLK_UART_SEL_OSC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ reg = 60;
+ break;
+ case SCLK_UART1:
+ if (rate == OSC_HZ) {
+ rk_clrsetreg(&cru->pmuclksel_con[8],
+ CLK_UART1_SEL_MASK,
+ CLK_UART1_SEL_OSC << CLK_UART1_SEL_SHIFT);
+ return 0;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[27],
+ CLK_UART1_SRC_SEL_MASK | CLK_UART1_SRC_DIV_MASK,
+ (clk_src << CLK_UART1_SRC_SEL_SHIFT) |
+ ((div - 1) << CLK_UART1_SRC_DIV_SHIFT));
+ rk_clrsetreg(&cru->pmuclksel_con[8],
+ CLK_UART1_SEL_MASK,
+ CLK_UART1_SEL_TOP << CLK_UART1_SEL_SHIFT);
+ return 0;
+ case SCLK_UART2:
+ reg = 61;
+ break;
+ case SCLK_UART3:
+ reg = 62;
+ break;
+ case SCLK_UART4:
+ reg = 63;
+ break;
+ case SCLK_UART5:
+ reg = 64;
+ break;
+ case SCLK_UART6:
+ reg = 65;
+ break;
+ case SCLK_UART7:
+ reg = 66;
+ break;
+ case SCLK_UART8:
+ reg = 67;
+ break;
+ case SCLK_UART9:
+ reg = 68;
+ break;
+ case SCLK_UART10:
+ reg = 69;
+ break;
+ case SCLK_UART11:
+ reg = 70;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[reg],
+ CLK_UART_SEL_MASK |
+ CLK_UART_DIV_MASK,
+ (clk_src << CLK_UART_SEL_SHIFT) |
+ ((div - 1) << CLK_UART_DIV_SHIFT));
+
+ return rk3576_uart_get_rate(priv, clk_id);
+}
+#endif
+
+static ulong rk3576_ufs_ref_get_rate(struct rk3576_clk_priv *priv, ulong clk_id)
+{
+ struct rk3576_cru *cru = priv->cru;
+ u32 src, div;
+
+ src = readl(&cru->pmuclksel_con[3]) & 0x3;
+ div = readl(&cru->pmuclksel_con[1]) & 0xff;
+ if (src == 0)
+ return OSC_HZ;
+ else if (src == 2)
+ return priv->ppll_hz / (div + 1);
+ else
+ return 26000000;
+}
+
+static ulong rk3576_clk_get_rate(struct clk *clk)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_LPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[LPLL], priv->cru,
+ LPLL);
+ priv->lpll_hz = rate;
+ break;
+ case PLL_BPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[BPLL], priv->cru,
+ BPLL);
+ priv->bpll_hz = rate;
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_VPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL], priv->cru,
+ VPLL);
+ break;
+ case PLL_AUPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL], priv->cru,
+ AUPLL);
+ break;
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL], priv->cru,
+ PPLL) * 2;
+ break;
+ case ACLK_BUS_ROOT:
+ case HCLK_BUS_ROOT:
+ case PCLK_BUS_ROOT:
+ rate = rk3576_bus_get_clk(priv, clk->id);
+ break;
+ case ACLK_TOP:
+ case HCLK_TOP:
+ case PCLK_TOP_ROOT:
+ case ACLK_TOP_MID:
+ rate = rk3576_top_get_clk(priv, clk->id);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ case CLK_I2C9:
+ rate = rk3576_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ rate = rk3576_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PMU1PWM:
+ rate = rk3576_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ rate = rk3576_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case BCLK_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case DCLK_DECOM:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ rate = rk3576_mmc_get_clk(priv, clk->id);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT0:
+ rate = OSC_HZ;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VO0_ROOT:
+ case ACLK_VO1_ROOT:
+ case HCLK_VOP_ROOT:
+ case PCLK_VOP_ROOT:
+ rate = rk3576_aclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ rate = rk3576_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC0_125M_SRC:
+ case CLK_GMAC1_125M_SRC:
+ rate = rk3576_gmac_get_clk(priv, clk->id);
+ break;
+ case CLK_UART_FRAC_0:
+ case CLK_UART_FRAC_1:
+ case CLK_UART_FRAC_2:
+ rate = rk3576_uart_frac_get_rate(priv, clk->id);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ case SCLK_UART10:
+ case SCLK_UART11:
+ rate = rk3576_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_DSIHOST0:
+ rate = rk3576_clk_csihost_get_clk(priv, clk->id);
+ break;
+ case DCLK_EBC:
+ case DCLK_EBC_FRAC_SRC:
+ rate = rk3576_dclk_ebc_get_clk(priv, clk->id);
+ break;
+#endif
+ case CLK_REF_UFS_CLKOUT:
+ case CLK_REF_OSC_MPHY:
+ rate = rk3576_ufs_ref_get_rate(priv, clk->id);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3576_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->ppll_hz) {
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL);
+ }
+ if (!priv->aupll_hz) {
+ priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL],
+ priv->cru, AUPLL);
+ }
+
+ switch (clk->id) {
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_VPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[VPLL], priv->cru,
+ VPLL, rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[VPLL],
+ priv->cru, VPLL);
+ break;
+ case PLL_AUPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[AUPLL], priv->cru,
+ AUPLL, rate);
+ priv->aupll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[AUPLL],
+ priv->cru, AUPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3576_pll_clks[PPLL],
+ priv->cru, PPLL) * 2;
+ break;
+ case ACLK_BUS_ROOT:
+ case HCLK_BUS_ROOT:
+ case PCLK_BUS_ROOT:
+ ret = rk3576_bus_set_clk(priv, clk->id, rate);
+ break;
+ case ACLK_TOP:
+ case HCLK_TOP:
+ case PCLK_TOP_ROOT:
+ case ACLK_TOP_MID:
+ ret = rk3576_top_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ case CLK_I2C8:
+ case CLK_I2C9:
+ ret = rk3576_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ case CLK_SPI3:
+ case CLK_SPI4:
+ ret = rk3576_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM1:
+ case CLK_PWM2:
+ case CLK_PMU1PWM:
+ ret = rk3576_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ ret = rk3576_adc_set_clk(priv, clk->id, rate);
+ break;
+ case CCLK_SRC_SDIO:
+ case CCLK_SRC_SDMMC0:
+ case CCLK_SRC_EMMC:
+ case BCLK_EMMC:
+ case SCLK_FSPI_X2:
+ case SCLK_FSPI1_X2:
+ case DCLK_DECOM:
+ case HCLK_SDMMC0:
+ case HCLK_EMMC:
+ case HCLK_SDIO:
+ ret = rk3576_mmc_set_clk(priv, clk->id, rate);
+ break;
+ case TCLK_EMMC:
+ case TCLK_WDT0:
+ ret = OSC_HZ;
+ break;
+
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ case CLK_AUDIO_FRAC_0:
+ case CLK_AUDIO_FRAC_1:
+ case CLK_AUDIO_FRAC_0_SRC:
+ case CLK_AUDIO_FRAC_1_SRC:
+ case CLK_CPLL_DIV2:
+ case CLK_CPLL_DIV4:
+ case CLK_CPLL_DIV10:
+ case FCLK_DDR_CM0_CORE:
+ case ACLK_PHP_ROOT:
+ ret = 0;
+ break;
+#ifndef CONFIG_SPL_BUILD
+ case ACLK_VOP_ROOT:
+ case ACLK_VOP:
+ case ACLK_VO0_ROOT:
+ case ACLK_VO1_ROOT:
+ case HCLK_VOP_ROOT:
+ case PCLK_VOP_ROOT:
+ ret = rk3576_aclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case DCLK_VP0:
+ case DCLK_VP0_SRC:
+ case DCLK_VP1:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2:
+ case DCLK_VP2_SRC:
+ ret = rk3576_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_GMAC0_PTP_REF_SRC:
+ case CLK_GMAC1_PTP_REF_SRC:
+ case CLK_GMAC0_PTP_REF:
+ case CLK_GMAC1_PTP_REF:
+ case CLK_GMAC0_125M_SRC:
+ case CLK_GMAC1_125M_SRC:
+ ret = rk3576_gmac_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_UART_FRAC_0:
+ case CLK_UART_FRAC_1:
+ case CLK_UART_FRAC_2:
+ ret = rk3576_uart_frac_set_rate(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ case SCLK_UART10:
+ case SCLK_UART11:
+ ret = rk3576_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_DSIHOST0:
+ ret = rk3576_clk_csihost_set_clk(priv, clk->id, rate);
+ break;
+ case DCLK_EBC:
+ case DCLK_EBC_FRAC_SRC:
+ ret = rk3576_dclk_ebc_set_clk(priv, clk->id, rate);
+ break;
+#endif
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+static int __maybe_unused rk3576_dclk_vop_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel;
+ const char *clock_dev_name = parent->dev->name;
+
+ if (parent->id == PLL_VPLL)
+ sel = 2;
+ else if (parent->id == PLL_GPLL)
+ sel = 0;
+ else if (parent->id == PLL_CPLL)
+ sel = 1;
+ else if (parent->id == PLL_BPLL)
+ sel = 3;
+ else
+ sel = 4;
+
+ switch (clk->id) {
+ case DCLK_VP0_SRC:
+ rk_clrsetreg(&cru->clksel_con[145], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP1_SRC:
+ rk_clrsetreg(&cru->clksel_con[146], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP2_SRC:
+ rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SRC_SEL_MASK,
+ sel << DCLK0_VOP_SRC_SEL_SHIFT);
+ break;
+ case DCLK_VP0:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK0_VOP_SEL_MASK,
+ sel << DCLK0_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VP1:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK1_VOP_SEL_MASK,
+ sel << DCLK1_VOP_SEL_SHIFT);
+ break;
+ case DCLK_VP2:
+ if (!strcmp(clock_dev_name, "hdmiphypll_clk0"))
+ sel = 1;
+ else
+ sel = 0;
+ rk_clrsetreg(&cru->clksel_con[147], DCLK2_VOP_SEL_MASK,
+ sel << DCLK2_VOP_SEL_SHIFT);
+ break;
+ case DCLK_EBC:
+ if (parent->id == PLL_GPLL)
+ sel = 0;
+ else if (parent->id == PLL_CPLL)
+ sel = 1;
+ else if (parent->id == PLL_VPLL)
+ sel = 2;
+ else if (parent->id == PLL_AUPLL)
+ sel = 3;
+ else if (parent->id == PLL_LPLL)
+ sel = 4;
+ else if (parent->id == DCLK_EBC_FRAC_SRC)
+ sel = 5;
+ else
+ sel = 6;
+ rk_clrsetreg(&cru->clksel_con[123], DCLK_EBC_SEL_MASK,
+ sel << DCLK_EBC_SEL_SHIFT);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int __maybe_unused rk3576_ufs_ref_set_parent(struct clk *clk,
+ struct clk *parent)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3576_cru *cru = priv->cru;
+ u32 sel;
+ const char *clock_dev_name = parent->dev->name;
+
+ if (parent->id == CLK_REF_MPHY_26M)
+ sel = 2;
+ else if (!strcmp(clock_dev_name, "xin24m"))
+ sel = 0;
+ else
+ sel = 1;
+
+ rk_clrsetreg(&cru->pmuclksel_con[3], 0x3, sel << 0);
+ return 0;
+}
+
+static int rk3576_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ switch (clk->id) {
+ case DCLK_VP0_SRC:
+ case DCLK_VP1_SRC:
+ case DCLK_VP2_SRC:
+ case DCLK_VP0:
+ case DCLK_VP1:
+ case DCLK_VP2:
+ case DCLK_EBC:
+ return rk3576_dclk_vop_set_parent(clk, parent);
+ case CLK_REF_OSC_MPHY:
+ return rk3576_ufs_ref_set_parent(clk, parent);
+ case CLK_AUDIO_FRAC_0_SRC:
+ case CLK_AUDIO_FRAC_1_SRC:
+ /* Might occur in cru assigned-clocks, can be ignored here */
+ return 0;
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+#endif
+
+static struct clk_ops rk3576_clk_ops = {
+ .get_rate = rk3576_clk_get_rate,
+ .set_rate = rk3576_clk_set_rate,
+#if (IS_ENABLED(OF_CONTROL)) || (!IS_ENABLED(OF_PLATDATA))
+ .set_parent = rk3576_clk_set_parent,
+#endif
+};
+
+static void rk3576_clk_init(struct rk3576_clk_priv *priv)
+{
+ int ret;
+
+ priv->spll_hz = 702000000;
+
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+ rk_clrsetreg(&priv->cru->clksel_con[123],
+ DCLK_EBC_FRAC_SRC_SEL_MASK,
+ (DCLK_EBC_FRAC_SRC_SEL_GPLL <<
+ DCLK_EBC_FRAC_SRC_SEL_SHIFT));
+}
+
+static int rk3576_clk_probe(struct udevice *dev)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_SPL_BUILD
+ /* relase presetn_bigcore_biu/cru/grf */
+ writel(0x1c001c00, 0x26010010);
+ /* set spll to normal mode */
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_SCRU_BASE + RK3576_PLL_CON(137));
+ writel(BITS_WITH_WMASK(1, 0x3U, 0),
+ RK3576_SCRU_BASE + RK3576_MODE_CON0);
+ /* fix ppll\aupll\cpll */
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PMU_PLL_CON(129));
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PLL_CON(97));
+ writel(BITS_WITH_WMASK(2, 0x7U, 6),
+ RK3576_CRU_BASE + RK3576_PLL_CON(105));
+ writel(BITS_WITH_WMASK(1, 0x3U, 6),
+ RK3576_CRU_BASE + RK3576_MODE_CON0);
+ writel(BITS_WITH_WMASK(1, 0x3U, 8),
+ RK3576_CRU_BASE + RK3576_MODE_CON0);
+ /* init cci */
+ writel(0xffff0000, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
+ rockchip_pll_set_rate(&rk3576_pll_clks[BPLL], priv->cru,
+ BPLL, LPLL_HZ);
+ if (!priv->armclk_enter_hz) {
+ ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,
+ LPLL, LPLL_HZ);
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3576_pll_clks[LPLL],
+ priv->cru, LPLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ rk_clrsetreg(&priv->cru->litclksel_con[0], CLK_LITCORE_DIV_MASK,
+ 0 << CLK_LITCORE_DIV_SHIFT);
+ }
+ /* init cci */
+ writel(0xffff20cb, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
+
+ /* Change bigcore rm from 4 to 3 */
+ writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x3c);
+ writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x44);
+ writel(0x00020002, RK3576_BIGCORE_GRF_BASE + 0x38);
+ udelay(1);
+ writel(0x00020000, RK3576_BIGCORE_GRF_BASE + 0x38);
+ /* Change litcore rm from 4 to 3 */
+ writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x3c);
+ writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x44);
+ writel(0x00020002, RK3576_LITCORE_GRF_BASE + 0x38);
+ udelay(1);
+ writel(0x00020000, RK3576_LITCORE_GRF_BASE + 0x38);
+ /* Change cci rm form 4 to 3 */
+ writel(0x001c000c, RK3576_CCI_GRF_BASE + 0x54);
+#endif
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+
+ rk3576_clk_init(priv);
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev, 1);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3576_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3576_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3576_clk_bind(struct udevice *dev)
+{
+ int ret;
+ struct udevice *sys_child;
+ struct sysreset_reg *priv;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3576_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3576_cru,
+ glb_srsr_snd);
+ dev_set_priv(sys_child, priv);
+ }
+
+#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
+ ret = offsetof(struct rk3576_cru, softrst_con[0]);
+ ret = rk3576_reset_bind_lut(dev, ret, 32776);
+ if (ret)
+ debug("Warning: software reset driver bind failed\n");
+#endif
+
+ return 0;
+}
+
+static const struct udevice_id rk3576_clk_ids[] = {
+ { .compatible = "rockchip,rk3576-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3576_cru) = {
+ .name = "rockchip_rk3576_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3576_clk_ids,
+ .priv_auto = sizeof(struct rk3576_clk_priv),
+ .of_to_plat = rk3576_clk_ofdata_to_platdata,
+ .ops = &rk3576_clk_ops,
+ .bind = rk3576_clk_bind,
+ .probe = rk3576_clk_probe,
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 13/20] clk: rockchip: Add rk3576 clk support
2024-11-21 14:27 ` [PATCH 13/20] clk: rockchip: Add rk3576 clk support Heiko Stuebner
@ 2025-01-30 23:18 ` Jonas Karlman
0 siblings, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:18 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg, philipp.tomsich, kever.yang, lukma, seanga2, peng.fan,
jh80.chung, joe.hershberger, rfried.dev, quentin.schulz,
detlev.casanova, u-boot, sebastian.reichel, Elaine Zhang
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> Add clock driver support for Rockchip RK3576 SoC.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> [adapted to mainline u-boot]
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> .../include/asm/arch-rockchip/cru_rk3576.h | 486 ++++
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3576.c | 2517 +++++++++++++++++
> 3 files changed, 3004 insertions(+)
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> create mode 100644 drivers/clk/rockchip/clk_rk3576.c
>
> diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3576.h b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> new file mode 100644
> index 00000000000..893d92ff5f7
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> @@ -0,0 +1,486 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
> +#ifndef _ASM_ARCH_CRU_RK3576_H
> +#define _ASM_ARCH_CRU_RK3576_H
> +
> +#define MHz 1000000
> +#define KHz 1000
> +#define OSC_HZ (24 * MHz)
> +
> +#define CPU_PVTPLL_HZ (1008 * MHz)
> +#define LPLL_HZ (816 * MHz)
> +#define GPLL_HZ (1188 * MHz)
> +#define CPLL_HZ (1000 * MHz)
> +#define PPLL_HZ (1100 * MHz)
> +#define GMAC0_PTP_REFCLK_IN (24 * MHz)
> +#define GMAC1_PTP_REFCLK_IN (24 * MHz)
> +
> +/* RK3576 pll id */
> +enum rk3576_pll_id {
> + BPLL,
> + LPLL,
> + DPLL,
> + CPLL,
> + GPLL,
> + VPLL,
> + AUPLL,
> + SPLL,
> + PPLL,
> + PLL_COUNT,
> +};
> +
> +struct rk3576_clk_info {
> + unsigned long id;
> + char *name;
> + bool is_cru;
> +};
rk3576_clk_info is not used for anything and can be dropped.
> +
> +struct rk3576_clk_priv {
> + struct rk3576_cru *cru;
> + struct rk3576_grf *grf;
This grf member is not used for anything in the clk driver and can be
dropped.
> + ulong ppll_hz;
> + ulong gpll_hz;
> + ulong cpll_hz;
> + ulong vpll_hz;
> + ulong aupll_hz;
> + ulong spll_hz;
> + ulong lpll_hz;
> + ulong bpll_hz;
> + ulong armclk_hz;
> + ulong armclk_enter_hz;
> + ulong armclk_init_hz;
> + bool sync_kernel;
> + bool set_armclk_rate;
> +};
> +
[snip]
> diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
> index 9e379cc2e3b..855bf318de7 100644
> --- a/drivers/clk/rockchip/Makefile
> +++ b/drivers/clk/rockchip/Makefile
> @@ -16,6 +16,7 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
> obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
> +obj-$(CONFIG_ROCKCHIP_RK3576) += clk_rk3576.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o
> diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
> new file mode 100644
> index 00000000000..c11dd594a72
> --- /dev/null
> +++ b/drivers/clk/rockchip/clk_rk3576.c
> @@ -0,0 +1,2517 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
[snip]
> +
> +static int rk3576_clk_probe(struct udevice *dev)
> +{
> + struct rk3576_clk_priv *priv = dev_get_priv(dev);
> + int ret;
> +
> + priv->sync_kernel = false;
> +
> +#ifdef CONFIG_SPL_BUILD
> + /* relase presetn_bigcore_biu/cru/grf */
> + writel(0x1c001c00, 0x26010010);
> + /* set spll to normal mode */
> + writel(BITS_WITH_WMASK(2, 0x7U, 6),
> + RK3576_SCRU_BASE + RK3576_PLL_CON(137));
> + writel(BITS_WITH_WMASK(1, 0x3U, 0),
> + RK3576_SCRU_BASE + RK3576_MODE_CON0);
> + /* fix ppll\aupll\cpll */
> + writel(BITS_WITH_WMASK(2, 0x7U, 6),
> + RK3576_CRU_BASE + RK3576_PMU_PLL_CON(129));
> + writel(BITS_WITH_WMASK(2, 0x7U, 6),
> + RK3576_CRU_BASE + RK3576_PLL_CON(97));
> + writel(BITS_WITH_WMASK(2, 0x7U, 6),
> + RK3576_CRU_BASE + RK3576_PLL_CON(105));
> + writel(BITS_WITH_WMASK(1, 0x3U, 6),
> + RK3576_CRU_BASE + RK3576_MODE_CON0);
> + writel(BITS_WITH_WMASK(1, 0x3U, 8),
> + RK3576_CRU_BASE + RK3576_MODE_CON0);
> + /* init cci */
> + writel(0xffff0000, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
> + rockchip_pll_set_rate(&rk3576_pll_clks[BPLL], priv->cru,
> + BPLL, LPLL_HZ);
> + if (!priv->armclk_enter_hz) {
> + ret = rockchip_pll_set_rate(&rk3576_pll_clks[LPLL], priv->cru,
> + LPLL, LPLL_HZ);
> + priv->armclk_enter_hz =
> + rockchip_pll_get_rate(&rk3576_pll_clks[LPLL],
> + priv->cru, LPLL);
> + priv->armclk_init_hz = priv->armclk_enter_hz;
> + rk_clrsetreg(&priv->cru->litclksel_con[0], CLK_LITCORE_DIV_MASK,
> + 0 << CLK_LITCORE_DIV_SHIFT);
> + }
> + /* init cci */
> + writel(0xffff20cb, RK3576_CRU_BASE + RK3576_CCI_CLKSEL_CON(4));
> +
> + /* Change bigcore rm from 4 to 3 */
> + writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x3c);
> + writel(0x001c000c, RK3576_BIGCORE_GRF_BASE + 0x44);
> + writel(0x00020002, RK3576_BIGCORE_GRF_BASE + 0x38);
> + udelay(1);
> + writel(0x00020000, RK3576_BIGCORE_GRF_BASE + 0x38);
> + /* Change litcore rm from 4 to 3 */
> + writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x3c);
> + writel(0x001c000c, RK3576_LITCORE_GRF_BASE + 0x44);
> + writel(0x00020002, RK3576_LITCORE_GRF_BASE + 0x38);
> + udelay(1);
> + writel(0x00020000, RK3576_LITCORE_GRF_BASE + 0x38);
> + /* Change cci rm form 4 to 3 */
> + writel(0x001c000c, RK3576_CCI_GRF_BASE + 0x54);
> +#endif
> +
> + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
> + if (IS_ERR(priv->grf))
> + return PTR_ERR(priv->grf);
This driver is not using grf, so this can be dropped and should also
save a few ms of boot time.
Regards,
Jonas
> +
> + rk3576_clk_init(priv);
> +
> + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
> + ret = clk_set_defaults(dev, 1);
> + if (ret)
> + debug("%s clk_set_defaults failed %d\n", __func__, ret);
> + else
> + priv->sync_kernel = true;
> +
> + return 0;
> +}
[snip]
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 14/20] reset: rockchip: implement rk3576 lookup table
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (12 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 13/20] clk: rockchip: Add rk3576 clk support Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 14:27 ` [PATCH 15/20] ram: rockchip: Add rk3576 ddr driver support Heiko Stuebner
` (7 subsequent siblings)
21 siblings, 0 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel, Elaine Zhang
From: Elaine Zhang <zhangqing@rock-chips.com>
The current DT bindings for the rk3576 clock use a different ID than the
one that is supposed to be written to the hardware registers.
Thus, we cannot use directly the id provided in the phandle, but rather
use a lookup table to correctly setup the hardware.
This follows the implementation done in the Linux-Kernel and also
how the rk3588 does this both in the Linux-Kernel as well as U-Boot.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
[adapted from mainline Linux code for u-boot]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/include/asm/arch-rockchip/clock.h | 10 +
drivers/reset/Makefile | 2 +-
drivers/reset/rst-rk3576.c | 647 +++++++++++++++++++++
3 files changed, 658 insertions(+), 1 deletion(-)
create mode 100644 drivers/reset/rst-rk3576.c
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h
index 82305ef17ae..cbce708061d 100644
--- a/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -209,6 +209,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
*/
int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
u32 reg_offset, u32 reg_number);
+/*
+ * rk3576_reset_bind_lut() - Bind soft reset device as child of clock device
+ * using dedicated RK3576 lookup table
+ *
+ * @pdev: clock udevice
+ * @reg_offset: the first offset in cru for softreset registers
+ * @reg_number: the reg numbers of softreset registers
+ * Return: 0 success, or error value
+ */
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
/*
* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
* using dedicated RK3588 lookup table
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index d99a78c9828..2d43a326fc2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
-obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
+obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3576.o rst-rk3588.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
diff --git a/drivers/reset/rst-rk3576.c b/drivers/reset/rst-rk3576.c
new file mode 100644
index 00000000000..e64e27c1987
--- /dev/null
+++ b/drivers/reset/rst-rk3576.c
@@ -0,0 +1,647 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2024 Collabora Ltd.
+ * Author: Detlev Casanova <detlev.casanova@collabora.com>
+ * Based on Sebastien Reichel's implementation for RK3588
+ */
+
+#include <dm.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dt-bindings/reset/rockchip,rk3576-cru.h>
+
+/* 0x27200000 + 0x0A00 */
+#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + (reg) * 16 + (bit))
+/* 0x27208000 + 0x0A00 */
+#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000 * 4 + (reg) * 16 + (bit))
+/* 0x27210000 + 0x0A00 */
+#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + (reg) * 16 + (bit))
+/* 0x27220000 + 0x0A00 */
+#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + (reg) * 16 + (bit))
+
+/* mapping table for reset ID to register offset */
+static const int rk3576_register_offset[] = {
+ /* SOFTRST_CON01 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14),
+
+ /* SOFTRST_CON02 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1),
+
+ /* SOFTRST_CON06 */
+ RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2),
+
+ /* SOFTRST_CON07 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15),
+
+ /* SOFTRST_CON08 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14),
+
+ /* SOFTRST_CON09 */
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12),
+
+ /* SOFTRST_CON11 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15),
+
+ /* SOFTRST_CON12 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15),
+
+ /* SOFTRST_CON13 */
+ RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15),
+
+ /* SOFTRST_CON14 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15),
+
+ /* SOFTRST_CON15 */
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15),
+
+ /* SOFTRST_CON16 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11),
+
+ /* SOFTRST_CON17 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15),
+
+ /* SOFTRST_CON18 */
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15),
+
+ /* SOFTRST_CON19 */
+ RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13),
+
+ /* SOFTRST_CON20 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13),
+
+ /* SOFTRST_CON21 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15),
+
+ /* SOFTRST_CON22 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15),
+
+ /* SOFTRST_CON23 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11),
+
+ /* SOFTRST_CON25 */
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6),
+
+ /* SOFTRST_CON26 */
+ RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6),
+
+ /* SOFTRST_CON27 */
+ RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1),
+
+ /* SOFTRST_CON28 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12),
+
+ /* SOFTRST_CON29 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3),
+
+ /* SOFTRST_CON31 */
+ RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15),
+
+ /* SOFTRST_CON32 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13),
+
+ /* SOFTRST_CON33 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12),
+
+ /* SOFTRST_CON34 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15),
+
+ /* SOFTRST_CON35 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14),
+
+ /* SOFTRST_CON36 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9),
+
+ /* SOFTRST_CON37 */
+ RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7),
+
+ /* SOFTRST_CON40 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3),
+
+ /* SOFTRST_CON42 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12),
+
+ /* SOFTRST_CON43 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13),
+
+ /* SOFTRST_CON45 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9),
+
+ /* SOFTRST_CON47 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15),
+
+ /* SOFTRST_CON48 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2),
+
+ /* SOFTRST_CON49 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15),
+
+ /* SOFTRST_CON50 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12),
+
+ /* SOFTRST_CON51 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6),
+
+ /* SOFTRST_CON53 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11),
+
+ /* SOFTRST_CON54 */
+ RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8),
+
+ /* SOFTRST_CON59 */
+ RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5),
+
+ /* SOFTRST_CON61 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13),
+
+ /* SOFTRST_CON62 */
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3),
+
+ /* SOFTRST_CON63 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14),
+
+ /* SOFTRST_CON64 */
+ RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14),
+
+ /* SOFTRST_CON65 */
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15),
+
+ /* SOFTRST_CON66 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2),
+
+ /* SOFTRST_CON67 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14),
+
+ /* SOFTRST_CON68 */
+ RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0),
+ RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12),
+ RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13),
+
+ /* SOFTRST_CON69 */
+ RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13),
+ RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14),
+ RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15),
+
+ /* SOFTRST_CON72 */
+ RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6),
+ RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7),
+ RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9),
+ RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10),
+ RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11),
+ RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12),
+
+ /* SOFTRST_CON75 */
+ RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1),
+
+ /* SOFTRST_CON78 */
+ RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4),
+
+ /* SOFTRST_CON79 */
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2),
+ RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3),
+ RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4),
+ RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5),
+
+ /* PPLL_SOFTRST_CON00 */
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8),
+
+ /* PPLL_SOFTRST_CON01 */
+ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5),
+ RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8),
+
+ /* SECURENS_SOFTRST_CON00 */
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8),
+ RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9),
+
+ /* PMU1_SOFTRST_CON00 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15),
+
+ /* PMU1_SOFTRST_CON01 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHDP, 1, 13),
+
+ /* PMU1_SOFTRST_CON02 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3),
+
+ /* PMU1_SOFTRST_CON03 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13),
+
+ /* PMU1_SOFTRST_CON04 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12),
+
+ /* PMU1_SOFTRST_CON05 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15),
+
+ /* PMU1_SOFTRST_CON06 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1),
+
+ /* PMU1_SOFTRST_CON07 */
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6),
+ RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7),
+};
+
+int rk3576_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
+{
+ return rockchip_reset_bind_lut(pdev, rk3576_register_offset,
+ reg_offset, reg_number);
+}
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* [PATCH 15/20] ram: rockchip: Add rk3576 ddr driver support
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (13 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 14/20] reset: rockchip: implement rk3576 lookup table Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-30 23:13 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 16/20] rockchip: otp: Add support for RK3576 Heiko Stuebner
` (6 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Add ddr driver for rk3576 to get the ram capacity.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3576.c | 65 +++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3576.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index 36dc0500dab..442fe73deb6 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
+obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
diff --git a/drivers/ram/rockchip/sdram_rk3576.c b/drivers/ram/rockchip/sdram_rk3576.c
new file mode 100644
index 00000000000..fa4187a5860
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3576.c
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2024 Rockchip Electronics Co., Ltd.
+ */
+
+#include <config.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3576.h>
+#include <asm/arch-rockchip/sdram.h>
+
+struct dram_info {
+ struct ram_info info;
+ struct rk3576_pmu1grf *pmugrf;
+};
+
+static int rk3576_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+
+ /*
+ * On a 16GB board the DDR ATAG reports:
+ * start 0x40000000, size 0x400000000
+ * While the size value from the pmugrf below reports
+ * pmugrf->osreg2: 0x400000000
+ * pmugrf->osreg4: 0x10000000
+ * So it seems only osreg2 is responsible for the ram size.
+ */
+ priv->info.base = CFG_SYS_SDRAM_BASE;
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
+
+ return 0;
+}
+
+static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3576_dmc_ops = {
+ .get_info = rk3576_dmc_get_info,
+};
+
+static const struct udevice_id rk3576_dmc_ids[] = {
+ { .compatible = "rockchip,rk3576-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3576) = {
+ .name = "rockchip_rk3576_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3576_dmc_ids,
+ .ops = &rk3576_dmc_ops,
+ .probe = rk3576_dmc_probe,
+ .priv_auto = sizeof(struct dram_info),
+};
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 15/20] ram: rockchip: Add rk3576 ddr driver support
2024-11-21 14:27 ` [PATCH 15/20] ram: rockchip: Add rk3576 ddr driver support Heiko Stuebner
@ 2025-01-30 23:13 ` Jonas Karlman
0 siblings, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:13 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg, philipp.tomsich, kever.yang, lukma, seanga2, peng.fan,
jh80.chung, joe.hershberger, rfried.dev, quentin.schulz,
detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> Add ddr driver for rk3576 to get the ram capacity.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3576.c | 65 +++++++++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
> create mode 100644 drivers/ram/rockchip/sdram_rk3576.c
>
> diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
> index 36dc0500dab..442fe73deb6 100644
> --- a/drivers/ram/rockchip/Makefile
> +++ b/drivers/ram/rockchip/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
> obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
> obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
> obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
> +obj-$(CONFIG_ROCKCHIP_RK3576) += sdram_rk3576.o
> obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
> obj-$(CONFIG_ROCKCHIP_RV1126) += sdram_rv1126.o sdram_pctl_px30.o
> obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
> diff --git a/drivers/ram/rockchip/sdram_rk3576.c b/drivers/ram/rockchip/sdram_rk3576.c
> new file mode 100644
> index 00000000000..fa4187a5860
> --- /dev/null
> +++ b/drivers/ram/rockchip/sdram_rk3576.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2024 Rockchip Electronics Co., Ltd.
> + */
> +
> +#include <config.h>
> +#include <dm.h>
> +#include <ram.h>
> +#include <syscon.h>
> +#include <asm/arch-rockchip/clock.h>
> +#include <asm/arch-rockchip/grf_rk3576.h>
> +#include <asm/arch-rockchip/sdram.h>
> +
> +struct dram_info {
> + struct ram_info info;
> + struct rk3576_pmu1grf *pmugrf;
> +};
> +
> +static int rk3576_dmc_probe(struct udevice *dev)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
> +
> + /*
> + * On a 16GB board the DDR ATAG reports:
> + * start 0x40000000, size 0x400000000
> + * While the size value from the pmugrf below reports
> + * pmugrf->osreg2: 0x400000000
> + * pmugrf->osreg4: 0x10000000
> + * So it seems only osreg2 is responsible for the ram size.
> + */
> + priv->info.base = CFG_SYS_SDRAM_BASE;
> + priv->info.size =
> + rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg[2]);
> +
> + return 0;
> +}
> +
> +static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info)
> +{
> + struct dram_info *priv = dev_get_priv(dev);
> +
> + *info = priv->info;
> +
> + return 0;
> +}
Both the probe and above get_info can be simplified into something like:
#define PMU1GRF_BASE 0x26026000
#define OS_REG2_REG 0x208
static int rk3576_dmc_get_info(struct udevice *dev, struct ram_info *info)
{
info->base = CFG_SYS_SDRAM_BASE;
info->size = rockchip_sdram_size(PMU1GRF_BASE + OS_REG2_REG);
return 0;
}
With above the grf_rk3576.h could also be dropped/removed.
> +
> +static struct ram_ops rk3576_dmc_ops = {
> + .get_info = rk3576_dmc_get_info,
> +};
> +
> +static const struct udevice_id rk3576_dmc_ids[] = {
> + { .compatible = "rockchip,rk3576-dmc" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(dmc_rk3576) = {
> + .name = "rockchip_rk3576_dmc",
> + .id = UCLASS_RAM,
> + .of_match = rk3576_dmc_ids,
> + .ops = &rk3576_dmc_ops,
> + .probe = rk3576_dmc_probe,
> + .priv_auto = sizeof(struct dram_info),
With the probe function removed we can also remove the priv data.
> +};
Regards,
Jonas
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 16/20] rockchip: otp: Add support for RK3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (14 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 15/20] ram: rockchip: Add rk3576 ddr driver support Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-26 18:37 ` Quentin Schulz
2024-11-21 14:27 ` [PATCH 17/20] mmc: rockchip_sdhci: " Heiko Stuebner
` (5 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Add support for RK3588 compatible.
The RK3576 OTP uses the same read mechanism as the RK3588, just
with different values for offset and size.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/misc/rockchip-otp.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/misc/rockchip-otp.c b/drivers/misc/rockchip-otp.c
index 2123c31038f..8c8715e6412 100644
--- a/drivers/misc/rockchip-otp.c
+++ b/drivers/misc/rockchip-otp.c
@@ -361,6 +361,13 @@ static const struct rockchip_otp_data rk3568_data = {
.block_size = 2,
};
+static const struct rockchip_otp_data rk3576_data = {
+ .read = rockchip_rk3588_otp_read,
+ .offset = 0x700,
+ .size = 0x100,
+ .block_size = 4,
+};
+
static const struct rockchip_otp_data rk3588_data = {
.read = rockchip_rk3588_otp_read,
.offset = 0xC00,
@@ -387,6 +394,10 @@ static const struct udevice_id rockchip_otp_ids[] = {
.compatible = "rockchip,rk3568-otp",
.data = (ulong)&rk3568_data,
},
+ {
+ .compatible = "rockchip,rk3576-otp",
+ .data = (ulong)&rk3576_data,
+ },
{
.compatible = "rockchip,rk3588-otp",
.data = (ulong)&rk3588_data,
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 16/20] rockchip: otp: Add support for RK3576
2024-11-21 14:27 ` [PATCH 16/20] rockchip: otp: Add support for RK3576 Heiko Stuebner
@ 2024-11-26 18:37 ` Quentin Schulz
0 siblings, 0 replies; 44+ messages in thread
From: Quentin Schulz @ 2024-11-26 18:37 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 11/21/24 3:27 PM, Heiko Stuebner wrote:
> Add support for RK3588 compatible.
RK3576?
Cheers,
Quentin
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 17/20] mmc: rockchip_sdhci: Add support for RK3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (15 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 16/20] rockchip: otp: Add support for RK3576 Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 22:38 ` Jaehoon Chung
2025-01-30 23:25 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576 Heiko Stuebner
` (4 subsequent siblings)
21 siblings, 2 replies; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Add support for RK3576 to the rockchip sdhci driver.
It's pretty similar to its cousins found in the RK3568 and RK3588 and the
specific hs400-tx-tap number was taken from the vendor-u-boot.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/mmc/rockchip_sdhci.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index da630b9d97a..9571e7d66c9 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -656,6 +656,14 @@ static const struct sdhci_data rk3568_data = {
.hs400_txclk_tapnum = 0x8,
};
+static const struct sdhci_data rk3576_data = {
+ .set_ios_post = rk3568_sdhci_set_ios_post,
+ .set_clock = rk3568_sdhci_set_clock,
+ .config_dll = rk3568_sdhci_config_dll,
+ .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
+ .hs400_txclk_tapnum = 0x7,
+};
+
static const struct sdhci_data rk3588_data = {
.set_ios_post = rk3568_sdhci_set_ios_post,
.set_clock = rk3568_sdhci_set_clock,
@@ -673,6 +681,10 @@ static const struct udevice_id sdhci_ids[] = {
.compatible = "rockchip,rk3568-dwcmshc",
.data = (ulong)&rk3568_data,
},
+ {
+ .compatible = "rockchip,rk3576-dwcmshc",
+ .data = (ulong)&rk3576_data,
+ },
{
.compatible = "rockchip,rk3588-dwcmshc",
.data = (ulong)&rk3588_data,
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [PATCH 17/20] mmc: rockchip_sdhci: Add support for RK3576
2024-11-21 14:27 ` [PATCH 17/20] mmc: rockchip_sdhci: " Heiko Stuebner
@ 2024-11-21 22:38 ` Jaehoon Chung
2025-01-30 23:25 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Jaehoon Chung @ 2024-11-21 22:38 UTC (permalink / raw)
To: 'Heiko Stuebner', sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, joe.hershberger, rfried.dev, jonas,
quentin.schulz, detlev.casanova, u-boot, sebastian.reichel
> -----Original Message-----
> From: Heiko Stuebner <heiko@sntech.de>
> Sent: Thursday, November 21, 2024 11:27 PM
> To: sjg@chromium.org; philipp.tomsich@vrull.eu; kever.yang@rock-chips.com
> Cc: heiko@sntech.de; lukma@denx.de; seanga2@gmail.com; peng.fan@nxp.com; jh80.chung@samsung.com;
> joe.hershberger@ni.com; rfried.dev@gmail.com; jonas@kwiboo.se; quentin.schulz@cherry.de;
> detlev.casanova@collabora.com; u-boot@lists.denx.de; sebastian.reichel@collabora.com
> Subject: [PATCH 17/20] mmc: rockchip_sdhci: Add support for RK3576
>
> Add support for RK3576 to the rockchip sdhci driver.
>
> It's pretty similar to its cousins found in the RK3568 and RK3588 and the
> specific hs400-tx-tap number was taken from the vendor-u-boot.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/rockchip_sdhci.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index da630b9d97a..9571e7d66c9 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -656,6 +656,14 @@ static const struct sdhci_data rk3568_data = {
> .hs400_txclk_tapnum = 0x8,
> };
>
> +static const struct sdhci_data rk3576_data = {
> + .set_ios_post = rk3568_sdhci_set_ios_post,
> + .set_clock = rk3568_sdhci_set_clock,
> + .config_dll = rk3568_sdhci_config_dll,
> + .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
> + .hs400_txclk_tapnum = 0x7,
> +};
> +
> static const struct sdhci_data rk3588_data = {
> .set_ios_post = rk3568_sdhci_set_ios_post,
> .set_clock = rk3568_sdhci_set_clock,
> @@ -673,6 +681,10 @@ static const struct udevice_id sdhci_ids[] = {
> .compatible = "rockchip,rk3568-dwcmshc",
> .data = (ulong)&rk3568_data,
> },
> + {
> + .compatible = "rockchip,rk3576-dwcmshc",
> + .data = (ulong)&rk3576_data,
> + },
> {
> .compatible = "rockchip,rk3588-dwcmshc",
> .data = (ulong)&rk3588_data,
> --
> 2.45.2
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 17/20] mmc: rockchip_sdhci: Add support for RK3576
2024-11-21 14:27 ` [PATCH 17/20] mmc: rockchip_sdhci: " Heiko Stuebner
2024-11-21 22:38 ` Jaehoon Chung
@ 2025-01-30 23:25 ` Jonas Karlman
1 sibling, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:25 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg, philipp.tomsich, kever.yang, lukma, seanga2, peng.fan,
jh80.chung, joe.hershberger, rfried.dev, quentin.schulz,
detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> Add support for RK3576 to the rockchip sdhci driver.
>
> It's pretty similar to its cousins found in the RK3568 and RK3588 and the
> specific hs400-tx-tap number was taken from the vendor-u-boot.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/mmc/rockchip_sdhci.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index da630b9d97a..9571e7d66c9 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -656,6 +656,14 @@ static const struct sdhci_data rk3568_data = {
> .hs400_txclk_tapnum = 0x8,
> };
>
> +static const struct sdhci_data rk3576_data = {
> + .set_ios_post = rk3568_sdhci_set_ios_post,
> + .set_clock = rk3568_sdhci_set_clock,
> + .config_dll = rk3568_sdhci_config_dll,
> + .hs200_txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT,
> + .hs400_txclk_tapnum = 0x7,
Please add following to fix HS200+ mode together with [1] and [2].
.hs400_cmdout_tapnum = 0x7,
.hs400_strbin_tapnum = 0x5,
.ddr50_strbin_delay_num = 0xa,
[1] https://patchwork.ozlabs.org/patch/2038152/
[2] https://patchwork.ozlabs.org/patch/2038155/
Regards,
Jonas
> +};
> +
> static const struct sdhci_data rk3588_data = {
> .set_ios_post = rk3568_sdhci_set_ios_post,
> .set_clock = rk3568_sdhci_set_clock,
> @@ -673,6 +681,10 @@ static const struct udevice_id sdhci_ids[] = {
> .compatible = "rockchip,rk3568-dwcmshc",
> .data = (ulong)&rk3568_data,
> },
> + {
> + .compatible = "rockchip,rk3576-dwcmshc",
> + .data = (ulong)&rk3576_data,
> + },
> {
> .compatible = "rockchip,rk3588-dwcmshc",
> .data = (ulong)&rk3588_data,
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (16 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 17/20] mmc: rockchip_sdhci: " Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2024-11-21 22:38 ` Jaehoon Chung
2024-11-21 14:27 ` [PATCH 19/20] net: dwc_eth_qos_rockchip: Add support for RK3576 Heiko Stuebner
` (3 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
The rk3576 uses a different base-compatible, as starting with this
generation, the clock phase tuning is done via registers inside
the mmc controller and not from inside the CRU.
In U-Boot we do not tune at all, so no other code changes are
necessary.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/mmc/rockchip_dw_mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
index 422b8f7e4c8..7a72abaa38a 100644
--- a/drivers/mmc/rockchip_dw_mmc.c
+++ b/drivers/mmc/rockchip_dw_mmc.c
@@ -171,6 +171,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
static const struct udevice_id rockchip_dwmmc_ids[] = {
{ .compatible = "rockchip,rk2928-dw-mshc" },
{ .compatible = "rockchip,rk3288-dw-mshc" },
+ { .compatible = "rockchip,rk3576-dw-mshc" },
{ }
};
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* RE: [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576
2024-11-21 14:27 ` [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576 Heiko Stuebner
@ 2024-11-21 22:38 ` Jaehoon Chung
0 siblings, 0 replies; 44+ messages in thread
From: Jaehoon Chung @ 2024-11-21 22:38 UTC (permalink / raw)
To: 'Heiko Stuebner', sjg, philipp.tomsich, kever.yang
Cc: lukma, seanga2, peng.fan, joe.hershberger, rfried.dev, jonas,
quentin.schulz, detlev.casanova, u-boot, sebastian.reichel
> -----Original Message-----
> From: Heiko Stuebner <heiko@sntech.de>
> Sent: Thursday, November 21, 2024 11:27 PM
> To: sjg@chromium.org; philipp.tomsich@vrull.eu; kever.yang@rock-chips.com
> Cc: heiko@sntech.de; lukma@denx.de; seanga2@gmail.com; peng.fan@nxp.com; jh80.chung@samsung.com;
> joe.hershberger@ni.com; rfried.dev@gmail.com; jonas@kwiboo.se; quentin.schulz@cherry.de;
> detlev.casanova@collabora.com; u-boot@lists.denx.de; sebastian.reichel@collabora.com
> Subject: [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576
>
> The rk3576 uses a different base-compatible, as starting with this
> generation, the clock phase tuning is done via registers inside
> the mmc controller and not from inside the CRU.
>
> In U-Boot we do not tune at all, so no other code changes are
> necessary.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/rockchip_dw_mmc.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c
> index 422b8f7e4c8..7a72abaa38a 100644
> --- a/drivers/mmc/rockchip_dw_mmc.c
> +++ b/drivers/mmc/rockchip_dw_mmc.c
> @@ -171,6 +171,7 @@ static int rockchip_dwmmc_bind(struct udevice *dev)
> static const struct udevice_id rockchip_dwmmc_ids[] = {
> { .compatible = "rockchip,rk2928-dw-mshc" },
> { .compatible = "rockchip,rk3288-dw-mshc" },
> + { .compatible = "rockchip,rk3576-dw-mshc" },
> { }
> };
>
> --
> 2.45.2
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 19/20] net: dwc_eth_qos_rockchip: Add support for RK3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (17 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 18/20] mmc: rockchip_dw_mmc: Add support for rk3576 Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-30 23:30 ` Jonas Karlman
2024-11-21 14:27 ` [PATCH 20/20] rockchip: rk3576: Add support for ROC-RK3576-PC board Heiko Stuebner
` (2 subsequent siblings)
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
Add rk_gmac_ops and other special handling that is needed for GMAC to
work on RK3576.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/net/dwc_eth_qos.c | 4 +
drivers/net/dwc_eth_qos_rockchip.c | 141 ++++++++++++++++++++++++++++-
2 files changed, 144 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 2279481d935..1a05d285576 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1615,6 +1615,10 @@ static const struct udevice_id eqos_ids[] = {
.compatible = "rockchip,rk3568-gmac",
.data = (ulong)&eqos_rockchip_config
},
+ {
+ .compatible = "rockchip,rk3576-gmac",
+ .data = (ulong)&eqos_rockchip_config
+ },
{
.compatible = "rockchip,rk3588-gmac",
.data = (ulong)&eqos_rockchip_config
diff --git a/drivers/net/dwc_eth_qos_rockchip.c b/drivers/net/dwc_eth_qos_rockchip.c
index 9fc8c686b88..7115fe49bd5 100644
--- a/drivers/net/dwc_eth_qos_rockchip.c
+++ b/drivers/net/dwc_eth_qos_rockchip.c
@@ -131,6 +131,132 @@ static int rk3568_set_gmac_speed(struct udevice *dev)
return 0;
}
+#define RK3576_SDGMAC_GRF_GMAC0_CON 0x020
+#define RK3576_SDGMAC_GRF_GMAC1_CON 0x024
+
+#define RK3576_GMAC_CLK_RMII_MODE GRF_BIT(3)
+#define RK3576_GMAC_CLK_RGMII_MODE GRF_CLR_BIT(3)
+
+#define RK3576_GMAC_CLK_RMII_DIV2 GRF_BIT(5)
+#define RK3576_GMAC_CLK_RMII_DIV20 GRF_CLR_BIT(5)
+#define RK3576_GMAC_CLK_RGMII_DIV1 (GRF_CLR_BIT(5) | GRF_CLR_BIT(6))
+#define RK3576_GMAC_CLK_RGMII_DIV5 (GRF_BIT(5) | GRF_BIT(6))
+#define RK3576_GMAC_CLK_RGMII_DIV50 (GRF_CLR_BIT(5) | GRF_BIT(6))
+
+/* FIXME-check: in TRM swapped compared to rk3588 */
+#define RK3576_GMAC_CLK_SELECT_IO GRF_BIT(7)
+#define RK3576_GMAC_CLK_SELECT_CRU GRF_CLR_BIT(7)
+
+#define RK3576_GMAC_CLK_GATE GRF_BIT(0)
+#define RK3576_GMAC_CLK_NOGATE GRF_CLR_BIT(0)
+
+#define RK3576_IOC_GRF_MISC_CON2 0x6408
+#define RK3576_IOC_GRF_MISC_CON3 0x640c
+#define RK3576_IOC_GRF_MISC_CON4 0x6410
+#define RK3576_IOC_GRF_MISC_CON5 0x6414
+
+#define RK3576_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
+#define RK3576_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
+#define RK3576_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7f, 8)
+#define RK3576_GMAC_TXCLK_DLY_ENABLE GRF_BIT(7)
+#define RK3576_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(7)
+#define RK3576_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7f, 0)
+
+static int rk3576_set_to_rgmii(struct udevice *dev,
+ int tx_delay, int rx_delay)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 delay_con_m0, delay_con_m1, con, val;
+
+ con = (data->id == 1) ? RK3576_SDGMAC_GRF_GMAC1_CON :
+ RK3576_SDGMAC_GRF_GMAC0_CON;
+ regmap_write(data->grf, con, RK3576_GMAC_CLK_RGMII_MODE);
+
+ delay_con_m0 = data->id ? RK3576_IOC_GRF_MISC_CON4 :
+ RK3576_IOC_GRF_MISC_CON2;
+ delay_con_m1 = data->id ? RK3576_IOC_GRF_MISC_CON5 :
+ RK3576_IOC_GRF_MISC_CON3;
+
+ val = RK3576_GMAC_RXCLK_DLY_ENABLE | RK3576_GMAC_TXCLK_DLY_ENABLE;
+ val |= RK3576_GMAC_CLK_RX_DL_CFG(rx_delay);
+ val |= RK3576_GMAC_CLK_TX_DL_CFG(tx_delay);
+
+ regmap_write(data->php_grf, delay_con_m0, val);
+ regmap_write(data->php_grf, delay_con_m1, val);
+
+ return 0;
+}
+
+static int rk3576_set_to_rmii(struct udevice *dev)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 con;
+
+ con = (data->id == 1) ? RK3576_SDGMAC_GRF_GMAC1_CON :
+ RK3576_SDGMAC_GRF_GMAC0_CON;
+ regmap_write(data->grf, con, RK3576_GMAC_CLK_RMII_MODE);
+
+ return 0;
+}
+
+static int rk3576_set_gmac_speed(struct udevice *dev)
+{
+ struct eqos_priv *eqos = dev_get_priv(dev);
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 con, val;
+
+ con = (data->id == 1) ? RK3576_SDGMAC_GRF_GMAC1_CON :
+ RK3576_SDGMAC_GRF_GMAC0_CON;
+
+ switch (eqos->phy->speed) {
+ case SPEED_10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RMII_DIV20;
+ else
+ val = RK3576_GMAC_CLK_RGMII_DIV50;
+ break;
+ case SPEED_100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RMII_DIV2;
+ else
+ val = RK3576_GMAC_CLK_RGMII_DIV5;
+ break;
+ case SPEED_1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ val = RK3576_GMAC_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write(data->grf, con, val);
+
+ return 0;
+}
+
+static void rk3576_set_clock_selection(struct udevice *dev, bool enable)
+{
+ struct eth_pdata *pdata = dev_get_plat(dev);
+ struct rockchip_platform_data *data = pdata->priv_pdata;
+ u32 con, val;
+
+ con = (data->id == 1) ? RK3576_SDGMAC_GRF_GMAC1_CON :
+ RK3576_SDGMAC_GRF_GMAC0_CON;
+
+ val = data->clock_input ? RK3576_GMAC_CLK_SELECT_IO :
+ RK3576_GMAC_CLK_SELECT_CRU;
+
+ val |= enable ? RK3576_GMAC_CLK_NOGATE :
+ RK3576_GMAC_CLK_GATE;
+
+ regmap_write(data->grf, con, val);
+}
+
/* sys_grf */
#define RK3588_GRF_GMAC_CON7 0x031c
#define RK3588_GRF_GMAC_CON8 0x0320
@@ -274,6 +400,18 @@ static const struct rk_gmac_ops rk_gmac_ops[] = {
0x0, /* sentinel */
},
},
+ {
+ .compatible = "rockchip,rk3576-gmac",
+ .set_to_rgmii = rk3576_set_to_rgmii,
+ .set_to_rmii = rk3576_set_to_rmii,
+ .set_gmac_speed = rk3576_set_gmac_speed,
+ .set_clock_selection = rk3576_set_clock_selection,
+ .regs = {
+ 0x2a220000, /* gmac0 */
+ 0x2a230000, /* gmac1 */
+ 0x0, /* sentinel */
+ },
+ },
{
.compatible = "rockchip,rk3588-gmac",
.set_to_rgmii = rk3588_set_to_rgmii,
@@ -351,7 +489,8 @@ static int eqos_probe_resources_rk(struct udevice *dev)
goto err_free;
}
- if (device_is_compatible(dev, "rockchip,rk3588-gmac")) {
+ if (device_is_compatible(dev, "rockchip,rk3588-gmac") ||
+ device_is_compatible(dev, "rockchip,rk3576-gmac")) {
data->php_grf =
syscon_regmap_lookup_by_phandle(dev, "rockchip,php-grf");
if (IS_ERR(data->php_grf)) {
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 19/20] net: dwc_eth_qos_rockchip: Add support for RK3576
2024-11-21 14:27 ` [PATCH 19/20] net: dwc_eth_qos_rockchip: Add support for RK3576 Heiko Stuebner
@ 2025-01-30 23:30 ` Jonas Karlman
0 siblings, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:30 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg, philipp.tomsich, kever.yang, lukma, seanga2, peng.fan,
jh80.chung, joe.hershberger, rfried.dev, quentin.schulz,
detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> Add rk_gmac_ops and other special handling that is needed for GMAC to
> work on RK3576.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> drivers/net/dwc_eth_qos.c | 4 +
> drivers/net/dwc_eth_qos_rockchip.c | 141 ++++++++++++++++++++++++++++-
> 2 files changed, 144 insertions(+), 1 deletion(-)
[snip]
The code added in this patch does not seem to match the code added in
mainline Linux kernel.
Feel free to squash "fixup: net: dwc_eth_qos_rockchip: Add support for
RK3576" at [1] to adjust this to closer match the Linux kernel driver,
similar to remaining supported SoCs in this driver.
[1] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3576-2025.04-wip/
Regards,
Jonas
^ permalink raw reply [flat|nested] 44+ messages in thread
* [PATCH 20/20] rockchip: rk3576: Add support for ROC-RK3576-PC board
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (18 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 19/20] net: dwc_eth_qos_rockchip: Add support for RK3576 Heiko Stuebner
@ 2024-11-21 14:27 ` Heiko Stuebner
2025-01-30 23:39 ` Jonas Karlman
2024-11-26 19:26 ` [PATCH 00/20] Support for the RK3576 Detlev Casanova
2025-04-06 15:09 ` Kever Yang
21 siblings, 1 reply; 44+ messages in thread
From: Heiko Stuebner @ 2024-11-21 14:27 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, detlev.casanova, u-boot,
sebastian.reichel
The ROC-RK3576-PC is a SBC made by Firefly, designed around the RK3576
SoC. This adds the needed board infrastructure and config for it.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
arch/arm/dts/rk3576-roc-pc-u-boot.dtsi | 12 ++++
arch/arm/mach-rockchip/rk3576/Kconfig | 9 +++
board/firefly/roc-pc-rk3576/Kconfig | 12 ++++
board/firefly/roc-pc-rk3576/MAINTAINERS | 7 +++
configs/roc-pc-rk3576_defconfig | 77 +++++++++++++++++++++++++
doc/board/rockchip/rockchip.rst | 3 +
include/configs/roc-pc-rk3576.h | 15 +++++
7 files changed, 135 insertions(+)
create mode 100644 arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
create mode 100644 board/firefly/roc-pc-rk3576/Kconfig
create mode 100644 board/firefly/roc-pc-rk3576/MAINTAINERS
create mode 100644 configs/roc-pc-rk3576_defconfig
create mode 100644 include/configs/roc-pc-rk3576.h
diff --git a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
new file mode 100644
index 00000000000..0cfc7b5dcd6
--- /dev/null
+++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net>
+ *
+ */
+
+#include "rk3576-u-boot.dtsi"
+
+&sdhci {
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+};
diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
index 2e46b2b90d2..4c2328e5699 100644
--- a/arch/arm/mach-rockchip/rk3576/Kconfig
+++ b/arch/arm/mach-rockchip/rk3576/Kconfig
@@ -1,5 +1,12 @@
if ROCKCHIP_RK3576
+config TARGET_ROC_PC_RK3576
+ bool "ROC_PC_RK3576"
+ select BOARD_LATE_INIT
+ help
+ ROC-RK3576-PC is a single board computer from Firefly
+ using the Rockchp RK3576.
+
config ROCKCHIP_BOOT_MODE_REG
default 0x26024040
@@ -45,4 +52,6 @@ config SPL_STACK_R_ADDR
config SPL_STACK_R_MALLOC_SIMPLE_LEN
default 0x200000
+source board/firefly/roc-pc-rk3576/Kconfig
+
endif
diff --git a/board/firefly/roc-pc-rk3576/Kconfig b/board/firefly/roc-pc-rk3576/Kconfig
new file mode 100644
index 00000000000..2fc0f913c37
--- /dev/null
+++ b/board/firefly/roc-pc-rk3576/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ROC_PC_RK3576
+
+config SYS_BOARD
+ default "roc-pc-rk3576"
+
+config SYS_VENDOR
+ default "firefly"
+
+config SYS_CONFIG_NAME
+ default "roc-pc-rk3576"
+
+endif
diff --git a/board/firefly/roc-pc-rk3576/MAINTAINERS b/board/firefly/roc-pc-rk3576/MAINTAINERS
new file mode 100644
index 00000000000..aa8897c16fc
--- /dev/null
+++ b/board/firefly/roc-pc-rk3576/MAINTAINERS
@@ -0,0 +1,7 @@
+ROC-RK3576-PC
+M: Heiko Stuebner <heiko@sntech.de>
+S: Maintained
+F: board/firefly/roc-pc-rk3576
+F: include/configs/roc-pc-rk3576.h
+F: configs/roc-pc-rk3576_defconfig
+F: arch/arm/dts/rk3576-roc-pc*
diff --git a/configs/roc-pc-rk3576_defconfig b/configs/roc-pc-rk3576_defconfig
new file mode 100644
index 00000000000..25e4fa1e8f6
--- /dev/null
+++ b/configs/roc-pc-rk3576_defconfig
@@ -0,0 +1,77 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-roc-pc"
+CONFIG_ROCKCHIP_RK3576=y
+CONFIG_SPL_SERIAL=y
+CONFIG_TARGET_ROC_PC_RK3576=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0x2AD40000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-roc-pc.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_PAD_TO=0x7f8000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_DWC_ETH_QOS_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
index 6b544e957b2..5b01d536c05 100644
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -125,6 +125,9 @@ List of mainline supported Rockchip boards:
- Radxa ROCK 3A (rock-3a-rk3568)
- Radxa ROCK 3B (rock-3b-rk3568)
+* rk3576
+ - Firefly ROC-RK3576-PC (roc-pc-rk3576)
+
* rk3588
- ArmSoM Sige7 (sige7-rk3588)
- Rockchip EVB (evb-rk3588)
diff --git a/include/configs/roc-pc-rk3576.h b/include/configs/roc-pc-rk3576.h
new file mode 100644
index 00000000000..ac98d516478
--- /dev/null
+++ b/include/configs/roc-pc-rk3576.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef __ROC_PC_RK3576_H
+#define __ROC_PC_RK3576_H
+
+#include <configs/rk3576_common.h>
+
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#endif
--
2.45.2
^ permalink raw reply related [flat|nested] 44+ messages in thread* Re: [PATCH 20/20] rockchip: rk3576: Add support for ROC-RK3576-PC board
2024-11-21 14:27 ` [PATCH 20/20] rockchip: rk3576: Add support for ROC-RK3576-PC board Heiko Stuebner
@ 2025-01-30 23:39 ` Jonas Karlman
0 siblings, 0 replies; 44+ messages in thread
From: Jonas Karlman @ 2025-01-30 23:39 UTC (permalink / raw)
To: Heiko Stuebner
Cc: sjg, philipp.tomsich, kever.yang, lukma, seanga2, peng.fan,
jh80.chung, joe.hershberger, rfried.dev, quentin.schulz,
detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
On 2024-11-21 15:27, Heiko Stuebner wrote:
> The ROC-RK3576-PC is a SBC made by Firefly, designed around the RK3576
> SoC. This adds the needed board infrastructure and config for it.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> arch/arm/dts/rk3576-roc-pc-u-boot.dtsi | 12 ++++
> arch/arm/mach-rockchip/rk3576/Kconfig | 9 +++
> board/firefly/roc-pc-rk3576/Kconfig | 12 ++++
> board/firefly/roc-pc-rk3576/MAINTAINERS | 7 +++
> configs/roc-pc-rk3576_defconfig | 77 +++++++++++++++++++++++++
> doc/board/rockchip/rockchip.rst | 3 +
> include/configs/roc-pc-rk3576.h | 15 +++++
> 7 files changed, 135 insertions(+)
> create mode 100644 arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> create mode 100644 board/firefly/roc-pc-rk3576/Kconfig
> create mode 100644 board/firefly/roc-pc-rk3576/MAINTAINERS
> create mode 100644 configs/roc-pc-rk3576_defconfig
> create mode 100644 include/configs/roc-pc-rk3576.h
>
> diff --git a/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> new file mode 100644
> index 00000000000..0cfc7b5dcd6
> --- /dev/null
> +++ b/arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2023 Joshua Riek <jjriek@verizon.net>
> + *
> + */
> +
> +#include "rk3576-u-boot.dtsi"
> +
> +&sdhci {
> + cap-mmc-highspeed;
> + mmc-hs200-1_8v;
mmc-hs200-1_8v is already implied by mmc-hs400-1_8v in dts/upstream and
can be dropped.
> +};
> diff --git a/arch/arm/mach-rockchip/rk3576/Kconfig b/arch/arm/mach-rockchip/rk3576/Kconfig
> index 2e46b2b90d2..4c2328e5699 100644
> --- a/arch/arm/mach-rockchip/rk3576/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3576/Kconfig
> @@ -1,5 +1,12 @@
> if ROCKCHIP_RK3576
>
> +config TARGET_ROC_PC_RK3576
> + bool "ROC_PC_RK3576"
Should probably match the model prop, "Firefly ROC-RK3576-PC".
> + select BOARD_LATE_INIT
This is already selected by the SoC Kconfig symbol and can be dropped.
> + help
> + ROC-RK3576-PC is a single board computer from Firefly
> + using the Rockchp RK3576.
s/Rockchp/Rockchip/
> +
> config ROCKCHIP_BOOT_MODE_REG
> default 0x26024040
>
> @@ -45,4 +52,6 @@ config SPL_STACK_R_ADDR
> config SPL_STACK_R_MALLOC_SIMPLE_LEN
> default 0x200000
>
> +source board/firefly/roc-pc-rk3576/Kconfig
> +
> endif
> diff --git a/board/firefly/roc-pc-rk3576/Kconfig b/board/firefly/roc-pc-rk3576/Kconfig
> new file mode 100644
> index 00000000000..2fc0f913c37
> --- /dev/null
> +++ b/board/firefly/roc-pc-rk3576/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_ROC_PC_RK3576
> +
> +config SYS_BOARD
> + default "roc-pc-rk3576"
> +
> +config SYS_VENDOR
> + default "firefly"
> +
> +config SYS_CONFIG_NAME
> + default "roc-pc-rk3576"
> +
> +endif
> diff --git a/board/firefly/roc-pc-rk3576/MAINTAINERS b/board/firefly/roc-pc-rk3576/MAINTAINERS
> new file mode 100644
> index 00000000000..aa8897c16fc
> --- /dev/null
> +++ b/board/firefly/roc-pc-rk3576/MAINTAINERS
> @@ -0,0 +1,7 @@
> +ROC-RK3576-PC
> +M: Heiko Stuebner <heiko@sntech.de>
> +S: Maintained
> +F: board/firefly/roc-pc-rk3576
> +F: include/configs/roc-pc-rk3576.h
> +F: configs/roc-pc-rk3576_defconfig
> +F: arch/arm/dts/rk3576-roc-pc*
> diff --git a/configs/roc-pc-rk3576_defconfig b/configs/roc-pc-rk3576_defconfig
> new file mode 100644
> index 00000000000..25e4fa1e8f6
> --- /dev/null
> +++ b/configs/roc-pc-rk3576_defconfig
> @@ -0,0 +1,77 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_SYS_HAS_NONCACHED_MEMORY=y
This non-cached memory option is only needed for the pcie rtl ethernet
driver and can possible be dropped.
> +CONFIG_COUNTER_FREQUENCY=24000000
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3576-roc-pc"
> +CONFIG_ROCKCHIP_RK3576=y
> +CONFIG_SPL_SERIAL=y
> +CONFIG_TARGET_ROC_PC_RK3576=y
> +CONFIG_SYS_LOAD_ADDR=0xc00800
Should probably be in the 0x40000000+ range.
> +CONFIG_DEBUG_UART_BASE=0x2AD40000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3576-roc-pc.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
This is not really needed, only add multiple Model: lines on the console.
> +CONFIG_SPL_MAX_SIZE=0x40000
> +CONFIG_SPL_PAD_TO=0x7f8000
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_SPL_ATF=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_I2C=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_PCI=y
> +CONFIG_CMD_USB=y
> +CONFIG_CMD_ROCKUSB=y
> +CONFIG_CMD_USB_MASS_STORAGE=y
The PCI and USB commands it possible not yet needed as there is no USB
or PCIe support yet.
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_REGULATOR=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_OF_LIVE=y
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_SPL_CLK=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_LED=y
> +CONFIG_LED_GPIO=y
> +CONFIG_MISC=y
> +CONFIG_SUPPORT_EMMC_RPMB=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_SDMA=y
> +CONFIG_MMC_SDHCI_ROCKCHIP=y
> +CONFIG_PHY_REALTEK=y
This board seem to use Motorcomm phy and should instead use
CONFIG_PHY_MOTORCOMM=y.
> +CONFIG_DWC_ETH_QOS=y
> +CONFIG_DWC_ETH_QOS_ROCKCHIP=y
> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y
> +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
> +CONFIG_PHY_ROCKCHIP_USBDP=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_SPL_RAM=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYS_NS16550_MEM32=y
> +CONFIG_SYSRESET=y
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC3=y
> +CONFIG_USB_DWC3_GENERIC=y
USB is not yet supported and these could be dropped.
> +CONFIG_ERRNO_STR=y
> diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst
> index 6b544e957b2..5b01d536c05 100644
> --- a/doc/board/rockchip/rockchip.rst
> +++ b/doc/board/rockchip/rockchip.rst
> @@ -125,6 +125,9 @@ List of mainline supported Rockchip boards:
> - Radxa ROCK 3A (rock-3a-rk3568)
> - Radxa ROCK 3B (rock-3b-rk3568)
>
> +* rk3576
> + - Firefly ROC-RK3576-PC (roc-pc-rk3576)
> +
> * rk3588
> - ArmSoM Sige7 (sige7-rk3588)
> - Rockchip EVB (evb-rk3588)
> diff --git a/include/configs/roc-pc-rk3576.h b/include/configs/roc-pc-rk3576.h
> new file mode 100644
> index 00000000000..ac98d516478
> --- /dev/null
> +++ b/include/configs/roc-pc-rk3576.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
> + */
> +
> +#ifndef __ROC_PC_RK3576_H
> +#define __ROC_PC_RK3576_H
> +
> +#include <configs/rk3576_common.h>
This include should be moved below ROCKCHIP_DEVICE_SETTINGS.
Regards,
Jonas
> +
> +#define ROCKCHIP_DEVICE_SETTINGS \
> + "stdout=serial,vidconsole\0" \
> + "stderr=serial,vidconsole\0"
> +
> +#endif
^ permalink raw reply [flat|nested] 44+ messages in thread
* Re: [PATCH 00/20] Support for the RK3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (19 preceding siblings ...)
2024-11-21 14:27 ` [PATCH 20/20] rockchip: rk3576: Add support for ROC-RK3576-PC board Heiko Stuebner
@ 2024-11-26 19:26 ` Detlev Casanova
2025-04-06 15:09 ` Kever Yang
21 siblings, 0 replies; 44+ messages in thread
From: Detlev Casanova @ 2024-11-26 19:26 UTC (permalink / raw)
To: sjg, philipp.tomsich, kever.yang, Heiko Stuebner
Cc: heiko, lukma, seanga2, peng.fan, jh80.chung, joe.hershberger,
rfried.dev, jonas, quentin.schulz, u-boot, sebastian.reichel
Hi Heiko
On Thursday, 21 November 2024 09:27:11 EST Heiko Stuebner wrote:
> This adds support for the RK3576 SoC from Rockchip.
>
> Currently supported (and tested) features are accessing and reading from
> sdhci and sdmmc devices as well as pxe-booting via the network interface.
>
> As can be seen by the DONOTMERGE labels, this needs to wait a bit still.
>
> The core RK3576 devicetrees will be part of 6.13-rc1, but the Firefly
> board I only submitted last week, so this would only appear in 6.14-rc1 .
>
> If someone from Collabora could provide a board patch for the ArmSom
> board they are working with, this would speed things up a bit ;-) .
I'm doing some testing with this patch set on the sige 5 and things seem to
work well so far.
I don't have working sdhci and sdmmc yet though, I'll have a look and provide
patches for the board when it works :)
I will also send som Tested-by's later.
Detlev.
> Checkpatch seems mostly happy too.
>
>
> Detlev Casanova (3):
> dt-bindings: clock, reset: Add support for rk3576
> DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT
> arm: rockchip: add RK3576-specific syscon ids
>
> Elaine Zhang (2):
> clk: rockchip: Add rk3576 clk support
> reset: rockchip: implement rk3576 lookup table
>
> Finley Xiao (1):
> dt-bindings: power: Add support for RK3576 SoC
>
> Heiko Stuebner (11):
> dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
> DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node
> DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC
> binding
> DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
> rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
> ram: rockchip: Add rk3576 ddr driver support
> rockchip: otp: Add support for RK3576
> mmc: rockchip_sdhci: Add support for RK3576
> mmc: rockchip_dw_mmc: Add support for rk3576
> net: dwc_eth_qos_rockchip: Add support for RK3576
> rockchip: rk3576: Add support for ROC-RK3576-PC board
>
> Steven Liu (1):
> pinctrl: rockchip: support rk3576 pinctrl
>
> Xuhui Lin (2):
> rockchip: mkimage: Add rk3576 support
> arm: rockchip: Add RK3576 arch core support
>
> arch/arm/dts/rk3576-roc-pc-u-boot.dtsi | 12 +
> arch/arm/dts/rk3576-u-boot.dtsi | 119 +
> arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
> arch/arm/include/asm/arch-rockchip/clock.h | 12 +
> .../include/asm/arch-rockchip/cru_rk3576.h | 486 ++
> .../include/asm/arch-rockchip/grf_rk3576.h | 225 +
> .../include/asm/arch-rockchip/ioc_rk3576.h | 244 +
> arch/arm/mach-rockchip/Kconfig | 46 +-
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3576/Kconfig | 57 +
> arch/arm/mach-rockchip/rk3576/Makefile | 9 +
> arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +
> arch/arm/mach-rockchip/rk3576/rk3576.c | 169 +
> arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 +
> arch/arm/mach-rockchip/sdram.c | 11 +-
> board/firefly/roc-pc-rk3576/Kconfig | 12 +
> board/firefly/roc-pc-rk3576/MAINTAINERS | 7 +
> configs/roc-pc-rk3576_defconfig | 77 +
> doc/board/rockchip/rockchip.rst | 12 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3576.c | 2517 +++++++
> drivers/misc/rockchip-otp.c | 11 +
> drivers/mmc/rockchip_dw_mmc.c | 1 +
> drivers/mmc/rockchip_sdhci.c | 12 +
> drivers/net/dwc_eth_qos.c | 4 +
> drivers/net/dwc_eth_qos_rockchip.c | 141 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3576.c | 287 +
> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 3 +
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3576.c | 65 +
> drivers/reset/Makefile | 2 +-
> drivers/reset/rst-rk3576.c | 647 ++
> dts/upstream/Bindings/arm/rockchip.yaml | 5 +
> .../Bindings/clock/rockchip,rk3576-cru.yaml | 56 +
> .../power/rockchip,power-controller.yaml | 1 +
> .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++
> .../dt-bindings/power/rockchip,rk3576-power.h | 30 +
> .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 ++
> .../src/arm64/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++
> .../src/arm64/rockchip/rk3576-roc-pc.dts | 736 +++
> dts/upstream/src/arm64/rockchip/rk3576.dtsi | 1717 +++++
> include/configs/rk3576_common.h | 42 +
> include/configs/roc-pc-rk3576.h | 15 +
> tools/rkcommon.c | 1 +
> 46 files changed, 14798 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
> create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> create mode 100644 board/firefly/roc-pc-rk3576/Kconfig
> create mode 100644 board/firefly/roc-pc-rk3576/MAINTAINERS
> create mode 100644 configs/roc-pc-rk3576_defconfig
> create mode 100644 drivers/clk/rockchip/clk_rk3576.c
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3576.c
> create mode 100644 drivers/ram/rockchip/sdram_rk3576.c
> create mode 100644 drivers/reset/rst-rk3576.c
> create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> create mode 100644
> dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h create mode
> 100644 dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
> create mode 100644
> dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h create mode
> 100644 dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi create mode
> 100644 dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts create mode 100644
> dts/upstream/src/arm64/rockchip/rk3576.dtsi
> create mode 100644 include/configs/rk3576_common.h
> create mode 100644 include/configs/roc-pc-rk3576.h
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 00/20] Support for the RK3576
2024-11-21 14:27 [PATCH 00/20] Support for the RK3576 Heiko Stuebner
` (20 preceding siblings ...)
2024-11-26 19:26 ` [PATCH 00/20] Support for the RK3576 Detlev Casanova
@ 2025-04-06 15:09 ` Kever Yang
2025-04-07 15:09 ` Heiko Stübner
21 siblings, 1 reply; 44+ messages in thread
From: Kever Yang @ 2025-04-06 15:09 UTC (permalink / raw)
To: Heiko Stuebner, sjg, philipp.tomsich
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, quentin.schulz, detlev.casanova, u-boot, sebastian.reichel
Hi Heiko,
Do you have new version for this patch set?
Thanks,
- Kever
On 2024/11/21 22:27, Heiko Stuebner wrote:
> This adds support for the RK3576 SoC from Rockchip.
>
> Currently supported (and tested) features are accessing and reading from
> sdhci and sdmmc devices as well as pxe-booting via the network interface.
>
> As can be seen by the DONOTMERGE labels, this needs to wait a bit still.
>
> The core RK3576 devicetrees will be part of 6.13-rc1, but the Firefly
> board I only submitted last week, so this would only appear in 6.14-rc1 .
>
> If someone from Collabora could provide a board patch for the ArmSom
> board they are working with, this would speed things up a bit ;-) .
>
> Checkpatch seems mostly happy too.
>
>
> Detlev Casanova (3):
> dt-bindings: clock, reset: Add support for rk3576
> DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT
> arm: rockchip: add RK3576-specific syscon ids
>
> Elaine Zhang (2):
> clk: rockchip: Add rk3576 clk support
> reset: rockchip: implement rk3576 lookup table
>
> Finley Xiao (1):
> dt-bindings: power: Add support for RK3576 SoC
>
> Heiko Stuebner (11):
> dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
> DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node
> DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC
> binding
> DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
> rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
> ram: rockchip: Add rk3576 ddr driver support
> rockchip: otp: Add support for RK3576
> mmc: rockchip_sdhci: Add support for RK3576
> mmc: rockchip_dw_mmc: Add support for rk3576
> net: dwc_eth_qos_rockchip: Add support for RK3576
> rockchip: rk3576: Add support for ROC-RK3576-PC board
>
> Steven Liu (1):
> pinctrl: rockchip: support rk3576 pinctrl
>
> Xuhui Lin (2):
> rockchip: mkimage: Add rk3576 support
> arm: rockchip: Add RK3576 arch core support
>
> arch/arm/dts/rk3576-roc-pc-u-boot.dtsi | 12 +
> arch/arm/dts/rk3576-u-boot.dtsi | 119 +
> arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
> arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
> arch/arm/include/asm/arch-rockchip/clock.h | 12 +
> .../include/asm/arch-rockchip/cru_rk3576.h | 486 ++
> .../include/asm/arch-rockchip/grf_rk3576.h | 225 +
> .../include/asm/arch-rockchip/ioc_rk3576.h | 244 +
> arch/arm/mach-rockchip/Kconfig | 46 +-
> arch/arm/mach-rockchip/Makefile | 1 +
> arch/arm/mach-rockchip/rk3576/Kconfig | 57 +
> arch/arm/mach-rockchip/rk3576/Makefile | 9 +
> arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +
> arch/arm/mach-rockchip/rk3576/rk3576.c | 169 +
> arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 +
> arch/arm/mach-rockchip/sdram.c | 11 +-
> board/firefly/roc-pc-rk3576/Kconfig | 12 +
> board/firefly/roc-pc-rk3576/MAINTAINERS | 7 +
> configs/roc-pc-rk3576_defconfig | 77 +
> doc/board/rockchip/rockchip.rst | 12 +
> drivers/clk/rockchip/Makefile | 1 +
> drivers/clk/rockchip/clk_rk3576.c | 2517 +++++++
> drivers/misc/rockchip-otp.c | 11 +
> drivers/mmc/rockchip_dw_mmc.c | 1 +
> drivers/mmc/rockchip_sdhci.c | 12 +
> drivers/net/dwc_eth_qos.c | 4 +
> drivers/net/dwc_eth_qos_rockchip.c | 141 +-
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl-rk3576.c | 287 +
> drivers/pinctrl/rockchip/pinctrl-rockchip.h | 3 +
> drivers/ram/rockchip/Makefile | 1 +
> drivers/ram/rockchip/sdram_rk3576.c | 65 +
> drivers/reset/Makefile | 2 +-
> drivers/reset/rst-rk3576.c | 647 ++
> dts/upstream/Bindings/arm/rockchip.yaml | 5 +
> .../Bindings/clock/rockchip,rk3576-cru.yaml | 56 +
> .../power/rockchip,power-controller.yaml | 1 +
> .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++
> .../dt-bindings/power/rockchip,rk3576-power.h | 30 +
> .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 ++
> .../src/arm64/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++
> .../src/arm64/rockchip/rk3576-roc-pc.dts | 736 +++
> dts/upstream/src/arm64/rockchip/rk3576.dtsi | 1717 +++++
> include/configs/rk3576_common.h | 42 +
> include/configs/roc-pc-rk3576.h | 15 +
> tools/rkcommon.c | 1 +
> 46 files changed, 14798 insertions(+), 8 deletions(-)
> create mode 100644 arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
> create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
> create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
> create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
> create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
> create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> create mode 100644 board/firefly/roc-pc-rk3576/Kconfig
> create mode 100644 board/firefly/roc-pc-rk3576/MAINTAINERS
> create mode 100644 configs/roc-pc-rk3576_defconfig
> create mode 100644 drivers/clk/rockchip/clk_rk3576.c
> create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3576.c
> create mode 100644 drivers/ram/rockchip/sdram_rk3576.c
> create mode 100644 drivers/reset/rst-rk3576.c
> create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> create mode 100644 dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
> create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
> create mode 100644 dts/upstream/src/arm64/rockchip/rk3576.dtsi
> create mode 100644 include/configs/rk3576_common.h
> create mode 100644 include/configs/roc-pc-rk3576.h
>
^ permalink raw reply [flat|nested] 44+ messages in thread* Re: [PATCH 00/20] Support for the RK3576
2025-04-06 15:09 ` Kever Yang
@ 2025-04-07 15:09 ` Heiko Stübner
0 siblings, 0 replies; 44+ messages in thread
From: Heiko Stübner @ 2025-04-07 15:09 UTC (permalink / raw)
To: sjg, philipp.tomsich, Kever Yang
Cc: lukma, seanga2, peng.fan, jh80.chung, joe.hershberger, rfried.dev,
jonas, quentin.schulz, detlev.casanova, u-boot, sebastian.reichel
Hi Kever,
Am Sonntag, 6. April 2025, 17:09:59 Mitteleuropäische Sommerzeit schrieb Kever Yang:
> Hi Heiko,
>
> Do you have new version for this patch set?
with 6.15-tc1 the devicetree for my Firefly board now also made it to the
dt-rebasing repository, where I can cherry-pick it from for u-boot.
So yes, I'll try to come forward with an updated version hopefully
this week.
Heiko
> On 2024/11/21 22:27, Heiko Stuebner wrote:
> > This adds support for the RK3576 SoC from Rockchip.
> >
> > Currently supported (and tested) features are accessing and reading from
> > sdhci and sdmmc devices as well as pxe-booting via the network interface.
> >
> > As can be seen by the DONOTMERGE labels, this needs to wait a bit still.
> >
> > The core RK3576 devicetrees will be part of 6.13-rc1, but the Firefly
> > board I only submitted last week, so this would only appear in 6.14-rc1 .
> >
> > If someone from Collabora could provide a board patch for the ArmSom
> > board they are working with, this would speed things up a bit ;-) .
> >
> > Checkpatch seems mostly happy too.
> >
> >
> > Detlev Casanova (3):
> > dt-bindings: clock, reset: Add support for rk3576
> > DONOTMERGE: arm64: dts: rockchip: Add rk3576 SoC base DT
> > arm: rockchip: add RK3576-specific syscon ids
> >
> > Elaine Zhang (2):
> > clk: rockchip: Add rk3576 clk support
> > reset: rockchip: implement rk3576 lookup table
> >
> > Finley Xiao (1):
> > dt-bindings: power: Add support for RK3576 SoC
> >
> > Heiko Stuebner (11):
> > dt-bindings: clock, reset: fix top-comment indentation rk3576 headers
> > DONOTMERGE: arm64: dts: rockchip: add rk3576 otp node
> > DONOTMERGE: dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC
> > binding
> > DONOTMERGE: arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC
> > rockchip: sdram: honor CFG_SYS_SDRAM_BASE when defining ram regions
> > ram: rockchip: Add rk3576 ddr driver support
> > rockchip: otp: Add support for RK3576
> > mmc: rockchip_sdhci: Add support for RK3576
> > mmc: rockchip_dw_mmc: Add support for rk3576
> > net: dwc_eth_qos_rockchip: Add support for RK3576
> > rockchip: rk3576: Add support for ROC-RK3576-PC board
> >
> > Steven Liu (1):
> > pinctrl: rockchip: support rk3576 pinctrl
> >
> > Xuhui Lin (2):
> > rockchip: mkimage: Add rk3576 support
> > arm: rockchip: Add RK3576 arch core support
> >
> > arch/arm/dts/rk3576-roc-pc-u-boot.dtsi | 12 +
> > arch/arm/dts/rk3576-u-boot.dtsi | 119 +
> > arch/arm/include/asm/arch-rk3576/boot0.h | 11 +
> > arch/arm/include/asm/arch-rk3576/gpio.h | 11 +
> > arch/arm/include/asm/arch-rockchip/clock.h | 12 +
> > .../include/asm/arch-rockchip/cru_rk3576.h | 486 ++
> > .../include/asm/arch-rockchip/grf_rk3576.h | 225 +
> > .../include/asm/arch-rockchip/ioc_rk3576.h | 244 +
> > arch/arm/mach-rockchip/Kconfig | 46 +-
> > arch/arm/mach-rockchip/Makefile | 1 +
> > arch/arm/mach-rockchip/rk3576/Kconfig | 57 +
> > arch/arm/mach-rockchip/rk3576/Makefile | 9 +
> > arch/arm/mach-rockchip/rk3576/clk_rk3576.c | 32 +
> > arch/arm/mach-rockchip/rk3576/rk3576.c | 169 +
> > arch/arm/mach-rockchip/rk3576/syscon_rk3576.c | 26 +
> > arch/arm/mach-rockchip/sdram.c | 11 +-
> > board/firefly/roc-pc-rk3576/Kconfig | 12 +
> > board/firefly/roc-pc-rk3576/MAINTAINERS | 7 +
> > configs/roc-pc-rk3576_defconfig | 77 +
> > doc/board/rockchip/rockchip.rst | 12 +
> > drivers/clk/rockchip/Makefile | 1 +
> > drivers/clk/rockchip/clk_rk3576.c | 2517 +++++++
> > drivers/misc/rockchip-otp.c | 11 +
> > drivers/mmc/rockchip_dw_mmc.c | 1 +
> > drivers/mmc/rockchip_sdhci.c | 12 +
> > drivers/net/dwc_eth_qos.c | 4 +
> > drivers/net/dwc_eth_qos_rockchip.c | 141 +-
> > drivers/pinctrl/rockchip/Makefile | 1 +
> > drivers/pinctrl/rockchip/pinctrl-rk3576.c | 287 +
> > drivers/pinctrl/rockchip/pinctrl-rockchip.h | 3 +
> > drivers/ram/rockchip/Makefile | 1 +
> > drivers/ram/rockchip/sdram_rk3576.c | 65 +
> > drivers/reset/Makefile | 2 +-
> > drivers/reset/rst-rk3576.c | 647 ++
> > dts/upstream/Bindings/arm/rockchip.yaml | 5 +
> > .../Bindings/clock/rockchip,rk3576-cru.yaml | 56 +
> > .../power/rockchip,power-controller.yaml | 1 +
> > .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++
> > .../dt-bindings/power/rockchip,rk3576-power.h | 30 +
> > .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 ++
> > .../src/arm64/rockchip/rk3576-pinctrl.dtsi | 5775 +++++++++++++++++
> > .../src/arm64/rockchip/rk3576-roc-pc.dts | 736 +++
> > dts/upstream/src/arm64/rockchip/rk3576.dtsi | 1717 +++++
> > include/configs/rk3576_common.h | 42 +
> > include/configs/roc-pc-rk3576.h | 15 +
> > tools/rkcommon.c | 1 +
> > 46 files changed, 14798 insertions(+), 8 deletions(-)
> > create mode 100644 arch/arm/dts/rk3576-roc-pc-u-boot.dtsi
> > create mode 100644 arch/arm/dts/rk3576-u-boot.dtsi
> > create mode 100644 arch/arm/include/asm/arch-rk3576/boot0.h
> > create mode 100644 arch/arm/include/asm/arch-rk3576/gpio.h
> > create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3576.h
> > create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3576.h
> > create mode 100644 arch/arm/include/asm/arch-rockchip/ioc_rk3576.h
> > create mode 100644 arch/arm/mach-rockchip/rk3576/Kconfig
> > create mode 100644 arch/arm/mach-rockchip/rk3576/Makefile
> > create mode 100644 arch/arm/mach-rockchip/rk3576/clk_rk3576.c
> > create mode 100644 arch/arm/mach-rockchip/rk3576/rk3576.c
> > create mode 100644 arch/arm/mach-rockchip/rk3576/syscon_rk3576.c
> > create mode 100644 board/firefly/roc-pc-rk3576/Kconfig
> > create mode 100644 board/firefly/roc-pc-rk3576/MAINTAINERS
> > create mode 100644 configs/roc-pc-rk3576_defconfig
> > create mode 100644 drivers/clk/rockchip/clk_rk3576.c
> > create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3576.c
> > create mode 100644 drivers/ram/rockchip/sdram_rk3576.c
> > create mode 100644 drivers/reset/rst-rk3576.c
> > create mode 100644 dts/upstream/Bindings/clock/rockchip,rk3576-cru.yaml
> > create mode 100644 dts/upstream/include/dt-bindings/clock/rockchip,rk3576-cru.h
> > create mode 100644 dts/upstream/include/dt-bindings/power/rockchip,rk3576-power.h
> > create mode 100644 dts/upstream/include/dt-bindings/reset/rockchip,rk3576-cru.h
> > create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-pinctrl.dtsi
> > create mode 100644 dts/upstream/src/arm64/rockchip/rk3576-roc-pc.dts
> > create mode 100644 dts/upstream/src/arm64/rockchip/rk3576.dtsi
> > create mode 100644 include/configs/rk3576_common.h
> > create mode 100644 include/configs/roc-pc-rk3576.h
> >
>
^ permalink raw reply [flat|nested] 44+ messages in thread