[PATCH 0/4] rockchip: Always init clocks in SPL build for RK35xx

[PATCH 0/4] rockchip: Always init clocks in SPL build for RK35xx

[Jonas Karlman]

This series flag clock drivers for probe after bind in SPL builds for
a few RK35xx SoCs that require core PLLs and clocks to be initialized at
an early phase.

This should help e.g. ensure SPLL is initialized correctly on RK3588 and
CPU core rate is initialized on RK3576 when booting from RAM/USB.

The series may possible depend on the series "rockchip: Miscellaneous
RK35xx clock fixes" [1] for a clean apply.

[1] https://patchwork.ozlabs.org/cover/2278934/

Jonas Karlman (4):
  clk: rockchip: rk3568: Always init clocks in SPL build
  clk: rockchip: rk3588: Always init clocks in SPL build
  clk: rockchip: rk3576: Always init clocks in SPL build
  clk: rockchip: rk3528: Always init clocks in SPL build

 drivers/clk/rockchip/clk_rk3528.c |  4 ++++
 drivers/clk/rockchip/clk_rk3568.c |  4 ++++
 drivers/clk/rockchip/clk_rk3576.c |  4 ++++
 drivers/clk/rockchip/clk_rk3588.c | 14 ++++++++++++++
 4 files changed, 26 insertions(+)

-- 
2.54.0

[PATCH 1/4] clk: rockchip: rk3568: Always init clocks in SPL build

[Jonas Karlman]

The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.

Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3568.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk_rk3568.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index 9f3e9322161e..5a05f1b4de00 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -2934,6 +2934,10 @@ static int rk3568_clk_bind(struct udevice *dev)
 	struct udevice *sys_child;
 	struct sysreset_reg *priv;
 
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 				 &sys_child);
-- 
2.54.0

Re: [PATCH 1/4] clk: rockchip: rk3568: Always init clocks in SPL build

[Simon Glass]

Hi Jonas,

On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
> clk: rockchip: rk3568: Always init clocks in SPL build
>
> The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.

>
> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3568.

Just to check: "is initialized to 150 MHz" reads as if this already
happens. My understanding is that probe() contains the ACLK_BUS setup,
but nothing forces the CRU to be probed in SPL, so it is silently
skipped. Please spell that out - something like "the clock driver is
currently only probed on demand, so the ACLK_BUS init in probe() is
skipped when no SPL consumer references it" - so the motivation
matches the speedup Alexey reported on the rk3576 patch.

>
> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3568.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>
> drivers/clk/rockchip/clk_rk3568.c | 4 ++++
>  1 file changed, 4 insertions(+)

> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
> @@ -2938,6 +2938,10 @@ static int rk3568_clk_bind(struct udevice *dev)
>       struct udevice *sys_child;
>       struct sysreset_reg *priv;
>
> +     /* Ensure clocks are initialized after bind in SPL build */
> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> +

Have you considered marking the CRU node bootph-all (or equivalent) in
the DT instead? That is the more usual DM way to force a device up
early, and it avoids sprinkling a phase check into every SoC driver.
If PROBE_AFTER_BIND is genuinely the right hammer here, please add a
note in the commit message explaining why.

Regards,
Simon

Re: [PATCH 1/4] clk: rockchip: rk3568: Always init clocks in SPL build

[Jonas Karlman]

Hi Simon,

On 8/8/2026 7:30 PM, Simon Glass wrote:
> Hi Jonas,
> 
> On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
>> clk: rockchip: rk3568: Always init clocks in SPL build
>>
>> The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.
> 
>>
>> Ensure clock driver is always probed after bind for SPL builds to
>> initialize core PLLs and clocks in SPL phase on RK3568.
> 
> Just to check: "is initialized to 150 MHz" reads as if this already
> happens. My understanding is that probe() contains the ACLK_BUS setup,
> but nothing forces the CRU to be probed in SPL, so it is silently
> skipped. Please spell that out - something like "the clock driver is
> currently only probed on demand, so the ACLK_BUS init in probe() is
> skipped when no SPL consumer references it" - so the motivation
> matches the speedup Alexey reported on the rk3576 patch.

Correct, I will reword the commit message.

Unless the clock driver is probed in SPL, the ACLK_BUS never gets
initialized to 150 MHz.

> 
>>
>> Ensure clock driver is always probed after bind for SPL builds to
>> initialize core PLLs and clocks in SPL phase on RK3568.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>>
>> drivers/clk/rockchip/clk_rk3568.c | 4 ++++
>>  1 file changed, 4 insertions(+)
> 
>> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
>> @@ -2938,6 +2938,10 @@ static int rk3568_clk_bind(struct udevice *dev)
>>       struct udevice *sys_child;
>>       struct sysreset_reg *priv;
>>
>> +     /* Ensure clocks are initialized after bind in SPL build */
>> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
>> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
>> +
> 
> Have you considered marking the CRU node bootph-all (or equivalent) in
> the DT instead? That is the more usual DM way to force a device up
> early, and it avoids sprinkling a phase check into every SoC driver.
> If PROBE_AFTER_BIND is genuinely the right hammer here, please add a
> note in the commit message explaining why.

Use of bootph-all does not automatically triggers probe of the device.

The main issue is the on demand driver probing, and depending on what
boot source is used the clock driver may never be probed in SPL, e.g.
when booting from RAM/USB.

We should possible move out some of these one-time clock initialization
into e.g. arch_cpu_init() or similar in future to avoid having to use
probe after bind.

Regards,
Jonas

> 
> Regards,
> Simon

Re: [PATCH 1/4] clk: rockchip: rk3568: Always init clocks in SPL build

[Simon Glass]

Hi Jonas,

On Sat, 8 Aug 2026 at 13:33, Jonas Karlman <jonas@kwiboo.se> wrote:
>
> Hi Simon,
>
> On 8/8/2026 7:30 PM, Simon Glass wrote:
> > Hi Jonas,
> >
> > On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
> >> clk: rockchip: rk3568: Always init clocks in SPL build
> >>
> >> The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.
> >
> >>
> >> Ensure clock driver is always probed after bind for SPL builds to
> >> initialize core PLLs and clocks in SPL phase on RK3568.
> >
> > Just to check: "is initialized to 150 MHz" reads as if this already
> > happens. My understanding is that probe() contains the ACLK_BUS setup,
> > but nothing forces the CRU to be probed in SPL, so it is silently
> > skipped. Please spell that out - something like "the clock driver is
> > currently only probed on demand, so the ACLK_BUS init in probe() is
> > skipped when no SPL consumer references it" - so the motivation
> > matches the speedup Alexey reported on the rk3576 patch.
>
> Correct, I will reword the commit message.
>
> Unless the clock driver is probed in SPL, the ACLK_BUS never gets
> initialized to 150 MHz.
>
> >
> >>
> >> Ensure clock driver is always probed after bind for SPL builds to
> >> initialize core PLLs and clocks in SPL phase on RK3568.
> >>
> >> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> >>
> >> drivers/clk/rockchip/clk_rk3568.c | 4 ++++
> >>  1 file changed, 4 insertions(+)
> >
> >> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
> >> @@ -2938,6 +2938,10 @@ static int rk3568_clk_bind(struct udevice *dev)
> >>       struct udevice *sys_child;
> >>       struct sysreset_reg *priv;
> >>
> >> +     /* Ensure clocks are initialized after bind in SPL build */
> >> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
> >> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> >> +
> >
> > Have you considered marking the CRU node bootph-all (or equivalent) in
> > the DT instead? That is the more usual DM way to force a device up
> > early, and it avoids sprinkling a phase check into every SoC driver.
> > If PROBE_AFTER_BIND is genuinely the right hammer here, please add a
> > note in the commit message explaining why.
>
> Use of bootph-all does not automatically triggers probe of the device.
>
> The main issue is the on demand driver probing, and depending on what
> boot source is used the clock driver may never be probed in SPL, e.g.
> when booting from RAM/USB.

Ah yes, good point. I had assumed that any boot device would request the clock.

>
> We should possible move out some of these one-time clock initialization
> into e.g. arch_cpu_init() or similar in future to avoid having to use
> probe after bind.

Also if you just need it to be done before booting, I suppose it could
be done later. But what you have sems fine.

So with the reword:

Reviewed-by: Simon Glass <sjg@chromium.org>

Regards,
Simon

Re: [PATCH 1/4] clk: rockchip: rk3568: Always init clocks in SPL build

[Quentin Schulz]

Hi Jonas,

On 8/4/26 2:26 AM, Jonas Karlman wrote:
> The ACLK_BUS clock is initialized to 150 MHz in SPL on RK3568.
> 
> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3568.
> 

You explain what this does but not why? What are the symptoms? Why is 
this the proper way to fix the issue?

Based on Heiko's message, I'm guessing the issue is that we need 
something to setup clocks that are only accessible from the secure world 
and SPL happens to be running in it, but not proper (nor is the kernel). 
Hence why Heiko needs this in order for the "DSI panel to work again" 
(I'm assuming in the kernel hence why any fix in any driver/device tree 
to enable the clock is not gonna help with the issue).

This seems to be a bandaid patch instead of fixing the issue (that is, 
the kernel should enable/control this clock through some mechanisms, 
e.g. by interacting with TF-A through SCMI).

Heiko also said "my DSI panel work again" which implies it worked at 
some point and got broken since, so it'd be nice to know what broke it 
so we can have all the clues necessary to fix the issue in the long 
term. Considering we broke something, I won't resist too much on this 
patch even though based on the above guesses we're fixing a kernel bug 
in U-Boot.

Can you please confirm my guess or clarify?

Cheers,
Quentin

> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
>   drivers/clk/rockchip/clk_rk3568.c | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
> index 9f3e9322161e..5a05f1b4de00 100644
> --- a/drivers/clk/rockchip/clk_rk3568.c
> +++ b/drivers/clk/rockchip/clk_rk3568.c
> @@ -2934,6 +2934,10 @@ static int rk3568_clk_bind(struct udevice *dev)
>   	struct udevice *sys_child;
>   	struct sysreset_reg *priv;
>   
> +	/* Ensure clocks are initialized after bind in SPL build */
> +	if (IS_ENABLED(CONFIG_SPL_BUILD))
> +		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> +
>   	/* The reset driver does not have a device node, so bind it here */
>   	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
>   				 &sys_child);

[PATCH 2/4] clk: rockchip: rk3588: Always init clocks in SPL build

[Jonas Karlman]

The CPU PLLs and SPLL are only initialized in SPL on RK3588.

Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk_rk3588.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
index 5236c3fa985e..5313457aec92 100644
--- a/drivers/clk/rockchip/clk_rk3588.c
+++ b/drivers/clk/rockchip/clk_rk3588.c
@@ -2004,6 +2004,10 @@ static int rk3588_clk_bind(struct udevice *dev)
 	struct udevice *sys_child;
 	struct sysreset_reg *priv;
 
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 				 &sys_child);
@@ -2133,6 +2137,15 @@ static int rk3588_scru_clk_probe(struct udevice *dev)
 	return 0;
 }
 
+static int rk3588_scru_clk_bind(struct udevice *dev)
+{
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+	return 0;
+}
+
 static const struct clk_ops rk3588_scru_clk_ops = {
 	.get_rate = rk3588_scru_clk_get_rate,
 	.set_rate = rk3588_scru_clk_set_rate,
@@ -2142,6 +2155,7 @@ U_BOOT_DRIVER(rockchip_rk3588_scru) = {
 	.name	= "rockchip_rk3588_scru",
 	.id	= UCLASS_CLK,
 	.ops	= &rk3588_scru_clk_ops,
+	.bind	= rk3588_scru_clk_bind,
 	.probe	= rk3588_scru_clk_probe,
 };
 
-- 
2.54.0

Re: [PATCH 2/4] clk: rockchip: rk3588: Always init clocks in SPL build

[Simon Glass]

Hi Jonas,

On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
> clk: rockchip: rk3588: Always init clocks in SPL build
>
> The CPU PLLs and SPLL are only initialized in SPL on RK3588.
>
> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3588.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>
> drivers/clk/rockchip/clk_rk3588.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)

> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
> @@ -2138,6 +2142,15 @@ static int rk3588_scru_clk_probe(struct udevice *dev)
>       return 0;
>  }
>
> +static int rk3588_scru_clk_bind(struct udevice *dev)
> +{
> +     /* Ensure clocks are initialized after bind in SPL build */
> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> +
> +     return 0;
> +}

The entire SCRU section starting at line 2052 is wrapped in #ifdef
CONFIG_XPL_BUILD, so this bind function only exists in an XPL build -
s0 are you specifically wanting this to only happen in the SPL phase?
If so, I think you should use xpl_phase() == PHASE_SPL

> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
> @@ -2009,6 +2009,10 @@ static int rk3588_clk_bind(struct udevice *dev)
>       struct udevice *sys_child;
>       struct sysreset_reg *priv;
>
> +     /* Ensure clocks are initialized after bind in SPL build */
> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
> +

Same question here.

Regards,
Simon

Re: [PATCH 2/4] clk: rockchip: rk3588: Always init clocks in SPL build

[Jonas Karlman]

Hi Simon,

On 8/8/2026 7:32 PM, Simon Glass wrote:
> Hi Jonas,
> 
> On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
>> clk: rockchip: rk3588: Always init clocks in SPL build
>>
>> The CPU PLLs and SPLL are only initialized in SPL on RK3588.
>>
>> Ensure clock driver is always probed after bind for SPL builds to
>> initialize core PLLs and clocks in SPL phase on RK3588.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>>
>> drivers/clk/rockchip/clk_rk3588.c | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
> 
>> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
>> @@ -2138,6 +2142,15 @@ static int rk3588_scru_clk_probe(struct udevice *dev)
>>       return 0;
>>  }
>>
>> +static int rk3588_scru_clk_bind(struct udevice *dev)
>> +{
>> +     /* Ensure clocks are initialized after bind in SPL build */
>> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
>> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
>> +
>> +     return 0;
>> +}
> 
> The entire SCRU section starting at line 2052 is wrapped in #ifdef
> CONFIG_XPL_BUILD, so this bind function only exists in an XPL build -
> s0 are you specifically wanting this to only happen in the SPL phase?
> If so, I think you should use xpl_phase() == PHASE_SPL

Correct, this should only happen in SPL builds, as originally intended.

The change to XPL came from "drivers: Use CONFIG_XPL_BUILD instead of
CONFIG_SPL_BUILD" and you not wanting to address my remarks about the
unintended changes for the Rockchip platform ;-)

I have future refactoring plans for all RK35xx clock drivers, e.g.
change to use FIELD_PREP_WM16 and more, was hoping to defer the
unintended use of XPL_BUILD until such future series.

For now we only have SPL support for RK35xx, so the mixed use of XPL and
SPL have no real difference until that changes.

Regards,
Jonas

> 
>> diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c
>> @@ -2009,6 +2009,10 @@ static int rk3588_clk_bind(struct udevice *dev)
>>       struct udevice *sys_child;
>>       struct sysreset_reg *priv;
>>
>> +     /* Ensure clocks are initialized after bind in SPL build */
>> +     if (IS_ENABLED(CONFIG_SPL_BUILD))
>> +             dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
>> +
> 
> Same question here.
> 
> Regards,
> Simon

[PATCH 3/4] clk: rockchip: rk3576: Always init clocks in SPL build

[Jonas Karlman]

The ore PLLs are only initialized in SPL on RK3576.

Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3576.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk_rk3576.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c
index 75b705ffba2f..1988f0472dec 100644
--- a/drivers/clk/rockchip/clk_rk3576.c
+++ b/drivers/clk/rockchip/clk_rk3576.c
@@ -2526,6 +2526,10 @@ static int rk3576_clk_bind(struct udevice *dev)
 	struct udevice *sys_child;
 	struct sysreset_reg *priv;
 
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 				 &sys_child);
-- 
2.54.0

Re: [PATCH 3/4] clk: rockchip: rk3576: Always init clocks in SPL build

[Alexey Charkov]

Hi Jonas,

Thanks a lot for your work on this!

On Tue, Aug 4, 2026 at 4:26 AM Jonas Karlman <jonas@kwiboo.se> wrote:
>
> The ore PLLs are only initialized in SPL on RK3576.

/s/ore/core/ ?

> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3576.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> ---
>  drivers/clk/rockchip/clk_rk3576.c | 4 ++++
>  1 file changed, 4 insertions(+)

Tested it with my 41MB Falcon Linux payload on a Flipper One (RK3576),
and it gives a very noticeable improvement in loading speed: time from
start of BL33 to initramfs goes down from ~20s to ~3s, which is quite
welcome :)

Tested-by: Alexey Charkov <alchark@flipper.net>

Best regards,
Alexey

Re: [PATCH 3/4] clk: rockchip: rk3576: Always init clocks in SPL build

[Jonas Karlman]

Hi Alexey,

On 8/5/2026 9:21 AM, Alexey Charkov wrote:
> Hi Jonas,
> 
> Thanks a lot for your work on this!

Thanks for testing!

I think using the 'probe after bind' flag ended up being the most
logical way to ensure the clocks are initialized early in SPL.

> 
> On Tue, Aug 4, 2026 at 4:26 AM Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> The ore PLLs are only initialized in SPL on RK3576.
> 
> /s/ore/core/ ?

Hehe, correct, my bad, that is what happens when one tries to send out
patches in the middle of the night ;-)

Will send a v2 unless Quentin wants to fixup when applying.

Regards,
Jonas

> 
>> Ensure clock driver is always probed after bind for SPL builds to
>> initialize core PLLs and clocks in SPL phase on RK3576.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> ---
>>  drivers/clk/rockchip/clk_rk3576.c | 4 ++++
>>  1 file changed, 4 insertions(+)
> 
> Tested it with my 41MB Falcon Linux payload on a Flipper One (RK3576),
> and it gives a very noticeable improvement in loading speed: time from
> start of BL33 to initramfs goes down from ~20s to ~3s, which is quite
> welcome :)
> 
> Tested-by: Alexey Charkov <alchark@flipper.net>
> 
> Best regards,
> Alexey

Re: [PATCH 3/4] clk: rockchip: rk3576: Always init clocks in SPL build

[Quentin Schulz]

Hi Alexey, Jonas,

On 8/5/26 9:21 AM, Alexey Charkov wrote:
> Hi Jonas,
> 
> Thanks a lot for your work on this!
> 
> On Tue, Aug 4, 2026 at 4:26 AM Jonas Karlman <jonas@kwiboo.se> wrote:
>>
>> The ore PLLs are only initialized in SPL on RK3576.
> 
> /s/ore/core/ ?
> 
>> Ensure clock driver is always probed after bind for SPL builds to
>> initialize core PLLs and clocks in SPL phase on RK3576.
>>
>> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
>> ---
>>   drivers/clk/rockchip/clk_rk3576.c | 4 ++++
>>   1 file changed, 4 insertions(+)
> 
> Tested it with my 41MB Falcon Linux payload on a Flipper One (RK3576),
> and it gives a very noticeable improvement in loading speed: time from
> start of BL33 to initramfs goes down from ~20s to ~3s, which is quite
> welcome :)
> 

OK but why this improvement? Which clock(s) is responsible for this 
speed improvement? This sounds a bit like CPU OPPs without controlling 
the regulator and it worries me, but maybe I'm wrong here?

Please help me understand what this actually fixes/helps with and how.

Cheers,
Quentin

Re: [PATCH 3/4] clk: rockchip: rk3576: Always init clocks in SPL build

[Simon Glass]

Hi Jonas,

On 2026-08-04T00:26:39, Jonas Karlman <jonas@kwiboo.se> wrote:
> clk: rockchip: rk3576: Always init clocks in SPL build

>
> The ore PLLs are only initialized in SPL on RK3576.

Typo — ore should be core.

>
> The ore PLLs are only initialized in SPL on RK3576.
>
> Ensure clock driver is always probed after bind for SPL builds to
> initialize core PLLs and clocks in SPL phase on RK3576.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Tested-by: Alexey Charkov <alchark@flipper.net>
>
> drivers/clk/rockchip/clk_rk3576.c | 4 ++++
>  1 file changed, 4 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

Regards,
Simon

[PATCH 4/4] clk: rockchip: rk3528: Always init clocks in SPL build

[Jonas Karlman]

The core PLLs and clocks are only initialized in SPL on RK3528.

Ensure clock driver is always probed after bind for SPL builds to
initialize core PLLs and clocks in SPL phase on RK3528.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk_rk3528.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c
index 83e302dbc3c4..976ef0e0a919 100644
--- a/drivers/clk/rockchip/clk_rk3528.c
+++ b/drivers/clk/rockchip/clk_rk3528.c
@@ -1715,6 +1715,10 @@ static int rk3528_clk_bind(struct udevice *dev)
 	struct sysreset_reg *priv;
 	int ret;
 
+	/* Ensure clocks are initialized after bind in SPL build */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
 	/* The reset driver does not have a device node, so bind it here */
 	ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
 				 &sys_child);
-- 
2.54.0

Re: [PATCH 0/4] rockchip: Always init clocks in SPL build for RK35xx

[Heiko Stübner]

Am Dienstag, 4. August 2026, 02:26:38 Mitteleuropäische Sommerzeit schrieb Jonas Karlman:
> This series flag clock drivers for probe after bind in SPL builds for
> a few RK35xx SoCs that require core PLLs and clocks to be initialized at
> an early phase.
> 
> This should help e.g. ensure SPLL is initialized correctly on RK3588 and
> CPU core rate is initialized on RK3576 when booting from RAM/USB.
> 
> The series may possible depend on the series "rockchip: Miscellaneous
> RK35xx clock fixes" [1] for a clean apply.
> 
> [1] https://patchwork.ozlabs.org/cover/2278934/

Tested-by: Heiko Stuebner <heiko@sntech.de>

This and the misc fixes series together make my DSI panel work again,
which seemingly broke somewhere in between.

Thanks
Heiko