* [U-Boot-Users] [PATCH v3] Add MIMC200 board
@ 2008-07-30 9:14 Mark Jackson
2008-07-30 10:24 ` Wolfgang Denk
0 siblings, 1 reply; 2+ messages in thread
From: Mark Jackson @ 2008-07-30 9:14 UTC (permalink / raw)
To: u-boot
The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM.
---
CREDITS | 4 +
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/mimc/mimc200/Makefile | 40 ++++++++
board/mimc/mimc200/config.mk | 3 +
board/mimc/mimc200/mimc200.c | 209 +++++++++++++++++++++++++++++++++++++++++
board/mimc/mimc200/u-boot.lds | 73 ++++++++++++++
common/console.c | 5 +
include/configs/mimc200.h | 177 ++++++++++++++++++++++++++++++++++
10 files changed, 519 insertions(+), 0 deletions(-)
diff --git a/CREDITS b/CREDITS
index 2b0dab7..5010c78 100644
--- a/CREDITS
+++ b/CREDITS
@@ -217,6 +217,10 @@ H: Rich Ireland
E: r.ireland at computer.org
D: FPGA device configuration driver
+H: Mark Jackson
+E: mpfj at mimc.co.uk
+D: Port to MIMC200 board
+
N: Gary Jennejohn
E: garyj at jennejohn.org, gj at denx.de
D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB"
diff --git a/MAINTAINERS b/MAINTAINERS
index cbe5c47..d4f6639 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -709,6 +709,10 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
ATSTK1006 AT32AP7000
ATNGW100 AT32AP7000
+Mark Jackson <mpfj@mimc.co.uk>
+
+ MIMC200 AT32AP7000
+
#########################################################################
# SuperH Systems: #
# #
diff --git a/MAKEALL b/MAKEALL
index c1a9c60..cfd376c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -715,6 +715,7 @@ LIST_avr32=" \
atstk1004 \
atstk1006 \
atngw100 \
+ mimc200 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index 369bbd7..d434ea3 100644
--- a/Makefile
+++ b/Makefile
@@ -2914,6 +2914,9 @@ atstk1004_config : unconfig
atstk1006_config : unconfig
@$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x
+mimc200_config : unconfig
+ @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
+
#========================================================================
# SH3 (SuperH)
#========================================================================
diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile
new file mode 100644
index 0000000..9f3849f
--- /dev/null
+++ b/board/mimc/mimc200/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2005-2006 Atmel Corporation
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB := $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/mimc/mimc200/config.mk b/board/mimc/mimc200/config.mk
new file mode 100644
index 0000000..9a794e5
--- /dev/null
+++ b/board/mimc/mimc200/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE = 0x00000000
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS += --gc-sections
diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c
new file mode 100644
index 0000000..089fc6c
--- /dev/null
+++ b/board/mimc/mimc200/mimc200.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <lcd.h>
+
+#define SM_PM_GCCTRL 0x0060
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+ .data_bits = SDRAM_DATA_16BIT,
+ .row_bits = 13,
+ .col_bits = 9,
+ .bank_bits = 2,
+ .cas = 3,
+ .twr = 2,
+ .trc = 6,
+ .trp = 2,
+ .trcd = 2,
+ .tras = 6,
+ .txsr = 6,
+ /* 15.6 us */
+ .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
+};
+
+int board_early_init_f(void)
+{
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+ gpio_enable_ebi();
+ gpio_enable_usart1();
+
+ /* enable higher address lines for larger flash devices */
+ gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */
+ gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */
+ gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */
+
+ /* enable data flash chip select */
+ gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */
+
+ /* de-assert "force sys reset" pin */
+ gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */
+ gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT);
+
+ /* init custom i/o */
+ /* cpu type inputs */
+ gpio_select_pio(GPIO_PIN_PE19, 0);
+ gpio_select_pio(GPIO_PIN_PE20, 0);
+ gpio_select_pio(GPIO_PIN_PE23, 0);
+ /* main board type inputs */
+ gpio_select_pio(GPIO_PIN_PB19, 0);
+ gpio_select_pio(GPIO_PIN_PB29, 0);
+ /* DEBUG input (use weak pullup) */
+ gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP);
+
+ /* are we suppressing the console ? */
+ if (gpio_get_value(GPIO_PIN_PE21) == 1)
+ {
+ gd->flags |= GD_FLG_SILENT;
+ }
+
+ /* reset phys */
+ gpio_select_pio(GPIO_PIN_PE24, 0);
+ gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */
+ gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT);
+
+ /* GCLK0 - 10MHz clock */
+ writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL);
+ gpio_select_periph_A(GPIO_PIN_PA30, 0);
+
+ udelay(5000);
+
+ /* release phys reset */
+ gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */
+
+#if defined(CONFIG_MACB)
+ /* init macb0 pins */
+ gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
+ gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
+ gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
+ gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
+ gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
+ gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
+ gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
+ gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
+ gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
+ gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
+#if !defined(CONFIG_RMII)
+ gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
+ gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
+ gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
+ gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
+ gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
+ gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
+ gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
+ gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
+#endif
+
+ /* init macb1 pins */
+ gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
+ gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
+ gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
+ gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
+ gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
+ gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
+ gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
+ gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
+ gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
+ gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
+#if !defined(CONFIG_RMII)
+ gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
+ gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
+ gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
+ gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
+ gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
+ gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
+ gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
+ gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
+#endif
+#endif
+
+#if defined(CONFIG_MMC)
+ gpio_enable_mmci();
+#endif
+
+ return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
+}
+
+void board_init_info(void)
+{
+ gd->bd->bi_phy_id[0] = 0x01;
+ gd->bd->bi_phy_id[1] = 0x03;
+}
+
+/* SPI chip select control */
+#ifdef CONFIG_ATMEL_SPI
+#include <spi.h>
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return (bus == 0) && (cs == 0);
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+#ifdef CONFIG_CMD_NET
+extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
+
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
+
+ return 0;
+}
+#endif
diff --git a/board/mimc/mimc200/u-boot.lds b/board/mimc/mimc200/u-boot.lds
new file mode 100644
index 0000000..e736adf
--- /dev/null
+++ b/board/mimc/mimc200/u-boot.lds
@@ -0,0 +1,73 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0;
+ _text = .;
+ .text : {
+ *(.exception.text)
+ *(.text)
+ *(.text.*)
+ }
+ _etext = .;
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+
+ . = ALIGN(8);
+ _data = .;
+ .data : {
+ *(.data)
+ *(.data.*)
+ }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : {
+ KEEP(*(.u_boot_cmd))
+ }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ _got = .;
+ .got : {
+ *(.got)
+ }
+ _egot = .;
+
+ . = ALIGN(8);
+ _edata = .;
+
+ .bss : {
+ *(.bss)
+ *(.bss.*)
+ }
+ . = ALIGN(8);
+ _end = .;
+}
diff --git a/common/console.c b/common/console.c
index 1b095b1..fc02e71 100644
--- a/common/console.c
+++ b/common/console.c
@@ -173,6 +173,11 @@ int getc (void)
int tstc (void)
{
+#if defined(CONFIG_SILENT_CONSOLE) && defined(CONFIG_SILENT_CONSOLE_INPUT)
+ if (gd->flags & GD_FLG_SILENT)
+ return 0;
+#endif
+
if (gd->flags & GD_FLG_DEVINIT) {
/* Test the standard input */
return ftstc (stdin);
diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h
new file mode 100644
index 0000000..3486be0
--- /dev/null
+++ b/include/configs/mimc200.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Configuration settings for the AVR32 Network Gateway
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/memory-map.h>
+
+#define CONFIG_AVR32 1
+#define CONFIG_AT32AP 1
+#define CONFIG_AT32AP7000 1
+#define CONFIG_MIMC200 1
+
+#define CONFIG_MIMC200_EXT_FLASH 1
+
+#define CFG_HZ 1000
+
+/*
+ * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL 1
+#define CFG_POWER_MANAGER 1
+#define CFG_OSC0_HZ 10000000
+#define CFG_PLL0_DIV 1
+#define CFG_PLL0_MUL 15
+#define CFG_PLL0_SUPPRESS_CYCLES 16
+#define CFG_CLKDIV_CPU 0
+#define CFG_CLKDIV_HSB 1
+#define CFG_CLKDIV_PBA 2
+#define CFG_CLKDIV_PBB 1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ * icp = PLLOPT<2>
+ * ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CFG_PLL0_OPT 0x04
+
+#define CONFIG_USART1 1
+#define CONFIG_MIMC200_DBGLINK 1
+
+/* User serviceable stuff */
+#define CONFIG_DOS_PARTITION 1
+
+#define CONFIG_CMDLINE_TAG 1
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_STACKSIZE (2048)
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS \
+ "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2"
+#define CONFIG_BOOTCOMMAND \
+ "fsload; bootm"
+
+#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
+#define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY 0
+#define CONFIG_ZERO_BOOTDELAY_CHECK 1
+#define CONFIG_AUTOBOOT 1
+
+/*
+ * After booting the board for the first time, new ethernet addresses
+ * should be generated and assigned to the environment variables
+ * "ethaddr" and "eth1addr". This is normally done during production.
+ */
+#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
+#define CONFIG_NET_MULTI 1
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+#define CONFIG_DOS_PARTITION 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_NET
+
+#define CONFIG_ATMEL_USART 1
+#define CONFIG_MACB 1
+#define CONFIG_PIO2 1
+#define CFG_NR_PIOS 5
+#define CFG_HSDRAMC 1
+#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
+
+#define CFG_DCACHE_LINESZ 32
+#define CFG_ICACHE_LINESZ 32
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CFG_FLASH_CFI 1
+#define CFG_FLASH_CFI_DRIVER 1
+
+#define CFG_FLASH_BASE 0x00000000
+#define CFG_FLASH_SIZE 0x800000
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_MAX_FLASH_SECT 135
+
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+
+#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE EBI_SDRAM_BASE
+
+#define CFG_FRAM_BASE 0x08000000
+#define CFG_FRAM_SIZE 0x20000
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 65536
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
+
+#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
+
+#define CFG_MALLOC_LEN (1024*1024)
+#define CFG_DMA_ALLOC_LEN (16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
+#define CFG_BOOTPARAMS_LEN (16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CFG_PROMPT "U-Boot> "
+#define CFG_CBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
+#define CFG_LONGHELP 1
+
+#define CFG_MEMTEST_START EBI_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
+
+#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
+
+#endif /* __CONFIG_H */
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [U-Boot-Users] [PATCH v3] Add MIMC200 board
2008-07-30 9:14 [U-Boot-Users] [PATCH v3] Add MIMC200 board Mark Jackson
@ 2008-07-30 10:24 ` Wolfgang Denk
0 siblings, 0 replies; 2+ messages in thread
From: Wolfgang Denk @ 2008-07-30 10:24 UTC (permalink / raw)
To: u-boot
In message <489030FA.2030908@mimc.co.uk> you wrote:
> The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM.
> ---
>
> CREDITS | 4 +
> MAINTAINERS | 4 +
> MAKEALL | 1 +
> Makefile | 3 +
> board/mimc/mimc200/Makefile | 40 ++++++++
> board/mimc/mimc200/config.mk | 3 +
> board/mimc/mimc200/mimc200.c | 209 +++++++++++++++++++++++++++++++++++++++++
> board/mimc/mimc200/u-boot.lds | 73 ++++++++++++++
> common/console.c | 5 +
> include/configs/mimc200.h | 177 ++++++++++++++++++++++++++++++++++
> 10 files changed, 519 insertions(+), 0 deletions(-)
Please splitt the changes to common/console.c into a separate patch.
And make sure to explain exactly why this is needed, and why you think
your implementation works (for example, why do you add the test only
to tstc() but not to getc() ?)
Without better explanations I reject the common/console.c part of the
patch.
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
CONSUMER NOTICE: Because of the "Uncertainty Principle," It Is
Impossible for the Consumer to Find Out at the Same Time Both
Precisely Where This Product Is and How Fast It Is Moving.
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2008-07-30 9:14 [U-Boot-Users] [PATCH v3] Add MIMC200 board Mark Jackson
2008-07-30 10:24 ` Wolfgang Denk
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