From: Neha Malcom Francis <n-francis@ti.com>
To: Bryan Brattlof <bb@ti.com>, Santhosh Kumar K <s-k6@ti.com>
Cc: <trini@konsulko.com>, <m-chawdhry@ti.com>, <nm@ti.com>,
<u-kumar1@ti.com>, <vigneshr@ti.com>, <u-boot@lists.denx.de>,
<w.egorov@phytec.de>
Subject: Re: [PATCH v4 5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC
Date: Thu, 24 Oct 2024 09:33:58 +0530 [thread overview]
Message-ID: <689bda91-9d6a-4ae4-9ccf-b2e5af6c53cd@ti.com> (raw)
In-Reply-To: <20241023144559.dtwggwlxwljpky6p@bryanbrattlof.com>
Hi Bryan
On 23/10/24 20:15, Bryan Brattlof wrote:
> On October 21, 2024 thus sayeth Santhosh Kumar K:
>> From: Neha Malcom Francis <n-francis@ti.com>
>>
>> Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL
>> only when the config has been enabled.
>>
>> Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
>> ---
>> drivers/ram/Kconfig | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
>> index f7e357f24da7..533d0c629a64 100644
>> --- a/drivers/ram/Kconfig
>> +++ b/drivers/ram/Kconfig
>> @@ -116,6 +116,16 @@ config IMXRT_SDRAM
>> to support external memories like sdram, psram & nand.
>> This driver is for the sdram memory interface with the SEMC.
>>
>> +config K3_INLINE_ECC
>> + bool "Enable TI Inline ECC support"
>> + depends on K3_DDRSS
>> + help
>> + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space
>> + is used for ECC storage and the rest 8/9th is available for system
>> + use. Enabling ECC increases boot time as the ECC protected regions
>> + need to be primed with a predefined value prior to enabling ECC
>> + check.
>> +
>
> I agree size will always be a complaint at such an early stage of boot
> but we're already adding the ECC configuration in the memory{} node.
>
> We should do one or the other but not both. It would be hard to debug
> problems if someone added the protected{} node but not enable this
> config
Actually I do agree with this, maybe we can get rid of the flag ti,ecc-enable
which is redundant. In multi-DDR systems, it was still a possibility that we
could use it to select the DDR we want ECC enabled on, but that hasn't been
tested nor does it make any sense since they'll be interleaved anyways.
--
Thanking You
Neha Malcom Francis
next prev parent reply other threads:[~2024-10-24 4:04 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-21 4:40 [PATCH v4 0/8] Inline ECC Series Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 1/8] ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 2/8] ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue Santhosh Kumar K
2024-10-23 4:44 ` Manorit Chawdhry
2024-12-12 14:38 ` Santhosh Kumar K
2024-10-23 14:39 ` Bryan Brattlof
2024-10-24 4:01 ` Neha Malcom Francis
2024-10-24 16:19 ` Bryan Brattlof
2024-12-06 12:53 ` Wadim Egorov
2024-12-06 17:40 ` Bryan Brattlof
2024-12-12 14:39 ` Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 3/8] ram: k3-ddrss: Setup ECC region start and range Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 4/8] ram: k3-ddrss: Enable ECC interrupts Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 5/8] drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC Santhosh Kumar K
2024-10-23 14:45 ` Bryan Brattlof
2024-10-24 4:03 ` Neha Malcom Francis [this message]
2024-12-12 14:39 ` Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 6/8] configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2 Santhosh Kumar K
2024-10-23 14:48 ` Bryan Brattlof
2024-12-12 14:40 ` Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 7/8] board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled Santhosh Kumar K
2024-10-22 10:04 ` Wadim Egorov
2024-12-12 14:40 ` Santhosh Kumar K
2024-10-21 4:40 ` [PATCH v4 8/8] arm: dts: k3-*-ddr: Add ss_cfg reg entry Santhosh Kumar K
2024-10-22 9:22 ` Neha Malcom Francis
2024-12-12 14:40 ` Santhosh Kumar K
2024-12-12 14:38 ` [PATCH v4 0/8] Inline ECC Series Santhosh Kumar K
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