[PATCH v2 0/8] Renesas RZ/N1 additional drivers

[PATCH v2 0/8] Renesas RZ/N1 additional drivers

[Ralph Siemsen]

Enable many more of the peripherals found on Renesas RZ/N1 SoC,
including GPIO, MMC, QSPI, NAND, Ethernet GMAC/switch/converters.

This builds on top of the basic support that was added in May 2023:
https://lists.u-boot-project.org/pipermail/u-boot/2023-May/518098.html

It has been tested on the Schneider RZ/N1 board, including support
for USB (DFU/fastboot/UMS) using the driver from Romain Gantois:
https://lists.u-boot-project.org/pipermail/u-boot/2026-July/623625.html

This patch series is based on v2026.10-rc2.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
Changes in v2:
- subsystem changes were split into separate patches:
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-pinctrl-v2-1-95dec872b1ca@linaro.org/T/#u
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-spi-v2-0-973d5fa092f2@linaro.org/T/#t
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-gpio-v2-1-7490cc61b337@linaro.org/
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-net-v2-0-ff03583dc2b0@linaro.org/T/#t
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-mmc-v2-1-51e4d8a717b8@linaro.org/T/#u
  https://lore.kernel.org/u-boot/20260814-rzn1-2026-10-nand-v2-1-7aadfa5ca3d4@linaro.org/
- also depends on the USB driver from Romain Gantois:
  https://lists.u-boot-project.org/pipermail/u-boot/2026-July/623625.html

To: u-boot@lists.u-boot-project.org
Cc: Ralph Siemsen <ralph.siemsen@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Udit Kumar <u-kumar1@ti.com>

---
Ralph Siemsen (8):
      board: schneider: rzn1-snarc: set serial number
      board: schneider: rzn1-snarc: add rzn1.env
      board: schneider: rzn1-snarc: update MAINTAINERS
      ARM: renesas: RZ/N1 QSPI controller features
      ARM: dts: r9a06g032: sync with upstream
      ARM: dts: r9a06g032: add QSPI controller
      ARM: dts: r9a06g032-rzn1-snarc: enable new drivers
      configs: rzn1_snarc_defconfig: enable new drivers

 arch/arm/dts/r9a06g032-rzn1-snarc.dts  | 376 ++++++++++++++++++++++++++++++++-
 arch/arm/dts/r9a06g032.dtsi            | 282 +++++++++++++++++++++++--
 arch/arm/mach-renesas/Kconfig          |   4 +
 board/schneider/rzn1-snarc/MAINTAINERS |   3 +
 board/schneider/rzn1-snarc/rzn1.c      |  25 +++
 board/schneider/rzn1-snarc/rzn1.env    |  21 ++
 configs/rzn1_snarc_defconfig           |  76 +++++++
 include/configs/rzn1-snarc.h           |   5 +
 8 files changed, 771 insertions(+), 21 deletions(-)
---
base-commit: 36c377b9859ffb53eb1e39ea31e8d96d1e0fe1e5
change-id: 20260811-rzn1-2026-10-e7e9695debbf

Best regards,
--  
Ralph Siemsen <ralph.siemsen@linaro.org>

[PATCH v2 1/8] board: schneider: rzn1-snarc: set serial number

[Ralph Siemsen]

Obtain the board serial number from OTP. Make it visible in the
'serial#' environment variable, and also in DFU/fastboot/UMS mode.

This helps to distinguish multiple boards connected to the same LAVA
controller.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 board/schneider/rzn1-snarc/rzn1.c | 25 +++++++++++++++++++++++++
 include/configs/rzn1-snarc.h      |  5 +++++
 2 files changed, 30 insertions(+)

diff --git a/board/schneider/rzn1-snarc/rzn1.c b/board/schneider/rzn1-snarc/rzn1.c
index e1d5b5b0497..38aa2ed9d4e 100644
--- a/board/schneider/rzn1-snarc/rzn1.c
+++ b/board/schneider/rzn1-snarc/rzn1.c
@@ -1,11 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0+
 
+#include <asm/io.h>
+#include <configs/rzn1-snarc.h>
 #include <dm.h>
+#include <env.h>
+#include <g_dnl.h>
 #include <ram.h>
 #include <asm/global_data.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static inline uint32_t hosted_readl(uint32_t addr)
+{
+	/* No hypervisor yet, just do a direct read */
+	return readl(addr);
+}
+
 int board_init(void)
 {
 	gd->bd->bi_boot_params = gd->ram_base + 0x100;
@@ -13,6 +23,21 @@ int board_init(void)
 	return 0;
 }
 
+int board_late_init(void)
+{
+	char serial_string[32];
+
+	/* Obtain serial number from OTP */
+	snprintf(serial_string, sizeof(serial_string),
+		 "LCES2-0x%08x%08x",
+		 hosted_readl(RZN1_SERIAL_LOW),
+		 hosted_readl(RZN1_SERIAL_HIGH));
+	env_set("serial#", serial_string);
+	g_dnl_set_serialnumber((char *)serial_string);
+
+	return 0;
+}
+
 int dram_init(void)
 {
 	struct udevice *dev;
diff --git a/include/configs/rzn1-snarc.h b/include/configs/rzn1-snarc.h
index 9fee2ece54a..75fada671af 100644
--- a/include/configs/rzn1-snarc.h
+++ b/include/configs/rzn1-snarc.h
@@ -10,4 +10,9 @@
 #define CFG_SYS_INIT_RAM_ADDR	0x20000000
 #define CFG_SYS_INIT_RAM_SIZE	(1 * 1024 * 1024)
 
+/* One-time programmable OTP */
+#define RZN1_OTP_BASE		0x40007000
+#define   RZN1_SERIAL_LOW	(RZN1_OTP_BASE + 0x08)
+#define   RZN1_SERIAL_HIGH	(RZN1_OTP_BASE + 0x0c)
+
 #endif	/* __RZN1_SNARC_H */

-- 
2.55.0

[PATCH v2 2/8] board: schneider: rzn1-snarc: add rzn1.env

[Ralph Siemsen]

Add default u-boot environment for Schneider RZ/N1 board:
- Ethernet: default MAC addresses, use end1 interface
- dfu_alt_info partitions for DFU
- legacy bootargs

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 board/schneider/rzn1-snarc/rzn1.env | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/board/schneider/rzn1-snarc/rzn1.env b/board/schneider/rzn1-snarc/rzn1.env
new file mode 100644
index 00000000000..bc4f7e77b8f
--- /dev/null
+++ b/board/schneider/rzn1-snarc/rzn1.env
@@ -0,0 +1,21 @@
+ethaddr=00:00:0a:02:57:cd
+eth1addr=00:00:0a:02:57:ce
+ethact=end1
+dfu_alt_info=
+	sf 0:0=sf_fsbl raw 0 40000;
+	   sf_unused_mtd3 raw 40000 40000;
+	   sf_configcms raw 80000 40000;
+	   sf_unused_mtd5 raw c0000 40000;
+	   sf_env raw 100000 40000;
+	   sf_unused_mtd7 raw 140000 100000;
+	   sf_uboot0 raw 240000 100000;
+	   sf_uboot1 raw 340000 100000;
+	   sf_trustedfw0 raw 440000 100000;
+	   sf_trustedfw1 raw 540000 100000;
+	   sf_cm3_0 raw 640000 100000;
+	   sf_cm3_1 raw 740000 100000;
+	   sf_data raw 840000 0
+	&nand 0=ubi0 partubi 0 1
+	&ram r_kernel ram 80008000 d80000;
+	    r_vxworks ram 80008000 d80000
+bootargs=console=ttyS0,115200 rootfstype=ramfs coherent_pool=2M

-- 
2.55.0

[PATCH v2 3/8] board: schneider: rzn1-snarc: update MAINTAINERS

[Ralph Siemsen]

Add NAND, ethernet switch and media converters.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 board/schneider/rzn1-snarc/MAINTAINERS | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/board/schneider/rzn1-snarc/MAINTAINERS b/board/schneider/rzn1-snarc/MAINTAINERS
index a39b96c1163..f8ae9e1cb6c 100644
--- a/board/schneider/rzn1-snarc/MAINTAINERS
+++ b/board/schneider/rzn1-snarc/MAINTAINERS
@@ -2,6 +2,9 @@ RZN1 SNARC
 M:	Ralph Siemsen <ralph.siemsen@linaro.org>
 S:	Maintained
 F:	board/schneider/rzn1-snarc/
+F:	drivers/mtd/nand/raw/evatronix_nand.[ch]
+F:	drivers/net/rzn1_a5psw.c
+F:	drivers/net/rzn1_miic.c
 F:	arch/arm/dts/r9a06g032-ddr.dtsi
 F:	arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
 F:	arch/arm/dts/r9a06g032-rzn1-snarc.dts

-- 
2.55.0

[PATCH v2 4/8] ARM: renesas: RZ/N1 QSPI controller features

[Ralph Siemsen]

The Renesas RZ/N1 has a QSPI controller which offers memory-mapped
"Direct Access" mode, so enable SPI_DIRMAP for this platform.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 arch/arm/mach-renesas/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
index f86acc31039..4d16d541443 100644
--- a/arch/arm/mach-renesas/Kconfig
+++ b/arch/arm/mach-renesas/Kconfig
@@ -70,9 +70,13 @@ config RZN1
 	select DM
 	select DM_ETH
 	select DM_SERIAL
+	select DM_SPI
 	select PINCTRL
 	select PINCONF
 	select REGMAP
+	select SPI
+	select SPI_MEM
+	select SPI_DIRMAP
 	select SYSRESET
 	select SYSRESET_SYSCON
 	imply CMD_DM

-- 
2.55.0

[PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Ralph Siemsen]

Sync with dts/upstream/src/arm/renesas/r9a06g032.dtsi

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 arch/arm/dts/r9a06g032.dtsi | 270 +++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 254 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
index 0fa565a1c3a..f4f760aff28 100644
--- a/arch/arm/dts/r9a06g032.dtsi
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -13,6 +13,7 @@
 	compatible = "renesas,r9a06g032";
 	#address-cells = <1>;
 	#size-cells = <1>;
+	interrupt-parent = <&gic>;
 
 	cpus {
 		#address-cells = <1>;
@@ -63,7 +64,6 @@
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		interrupt-parent = <&gic>;
 		ranges;
 
 		rtc0: rtc@40006000 {
@@ -73,8 +73,8 @@
 				     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
 				     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
 			interrupt-names = "alarm", "timer", "pps";
-			clocks = <&sysctrl R9A06G032_HCLK_RTC>;
-			clock-names = "hclk";
+			clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
+			clock-names = "hclk", "xtal";
 			power-domains = <&sysctrl>;
 			status = "disabled";
 		};
@@ -211,8 +211,8 @@
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
 			clock-names = "baudclk", "apb_pclk";
-			dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
-			dma-names = "rx", "tx";
+			dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
@@ -224,8 +224,8 @@
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
 			clock-names = "baudclk", "apb_pclk";
-			dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
-			dma-names = "rx", "tx";
+			dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
@@ -237,8 +237,8 @@
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
 			clock-names = "baudclk", "apb_pclk";
-			dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
-			dma-names = "rx", "tx";
+			dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
@@ -250,8 +250,8 @@
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
 			clock-names = "baudclk", "apb_pclk";
-			dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
-			dma-names = "rx", "tx";
+			dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
@@ -263,8 +263,40 @@
 			reg-io-width = <4>;
 			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
 			clock-names = "baudclk", "apb_pclk";
-			dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
-			dma-names = "rx", "tx";
+			dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
+		i2c1: i2c@40063000 {
+			compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
+			reg = <0x40063000 0x100>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>;
+			clock-names = "ref", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@40064000 {
+			compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
+			reg = <0x40064000 0x100>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>;
+			clock-names = "ref", "pclk";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		adc: adc@40065000 {
+			compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
+			reg = <0x40065000 0x200>;
+			clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
+			clock-names = "pclk", "adc";
+			power-domains = <&sysctrl>;
+			#io-channel-cells = <1>;
 			status = "disabled";
 		};
 
@@ -276,6 +308,30 @@
 			status = "okay";
 		};
 
+		sdio1: mmc@40100000 {
+			compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
+			reg = <0x40100000 0x1000>;
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int", "wakeup";
+			clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>;
+			clock-names = "clk_xin", "clk_ahb";
+			no-1-8-v;
+			status = "disabled";
+		};
+
+		sdio2: mmc@40101000 {
+			compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
+			reg = <0x40101000 0x1000>;
+			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "int", "wakeup";
+			clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>;
+			clock-names = "clk_xin", "clk_ahb";
+			no-1-8-v;
+			status = "disabled";
+		};
+
 		nand_controller: nand-controller@40102000 {
 			compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
 			reg = <0x40102000 0x2000>;
@@ -316,10 +372,27 @@
 			data-width = <8>;
 		};
 
+		gmac1: ethernet@44000000 {
+			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
+			reg = <0x44000000 0x2000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+			clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
+			clock-names = "stmmaceth";
+			power-domains = <&sysctrl>;
+			snps,multicast-filter-bins = <256>;
+			snps,perfect-filter-entries = <128>;
+			tx-fifo-depth = <2048>;
+			rx-fifo-depth = <4096>;
+			pcs-handle = <&mii_conv1>;
+			status = "disabled";
+		};
+
 		gmac2: ethernet@44002000 {
 			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
 			reg = <0x44002000 0x2000>;
-			interrupt-parent = <&gic>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -380,6 +453,12 @@
 				 <&sysctrl R9A06G032_CLK_SWITCH>;
 			clock-names = "hclk", "clk";
 			power-domains = <&sysctrl>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
 			status = "disabled";
 
 			ethernet-ports {
@@ -436,8 +515,167 @@
 				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		/*
+		 * The GPIO mapping to the corresponding pins is not obvious.
+		 * See the hardware documentation for details.
+		 */
+		gpio0: gpio@5000b000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000b000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
+			clock-names = "bus";
+
+			/* GPIO0a[0]      connected to pin  GPIO0      */
+			/* GPIO0a[1..2]   connected to pins GPIO3..4   */
+			/* GPIO0a[3..4]   connected to pins GPIO9..10  */
+			/* GPIO0a[5]      connected to pin  GPIO12     */
+			/* GPIO0a[6..7]   connected to pins GPIO15..16 */
+			/* GPIO0a[8..9]   connected to pins GPIO21..22 */
+			/* GPIO0a[10]     connected to pin  GPIO24     */
+			/* GPIO0a[11..12] connected to pins GPIO27..28 */
+			/* GPIO0a[13..14] connected to pins GPIO33..34 */
+			/* GPIO0a[15]     connected to pin  GPIO36     */
+			/* GPIO0a[16..17] connected to pins GPIO39..40 */
+			/* GPIO0a[18..19] connected to pins GPIO45..46 */
+			/* GPIO0a[20]     connected to pin  GPIO48     */
+			/* GPIO0a[21..22] connected to pins GPIO51..52 */
+			/* GPIO0a[23..24] connected to pins GPIO57..58 */
+			/* GPIO0a[25..31] connected to pins GPIO62..68 */
+			gpio0a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = < 0  1  2  3  4  5  6  7
+					       8  9 10 11 12 13 14 15
+					      16 17 18 19 20 21 22 23
+					      24 25 26 27 28 29 30 31>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO0b[0..1]   connected to pins GPIO1..2   */
+			/* GPIO0b[2..5]   connected to pins GPIO5..8   */
+			/* GPIO0b[6]      connected to pin  GPIO11     */
+			/* GPIO0b[7..8]   connected to pins GPIO13..14 */
+			/* GPIO0b[9..12]  connected to pins GPIO17..20 */
+			/* GPIO0b[13]     connected to pin  GPIO23     */
+			/* GPIO0b[14..15] connected to pins GPIO25..26 */
+			/* GPIO0b[16..19] connected to pins GPIO29..32 */
+			/* GPIO0b[20]     connected to pin  GPIO35     */
+			/* GPIO0b[21..22] connected to pins GPIO37..38 */
+			/* GPIO0b[23..26] connected to pins GPIO41..44 */
+			/* GPIO0b[27]     connected to pin  GPIO47     */
+			/* GPIO0b[28..29] connected to pins GPIO49..50 */
+			/* GPIO0b[30..31] connected to pins GPIO53..54 */
+			gpio0b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+			};
+		};
+
+		gpio1: gpio@5000c000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000c000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
+			clock-names = "bus";
+
+			/* GPIO1a[0..4]  connected to pins GPIO69..73 */
+			/* GPIO1a[5..31] connected to pins GPIO95..121 */
+			gpio1a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = <32 33 34 35 36 37 38 39
+					      40 41 42 43 44 45 46 47
+					      48 49 50 51 52 53 54 55
+					      56 57 58 59 60 61 62 63>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO1b[0..1]   connected to pins GPIO55..56 */
+			/* GPIO1b[2..4]   connected to pins GPIO59..61 */
+			/* GPIO1b[5..25]  connected to pins GPIO74..94 */
+			/* GPIO1b[26..31] connected to pins GPIO150..155 */
+			gpio1b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+			};
+		};
+
+		gpio2: gpio@5000d000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x5000d000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
+			clock-names = "bus";
+
+			/* GPIO2a[0..27]  connected to pins GPIO122..149 */
+			/* GPIO2a[28..31] connected to pins GPIO156..159 */
+			gpio2a: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = <64 65 66 67 68 69 70 71
+					      72 73 74 75 76 77 78 79
+					      80 81 82 83 84 85 86 87
+					      88 89 90 91 92 93 94 95>;
+				#interrupt-cells = <2>;
+			};
+
+			/* GPIO2b[0..9] connected to pins GPIO160..169 */
+			gpio2b: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <10>;
+			};
+		};
+
+		gpioirqmux: interrupt-controller@51000480 {
+			compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+			reg = <0x51000480 0x20>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupt-map-mask = <0x7f>;
+
+			/*
+			 * Example mapping entry. Board DTs need to overwrite
+			 * 'interrupt-map' with their specific mapping. Check
+			 * the irqmux binding documentation for details.
+			 */
+			interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
 		can0: can@52104000 {
-			compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
+			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
 			reg = <0x52104000 0x800>;
 			reg-io-width = <4>;
 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +697,6 @@
 
 	timer {
 		compatible = "arm,armv7-timer";
-		interrupt-parent = <&gic>;
 		arm,cpu-registers-not-fw-configured;
 		always-on;
 		interrupts =
@@ -467,6 +704,7 @@
 			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
 	};
 
 	usbphy: usb-phy {

-- 
2.55.0

[PATCH v2 6/8] ARM: dts: r9a06g032: add QSPI controller

[Ralph Siemsen]

The RZ/N1 has a Quad-SPI controller based on Cadence IP core.

Take the devicetree for it from linux v7.1-rc2 commit
5be0b48a3b23 ("ARM: dts: renesas: r9a06g032: Describe the QSPI controller"

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
Changes in v2:
- update to exactly match linux-7.1 commit 5be0b48a3b23
- this means qspi driver needs a new compatible string added
---
 arch/arm/dts/r9a06g032.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
index f4f760aff28..164d30c5388 100644
--- a/arch/arm/dts/r9a06g032.dtsi
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -66,6 +66,18 @@
 		#size-cells = <1>;
 		ranges;
 
+		qspi0: spi@40005000 {
+			compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
+			reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
+				 <&sysctrl R9A06G032_HCLK_QSPI0>;
+			clock-names = "ref", "ahb", "apb";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		rtc0: rtc@40006000 {
 			compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
 			reg = <0x40006000 0x1000>;

-- 
2.55.0

[PATCH v2 7/8] ARM: dts: r9a06g032-rzn1-snarc: enable new drivers

[Ralph Siemsen]

Add pinmux and enable newly added drivers:
- MMC (SDIO)
- QSPI flash
- NAND flash
- USB controller
- GPIO
- Ethernet (designware)
- A5PSW ethernet switch
- MIIC media converter

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
Changes in v2:
- make it easier to compare with original r9a06g032-rzn1d400-db.dts
- reorder device nodes alphabetically (and matching the original)
- pinmux: change indentation, remove underscores from node names
---
 arch/arm/dts/r9a06g032-rzn1-snarc.dts | 376 +++++++++++++++++++++++++++++++++-
 1 file changed, 371 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/r9a06g032-rzn1-snarc.dts b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
index 7de8ee15ef3..08ea5c56f14 100644
--- a/arch/arm/dts/r9a06g032-rzn1-snarc.dts
+++ b/arch/arm/dts/r9a06g032-rzn1-snarc.dts
@@ -7,6 +7,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
 #include "r9a06g032.dtsi"
 
@@ -73,16 +74,375 @@
 	};
 };
 
+&eth_miic {
+	status = "okay";
+};
+
+&gmac2 {
+	status = "okay";
+	phy-connection-type = "rgmii-id";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&gpio0 {
+	pinctrl-0 = <&pins_gpio0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio1 {
+	pinctrl-0 = <&pins_gpio1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio2 {
+	pinctrl-0 = <&pins_gpio2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&mii_conv1 {
+	status = "okay";
+};
+
+&mii_conv2 {
+	status = "okay";
+};
+
+&mii_conv3 {
+	status = "okay";
+};
+
+&mii_conv4 {
+	status = "okay";
+};
+
+&mii_conv5 {
+	status = "okay";
+};
+
+&nand_controller {
+	pinctrl-0 = <&pins_nand>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	oob-reserved = <8>;
+	nand@0 {
+		label = "nand";
+		reg = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			/* 512MB */
+			label = "nand:ubi0";
+			reg = <0x0000000 0>;
+		};
+	};
+};
+
 &pinctrl {
 	status = "okay";
 
-	pins_uart0: pins_uart0 {
-		pinmux = <
-			RZN1_PINMUX(103, RZN1_FUNC_UART0_I)     /* UART0_TXD */
-			RZN1_PINMUX(104, RZN1_FUNC_UART0_I)     /* UART0_RXD */
-			>;
+	pins_eth3: pins-eth3 {
+		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXCLK */
+			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXD[0] */
+			 <RZN1_PINMUX(38, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXD[1] */
+			 <RZN1_PINMUX(39, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXD[2] */
+			 <RZN1_PINMUX(40, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXD[3] */
+			 <RZN1_PINMUX(41, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_TXEN */
+			 <RZN1_PINMUX(42, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_RXCLK */
+			 <RZN1_PINMUX(43, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_RXD[0] */
+			 <RZN1_PINMUX(44, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_RXD[1] */
+			 <RZN1_PINMUX(45, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_RXD[2] */
+			 <RZN1_PINMUX(46, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH3_RXD[3] */
+			 <RZN1_PINMUX(47, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;	/* ETH3_RXDV */
+		drive-strength = <6>;
 		bias-disable;
 	};
+
+	pins_eth4: pins-eth4 {
+		pinmux = <RZN1_PINMUX(48, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXCLK */
+			 <RZN1_PINMUX(49, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXD[0] */
+			 <RZN1_PINMUX(50, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXD[1] */
+			 <RZN1_PINMUX(51, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXD[2] */
+			 <RZN1_PINMUX(52, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXD[3] */
+			 <RZN1_PINMUX(53, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_TXEN */
+			 <RZN1_PINMUX(54, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_RXCLK */
+			 <RZN1_PINMUX(55, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_RXD[0] */
+			 <RZN1_PINMUX(56, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_RXD[1] */
+			 <RZN1_PINMUX(57, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_RXD[2] */
+			 <RZN1_PINMUX(58, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,	/* ETH4_RXD[3] */
+			 <RZN1_PINMUX(59, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;	/* ETH4_RXDV */
+		drive-strength = <6>;
+		bias-disable;
+	};
+
+	pins_gpio0: pins-gpio0 {
+		pinmux = <RZN1_PINMUX(13, RZN1_FUNC_GPIO)>,	/* GPIO0B[7] */
+			 <RZN1_PINMUX(14, RZN1_FUNC_GPIO)>,	/* GPIO0B[8] */
+			 <RZN1_PINMUX(15, RZN1_FUNC_GPIO)>,	/* GPIO0A[6] */
+			 <RZN1_PINMUX(16, RZN1_FUNC_GPIO)>,	/* GPIO0A[7] */
+			 <RZN1_PINMUX(17, RZN1_FUNC_GPIO)>,	/* GPIO0B[9] */
+			 <RZN1_PINMUX(18, RZN1_FUNC_GPIO)>,	/* GPIO0B[10] */
+			 <RZN1_PINMUX(22, RZN1_FUNC_GPIO)>,	/* GPIO0A[9] */
+			 <RZN1_PINMUX(23, RZN1_FUNC_GPIO)>;	/* GPIO0B[13] */
+		drive-strength = <6>;
+		bias-disable;
+
+		pins-gpio0-pullup {
+			pinmux = <RZN1_PINMUX(25, RZN1_FUNC_GPIO)>,	/* GPIO0B[14] - A70CI_EN_N */
+				 <RZN1_PINMUX(26, RZN1_FUNC_GPIO)>,	/* GPIO0B[15] - A71CH_EN_N */
+				 <RZN1_PINMUX(27, RZN1_FUNC_GPIO)>,	/* GPIO0A[11] - TRUST_M_EN_N */
+				 <RZN1_PINMUX(28, RZN1_FUNC_GPIO)>,	/* GPIO0A[12] - TRUST_X_EN_N */
+				 <RZN1_PINMUX(32, RZN1_FUNC_GPIO)>;	/* GPIO0B[19] - STMA100_EN_N*/
+			drive-strength = <6>;
+			bias-pull-up;
+		};
+
+	};
+
+	pins_gpio1: pins-gpio1 {
+		pinmux = <RZN1_PINMUX(108, RZN1_FUNC_GPIO)>,	/* GPIO1A[18] - for SPI1_SS_N[0] */
+			 <RZN1_PINMUX(109, RZN1_FUNC_GPIO)>,	/* GPIO1A[19] - for SPI0_SS_N[1] */
+			 <RZN1_PINMUX(110, RZN1_FUNC_GPIO)>,	/* GPIO1A[20] - for SPI0_SS_N[2] */
+			 <RZN1_PINMUX(114, RZN1_FUNC_GPIO)>;	/* GPIO1A[24] - for SPI0_SS_N[0] */
+	};
+
+	pins_gpio2: pins-gpio2 {
+		pinmux = <RZN1_PINMUX(147, RZN1_FUNC_GPIO)>,	/* Eth4 IRQ (GPIO2A[25],	*/
+			 <RZN1_PINMUX(148, RZN1_FUNC_GPIO)>,	/* Touch IRQ (GPIO2A[26])	*/
+			 <RZN1_PINMUX(149, RZN1_FUNC_GPIO)>;	/* Eth5 IRQ (GPIO2A[27])	*/
+	};
+
+	pins_mdio1: pins-mdio1 {
+		pinmux = <RZN1_PINMUX(152, RZN1_FUNC_ETH_MDIO)>,	/* MDIO1_MDC */
+			 <RZN1_PINMUX(153, RZN1_FUNC_ETH_MDIO)>,	/* MDIO1_MDIO */
+			 <RZN1_PINMUX(171, RZN1_FUNC_MDIO1_SWITCH)>;	/* MDIO1_MUX_SWITCH */
+	};
+
+	pins_nand: pins-nand {
+		pinmux = <RZN1_PINMUX(80, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_ALE */
+			 <RZN1_PINMUX(81, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_CLE */
+			 <RZN1_PINMUX(82, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_WE_N */
+			 <RZN1_PINMUX(83, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_RE_N */
+			 <RZN1_PINMUX(84, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[0] */
+			 <RZN1_PINMUX(85, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[1] */
+			 <RZN1_PINMUX(86, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[2] */
+			 <RZN1_PINMUX(87, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[3] */
+			 <RZN1_PINMUX(88, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[4] */
+			 <RZN1_PINMUX(89, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[5] */
+			 <RZN1_PINMUX(90, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[6] */
+			 <RZN1_PINMUX(91, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_IO[7] */
+			 <RZN1_PINMUX(92, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_CE_N[0] */
+			 <RZN1_PINMUX(93, RZN1_FUNC_CLK_ETH_NAND)>,	/* NAND_WP_N[0] */
+			 <RZN1_PINMUX(94, RZN1_FUNC_CLK_ETH_NAND)>;	/* NAND_RYBY_N[0] */
+	};
+
+	pins_qspi0: pins-qspi0 {
+		pinmux = <RZN1_PINMUX(74, RZN1_FUNC_QSPI)>,	/* QSPI0_CS_N[0] */
+			 <RZN1_PINMUX(75, RZN1_FUNC_QSPI)>,	/* QSPI0_IO[3] */
+			 <RZN1_PINMUX(76, RZN1_FUNC_QSPI)>,	/* QSPI0_IO[2] */
+			 <RZN1_PINMUX(77, RZN1_FUNC_QSPI)>,	/* QSPI0_IO[1] */
+			 <RZN1_PINMUX(78, RZN1_FUNC_QSPI)>,	/* QSPI0_IO[0] */
+			 <RZN1_PINMUX(79, RZN1_FUNC_QSPI)>;	/* QSPI0_CLK */
+		bias-disable;
+	};
+
+	pins_sdio1: pins-sdio1 {
+		pinmux = <RZN1_PINMUX(95, RZN1_FUNC_SDIO)>,	/* SDIO0_CMD */
+			 <RZN1_PINMUX(97, RZN1_FUNC_SDIO)>,	/* SDIO0_IO[0] */
+			 <RZN1_PINMUX(98, RZN1_FUNC_SDIO)>,	/* SDIO0_IO[1] */
+			 <RZN1_PINMUX(99, RZN1_FUNC_SDIO)>,	/* SDIO0_IO[2] */
+			 <RZN1_PINMUX(100, RZN1_FUNC_SDIO)>;	/* SDIO0_IO[3] */
+
+		pins_sdio1_clk: pins-sdio1-clk {
+			pinmux = <RZN1_PINMUX(96, RZN1_FUNC_SDIO)>;	/* SDIO0_CLK */
+			drive-strength = <12>;
+		};
+
+		pins_sdio1_cd_wp: pins-sdio1-cd-wp {
+			pinmux = <RZN1_PINMUX(101, RZN1_FUNC_SDIO_E)>,	/* SDIO0_CD_N */
+				 <RZN1_PINMUX(102, RZN1_FUNC_SDIO_E)>;	/* SDIO0_WP */
+			bias-pull-down;
+		};
+	};
+
+	pins_uart0: pins-uart0 {
+		pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>,	/* UART0_TXD */
+			 <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>;	/* UART0_RXD */
+		bias-disable;
+	};
+
+	pins_usb: pins-usb {
+		pins-usb-pdown {
+			pinmux = <RZN1_PINMUX(119, RZN1_FUNC_USB)>,	/* USB_PPON[1] */
+				 <RZN1_PINMUX(121, RZN1_FUNC_USB)>;	/* USB_PPON[2] */
+			drive-strength = <4>;
+			bias-pull-down;
+		};
+
+		pins-usb-pup {
+			pinmux = <RZN1_PINMUX(120, RZN1_FUNC_USB)>,	/* USB_OC[1] */
+				 <RZN1_PINMUX(122, RZN1_FUNC_USB)>;	/* USB_OC[2] */
+			drive-strength = <4>;
+			bias-pull-up;
+		};
+	};
+};
+
+&qspi0 {
+	pinctrl-0 = <&pins_qspi0>;
+	pinctrl-names = "default";
+	status = "okay";
+	//bootph-all;  /* causes malloc failure at boot */
+
+	flash@0 {
+		reg = <0>;
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <62500000>;
+		spi-cpha;
+		spi-cpol;
+		spi-rx-bus-width = <4>;
+		//bootph-all;  /* causes malloc failure at boot */
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				/* 256KB */
+				label = "qspi0:spl";
+				reg = <0x00000000 0x00040000>;
+			};
+			partition@40000 {
+				/* 256KB */
+				label = "qspi0:unused_mtd3";
+				reg = <0x00040000 0x00040000>;
+			};
+			partition@80000 {
+				/* 256KB */
+				label = "qspi0:configcms";
+				reg = <0x00080000 0x00040000>;
+			};
+			partition@c0000 {
+				/* 256KB */
+				label = "qspi0:unused_mtd5";
+				reg = <0x000C0000 0x00040000>;
+			};
+			partition@100000 {
+				/* 256KB */
+				label = "qspi0:env";
+				reg = <0x00100000 0x00040000>;
+			};
+			partition@140000 {
+				/* 1MB */
+				label = "qspi0:unused_mtd7";
+				reg = <0x00140000 0x00100000>;
+			};
+			partition@240000 {
+				/* 1MB */
+				label = "qspi0:uboot0fit";
+				reg = <0x00240000 0x00100000>;
+			};
+			partition@340000 {
+				/* 1MB */
+				label = "qspi0:uboot1fit";
+				reg = <0x00340000 0x00100000>;
+			};
+			partition@440000 {
+				/* 1MB */
+				label = "qspi0:tosfit0";
+				reg = <0x00440000 0x00100000>;
+			};
+			partition@540000 {
+				/* 1MB */
+				label = "qspi0:tosfit1";
+				reg = <0x00540000 0x00100000>;
+			};
+			partition@640000 {
+				/* 1MB */
+				label = "qspi0:cm3fit0";
+				reg = <0x00640000 0x00100000>;
+			};
+			partition@740000 {
+				/* 1MB */
+				label = "qspi0:cm3fit1";
+				reg = <0x00740000 0x00100000>;
+			};
+			partition@840000 {
+				/* Remaining */
+				label = "qspi0:data";
+				reg = <0x00840000 0>;
+			};
+		};
+	};
+};
+
+&sdio1 {
+	pinctrl-0 = <&pins_sdio1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&pins_eth3>, <&pins_eth4>, <&pins_mdio1>;
+
+	phy-reset-gpios = <&gpio2a 26 GPIO_ACTIVE_LOW>;
+	phy-reset-duration = <15>;
+
+	dsa,member = <0 0>;
+
+	syscon = <&plat_regs>;
+
+	mdio {
+		clock-frequency = <2500000>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		switch0phy4: ethernet-phy@4 {
+			reg = <4>;
+		};
+
+		switch0phy5: ethernet-phy@5 {
+			reg = <5>;
+		};
+	};
+};
+
+&switch_port0 {
+	label = "end0";
+	phy-mode = "rgmii-id";
+	phy-handle = <&switch0phy5>;
+	status = "okay";
+};
+
+&switch_port1 {
+	label = "end1";
+	phy-mode = "rgmii-id";
+	phy-handle = <&switch0phy4>;
+	status = "okay";
+};
+
+&switch_port4 {
+	/* Upstream to GMAC2 */
+	status = "okay";
 };
 
 &uart0 {
@@ -90,3 +450,9 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&udc {
+	pinctrl-0 = <&pins_usb>;
+	pinctrl-names = "default";
+	status = "okay";
+};

-- 
2.55.0

[PATCH v2 8/8] configs: rzn1_snarc_defconfig: enable new drivers

[Ralph Siemsen]

Enable drivers which are now functional on RZ/N1:
- Default environment from file rzn1.env
- MMC controller (ARASAN), and FAT and EXT4 filesystem support
- QSPI controller (Cadence), MTD and several flash vendors
- QSPI write protection feature
- GPIO driver (Designware)
- Ethernet (Designware + A5PSW + MIIC) and PHY
- Ethernet needs CONFIG_DW_ALTDESCRIPTORS
- NAND flash (Cadence/Evatronix)
- USB controller, gadget for DFU/fastboot/UMS
- BOARD_LATE_INIT for serial number in environment

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
---
 configs/rzn1_snarc_defconfig | 76 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig
index 65a9c25b4aa..dc3c076c5cf 100644
--- a/configs/rzn1_snarc_defconfig
+++ b/configs/rzn1_snarc_defconfig
@@ -3,21 +3,97 @@ CONFIG_SYS_ARCH_TIMER=y
 CONFIG_ARCH_RENESAS=y
 CONFIG_SYS_MALLOC_LEN=0xb0000
 CONFIG_SYS_MALLOC_F_LEN=0x800
+CONFIG_ENV_SOURCE_FILE="rzn1"
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="r9a06g032-rzn1-snarc"
 CONFIG_RZN1=y
 CONFIG_SYS_LOAD_ADDR=0x80008000
+CONFIG_ZYNQ_SDHCI_MAX_FREQ=50000000
 CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0x8fffffff
 # CONFIG_EFI_LOADER is not set
 # CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_CMD_BOOTZ=y
 CONFIG_CMD_MEMTEST=y
 CONFIG_SYS_ALT_MEMTEST=y
 # CONFIG_SYS_ALT_MEMTEST_BITFLIP is not set
+CONFIG_CMD_SHA1SUM=y
 CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MTD_OTP=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_MTDIDS_DEFAULT="nand0=nand0"
+CONFIG_MTDPARTS_DEFAULT="nand0:512M(ubi0)"
+CONFIG_EFI_PARTITION=y
+CONFIG_PARTITION_TYPE_GUID=y
 CONFIG_OF_CONTROL=y
 # CONFIG_OF_UPSTREAM is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_MTD=y
+CONFIG_DFU_NAND=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x81000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_OEM_RUN=y
+CONFIG_FASTBOOT_OEM_BOARD=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_MISC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_MTD=y
+CONFIG_CFI_FLASH=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_EVATRONIX=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_DSA=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_PHY_GIGE=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DW_ALTDESCRIPTOR=y
+CONFIG_MV88E6XXX=y
+CONFIG_RZN1_A5PSW=y
+CONFIG_RZN1_MIIC=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_FIXED=y
 CONFIG_RAM=y
 CONFIG_CADENCE_DDR_CTRL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_CADENCE_QSPI_WRITE_PROTECT=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Renesas Electronics"
+CONFIG_USB_GADGET_VENDOR_NUM=0x045b
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0239
+CONFIG_USB_GADGET_RENESAS_USBF=y

-- 
2.55.0

Re: [PATCH v2 1/8] board: schneider: rzn1-snarc: set serial number

[Marek Vasut via U-Boot]

On 8/14/26 8:38 PM, Ralph Siemsen wrote:

[...]

> +++ b/board/schneider/rzn1-snarc/rzn1.c
> @@ -1,11 +1,21 @@
>   // SPDX-License-Identifier: GPL-2.0+
>   
> +#include <asm/io.h>
> +#include <configs/rzn1-snarc.h>
>   #include <dm.h>
> +#include <env.h>
> +#include <g_dnl.h>
>   #include <ram.h>
>   #include <asm/global_data.h>
>   
>   DECLARE_GLOBAL_DATA_PTR;
>   
> +static inline uint32_t hosted_readl(uint32_t addr)

"inline" is not necessary, compiler will figure that out, drop it.

> +{
> +	/* No hypervisor yet, just do a direct read */
> +	return readl(addr);
> +}
> +
>   int board_init(void)
>   {
>   	gd->bd->bi_boot_params = gd->ram_base + 0x100;

[...]

Re: [PATCH v2 2/8] board: schneider: rzn1-snarc: add rzn1.env

[Marek Vasut via U-Boot]

On 8/14/26 8:38 PM, Ralph Siemsen wrote:
> Add default u-boot environment for Schneider RZ/N1 board:
> - Ethernet: default MAC addresses, use end1 interface
> - dfu_alt_info partitions for DFU
> - legacy bootargs
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>   board/schneider/rzn1-snarc/rzn1.env | 21 +++++++++++++++++++++
>   1 file changed, 21 insertions(+)
> 
> diff --git a/board/schneider/rzn1-snarc/rzn1.env b/board/schneider/rzn1-snarc/rzn1.env
> new file mode 100644
> index 00000000000..bc4f7e77b8f
> --- /dev/null
> +++ b/board/schneider/rzn1-snarc/rzn1.env
> @@ -0,0 +1,21 @@
> +ethaddr=00:00:0a:02:57:cd
> +eth1addr=00:00:0a:02:57:ce
> +ethact=end1
> +dfu_alt_info=
> +	sf 0:0=sf_fsbl raw 0 40000;
Use dfu mtd please , that is the future proofed replacement for dfu sf .

Re: [PATCH v2 3/8] board: schneider: rzn1-snarc: update MAINTAINERS

[Marek Vasut via U-Boot]

On 8/14/26 8:38 PM, Ralph Siemsen wrote:
> Add NAND, ethernet switch and media converters.
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>   board/schneider/rzn1-snarc/MAINTAINERS | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/board/schneider/rzn1-snarc/MAINTAINERS b/board/schneider/rzn1-snarc/MAINTAINERS
> index a39b96c1163..f8ae9e1cb6c 100644
> --- a/board/schneider/rzn1-snarc/MAINTAINERS
> +++ b/board/schneider/rzn1-snarc/MAINTAINERS
> @@ -2,6 +2,9 @@ RZN1 SNARC
>   M:	Ralph Siemsen <ralph.siemsen@linaro.org>
>   S:	Maintained
>   F:	board/schneider/rzn1-snarc/
> +F:	drivers/mtd/nand/raw/evatronix_nand.[ch]
> +F:	drivers/net/rzn1_a5psw.c
> +F:	drivers/net/rzn1_miic.c
>   F:	arch/arm/dts/r9a06g032-ddr.dtsi
>   F:	arch/arm/dts/r9a06g032-rzn1-snarc-u-boot.dtsi
>   F:	arch/arm/dts/r9a06g032-rzn1-snarc.dts
Use "N: rzn1" and deduplicate .

Re: [PATCH v2 4/8] ARM: renesas: RZ/N1 QSPI controller features

[Marek Vasut via U-Boot]

On 8/14/26 8:38 PM, Ralph Siemsen wrote:
> The Renesas RZ/N1 has a QSPI controller which offers memory-mapped
> "Direct Access" mode, so enable SPI_DIRMAP for this platform.
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>   arch/arm/mach-renesas/Kconfig | 4 ++++
>   1 file changed, 4 insertions(+)
> 
> diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
> index f86acc31039..4d16d541443 100644
> --- a/arch/arm/mach-renesas/Kconfig
> +++ b/arch/arm/mach-renesas/Kconfig
> @@ -70,9 +70,13 @@ config RZN1
>   	select DM
>   	select DM_ETH
>   	select DM_SERIAL
> +	select DM_SPI
>   	select PINCTRL
>   	select PINCONF
>   	select REGMAP
> +	select SPI

Shouldn't this be in board config ? Not all RZN1 boards likely require SPI ?

> +	select SPI_MEM
> +	select SPI_DIRMAP
Shouldn't this be selected by the SPI NOR driver instead ?

Re: [PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Marek Vasut via U-Boot]

On 8/14/26 8:38 PM, Ralph Siemsen wrote:
> Sync with dts/upstream/src/arm/renesas/r9a06g032.dtsi
> 
> Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
> ---
>   arch/arm/dts/r9a06g032.dtsi | 270 +++++++++++++++++++++++++++++++++++++++++---
Can you use dts/upstream/src/arm/renesas/r9a06g032.dtsi instead ?

Can you switch to OF_UPSTREAM ?

Re: [PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Ralph Siemsen]

On Sat, Aug 15, 2026 at 12:26:16AM +0200, Marek Vasut wrote:
>>---
>>  arch/arm/dts/r9a06g032.dtsi | 270 +++++++++++++++++++++++++++++++++++++++++---
>Can you use dts/upstream/src/arm/renesas/r9a06g032.dtsi instead ?
>
>Can you switch to OF_UPSTREAM ?

Almost, but not quite yet. The upstream version is missing the QSPI 
node, which just got added in the kernel side. So once that gets synced 
into U-boot then we can switch.

Ralph

Re: [PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Marek Vasut via U-Boot]

On 8/15/26 2:24 PM, Ralph Siemsen wrote:
> On Sat, Aug 15, 2026 at 12:26:16AM +0200, Marek Vasut wrote:
>>> ---
>>>  arch/arm/dts/r9a06g032.dtsi | 270 ++++++++++++++++++++++++++++++++++ 
>>> +++++++---
>> Can you use dts/upstream/src/arm/renesas/r9a06g032.dtsi instead ?
>>
>> Can you switch to OF_UPSTREAM ?
> 
> Almost, but not quite yet. The upstream version is missing the QSPI 
> node, which just got added in the kernel side. So once that gets synced 
> into U-boot then we can switch.
Can you put the missing bits into -u-boot.dtsi ?

Re: [PATCH v2 4/8] ARM: renesas: RZ/N1 QSPI controller features

[Ralph Siemsen]

On Sat, Aug 15, 2026 at 12:25:10AM +0200, Marek Vasut wrote:
>On 8/14/26 8:38 PM, Ralph Siemsen wrote:
>>
>>diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/Kconfig
>>index f86acc31039..4d16d541443 100644
>>--- a/arch/arm/mach-renesas/Kconfig
>>+++ b/arch/arm/mach-renesas/Kconfig
>>@@ -70,9 +70,13 @@ config RZN1
>>  	select DM
>>  	select DM_ETH
>>  	select DM_SERIAL
>>+	select DM_SPI
>>  	select PINCTRL
>>  	select PINCONF
>>  	select REGMAP
>>+	select SPI
>
>Shouldn't this be in board config ? Not all RZN1 boards likely require SPI ?

Any RZ/N1 board that makes use of the QSPI will want this. It could be 
done in the defconfig, but it is easy to miss, and not fun to debug 
(took many hours of printf() for me to find it)

>>+	select SPI_MEM
>>+	select SPI_DIRMAP
>Shouldn't this be selected by the SPI NOR driver instead ?

The same driver has other users, but they may not all want DIRMAP.

I will move these settings under TARGET_SCHNEIDER_RZN1 so they are 
specific to this board.

Ralph

Re: [PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Ralph Siemsen]

On Sun, Aug 16, 2026 at 01:25:09PM +0200, Marek Vasut wrote:
>On 8/15/26 2:24 PM, Ralph Siemsen wrote:
>>On Sat, Aug 15, 2026 at 12:26:16AM +0200, Marek Vasut wrote:
>>>>---
>>>> arch/arm/dts/r9a06g032.dtsi | 270 
>>>>++++++++++++++++++++++++++++++++++ +++++++---
>>>Can you use dts/upstream/src/arm/renesas/r9a06g032.dtsi instead ?
>>>
>>>Can you switch to OF_UPSTREAM ?
>>
>>Almost, but not quite yet. The upstream version is missing the QSPI 
>>node, which just got added in the kernel side. So once that gets 
>>synced into U-boot then we can switch.
>Can you put the missing bits into -u-boot.dtsi ?

As of v2026.10-rc3 this patch is no longer needed, Tom has pulled in 
recent-enough DTS with the qspi node present.

I will switch to OF_UPSTREAM.

Ralph

Re: [PATCH v2 5/8] ARM: dts: r9a06g032: sync with upstream

[Marek Vasut]

On 8/28/26 7:54 PM, Ralph Siemsen wrote:
> On Sun, Aug 16, 2026 at 01:25:09PM +0200, Marek Vasut wrote:
>> On 8/15/26 2:24 PM, Ralph Siemsen wrote:
>>> On Sat, Aug 15, 2026 at 12:26:16AM +0200, Marek Vasut wrote:
>>>>> ---
>>>>>  arch/arm/dts/r9a06g032.dtsi | 270 ++++++++++++++++++++++++++++++++ 
>>>>> ++ +++++++---
>>>> Can you use dts/upstream/src/arm/renesas/r9a06g032.dtsi instead ?
>>>>
>>>> Can you switch to OF_UPSTREAM ?
>>>
>>> Almost, but not quite yet. The upstream version is missing the QSPI 
>>> node, which just got added in the kernel side. So once that gets 
>>> synced into U-boot then we can switch.
>> Can you put the missing bits into -u-boot.dtsi ?
> 
> As of v2026.10-rc3 this patch is no longer needed, Tom has pulled in 
> recent-enough DTS with the qspi node present.
> 
> I will switch to OF_UPSTREAM.
That is very nice, thank you !

Re: [PATCH v2 4/8] ARM: renesas: RZ/N1 QSPI controller features

[Marek Vasut]

On 8/28/26 7:53 PM, Ralph Siemsen wrote:
> On Sat, Aug 15, 2026 at 12:25:10AM +0200, Marek Vasut wrote:
>> On 8/14/26 8:38 PM, Ralph Siemsen wrote:
>>>
>>> diff --git a/arch/arm/mach-renesas/Kconfig b/arch/arm/mach-renesas/ 
>>> Kconfig
>>> index f86acc31039..4d16d541443 100644
>>> --- a/arch/arm/mach-renesas/Kconfig
>>> +++ b/arch/arm/mach-renesas/Kconfig
>>> @@ -70,9 +70,13 @@ config RZN1
>>>      select DM
>>>      select DM_ETH
>>>      select DM_SERIAL
>>> +    select DM_SPI
>>>      select PINCTRL
>>>      select PINCONF
>>>      select REGMAP
>>> +    select SPI
>>
>> Shouldn't this be in board config ? Not all RZN1 boards likely require 
>> SPI ?
> 
> Any RZ/N1 board that makes use of the QSPI will want this.

That means, move to board defconfig.

> It could be 
> done in the defconfig, but it is easy to miss, and not fun to debug 
> (took many hours of printf() for me to find it)

That is board defconfig bug then.

>>> +    select SPI_MEM
>>> +    select SPI_DIRMAP
>> Shouldn't this be selected by the SPI NOR driver instead ?
> 
> The same driver has other users, but they may not all want DIRMAP.

Why would they not want dirmap ?

> I will move these settings under TARGET_SCHNEIDER_RZN1 so they are 
> specific to this board.
OK