From: "Scholz, Kevin" <k-scholz@ti.com>
To: "Francis, Neha" <n-francis@ti.com>,
Francesco Dolcini <francesco@dolcini.it>
Cc: Franz Schnyder <fra.schnyder@gmail.com>,
"trini@konsulko.com" <trini@konsulko.com>,
"K, Santhosh Kumar" <s-k6@ti.com>, "Brattlof, Bryan" <bb@ti.com>,
"Chawdhry, Manorit" <m-chawdhry@ti.com>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>,
"Kumar, Udit" <u-kumar1@ti.com>,
"Gujulan Elango, Hari Prasath" <gehariprasath@ti.com>,
"Scholz, Kevin" <k-scholz@ti.com>
Subject: RE: [EXTERNAL] Re: [PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool
Date: Wed, 20 May 2026 21:52:09 +0000 [thread overview]
Message-ID: <8d4936cd5b16494e9447d5f64d7b8e11@ti.com> (raw)
In-Reply-To: <fcba4a77-53a2-4f7f-be95-e9cefcf347a3@ti.com>
Francesco,
My understanding is that the Aquila board was previously having intermittent boot failures, hence the comparison of the TI EVM register values vs. the Aquila board register values. My understanding is that since then, two unrelated issues were identified resulting in the observed behavior, and both have been resolved.
However in general, more than one IO setting can be adequate for a given design, and it is also acceptable to have different IO settings for different board designs and/or for different DDRSS on the same board.
Regards,
Kevin
-----Original Message-----
From: Francis, Neha <n-francis@ti.com>
Sent: Tuesday, April 21, 2026 5:11 AM
To: Francesco Dolcini <francesco@dolcini.it>; Scholz, Kevin <k-scholz@ti.com>
Cc: Franz Schnyder <fra.schnyder@gmail.com>; trini@konsulko.com; K, Santhosh Kumar <s-k6@ti.com>; Brattlof, Bryan <bb@ti.com>; Chawdhry, Manorit <m-chawdhry@ti.com>; u-boot@lists.denx.de; Kumar, Udit <u-kumar1@ti.com>; Gujulan Elango, Hari Prasath <gehariprasath@ti.com>
Subject: Re: [EXTERNAL] Re: [PATCH v2 5/7] arm: dts: k3-am69: ddr: Update to v0.12.0 of DDR config tool
Hi Kevin
On 20/11/25 20:18, Francesco Dolcini wrote:
> Hello Kevin,
>
> On Thu, Nov 20, 2025 at 02:23:02PM +0000, Scholz, Kevin wrote:
>>
>> ODT is user configurable from the TDA4x (J784S4) DDR config tool.
>> Custom boards can modify this setting as needed.
>
> Thanks for explaining me the tool and the related config options and
> changes, however the question is why you have this difference in your
> specific configuration for AM69A SK board in which only dram3 has ODT
> enabled, and dram, dram1 and dram2 not. Is the layout/schematics of
> DRAM3 different from the others? Why?
Is there any specific reason for doing this as Francesco has pointed out?
>
> Francesco
>
--
Thanking You
Neha Malcom Francis
next prev parent reply other threads:[~2026-05-21 5:01 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 7:10 [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 1/7] arm: dts: k3-j7200: ddr: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 2/7] arm: dts: k3-j721s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 3/7] arm: dts: k3-am68: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 4/7] arm: dts: k3-j784s4: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 5/7] arm: dts: k3-am69: " Neha Malcom Francis
2025-11-07 15:44 ` Franz Schnyder
2025-11-10 4:25 ` Neha Malcom Francis
2025-11-20 8:16 ` Francesco Dolcini
2025-11-20 14:23 ` [EXTERNAL] " Scholz, Kevin
2025-11-20 14:48 ` Francesco Dolcini
2026-04-21 10:10 ` Neha Malcom Francis
2026-05-20 21:52 ` Scholz, Kevin [this message]
2026-05-21 5:47 ` Neha Malcom Francis
2026-05-21 6:26 ` Francesco Dolcini
2026-06-09 4:25 ` Kumar, Udit
2025-11-03 7:10 ` [PATCH v2 6/7] arm: dts: k3-j742s2: " Neha Malcom Francis
2025-11-03 7:10 ` [PATCH v2 7/7] doc: ti: k3: Add section for DDR configuration Neha Malcom Francis
2025-11-03 14:35 ` Romain Naour
2026-05-21 5:45 ` Neha Malcom Francis
2026-06-09 19:17 ` [PATCH v2 0/7] ti: j7: Update to v0.12.0 of DDR config tool Tom Rini
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