* [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk
@ 2025-03-30 16:24 Heinrich Schuchardt
2025-04-08 11:36 ` Leo Liang
2025-04-18 13:41 ` Yao Zi
0 siblings, 2 replies; 3+ messages in thread
From: Heinrich Schuchardt @ 2025-03-30 16:24 UTC (permalink / raw)
To: Rick Chen, Leo, Minda Chen, Hal Feng
Cc: Sumit Garg, E Shattow, Marek Vasut, u-boot, Heinrich Schuchardt
Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
name") the StarFive VisionFive 2 board fails to boot.
Before that patch the SPL debug UART showed warnings like:
clk_register: failed to get pll0_out device (parent of perh_root)
clk_register: failed to get pll0_out device (parent of qspi_ref_src)
clk_register: failed to get pll0_out device (parent of usb_125m)
clk_register: failed to get pll0_out device (parent of gmac_src)
clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)
The &pllclk clock needs to be enabled early.
Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
---
arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index ce7d9e16961..a9e318c4a31 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -102,6 +102,10 @@
bootph-pre-ram;
};
+&pllclk {
+ bootph-pre-ram;
+};
+
&syscrg {
bootph-pre-ram;
};
--
2.48.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk
2025-03-30 16:24 [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk Heinrich Schuchardt
@ 2025-04-08 11:36 ` Leo Liang
2025-04-18 13:41 ` Yao Zi
1 sibling, 0 replies; 3+ messages in thread
From: Leo Liang @ 2025-04-08 11:36 UTC (permalink / raw)
To: Heinrich Schuchardt
Cc: Rick Chen, Minda Chen, Hal Feng, Sumit Garg, E Shattow,
Marek Vasut, u-boot
On Sun, Mar 30, 2025 at 06:24:21PM +0200, Heinrich Schuchardt wrote:
> Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
> name") the StarFive VisionFive 2 board fails to boot.
>
> Before that patch the SPL debug UART showed warnings like:
>
> clk_register: failed to get pll0_out device (parent of perh_root)
> clk_register: failed to get pll0_out device (parent of qspi_ref_src)
> clk_register: failed to get pll0_out device (parent of usb_125m)
> clk_register: failed to get pll0_out device (parent of gmac_src)
> clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
> clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)
>
> The &pllclk clock needs to be enabled early.
>
> Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
> Suggested-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk
2025-03-30 16:24 [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk Heinrich Schuchardt
2025-04-08 11:36 ` Leo Liang
@ 2025-04-18 13:41 ` Yao Zi
1 sibling, 0 replies; 3+ messages in thread
From: Yao Zi @ 2025-04-18 13:41 UTC (permalink / raw)
To: Heinrich Schuchardt, Rick Chen, Leo, Minda Chen, Hal Feng
Cc: Sumit Garg, E Shattow, Marek Vasut, u-boot
On Sun, Mar 30, 2025 at 06:24:21PM +0200, Heinrich Schuchardt wrote:
> Since commit f98cd471f06b ("clk: clk-composite: Resolve parent clock by
> name") the StarFive VisionFive 2 board fails to boot.
>
> Before that patch the SPL debug UART showed warnings like:
>
> clk_register: failed to get pll0_out device (parent of perh_root)
> clk_register: failed to get pll0_out device (parent of qspi_ref_src)
> clk_register: failed to get pll0_out device (parent of usb_125m)
> clk_register: failed to get pll0_out device (parent of gmac_src)
> clk_register: failed to get pll0_out device (parent of gmac1_gtxclk)
> clk_register: failed to get pll0_out device (parent of gmac0_gtxclk)
>
> The &pllclk clock needs to be enabled early.
>
> Fixes: f98cd471f06b ("clk: clk-composite: Resolve parent clock by name")
> Suggested-by: Marek Vasut <marex@denx.de>
> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> ---
> arch/riscv/dts/jh7110-u-boot.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
Tested-by: Yao Zi <ziyao@disroot.org>
Sadly this didn't catch up with v2025.04, in which JH7110 SoCs are
broken...
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
> index ce7d9e16961..a9e318c4a31 100644
> --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -102,6 +102,10 @@
> bootph-pre-ram;
> };
>
> +&pllclk {
> + bootph-pre-ram;
> +};
> +
> &syscrg {
> bootph-pre-ram;
> };
> --
> 2.48.1
>
Thanks,
Yao Zi
^ permalink raw reply [flat|nested] 3+ messages in thread
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2025-03-30 16:24 [PATCH 1/1] riscv: dts: jh7110: add bootph-pre-ram for &pllclk Heinrich Schuchardt
2025-04-08 11:36 ` Leo Liang
2025-04-18 13:41 ` Yao Zi
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