[PATCH 0/3] Add support for LicheeRV Nano

[PATCH 0/3] Add support for LicheeRV Nano

[Thomas Bonnefille]

This patch series adds support in U-Boot for the Sophgo SG2002 RISCV SoC
and one board using this SoC, the LicheeRV Nano.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
Thomas Bonnefille (3):
      doc: add LicheeRV Nano and SG2002 SoC
      riscv: dts: sophgo: add device tree for LicheeRV Nano
      board: add support for LicheeRV Nano

 arch/riscv/Kconfig                        |  4 ++
 arch/riscv/dts/Makefile                   |  1 +
 arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++
 arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++
 board/sophgo/licheerv_nano/Kconfig        | 28 ++++++++++++
 board/sophgo/licheerv_nano/MAINTAINERS    |  4 ++
 board/sophgo/licheerv_nano/Makefile       |  5 +++
 board/sophgo/licheerv_nano/board.c        |  9 ++++
 configs/sipeed_licheerv_nano_defconfig    | 47 ++++++++++++++++++++
 doc/board/sophgo/licheerv_nano.rst        | 72 +++++++++++++++++++++++++++++++
 include/configs/licheerv_nano.h           | 24 +++++++++++
 11 files changed, 273 insertions(+)
---
base-commit: 3f772959501c99fbe5aa0b22a36efe3478d1ae1c
change-id: 20241024-licheerv-nano-c36d0432943b

Best regards,
-- 
Thomas Bonnefille <thomas.bonnefille@bootlin.com>

[PATCH 1/3] doc: add LicheeRV Nano and SG2002 SoC

[Thomas Bonnefille]

Provide a page describing the usage of U-Boot on the LicheeRV Nano and a
description of the board.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 doc/board/sophgo/licheerv_nano.rst | 72 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst
new file mode 100644
index 0000000000000000000000000000000000000000..70401e295c4a56845353c3a92ab4ec98678a1180
--- /dev/null
+++ b/doc/board/sophgo/licheerv_nano.rst
@@ -0,0 +1,72 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+LicheeRV Nano
+==========
+
+SG2002 RISC-V SoC
+------------------
+The SG2002 is a high-performance, low-power 64-bit RISC-V/ARM SoC from Sophgo.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+1. ns16550 UART Driver.
+2. Synopsys Designware MSHC Driver
+
+Building
+~~~~~~~~
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: console
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+   cd <U-Boot-dir>
+   make licheerv_nano_defconfig
+   make
+
+This will generate u-boot.bin
+
+Booting
+~~~~~~~
+Currently, we rely on vendor FSBL (First Stage Boot Loader) to initialize the
+clock and load the u-boot image, then bootup from it.
+
+To run u-boot.bin on top of FSBL, follow these steps:
+
+1. Use mainline OpenSBI with a newer version than 1.5 to generate fw_dynamic.
+
+2. Generate a compatible u-boot.bin using U-Boot with the LicheeRV Nano default
+   configuration.
+
+3. Use the vendor-provided tool [1] to create a unified fip.bin file containing
+   FSBL, OpenSBI, and U-Boot.
+   Note that you will have to use the file cv181x.bin as the FSBL.
+
+2. Place the generated fip.bin file into the FAT partition of the SD card.
+
+3. Insert the SD card into the board and power it on.
+
+The board will automatically execute the FSBL from the fip.bin file.
+Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke
+U-Boot.
+
+[1]: https://github.com/sophgo/fiptool
+
+
+Sample boot log from LicheeRV Nano board
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+.. code-block:: none
+
+   U-Boot 2024.10 (Oct 24 2024 - 15:00:20 +0200)licheerv_nano
+
+   DRAM:  256 MiB
+   Core:  19 devices, 11 uclasses, devicetree: separate
+   MMC:   mmc@4310000: 0
+   Loading Environment from nowhere... OK
+   In:    serial@4140000
+   Out:   serial@4140000
+   Err:   serial@4140000
+   Net:   No ethernet found.
+   Hit any key to stop autoboot:  0 
+   licheerv_nano# 

-- 
2.47.0

Re: [PATCH 1/3] doc: add LicheeRV Nano and SG2002 SoC

[Leo Liang]

Hi,

On Tue, Nov 12, 2024 at 03:57:36PM +0100, Thomas Bonnefille wrote:
> [EXTERNAL MAIL]
> 
> Provide a page describing the usage of U-Boot on the LicheeRV Nano and a
> description of the board.
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>  doc/board/sophgo/licheerv_nano.rst | 72 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/doc/board/sophgo/licheerv_nano.rst b/doc/board/sophgo/licheerv_nano.rst
> new file mode 100644
> index 0000000000000000000000000000000000000000..70401e295c4a56845353c3a92ab4ec98678a1180
> --- /dev/null
> +++ b/doc/board/sophgo/licheerv_nano.rst
> @@ -0,0 +1,72 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +LicheeRV Nano
> +==========

The title underline is too short and will fail `make htmldocs`.

> +
> +SG2002 RISC-V SoC
> +------------------
> +The SG2002 is a high-performance, low-power 64-bit RISC-V/ARM SoC from Sophgo.
> +
> +Mainline support
> +----------------
> +The support for following drivers are already enabled:
> +1. ns16550 UART Driver.
> +2. Synopsys Designware MSHC Driver
> +
> +Building
> +~~~~~~~~
> +1. Add the RISC-V toolchain to your PATH.
> +2. Setup ARCH & cross compilation environment variable:
> +
> +.. code-block:: console
> +
> +   export CROSS_COMPILE=<riscv64 toolchain prefix>
> +   cd <U-Boot-dir>
> +   make licheerv_nano_defconfig

The name of the defconfig does not seem to match what you provide in [patch 3/3] ?

> +   make
> +
> +This will generate u-boot.bin
> +
> +Booting
> +~~~~~~~
> +Currently, we rely on vendor FSBL (First Stage Boot Loader) to initialize the
> +clock and load the u-boot image, then bootup from it.
> +
> +To run u-boot.bin on top of FSBL, follow these steps:
> +
> +1. Use mainline OpenSBI with a newer version than 1.5 to generate fw_dynamic.
> +
> +2. Generate a compatible u-boot.bin using U-Boot with the LicheeRV Nano default
> +   configuration.
> +
> +3. Use the vendor-provided tool [1] to create a unified fip.bin file containing
> +   FSBL, OpenSBI, and U-Boot.
> +   Note that you will have to use the file cv181x.bin as the FSBL.
> +
> +2. Place the generated fip.bin file into the FAT partition of the SD card.
> +
> +3. Insert the SD card into the board and power it on.
> +
> +The board will automatically execute the FSBL from the fip.bin file.
> +Subsequently, it will transition to OpenSBI, and finally, OpenSBI will invoke
> +U-Boot.
> +
> +[1]: https://github.com/sophgo/fiptool
> +
> +
> +Sample boot log from LicheeRV Nano board
> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +.. code-block:: none
> +
> +   U-Boot 2024.10 (Oct 24 2024 - 15:00:20 +0200)licheerv_nano
> +
> +   DRAM:  256 MiB
> +   Core:  19 devices, 11 uclasses, devicetree: separate
> +   MMC:   mmc@4310000: 0
> +   Loading Environment from nowhere... OK
> +   In:    serial@4140000
> +   Out:   serial@4140000
> +   Err:   serial@4140000
> +   Net:   No ethernet found.
> +   Hit any key to stop autoboot:  0
> +   licheerv_nano#
> 
> --
> 2.47.0

Other than that,
LGTM.

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

[PATCH 2/3] riscv: dts: sophgo: add device tree for LicheeRV Nano

[Thomas Bonnefille]

Import a slightly modified version of the LicheeRV Nano and SG2002
device trees from the Linux Kernel. The current supported IPs are UART,
MMC, Timer, PLIC and CLINT.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/dts/Makefile                   |  1 +
 arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
 arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++++++++++
 3 files changed, 80 insertions(+)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 17cda483e128996bb944f5a2b9b7676d32e45ae5..0848cded398d45955dcc17b339dc1869829c6467 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
 dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
 dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb
+dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb
 dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
 dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
diff --git a/arch/riscv/dts/sg2002-licheerv-nano-b.dts b/arch/riscv/dts/sg2002-licheerv-nano-b.dts
new file mode 100644
index 0000000000000000000000000000000000000000..9871a75836c04a0b0943dc44c6a1090c90752dbd
--- /dev/null
+++ b/arch/riscv/dts/sg2002-licheerv-nano-b.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include "sg2002.dtsi"
+
+/ {
+	model = "LicheeRV Nano B";
+	compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
+
+	aliases {
+		gpio0 = &gpio0;
+		gpio1 = &gpio1;
+		gpio2 = &gpio2;
+		gpio3 = &gpio3;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+		serial4 = &uart4;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&osc {
+	clock-frequency = <25000000>;
+};
+
+&sdhci0 {
+	status = "okay";
+	bus-width = <4>;
+	no-1-8-v;
+	no-mmc;
+	no-sdio;
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/riscv/dts/sg2002.dtsi b/arch/riscv/dts/sg2002.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..0f97000fa8beaaa10a08d03211f7c4a0c2f6e001
--- /dev/null
+++ b/arch/riscv/dts/sg2002.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+	compatible = "sophgo,sg2002";
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>;
+	};
+};
+
+&plic {
+	compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-plic", "thead,c900-plic";
+};
+
+&clint {
+	compatible = "sophgo,sg2002-plic", "sophgo,cv1800b-clint", "thead,c900-clint";
+};
+
+&clk {
+	compatible = "sophgo,sg2002-clk", "sophgo,cv1800-clk";
+};
+
+&sdhci0 {
+	compatible = "sophgo,sg2002-dwcmshc", "sophgo,cv1800b-dwcmshc";
+};

-- 
2.47.0

Re: [PATCH 2/3] riscv: dts: sophgo: add device tree for LicheeRV Nano

[Leo Liang]

On Tue, Nov 12, 2024 at 03:57:37PM +0100, Thomas Bonnefille wrote:
> [EXTERNAL MAIL]
> 
> Import a slightly modified version of the LicheeRV Nano and SG2002
> device trees from the Linux Kernel. The current supported IPs are UART,
> MMC, Timer, PLIC and CLINT.
> 
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
>  arch/riscv/dts/Makefile                   |  1 +
>  arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
>  arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++++++++++
>  3 files changed, 80 insertions(+)

Hi Thomas,

Could we switch to use OF_UPSTREAM ?

Best regards,
Leo

Re: [PATCH 2/3] riscv: dts: sophgo: add device tree for LicheeRV Nano

[Thomas Bonnefille]

On Mon Nov 18, 2024 at 11:01 AM CET, Leo Liang wrote:
> On Tue, Nov 12, 2024 at 03:57:37PM +0100, Thomas Bonnefille wrote:
> > [EXTERNAL MAIL]
> > 
> > Import a slightly modified version of the LicheeRV Nano and SG2002
> > device trees from the Linux Kernel. The current supported IPs are UART,
> > MMC, Timer, PLIC and CLINT.
> > 
> > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > ---
> >  arch/riscv/dts/Makefile                   |  1 +
> >  arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
> >  arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++++++++++
> >  3 files changed, 80 insertions(+)
>
> Hi Thomas,
>
> Could we switch to use OF_UPSTREAM ?
>

Hello Leo,

Thank you for your review, I have a question though.

The LicheeRV Nano device tree isn't upstreamed yet. It's just in the
Sophgo SoC maintainer tree and should be merged in v6.13 so in ~10 weeks.
Can I keep it out of dts/upstream for the moment or should I merge it by
hand before ?

Re: [PATCH 2/3] riscv: dts: sophgo: add device tree for LicheeRV Nano

[Leo Liang]

On Tue, Nov 19, 2024 at 09:35:32PM +0100, Thomas Bonnefille wrote:
> [EXTERNAL MAIL]
> 
> On Mon Nov 18, 2024 at 11:01 AM CET, Leo Liang wrote:
> > On Tue, Nov 12, 2024 at 03:57:37PM +0100, Thomas Bonnefille wrote:
> > > [EXTERNAL MAIL]
> > >
> > > Import a slightly modified version of the LicheeRV Nano and SG2002
> > > device trees from the Linux Kernel. The current supported IPs are UART,
> > > MMC, Timer, PLIC and CLINT.
> > >
> > > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > > ---
> > >  arch/riscv/dts/Makefile                   |  1 +
> > >  arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
> > >  arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++++++++++
> > >  3 files changed, 80 insertions(+)
> >
> > Hi Thomas,
> >
> > Could we switch to use OF_UPSTREAM ?
> >
> 
> Hello Leo,
> 
> Thank you for your review, I have a question though.
> 
> The LicheeRV Nano device tree isn't upstreamed yet. It's just in the
> Sophgo SoC maintainer tree and should be merged in v6.13 so in ~10 weeks.
> Can I keep it out of dts/upstream for the moment or should I merge it by
> hand before ?

Hi Thomas,

Got it! So there should be a follow-up patch that 
switch to OF_UPSTREAM once the upstream LicheeRV Nano DTS is settled, right?

I can take this patch as is for now. Thanks!

Best regards,
Leo

Re: [PATCH 2/3] riscv: dts: sophgo: add device tree for LicheeRV Nano

[Thomas Bonnefille]

On Mon Nov 25, 2024 at 10:59 AM CET, Leo Liang wrote:
> On Tue, Nov 19, 2024 at 09:35:32PM +0100, Thomas Bonnefille wrote:
> > [EXTERNAL MAIL]
> > 
> > On Mon Nov 18, 2024 at 11:01 AM CET, Leo Liang wrote:
> > > On Tue, Nov 12, 2024 at 03:57:37PM +0100, Thomas Bonnefille wrote:
> > > > [EXTERNAL MAIL]
> > > >
> > > > Import a slightly modified version of the LicheeRV Nano and SG2002
> > > > device trees from the Linux Kernel. The current supported IPs are UART,
> > > > MMC, Timer, PLIC and CLINT.
> > > >
> > > > Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> > > > ---
> > > >  arch/riscv/dts/Makefile                   |  1 +
> > > >  arch/riscv/dts/sg2002-licheerv-nano-b.dts | 45 +++++++++++++++++++++++++++++++
> > > >  arch/riscv/dts/sg2002.dtsi                | 34 +++++++++++++++++++++++
> > > >  3 files changed, 80 insertions(+)
> > >
> > > Hi Thomas,
> > >
> > > Could we switch to use OF_UPSTREAM ?
> > >
> > 
> > Hello Leo,
> > 
> > Thank you for your review, I have a question though.
> > 
> > The LicheeRV Nano device tree isn't upstreamed yet. It's just in the
> > Sophgo SoC maintainer tree and should be merged in v6.13 so in ~10 weeks.
> > Can I keep it out of dts/upstream for the moment or should I merge it by
> > hand before ?
>
> Hi Thomas,
>
> Got it! So there should be a follow-up patch that 
> switch to OF_UPSTREAM once the upstream LicheeRV Nano DTS is settled, right?

Yes, of course, I'll do that when Linux 6.13 comes out.

>
> I can take this patch as is for now. Thanks!
>
> Best regards,
> Leo
Thank you very much !

Best regards, Thomas

[PATCH 3/3] board: add support for LicheeRV Nano

[Thomas Bonnefille]

The LicheeRV Nano is a small SBC using the Sophgo SG2002 RISCV SoC.

Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
 arch/riscv/Kconfig                     |  4 +++
 board/sophgo/licheerv_nano/Kconfig     | 28 ++++++++++++++++++++
 board/sophgo/licheerv_nano/MAINTAINERS |  4 +++
 board/sophgo/licheerv_nano/Makefile    |  5 ++++
 board/sophgo/licheerv_nano/board.c     |  9 +++++++
 configs/sipeed_licheerv_nano_defconfig | 47 ++++++++++++++++++++++++++++++++++
 include/configs/licheerv_nano.h        | 24 +++++++++++++++++
 7 files changed, 121 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016c52728862019c426f031262c40901ee51..91d531a4e9eb8e915bf47a4be2ad3392f64fa352 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -11,6 +11,9 @@ choice
 config TARGET_ANDES_AE350
 	bool "Support Andes ae350"
 
+config TARGET_LICHEERV_NANO
+	bool "Support LicheeRV Nano Board"
+
 config TARGET_MICROCHIP_ICICLE
 	bool "Support Microchip PolarFire-SoC Icicle Board"
 
@@ -88,6 +91,7 @@ source "board/sifive/unleashed/Kconfig"
 source "board/sifive/unmatched/Kconfig"
 source "board/sipeed/maix/Kconfig"
 source "board/sophgo/milkv_duo/Kconfig"
+source "board/sophgo/licheerv_nano/Kconfig"
 source "board/starfive/visionfive2/Kconfig"
 source "board/thead/th1520_lpi4a/Kconfig"
 source "board/xilinx/mbv/Kconfig"
diff --git a/board/sophgo/licheerv_nano/Kconfig b/board/sophgo/licheerv_nano/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..660d3c5d0958632cde45eeca58c2921881948452
--- /dev/null
+++ b/board/sophgo/licheerv_nano/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_LICHEERV_NANO
+
+config SYS_BOARD
+	default "licheerv_nano"
+
+config SYS_VENDOR
+	default "sophgo"
+
+config SYS_CPU
+	default "cv1800b"
+
+config SYS_CONFIG_NAME
+	default "licheerv_nano"
+
+config TEXT_BASE
+	default 0x80200000
+
+config ENV_SIZE
+	default 0x20000
+
+config ENV_SECT_SIZE
+	default 0x40000
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOPHGO_CV1800B
+
+endif
diff --git a/board/sophgo/licheerv_nano/MAINTAINERS b/board/sophgo/licheerv_nano/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..88cab489c985925f736a9537ff797870bea38b9d
--- /dev/null
+++ b/board/sophgo/licheerv_nano/MAINTAINERS
@@ -0,0 +1,4 @@
+LicheeRV Nano
+M:	Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+S:	Maintained
+F:	board/sophgo/licheerv_nano/
diff --git a/board/sophgo/licheerv_nano/Makefile b/board/sophgo/licheerv_nano/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..59fcd5bfba91ceacb10f56692e9a1c82cc66d6cf
--- /dev/null
+++ b/board/sophgo/licheerv_nano/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+
+obj-y += board.o
diff --git a/board/sophgo/licheerv_nano/board.c b/board/sophgo/licheerv_nano/board.c
new file mode 100644
index 0000000000000000000000000000000000000000..eaa47be17396915e74c141e09fef752c07719f73
--- /dev/null
+++ b/board/sophgo/licheerv_nano/board.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
+ */
+
+int board_init(void)
+{
+	return 0;
+}
diff --git a/configs/sipeed_licheerv_nano_defconfig b/configs/sipeed_licheerv_nano_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..14fefa968c677f3d56c42f8ad6bd38c02b17b017
--- /dev/null
+++ b/configs/sipeed_licheerv_nano_defconfig
@@ -0,0 +1,47 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_LEN=0x820000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x82300000
+CONFIG_DEFAULT_DEVICE_TREE="sg2002-licheerv-nano-b"
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_LOAD_ADDR=0x80080000
+CONFIG_IDENT_STRING="licheerv_nano"
+CONFIG_TARGET_LICHEERV_NANO=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_FIT=y
+CONFIG_BOOTSTD_FULL=y
+# CONFIG_BOOTMETH_EFI_BOOTMGR is not set
+CONFIG_SD_BOOT=y
+CONFIG_BOOTCOMMAND="run distro_bootcmd"
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=544
+CONFIG_SYS_PROMPT="licheerv_nano# "
+# CONFIG_CMD_BOOTDEV is not set
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+# CONFIG_CMD_MII is not set
+CONFIG_CMD_SYSBOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_ENV_OVERWRITE=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_CLK_SOPHGO_CV1800B=y
+CONFIG_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_CV1800B=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_SYS_NS16550=y
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SPI=y
+CONFIG_CV1800B_SPIF=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CV1800B=y
diff --git a/include/configs/licheerv_nano.h b/include/configs/licheerv_nano.h
new file mode 100644
index 0000000000000000000000000000000000000000..2ea7943f66f46aa59f59d4aa7c2e8f7e4d84d301
--- /dev/null
+++ b/include/configs/licheerv_nano.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2024, Thomas Bonnefille <thomas.bonnefille@bootlin.com>
+ *
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_bootcmd.h>
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#define CFG_SYS_SDRAM_BASE         0x80000000
+
+#define CFG_EXTRA_ENV_SETTINGS  "consoledev=ttyS0\0" \
+								"baudrate=115200\0" \
+								"fdt_addr_r=0x82000000\0" \
+								"kernel_addr_r=0x81000000\0" \
+								"scriptaddr=0x80c00000\0" \
+								BOOTENV
+
+#endif /* __CONFIG_H */

-- 
2.47.0