* [PATCH v2 1/9] mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-27 13:28 ` Kathpalia, Tanmay
2026-05-20 10:45 ` [PATCH v2 2/9] mtd: spi: enable spi_nor_remove() in soft reset config Guodong Xu
` (7 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
Fix to select CONFIG_SPL_SPI_FLASH_TINY in SPL_BUILD stage.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- No change.
---
drivers/mtd/spi/Makefile | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 44e67cd913a..9a96be11e6d 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -8,14 +8,13 @@ spi-nor-y := sf_probe.o spi-nor-ids.o
ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
+endif
+
ifeq ($(CONFIG_$(PHASE_)SPI_FLASH_TINY),y)
spi-nor-y += spi-nor-tiny.o
else
spi-nor-y += spi-nor-core.o
endif
-else
-spi-nor-y += spi-nor-core.o
-endif
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 2/9] mtd: spi: enable spi_nor_remove() in soft reset config
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
2026-05-20 10:45 ` [PATCH v2 1/9] mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-27 13:40 ` Kathpalia, Tanmay
2026-05-20 10:45 ` [PATCH v2 3/9] spi: fsl: add support for Spacemit K1 SoC Guodong Xu
` (6 subsequent siblings)
8 siblings, 1 reply; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
spi_nor_remove() is only implemented in spi-nor-core.o, not spi-nor-tiny.o.
So make spi_nor_remove() only valid for CONFIG_SPI_FLASH_SOFT_RESET.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- No change.
---
drivers/mtd/spi/sf_probe.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 7100b64bf22..dee03662d45 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -229,9 +229,11 @@ static int spi_flash_std_remove(struct udevice *dev)
spi_mem_dirmap_destroy(flash->dirmap.rdesc);
}
- ret = spi_nor_remove(flash);
- if (ret)
- return ret;
+ if (CONFIG_IS_ENABLED(SPI_FLASH_SOFT_RESET)) {
+ ret = spi_nor_remove(flash);
+ if (ret)
+ return ret;
+ }
if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
spi_flash_mtd_unregister(flash);
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 2/9] mtd: spi: enable spi_nor_remove() in soft reset config
2026-05-20 10:45 ` [PATCH v2 2/9] mtd: spi: enable spi_nor_remove() in soft reset config Guodong Xu
@ 2026-05-27 13:40 ` Kathpalia, Tanmay
0 siblings, 0 replies; 16+ messages in thread
From: Kathpalia, Tanmay @ 2026-05-27 13:40 UTC (permalink / raw)
To: Guodong Xu, Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Sumit Garg, Casey Connolly, Neil Armstrong, Guodong Xu,
Rui Miguel Silva
On 5/20/2026 4:15 PM, Guodong Xu wrote:
> From: Raymond Mao <raymond.mao@riscstar.com>
>
> spi_nor_remove() is only implemented in spi-nor-core.o, not spi-nor-tiny.o.
>
> So make spi_nor_remove() only valid for CONFIG_SPI_FLASH_SOFT_RESET.
>
> Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
>
> ---
> v2:
> - No change.
> ---
> drivers/mtd/spi/sf_probe.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
> index 7100b64bf22..dee03662d45 100644
> --- a/drivers/mtd/spi/sf_probe.c
> +++ b/drivers/mtd/spi/sf_probe.c
> @@ -229,9 +229,11 @@ static int spi_flash_std_remove(struct udevice *dev)
> spi_mem_dirmap_destroy(flash->dirmap.rdesc);
> }
>
> - ret = spi_nor_remove(flash);
> - if (ret)
> - return ret;
> + if (CONFIG_IS_ENABLED(SPI_FLASH_SOFT_RESET)) {
> + ret = spi_nor_remove(flash);
> + if (ret)
> + return ret;
> + }
>
> if (CONFIG_IS_ENABLED(SPI_FLASH_MTD))
> spi_flash_mtd_unregister(flash);
The tiny configuration is already handled by the inline stub in spi-nor.h,
where spi_nor_remove() is a no-op for SPI_FLASH_TINY. So I think adding a
SPI_FLASH_SOFT_RESET guard around the remove call does not provide
additional value.
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 3/9] spi: fsl: add support for Spacemit K1 SoC
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
2026-05-20 10:45 ` [PATCH v2 1/9] mtd: spi: select SPL_SPI_FLASH_TINY in SPL stage Guodong Xu
2026-05-20 10:45 ` [PATCH v2 2/9] mtd: spi: enable spi_nor_remove() in soft reset config Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-20 10:45 ` [PATCH v2 4/9] spl: k1: enable SPI NOR flash detection and boot Guodong Xu
` (5 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
Make FSL QSPI driver supporting Spacemit K1 SoC.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- No change.
---
drivers/spi/fsl_qspi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 65ab3e306d7..5692510a558 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -267,6 +267,14 @@ static const struct fsl_qspi_devtype_data ls2080a_data = {
.little_endian = true,
};
+static const struct fsl_qspi_devtype_data spacemit_k1_data = {
+ .rxfifo = SZ_128,
+ .txfifo = SZ_256,
+ .ahb_buf_size = SZ_128,
+ .quirks = QUADSPI_QUIRK_TKT253890,
+ .little_endian = true,
+};
+
struct fsl_qspi {
struct udevice *dev;
void __iomem *iobase;
@@ -870,6 +878,7 @@ static const struct udevice_id fsl_qspi_ids[] = {
{ .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, },
{ .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls2080a_data, },
{ .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, },
+ { .compatible = "spacemit,k1-qspi", .data = (ulong)&spacemit_k1_data, },
{ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 4/9] spl: k1: enable SPI NOR flash detection and boot
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (2 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 3/9] spi: fsl: add support for Spacemit K1 SoC Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-20 10:45 ` [PATCH v2 5/9] riscv: binman: Always set default configuration in FIT image Guodong Xu
` (4 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
Add nor_early_init() to probe the QSPI controller and SPI NOR flash
in SPL. Switch spl_boot_device() to BOOT_DEVICE_SPI so the board
boots from SPI flash.
Change the default device tree to k1-musepi-pro, whose u-boot
overlay already defines the QSPI controller and flash node with
bootph-pre-ram markers. Enable the required SPI driver model and
flash config options.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Renamed and reworked from v1 11/16 "board: k1: enable SPI NOR
flash in SPL".
- New k1-musepi-pro-u-boot.dtsi overlay; default DT switched to it.
- SPL probes SPI NOR in early init and loads next stage from it.
---
arch/riscv/dts/k1-musepi-pro-u-boot.dtsi | 273 +++++++++++++++++++++++++++++++
board/spacemit/k1/spl.c | 24 ++-
configs/spacemit_k1_defconfig | 25 ++-
3 files changed, 319 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi
new file mode 100644
index 00000000000..8a9a2a09de9
--- /dev/null
+++ b/arch/riscv/dts/k1-musepi-pro-u-boot.dtsi
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright (C) 2026 RISCstar Ltd.
+ */
+
+#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include "binman.dtsi"
+
+/ {
+ aliases {
+ console = &uart0;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+};
+
+&syscon_mpmu {
+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>,
+ <&pll CLK_PLL1_D4>;
+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m",
+ "pll1_d4";
+};
+
+&syscon_apbc {
+ clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>,
+ <&pll CLK_PLL1_D4>,
+ <&syscon_mpmu CLK_PLL1_31P5>,
+ <&syscon_apmu CLK_PMUA_ACLK>;
+ clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m",
+ "pll1_d4", "pll1_d78_31p5", "pmua_aclk";
+};
+
+&uart0 {
+ bootph-pre-ram;
+};
+
+&osc_32k {
+ bootph-pre-ram;
+};
+
+&vctcxo_1m {
+ bootph-pre-ram;
+};
+
+&vctcxo_3m {
+ bootph-pre-ram;
+};
+
+&vctcxo_24m {
+ bootph-pre-ram;
+};
+
+&syscon_mpmu {
+ bootph-pre-ram;
+};
+
+&pll {
+ bootph-pre-ram;
+};
+
+&syscon_apmu {
+ bootph-pre-ram;
+};
+
+&syscon_apbc {
+ bootph-pre-ram;
+};
+
+&i2c2 {
+ bootph-pre-ram;
+ status = "okay";
+ pinctrl-0 = <&i2c2_0_cfg>;
+ pinctrl-names = "default";
+ resets = <&syscon_apbc RESET_TWSI2>;
+
+ eeprom@50 {
+ bootph-pre-ram;
+ status = "okay";
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ vcc-supply = <&buck3_1v8>; /* EEPROM_VCC1V8 */
+ pagesize = <16>;
+ read-only;
+ size = <256>;
+
+ nvmem-layout {
+ compatible = "onie,tlv-layout";
+
+ mac-address {
+ #nvmem-cell-cells = <1>;
+ };
+
+ num-macs {
+ };
+
+ serial-number {
+ };
+ };
+ };
+};
+
+&i2c8 {
+ bootph-pre-ram;
+ pinctrl-0 = <&i2c8_cfg>;
+ pinctrl-names = "default";
+ resets = <&syscon_apbc RESET_TWSI8>;
+ status = "okay";
+
+ pmic@41 {
+ bootph-pre-ram;
+ compatible = "spacemit,p1";
+ reg = <0x41>;
+ interrupts = <64>;
+ status = "okay";
+
+ regulators {
+ buck1 {
+ bootph-pre-ram;
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck3_1v8: buck3 {
+ bootph-pre-ram;
+ regulator-name = "vdd_1v8";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ buck6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3450000>;
+ regulator-ramp-delay = <5000>;
+ regulator-always-on;
+ };
+
+ aldo1 {
+ bootph-pre-ram;
+ regulator-name = "vdd_1v8_mmc";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ aldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ aldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo1 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-boot-on;
+ };
+
+ dldo2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo3 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo4 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo5 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ dldo6 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ regulator-always-on;
+ };
+
+ dldo7 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3400000>;
+ };
+ };
+ };
+};
+
+&qspi {
+ bootph-pre-ram;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_cfg>;
+ status = "okay";
+
+ flash@0 {
+ bootph-pre-ram;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <26500000>;
+ m25p,fast-read;
+ broken-flash-reset;
+ status = "okay";
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ type = "section";
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ };
+
+ ddr-fw {
+ type = "blob";
+ filename = "ddr_fw.bin";
+ align = <64>;
+ };
+
+ u-boot-any {
+ type = "section";
+ size = <0>;
+ offset = <0>;
+ };
+ };
+};
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index 2afabc72a3f..da4169fbc8c 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -16,6 +16,7 @@
#include <linux/delay.h>
#include <log.h>
#include <power/regulator.h>
+#include <spi_flash.h>
#include <spl.h>
#include <tlv_eeprom.h>
#include "tlv_codes.h"
@@ -306,6 +307,26 @@ void ddr_early_init(void)
log_info("DDR is not ready\n");
}
+void nor_early_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device(UCLASS_SPI, 0, &dev);
+ if (ret)
+ panic("Fail to detect spi controller.\n");
+ udelay(10);
+ ret = uclass_get_device(UCLASS_SPI_FLASH, 0, &dev);
+ if (ret)
+ log_info("Fail to detect spi nor flash.\n");
+ udelay(10);
+}
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+}
+
void board_init_f(ulong dummy)
{
u8 i2c_buf[I2C_BUF_SIZE] = { 0 };
@@ -331,11 +352,12 @@ void board_init_f(ulong dummy)
pmic_init();
ddr_early_init();
+ nor_early_init();
}
u32 spl_boot_device(void)
{
- return BOOT_DEVICE_NOR;
+ return BOOT_DEVICE_SPI;
}
void spl_board_init(void)
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index e71c079bef2..64c724c62a5 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -1,15 +1,19 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x5000
+CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
-CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-bananapi-f3"
+CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-musepi-pro"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_STACK=0xc083fb00
CONFIG_SPL_TEXT_BASE=0xc0801000
CONFIG_SPL_BSS_START_ADDR=0xc083fc00
CONFIG_SPL_BSS_MAX_SIZE=0x400
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0xc00000
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x100000
CONFIG_SYS_BOOTM_LEN=0xa000000
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_SPL_SIZE_LIMIT=0x31000
@@ -23,6 +27,8 @@ CONFIG_SPL_RISCV_MMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_FIT=y
+CONFIG_SPL_HAS_LOAD_FIT_ADDRESS=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_CBSIZE=256
@@ -64,3 +70,18 @@ CONFIG_SYS_NS16550=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_TIMER_EARLY=y
CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_FSL_QSPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_MEM=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x000a0000
+CONFIG_CMD_SPI=y
+CONFIG_SPL_SPI=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_SPI_FLASH_TINY=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 5/9] riscv: binman: Always set default configuration in FIT image
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (3 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 4/9] spl: k1: enable SPI NOR flash detection and boot Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-20 10:45 ` [PATCH v2 6/9] spacemit: k1: Add multiple device tree support Guodong Xu
` (3 subsequent siblings)
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
When CONFIG_MULTI_DTB_FIT is enabled, the FIT image contains multiple
device tree configurations for different boards. The default
configuration must be explicitly set to ensure the FIT framework
traverses all available configurations instead of falling back to
CONFIG_DEFAULT_DEVICE_TREE.
Without this default property, fit_find_config_node() will use
CONFIG_DEFAULT_DEVICE_TREE as the configuration name to match.
This prevents the SPL from correctly selecting the appropriate
DTB based on runtime board detection (e.g., from EEPROM).
Remove the conditional guard so that "default = conf-1" is always
present in the FIT image, regardless of CONFIG_MULTI_DTB_FIT.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- No change.
---
arch/riscv/dts/binman.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
index b518560bb94..84c261c6849 100644
--- a/arch/riscv/dts/binman.dtsi
+++ b/arch/riscv/dts/binman.dtsi
@@ -93,9 +93,7 @@
configurations {
-#ifndef CONFIG_MULTI_DTB_FIT
default = "conf-1";
-#endif
#if !defined(CONFIG_OF_BOARD) || defined(CONFIG_MULTI_DTB_FIT)
@conf-SEQ {
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 6/9] spacemit: k1: Add multiple device tree support
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (4 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 5/9] riscv: binman: Always set default configuration in FIT image Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-24 21:25 ` Aurelien Jarno
2026-05-26 13:36 ` Simon Glass
2026-05-20 10:45 ` [PATCH v2 7/9] pinctrl: add pinctrl driver for Spacemit K1 SoC Guodong Xu
` (2 subsequent siblings)
8 siblings, 2 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
Enable multiple DTB support in the FIT image for the Spacemit K1 SoC,
allowing a single U-Boot binary to support different board variants.
The SPL reads the board type from EEPROM and selects the corresponding
device tree at runtime via board_fit_config_name_match(), ensuring the
correct hardware description is passed to U-Boot proper.
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Reworked. Drop the v1 approach (new local k1-muse-pi-pro.dts,
enlarge SYS_MALLOC_F_LEN, MMODE switch).
- Use binman --fit-multi-config so u-boot.itb packs multiple board
DTs from the upstream tree.
---
board/spacemit/k1/spl.c | 42 ++++++++++++++++++++++++++++++++++--------
configs/spacemit_k1_defconfig | 2 ++
2 files changed, 36 insertions(+), 8 deletions(-)
diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
index da4169fbc8c..d749e21a2d5 100644
--- a/board/spacemit/k1/spl.c
+++ b/board/spacemit/k1/spl.c
@@ -13,6 +13,7 @@
#include <dm/device.h>
#include <dm/uclass.h>
#include <i2c.h>
+#include <linux/ctype.h>
#include <linux/delay.h>
#include <log.h>
#include <power/regulator.h>
@@ -55,6 +56,8 @@ struct ddr_cfg {
binman_sym_declare(ulong, ddr_fw, image_pos);
binman_sym_declare(ulong, ddr_fw, size);
+char product_name[I2C_BUF_SIZE] = "k1";
+
static void i2c_early_init(void)
{
struct udevice *bus;
@@ -322,14 +325,8 @@ void nor_early_init(void)
udelay(10);
}
-void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
-{
- return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
-}
-
void board_init_f(ulong dummy)
{
- u8 i2c_buf[I2C_BUF_SIZE] = { 0 };
int ret;
ret = spl_early_init();
@@ -344,11 +341,11 @@ void board_init_f(ulong dummy)
preloader_console_init();
i2c_early_init();
- ret = read_product_name(i2c_buf, I2C_BUF_SIZE);
+ ret = read_product_name(product_name, I2C_BUF_SIZE);
if (ret)
log_info("Fail to detect board:%d\n", ret);
else
- log_info("Get board name:%s\n", (char *)i2c_buf);
+ log_info("Get board name:%s\n", product_name);
pmic_init();
ddr_early_init();
@@ -363,3 +360,32 @@ u32 spl_boot_device(void)
void spl_board_init(void)
{
}
+
+int board_fit_config_name_match(const char *name)
+{
+ char fdt_name[I2C_BUF_SIZE];
+ int i;
+
+ memset(fdt_name, 0, I2C_BUF_SIZE);
+ if (!strncmp(product_name, "k1-x_", 5)) {
+ snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
+ &product_name[5]);
+ }
+ if (fdt_name[0] == '\0') {
+ /* set default board name */
+ sprintf(fdt_name, "k1-musepi-pro");
+ }
+ for (i = 0; i < I2C_BUF_SIZE; i++) {
+ if (fdt_name[i] == '\0')
+ break;
+ fdt_name[i] = tolower(fdt_name[i]);
+ }
+ if (!strcmp(name, fdt_name))
+ return 0;
+ return -ENOENT;
+}
+
+void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
+{
+ return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
+}
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 64c724c62a5..465788cc2e5 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=2
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-musepi-pro"
+CONFIG_OF_LIST="spacemit/k1-bananapi-f3 spacemit/k1-musepi-pro"
CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
CONFIG_SPL_STACK=0xc083fb00
CONFIG_SPL_TEXT_BASE=0xc0801000
@@ -27,6 +28,7 @@ CONFIG_SPL_RISCV_MMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_STACK_SIZE=0x100000
CONFIG_FIT=y
+CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_HAS_LOAD_FIT_ADDRESS=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000
CONFIG_SUPPORT_RAW_INITRD=y
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH v2 6/9] spacemit: k1: Add multiple device tree support
2026-05-20 10:45 ` [PATCH v2 6/9] spacemit: k1: Add multiple device tree support Guodong Xu
@ 2026-05-24 21:25 ` Aurelien Jarno
2026-05-26 13:24 ` Guodong Xu
2026-05-26 13:36 ` Simon Glass
1 sibling, 1 reply; 16+ messages in thread
From: Aurelien Jarno @ 2026-05-24 21:25 UTC (permalink / raw)
To: Guodong Xu
Cc: Takahiro Kuwano, u-boot, u-boot-spacemit, Vignesh R, Tom Rini,
Raymond Mao, Rick Chen, Leo, Huan Zhou, Peng Fan, Sam Protsenko,
Mayuresh Chitale, Yao Zi, Anis Chali, Dan Carpenter,
Sean Anderson, Heiko Schocher, Rasmus Villemoes, Philip Molloy,
Michal Simek, Yegor Yefremov, Eoin Dickson, Tanmay Kathpalia,
Sumit Garg, Casey Connolly, Neil Armstrong, Guodong Xu,
Rui Miguel Silva
Hi,
On 2026-05-20 06:45, Guodong Xu wrote:
> Enable multiple DTB support in the FIT image for the Spacemit K1 SoC,
> allowing a single U-Boot binary to support different board variants.
>
> The SPL reads the board type from EEPROM and selects the corresponding
> device tree at runtime via board_fit_config_name_match(), ensuring the
> correct hardware description is passed to U-Boot proper.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
>
> ---
> v2:
> - Reworked. Drop the v1 approach (new local k1-muse-pi-pro.dts,
> enlarge SYS_MALLOC_F_LEN, MMODE switch).
> - Use binman --fit-multi-config so u-boot.itb packs multiple board
> DTs from the upstream tree.
> ---
> board/spacemit/k1/spl.c | 42 ++++++++++++++++++++++++++++++++++--------
> configs/spacemit_k1_defconfig | 2 ++
> 2 files changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
> index da4169fbc8c..d749e21a2d5 100644
> --- a/board/spacemit/k1/spl.c
> +++ b/board/spacemit/k1/spl.c
> @@ -13,6 +13,7 @@
> #include <dm/device.h>
> #include <dm/uclass.h>
> #include <i2c.h>
> +#include <linux/ctype.h>
> #include <linux/delay.h>
> #include <log.h>
> #include <power/regulator.h>
> @@ -55,6 +56,8 @@ struct ddr_cfg {
> binman_sym_declare(ulong, ddr_fw, image_pos);
> binman_sym_declare(ulong, ddr_fw, size);
>
> +char product_name[I2C_BUF_SIZE] = "k1";
> +
> static void i2c_early_init(void)
> {
> struct udevice *bus;
> @@ -322,14 +325,8 @@ void nor_early_init(void)
> udelay(10);
> }
>
> -void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
> -{
> - return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
> -}
> -
> void board_init_f(ulong dummy)
> {
> - u8 i2c_buf[I2C_BUF_SIZE] = { 0 };
> int ret;
>
> ret = spl_early_init();
> @@ -344,11 +341,11 @@ void board_init_f(ulong dummy)
> preloader_console_init();
>
> i2c_early_init();
> - ret = read_product_name(i2c_buf, I2C_BUF_SIZE);
> + ret = read_product_name(product_name, I2C_BUF_SIZE);
> if (ret)
> log_info("Fail to detect board:%d\n", ret);
> else
> - log_info("Get board name:%s\n", (char *)i2c_buf);
> + log_info("Get board name:%s\n", product_name);
> pmic_init();
>
> ddr_early_init();
> @@ -363,3 +360,32 @@ u32 spl_boot_device(void)
> void spl_board_init(void)
> {
> }
> +
> +int board_fit_config_name_match(const char *name)
> +{
> + char fdt_name[I2C_BUF_SIZE];
> + int i;
> +
> + memset(fdt_name, 0, I2C_BUF_SIZE);
> + if (!strncmp(product_name, "k1-x_", 5)) {
> + snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
> + &product_name[5]);
> + }
I wonder if any normalisation would be better in board_init_f() as
board_fit_config_name_match() is basically called for each possible
board. Same for the tolower() loop below.
> + if (fdt_name[0] == '\0') {
> + /* set default board name */
> + sprintf(fdt_name, "k1-musepi-pro");
> + }
I am not sure k1-musepi-pro is a good default. The experience is that
the Banana-Pi F3 (known as k1-x_deb1 in the vendor code) doesn't have a
product name defined in the TLV EEPROM and thus should probably be the
default.
> + for (i = 0; i < I2C_BUF_SIZE; i++) {
> + if (fdt_name[i] == '\0')
> + break;
> + fdt_name[i] = tolower(fdt_name[i]);
> + }
> + if (!strcmp(name, fdt_name))
> + return 0;
I am not sure that all the vendor product names will match the linux dtb
names, so maybe just using a table to do the mapping would be better.
Anyway, as long as the musepi-pro is the only one supported that should
be fine.
Regards
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurelien@aurel32.net http://aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 6/9] spacemit: k1: Add multiple device tree support
2026-05-24 21:25 ` Aurelien Jarno
@ 2026-05-26 13:24 ` Guodong Xu
0 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-26 13:24 UTC (permalink / raw)
To: Aurelien Jarno
Cc: Takahiro Kuwano, u-boot, u-boot-spacemit, Vignesh R, Tom Rini,
Raymond Mao, Rick Chen, Leo, Huan Zhou, Peng Fan, Sam Protsenko,
Mayuresh Chitale, Yao Zi, Anis Chali, Dan Carpenter,
Sean Anderson, Heiko Schocher, Rasmus Villemoes, Philip Molloy,
Michal Simek, Yegor Yefremov, Eoin Dickson, Tanmay Kathpalia,
Sumit Garg, Casey Connolly, Neil Armstrong, Rui Miguel Silva,
Guodong Xu
Hi, Aurelien
Thanks for the review.
On Mon, May 25, 2026 at 5:26 AM Aurelien Jarno <aurelien@aurel32.net> wrote:
>
> Hi,
>
> On 2026-05-20 06:45, Guodong Xu wrote:
> > Enable multiple DTB support in the FIT image for the Spacemit K1 SoC,
> > allowing a single U-Boot binary to support different board variants.
> >
> > @@ -363,3 +360,32 @@ u32 spl_boot_device(void)
> > void spl_board_init(void)
> > {
> > }
> > +
> > +int board_fit_config_name_match(const char *name)
> > +{
> > + char fdt_name[I2C_BUF_SIZE];
> > + int i;
> > +
> > + memset(fdt_name, 0, I2C_BUF_SIZE);
> > + if (!strncmp(product_name, "k1-x_", 5)) {
> > + snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
> > + &product_name[5]);
> > + }
>
> I wonder if any normalisation would be better in board_init_f() as
> board_fit_config_name_match() is basically called for each possible
> board. Same for the tolower() loop below.
Agree, will move both into board_init_f() in v3.
>
> > + if (fdt_name[0] == '\0') {
> > + /* set default board name */
> > + sprintf(fdt_name, "k1-musepi-pro");
> > + }
>
> I am not sure k1-musepi-pro is a good default. The experience is that
> the Banana-Pi F3 (known as k1-x_deb1 in the vendor code) doesn't have a
> product name defined in the TLV EEPROM and thus should probably be the
> default.
Thank you for this observation. Agree.
Will change the default to spacemit/k1-bananapi-f3 in v3 so a
BPI-F3 with no TLV product name falls through to the correct DTB.
>
> > + for (i = 0; i < I2C_BUF_SIZE; i++) {
> > + if (fdt_name[i] == '\0')
> > + break;
> > + fdt_name[i] = tolower(fdt_name[i]);
> > + }
> > + if (!strcmp(name, fdt_name))
> > + return 0;
>
> I am not sure that all the vendor product names will match the linux dtb
> names, so maybe just using a table to do the mapping would be better.
> Anyway, as long as the musepi-pro is the only one supported that should
> be fine.
Agree. A table will be more flexible and easy-to-expand. In v3 I will use
an explicit per-board mapping:
k1-x_MUSE-Pi-Pro -> spacemit/k1-musepi-pro
k1-x_deb1 -> spacemit/k1-bananapi-f3
k1-x_milkv-jupiter -> spacemit/k1-milkv-jupiter
, falling back to spacemit/k1-bananapi-f3 by default.
With these, tolower() will not be necessary.
BR,
Guodong / docularxu
> Regards
> Aurelien
>
> --
> Aurelien Jarno GPG: 4096R/1DDD8C9B
> aurelien@aurel32.net http://aurel32.net
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v2 6/9] spacemit: k1: Add multiple device tree support
2026-05-20 10:45 ` [PATCH v2 6/9] spacemit: k1: Add multiple device tree support Guodong Xu
2026-05-24 21:25 ` Aurelien Jarno
@ 2026-05-26 13:36 ` Simon Glass
2026-06-04 14:21 ` Guodong Xu
1 sibling, 1 reply; 16+ messages in thread
From: Simon Glass @ 2026-05-26 13:36 UTC (permalink / raw)
To: Guodong Xu
Cc: Takahiro Kuwano, u-boot, u-boot-spacemit, Vignesh R, Tom Rini,
Raymond Mao, Rick Chen, Leo, Huan Zhou, Peng Fan, Sam Protsenko,
Mayuresh Chitale, Yao Zi, Anis Chali, Dan Carpenter,
Sean Anderson, Heiko Schocher, Rasmus Villemoes, Philip Molloy,
Michal Simek, Yegor Yefremov, Eoin Dickson, Tanmay Kathpalia,
Sumit Garg, Casey Connolly, Neil Armstrong, Guodong Xu,
Rui Miguel Silva
Hi Guodong,
On Tue, 19 May 2026 at 16:49, Guodong Xu <guodong@riscstar.com> wrote:
>
> Enable multiple DTB support in the FIT image for the Spacemit K1 SoC,
> allowing a single U-Boot binary to support different board variants.
>
> The SPL reads the board type from EEPROM and selects the corresponding
> device tree at runtime via board_fit_config_name_match(), ensuring the
> correct hardware description is passed to U-Boot proper.
>
> Signed-off-by: Guodong Xu <guodong@riscstar.com>
>
> ---
> v2:
> - Reworked. Drop the v1 approach (new local k1-muse-pi-pro.dts,
> enlarge SYS_MALLOC_F_LEN, MMODE switch).
> - Use binman --fit-multi-config so u-boot.itb packs multiple board
> DTs from the upstream tree.
> ---
> board/spacemit/k1/spl.c | 42 ++++++++++++++++++++++++++++++++++--------
> configs/spacemit_k1_defconfig | 2 ++
> 2 files changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/board/spacemit/k1/spl.c b/board/spacemit/k1/spl.c
> index da4169fbc8c..d749e21a2d5 100644
> --- a/board/spacemit/k1/spl.c
> +++ b/board/spacemit/k1/spl.c
> @@ -13,6 +13,7 @@
> #include <dm/device.h>
> #include <dm/uclass.h>
> #include <i2c.h>
> +#include <linux/ctype.h>
> #include <linux/delay.h>
> #include <log.h>
> #include <power/regulator.h>
> @@ -55,6 +56,8 @@ struct ddr_cfg {
> binman_sym_declare(ulong, ddr_fw, image_pos);
> binman_sym_declare(ulong, ddr_fw, size);
>
> +char product_name[I2C_BUF_SIZE] = "k1";
> +
> static void i2c_early_init(void)
> {
> struct udevice *bus;
> @@ -322,14 +325,8 @@ void nor_early_init(void)
> udelay(10);
> }
>
> -void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
> -{
> - return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
> -}
> -
> void board_init_f(ulong dummy)
> {
> - u8 i2c_buf[I2C_BUF_SIZE] = { 0 };
> int ret;
>
> ret = spl_early_init();
> @@ -344,11 +341,11 @@ void board_init_f(ulong dummy)
> preloader_console_init();
>
> i2c_early_init();
> - ret = read_product_name(i2c_buf, I2C_BUF_SIZE);
> + ret = read_product_name(product_name, I2C_BUF_SIZE);
> if (ret)
> log_info("Fail to detect board:%d\n", ret);
> else
> - log_info("Get board name:%s\n", (char *)i2c_buf);
> + log_info("Get board name:%s\n", product_name);
> pmic_init();
This is quite hacky. Firstly you should be able to delay selecting the
DT until board_init_r() - i.e. once SPL is running fully. Why is it
needed so early?
Then, you should be able to use a syscon driver to obtain the
information, using driver model. Do you have lots of size constraints
which prevent driver model in SPL?
>
> ddr_early_init();
> @@ -363,3 +360,32 @@ u32 spl_boot_device(void)
> void spl_board_init(void)
> {
> }
> +
> +int board_fit_config_name_match(const char *name)
> +{
> + char fdt_name[I2C_BUF_SIZE];
> + int i;
> +
> + memset(fdt_name, 0, I2C_BUF_SIZE);
> + if (!strncmp(product_name, "k1-x_", 5)) {
> + snprintf(fdt_name, I2C_BUF_SIZE, "%s-%s", "k1",
> + &product_name[5]);
> + }
> + if (fdt_name[0] == '\0') {
if (!*fdt_name) {
> + /* set default board name */
> + sprintf(fdt_name, "k1-musepi-pro");
> + }
> + for (i = 0; i < I2C_BUF_SIZE; i++) {
> + if (fdt_name[i] == '\0')
same
how about adding a helper function in lib/ to lower-case and return a string?
> + break;
> + fdt_name[i] = tolower(fdt_name[i]);
> + }
> + if (!strcmp(name, fdt_name))
> + return 0;
blank line before final return
> + return -ENOENT;
> +}
> +
> +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
> +{
> + return (void *)CONFIG_SPL_LOAD_FIT_ADDRESS;
> +}
> diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
> index 64c724c62a5..465788cc2e5 100644
> --- a/configs/spacemit_k1_defconfig
> +++ b/configs/spacemit_k1_defconfig
> @@ -5,6 +5,7 @@ CONFIG_NR_DRAM_BANKS=2
> CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000000
> CONFIG_DEFAULT_DEVICE_TREE="spacemit/k1-musepi-pro"
> +CONFIG_OF_LIST="spacemit/k1-bananapi-f3 spacemit/k1-musepi-pro"
> CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
> CONFIG_SPL_STACK=0xc083fb00
> CONFIG_SPL_TEXT_BASE=0xc0801000
> @@ -27,6 +28,7 @@ CONFIG_SPL_RISCV_MMODE=y
> # CONFIG_SPL_SMP is not set
> CONFIG_STACK_SIZE=0x100000
> CONFIG_FIT=y
> +CONFIG_MULTI_DTB_FIT=y
> CONFIG_SPL_HAS_LOAD_FIT_ADDRESS=y
> CONFIG_SPL_LOAD_FIT_ADDRESS=0x08000000
> CONFIG_SUPPORT_RAW_INITRD=y
>
> --
> 2.43.0
>
Regards,
Simon
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH v2 6/9] spacemit: k1: Add multiple device tree support
2026-05-26 13:36 ` Simon Glass
@ 2026-06-04 14:21 ` Guodong Xu
0 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-06-04 14:21 UTC (permalink / raw)
To: Simon Glass, Aurelien Jarno
Cc: Takahiro Kuwano, u-boot, u-boot-spacemit, Vignesh R, Tom Rini,
Raymond Mao, Rick Chen, Leo, Huan Zhou, Peng Fan, Sam Protsenko,
Mayuresh Chitale, Yao Zi, Anis Chali, Dan Carpenter,
Sean Anderson, Heiko Schocher, Rasmus Villemoes, Philip Molloy,
Michal Simek, Yegor Yefremov, Eoin Dickson, Tanmay Kathpalia,
Sumit Garg, Casey Connolly, Neil Armstrong, Guodong Xu,
Rui Miguel Silva
Hi Aurelien, Simon
Thanks both for the review.
I'm moving on from riscstar, so I won't be sending v3 of this series
myself. My colleague Raymond Mao (CC'd) will take it over and address
your comments.
Thanks again for taking the time to look at it.
Best regards,
Guodong Xu
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v2 7/9] pinctrl: add pinctrl driver for Spacemit K1 SoC
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (5 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 6/9] spacemit: k1: Add multiple device tree support Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-20 10:45 ` [PATCH v2 8/9] gpio: add gpio " Guodong Xu
2026-05-20 10:45 ` [PATCH v2 9/9] configs: k1: enable pinctrl and gpio Guodong Xu
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
Add pinctrl driver for Spacemit K1 SoC.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- No change.
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/spacemit/Kconfig | 9 +
drivers/pinctrl/spacemit/Makefile | 2 +
drivers/pinctrl/spacemit/pinctrl-k1.c | 550 ++++++++++++++++++++++++++++++++++
5 files changed, 563 insertions(+)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 578edbf8168..a3abe0ea04d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -419,6 +419,7 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/rockchip/Kconfig"
+source "drivers/pinctrl/spacemit/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/tegra/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 29fb9b484d0..ece7a57767c 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
+obj-$(CONFIG_$(PHASE_)PINCTRL_SPACEMIT_K1) += spacemit/
obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o
obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o
obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o
diff --git a/drivers/pinctrl/spacemit/Kconfig b/drivers/pinctrl/spacemit/Kconfig
new file mode 100644
index 00000000000..6aab89e160c
--- /dev/null
+++ b/drivers/pinctrl/spacemit/Kconfig
@@ -0,0 +1,9 @@
+config PINCTRL_SPACEMIT_K1
+ bool "Spacemit K1 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC && DM
+ help
+ Supports pin multiplexing control on Spacemit K1 SoCs.
+
+ The driver is controlled by a device tree node which contains both
+ the GPIO definitions and pin control functions for each available
+ multiplex function.
diff --git a/drivers/pinctrl/spacemit/Makefile b/drivers/pinctrl/spacemit/Makefile
new file mode 100644
index 00000000000..0dc43c72cb1
--- /dev/null
+++ b/drivers/pinctrl/spacemit/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-y += pinctrl-k1.o
diff --git a/drivers/pinctrl/spacemit/pinctrl-k1.c b/drivers/pinctrl/spacemit/pinctrl-k1.c
new file mode 100644
index 00000000000..a6a22eacac7
--- /dev/null
+++ b/drivers/pinctrl/spacemit/pinctrl-k1.c
@@ -0,0 +1,550 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ * Copyright (c) 2025-2026 RISCstar Ltd.
+ */
+
+#include <clk.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+
+/*
+ * +---------+----------+-----------+--------+--------+----------+--------+
+ * | pull | drive | schmitter | slew | edge | strong | mux |
+ * | up/down | strength | trigger | rate | detect | pull | mode |
+ * +---------+----------+-----------+--------+--------+----------+--------+
+ * 3 bits 3 bits 2 bits 1 bit 3 bits 1 bit 3 bits
+ */
+
+#define PAD_MUX GENMASK(2, 0)
+#define PAD_STRONG_PULL BIT(3)
+#define PAD_EDGE_RISE BIT(4)
+#define PAD_EDGE_FALL BIT(5)
+#define PAD_EDGE_CLEAR BIT(6)
+#define PAD_SLEW_RATE GENMASK(12, 11)
+#define PAD_SLEW_RATE_EN BIT(7)
+#define PAD_SCHMITT GENMASK(9, 8)
+#define PAD_DRIVE GENMASK(12, 10)
+#define PAD_PULLDOWN BIT(13)
+#define PAD_PULLUP BIT(14)
+#define PAD_PULL_EN BIT(15)
+
+#define PIN_POWER_STATE_1V8 1800
+#define PIN_POWER_STATE_3V3 3300
+
+enum spacemit_pin_io_type {
+ IO_TYPE_NONE = 0,
+ IO_TYPE_1V8,
+ IO_TYPE_3V3,
+ IO_TYPE_EXTERNAL,
+};
+
+struct spacemit_pin_io {
+ unsigned int pin : 12; // 0~4095
+ unsigned int io_type : 4; // 0~15
+ unsigned int ds : 8; // 0~255
+ unsigned int reserved : 8;
+};
+
+struct spacemit_pinctrl_data {
+ struct spacemit_pin_io *io_pins;
+ int nr_io_pins;
+
+ void __iomem * (*pin_to_reg)(struct udevice *dev, unsigned int pin);
+ int (*get_gpio_mux)(struct udevice *dev, unsigned int pin);
+ int (*get_pins)(struct udevice *dev);
+ int (*get_functions)(struct udevice *dev);
+ int (*get_io_type)(struct udevice *dev, unsigned int pin);
+};
+
+struct spacemit_pinctrl_priv {
+ void __iomem *regs;
+ struct spacemit_pin_io *io_pins;
+ int nr_io_pins;
+};
+
+struct spacemit_pin_mux_config {
+ const struct spacemit_pin *pin;
+ u32 config;
+};
+
+struct spacemit_pin_drv_strength {
+ unsigned int val : 8;
+ unsigned int ma : 16;
+ unsigned int reserved : 8;
+};
+
+static char pin_name[PINNAME_SIZE];
+
+/* External: IO voltage via external source, can be 1.8V or 3.3V */
+static struct spacemit_pin_io k1_io_pins[] = {
+ { 47, IO_TYPE_EXTERNAL, 0, },
+ { 48, IO_TYPE_EXTERNAL, 0, },
+ { 49, IO_TYPE_EXTERNAL, 0, },
+ { 50, IO_TYPE_EXTERNAL, 0, },
+ { 51, IO_TYPE_EXTERNAL, 0, },
+ { 52, IO_TYPE_EXTERNAL, 0, },
+ { 75, IO_TYPE_EXTERNAL, 0, },
+ { 76, IO_TYPE_EXTERNAL, 0, },
+ { 77, IO_TYPE_EXTERNAL, 0, },
+ { 78, IO_TYPE_EXTERNAL, 0, },
+ { 79, IO_TYPE_EXTERNAL, 0, },
+ { 80, IO_TYPE_EXTERNAL, 0, },
+ { 98, IO_TYPE_EXTERNAL, 0, },
+ { 99, IO_TYPE_EXTERNAL, 0, },
+ { 100, IO_TYPE_EXTERNAL, 0, },
+ { 101, IO_TYPE_EXTERNAL, 0, },
+ { 102, IO_TYPE_EXTERNAL, 0, },
+ { 103, IO_TYPE_EXTERNAL, 0, },
+ { 104, IO_TYPE_EXTERNAL, 0, },
+ { 105, IO_TYPE_EXTERNAL, 0, },
+ { 106, IO_TYPE_EXTERNAL, 0, },
+ { 107, IO_TYPE_EXTERNAL, 0, },
+ { 108, IO_TYPE_EXTERNAL, 0, },
+ { 109, IO_TYPE_EXTERNAL, 0, },
+};
+
+static inline int k1_get_pins(struct udevice *dev)
+{
+ return 128;
+}
+
+static inline int k1_get_functions(struct udevice *dev)
+{
+ return 7;
+}
+
+// The pin number equals to the gpio number.
+static void __iomem *k1_pin_to_reg(struct udevice *dev, unsigned int pin)
+{
+ struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
+ unsigned int offset = 1;
+
+ if (pin < 86) {
+ offset += pin;
+ } else if (pin < 93) {
+ offset += pin + 36;
+ } else if (pin < 98) {
+ offset += pin + 23;
+ } else if (pin == 98) { // QSPI_DAT3
+ offset += 92;
+ } else if (pin == 99) { // QSPI_DAT2
+ offset += 91;
+ } else if (pin == 100) { // QSPI_DAT1
+ offset += 90;
+ } else if (pin == 101) { // QSPI_DAT0
+ offset += 89;
+ } else if (pin == 102) { // QSPI_CLK
+ offset += 94;
+ } else if (pin == 103) { // QSPI_CS1
+ offset += 93;
+ } else if (pin < 111) {
+ offset += pin + 5;
+ } else if (pin < 128) {
+ offset += pin + 19;
+ } else {
+ dev_err(dev, "Invalid pin (%u)\n", pin);
+ return NULL;
+ }
+ return priv->regs + (offset << 2);
+}
+
+static int k1_get_gpio_mux(struct udevice *dev, unsigned int selector)
+{
+ u32 mux = 0;
+
+ if (selector < 70) {
+ mux = 0;
+ } else if (selector < 74) {
+ mux = 1;
+ } else if (selector < 93) {
+ mux = 0;
+ } else if (selector < 104) {
+ mux = 1;
+ } else if (selector < 110) {
+ mux = 4;
+ } else if (selector < 128) {
+ mux = 0;
+ } else {
+ dev_err(dev, "Invalid pin (%u)\n", selector);
+ return -EINVAL;
+ }
+ return mux;
+}
+
+static int k1_get_io_type(struct udevice *dev, unsigned int selector)
+{
+ if (selector < 47)
+ return IO_TYPE_1V8;
+ else if (selector < 53)
+ return IO_TYPE_EXTERNAL;
+ else if (selector < 75)
+ return IO_TYPE_1V8;
+ else if (selector < 81)
+ return IO_TYPE_EXTERNAL;
+ else if (selector < 98)
+ return IO_TYPE_1V8;
+ else if (selector < 110)
+ return IO_TYPE_EXTERNAL;
+ else if (selector < 128)
+ return IO_TYPE_1V8;
+ return -EINVAL;
+}
+
+/* use IO high level output current as the table */
+static struct spacemit_pin_drv_strength spacemit_ds_1v8_tbl[4] = {
+ { 0, 11 },
+ { 2, 21 },
+ { 4, 32 },
+ { 6, 42 },
+};
+
+static struct spacemit_pin_drv_strength spacemit_ds_3v3_tbl[8] = {
+ { 0, 7 },
+ { 2, 10 },
+ { 4, 13 },
+ { 6, 16 },
+ { 1, 19 },
+ { 3, 23 },
+ { 5, 26 },
+ { 7, 29 },
+};
+
+static inline u8 spacemit_get_ds_value(struct spacemit_pin_drv_strength *tbl,
+ u32 num, u32 ma)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ if (ma <= tbl[i].ma)
+ return tbl[i].val;
+
+ return tbl[num - 1].val;
+}
+
+static inline u32 spacemit_get_ds_ma(struct spacemit_pin_drv_strength *tbl,
+ u32 num, u32 val)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ if (val == tbl[i].val)
+ return tbl[i].ma;
+
+ return 0;
+}
+
+static inline u8 spacemit_get_drive_strength(enum spacemit_pin_io_type type,
+ u32 ma)
+{
+ switch (type) {
+ case IO_TYPE_1V8:
+ return spacemit_get_ds_value(spacemit_ds_1v8_tbl,
+ ARRAY_SIZE(spacemit_ds_1v8_tbl),
+ ma);
+ case IO_TYPE_3V3:
+ return spacemit_get_ds_value(spacemit_ds_3v3_tbl,
+ ARRAY_SIZE(spacemit_ds_3v3_tbl),
+ ma);
+ default:
+ return 0;
+ }
+}
+
+static inline u32 spacemit_get_drive_strength_ma(enum spacemit_pin_io_type type,
+ u32 value)
+{
+ switch (type) {
+ case IO_TYPE_1V8:
+ return spacemit_get_ds_ma(spacemit_ds_1v8_tbl,
+ ARRAY_SIZE(spacemit_ds_1v8_tbl),
+ value & 0x6);
+ case IO_TYPE_3V3:
+ return spacemit_get_ds_ma(spacemit_ds_3v3_tbl,
+ ARRAY_SIZE(spacemit_ds_3v3_tbl),
+ value);
+ default:
+ return 0;
+ }
+}
+
+static inline u16 spacemit_dt_get_pin(u32 value)
+{
+ return value >> 16;
+}
+
+static inline u16 spacemit_dt_get_pin_mux(u32 value)
+{
+ return value & GENMASK(15, 0);
+}
+
+static int spacemit_get_pins_count(struct udevice *dev)
+{
+ struct spacemit_pinctrl_data *data;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->get_pins)
+ return -EINVAL;
+ return data->get_pins(dev);
+}
+
+static const char *spacemit_get_pin_name(struct udevice *dev,
+ unsigned int selector)
+{
+ struct spacemit_pinctrl_data *data;
+ unsigned int npins;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->get_pins)
+ return NULL;
+ npins = data->get_pins(dev);
+
+ if (selector >= npins)
+ snprintf(pin_name, PINNAME_SIZE, "Error");
+ else
+ snprintf(pin_name, PINNAME_SIZE, "PIN%u", selector);
+
+ return pin_name;
+}
+
+static int spacemit_get_functions_count(struct udevice *dev)
+{
+ struct spacemit_pinctrl_data *data;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->get_functions)
+ return -EINVAL;
+ return data->get_functions(dev);
+}
+
+static int spacemit_get_pin_muxing(struct udevice *dev, unsigned int pin,
+ char *buf, int size)
+{
+ struct spacemit_pinctrl_data *data;
+ void __iomem *addr;
+ u32 mux, val;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->pin_to_reg)
+ return -EINVAL;
+
+ addr = data->pin_to_reg(dev, pin);
+ if (!addr)
+ return -EINVAL;
+
+ val = readl(addr);
+ mux = val & PAD_MUX;
+ snprintf(buf, size, "[%p] 0x%08x MUX%d", addr, val, mux);
+ return 0;
+}
+
+static int spacemit_pinctrl_request_gpio(struct udevice *dev,
+ unsigned int selector)
+{
+ struct spacemit_pinctrl_data *data;
+ void __iomem *addr;
+ int mux;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->pin_to_reg || !data->get_gpio_mux)
+ return -EINVAL;
+ addr = data->pin_to_reg(dev, selector);
+ mux = data->get_gpio_mux(dev, selector);
+ if (mux < 0) {
+ dev_err(dev, "Invalid pin (%d)\n", selector);
+ return -EINVAL;
+ }
+ clrsetbits_le32(addr, PAD_MUX, mux & PAD_MUX);
+ return 0;
+}
+
+static int spacemit_pinctrl_free_gpio(struct udevice *dev,
+ unsigned int selector)
+{
+ return 0;
+}
+
+static int spacemit_pinmux_set(struct udevice *dev, unsigned int pin,
+ unsigned int mux)
+{
+ struct spacemit_pinctrl_data *data;
+ void __iomem *addr;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->pin_to_reg)
+ return -EINVAL;
+ addr = data->pin_to_reg(dev, pin);
+ clrsetbits_le32(addr, PAD_MUX, mux & PAD_MUX);
+ return 0;
+}
+
+static int spacemit_pinmux_property_set(struct udevice *dev, u32 pinmux_group)
+{
+ u32 pin, mux;
+
+ pin = spacemit_dt_get_pin(pinmux_group);
+ mux = spacemit_dt_get_pin_mux(pinmux_group);
+ return spacemit_pinmux_set(dev, pin, mux);
+}
+
+static const struct pinconf_param spacemit_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, U32_MAX },
+ { "power-source", PIN_CONFIG_POWER_SOURCE, U32_MAX },
+};
+
+static int spacemit_pinconf_set(struct udevice *dev, unsigned int pin_selector,
+ unsigned int param, unsigned int argument)
+{
+ struct spacemit_pinctrl_data *data;
+ struct spacemit_pinctrl_priv *priv = dev_get_priv(dev);
+ void __iomem *addr;
+ u32 mask = 0;
+ unsigned int io_type;
+ u8 ds;
+ bool found;
+ int i;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ if (!data || !data->pin_to_reg)
+ return -EINVAL;
+ addr = data->pin_to_reg(dev, pin_selector);
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ clrbits_le32(addr, PAD_PULLUP | PAD_PULLDOWN | PAD_PULL_EN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
+ clrsetbits_le32(addr, mask, PAD_PULLDOWN | PAD_PULL_EN);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ mask = PAD_PULLDOWN | PAD_PULLUP | PAD_PULL_EN;
+ clrsetbits_le32(addr, mask, PAD_PULLUP | PAD_PULL_EN);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ io_type = IO_TYPE_1V8;
+ for (i = 0; i < priv->nr_io_pins; i++) {
+ if (priv->io_pins[i].pin != pin_selector)
+ continue;
+ io_type = priv->io_pins[i].io_type;
+ break;
+ }
+ if (io_type != IO_TYPE_3V3 && io_type != IO_TYPE_1V8) {
+ dev_err(dev, "Invalid IO type (%d)\n", io_type);
+ return -EINVAL;
+ }
+ ds = spacemit_get_drive_strength(io_type, argument);
+ clrsetbits_le32(addr, PAD_DRIVE, ds);
+ break;
+ case PIN_CONFIG_POWER_SOURCE:
+ for (i = 0, found = false; i < priv->nr_io_pins; i++) {
+ if (priv->io_pins[i].pin != pin_selector)
+ continue;
+ if (argument == PIN_POWER_STATE_3V3) {
+ priv->io_pins[i].io_type = IO_TYPE_3V3;
+ found = true;
+ } else if (argument == PIN_POWER_STATE_1V8) {
+ priv->io_pins[i].io_type = IO_TYPE_1V8;
+ found = true;
+ }
+ break;
+ }
+ if (!found && argument != PIN_POWER_STATE_1V8) {
+ dev_err(dev, "Invalid power source (%d)\n", argument);
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -EOPNOTSUPP;
+ }
+ return 0;
+}
+
+static int spacemit_pinctrl_probe(struct udevice *dev)
+{
+ struct spacemit_pinctrl_data *data;
+ struct spacemit_pinctrl_priv *priv;
+ struct clk_bulk clks;
+ size_t size;
+ int ret;
+
+ data = (struct spacemit_pinctrl_data *)dev_get_driver_data(dev);
+ priv = dev_get_priv(dev);
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
+ dev_err(dev, "Fail to get base address\n");
+ return -EINVAL;
+ }
+ priv->nr_io_pins = data->nr_io_pins;
+ size = priv->nr_io_pins * sizeof(struct spacemit_pin_io);
+ priv->io_pins = (struct spacemit_pin_io *)memdup(data->io_pins, size);
+ if (!priv->io_pins) {
+ dev_err(dev, "Fail to allocate memory\n");
+ return -ENOMEM;
+ }
+
+ ret = clk_get_bulk(dev, &clks);
+ if (ret) {
+ dev_err(dev, "Fail to get bulk clks\n");
+ goto out_get_clk;
+ }
+ ret = clk_enable_bulk(&clks);
+ if (ret) {
+ dev_err(dev, "Fail to enable bulk clks\n");
+ goto out_clks;
+ }
+ return 0;
+out_clks:
+ clk_release_bulk(&clks);
+out_get_clk:
+ free(priv->io_pins);
+ return ret;
+}
+
+static const struct spacemit_pinctrl_data k1_pinctrl_data = {
+ .io_pins = k1_io_pins,
+ .nr_io_pins = ARRAY_SIZE(k1_io_pins),
+ .pin_to_reg = k1_pin_to_reg,
+ .get_gpio_mux = k1_get_gpio_mux,
+ .get_pins = k1_get_pins,
+ .get_functions = k1_get_functions,
+ .get_io_type = k1_get_io_type,
+};
+
+static const struct udevice_id spacemit_pinctrl_ids[] = {
+ {
+ .compatible = "spacemit,k1-pinctrl",
+ .data = (uintptr_t)&k1_pinctrl_data,
+ }, { /* sentinel */ }
+};
+
+static const struct pinctrl_ops spacemit_pinctrl_ops = {
+ .get_pins_count = spacemit_get_pins_count,
+ .get_pin_name = spacemit_get_pin_name,
+ .get_functions_count = spacemit_get_functions_count,
+ .get_pin_muxing = spacemit_get_pin_muxing,
+ .set_state = pinctrl_generic_set_state,
+ .gpio_request_enable = spacemit_pinctrl_request_gpio,
+ .gpio_disable_free = spacemit_pinctrl_free_gpio,
+ .pinmux_set = spacemit_pinmux_set,
+ .pinmux_property_set = spacemit_pinmux_property_set,
+ .pinconf_num_params = ARRAY_SIZE(spacemit_pinconf_params),
+ .pinconf_params = spacemit_pinconf_params,
+ .pinconf_set = spacemit_pinconf_set,
+};
+
+U_BOOT_DRIVER(spacemit_pinctrl) = {
+ .name = "spacemit_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = spacemit_pinctrl_ids,
+ .ops = &spacemit_pinctrl_ops,
+ .priv_auto = sizeof(struct spacemit_pinctrl_priv),
+ .probe = spacemit_pinctrl_probe,
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 8/9] gpio: add gpio driver for Spacemit K1 SoC
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (6 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 7/9] pinctrl: add pinctrl driver for Spacemit K1 SoC Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
2026-05-20 10:45 ` [PATCH v2 9/9] configs: k1: enable pinctrl and gpio Guodong Xu
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
From: Raymond Mao <raymond.mao@riscstar.com>
Enable gpio driver for Spacemit K1 SoC.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Add .request and .rfree ops: delegate to pinctrl's
gpio_request_enable / gpio_disable_free.
- xlate(): use gpio_flags_xlate() instead of raw flags.
---
drivers/gpio/Kconfig | 8 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/spacemit_gpio.c | 253 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 262 insertions(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0b5466b39b8..fe6379f0e01 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -449,6 +449,14 @@ config SANDBOX_GPIO_COUNT
of 'anonymous' GPIOs that do not belong to any device or bank.
Select a suitable value depending on your needs.
+config SPACEMIT_GPIO
+ bool "Spacemit K1 GPIO driver"
+ depends on DM_GPIO && TARGET_SPACEMIT_K1
+ help
+ Support the GPIO device in Spacemit SoCs. The GPIOs are arranged
+ into a number of banks (different for each SoC type) each with 32
+ GPIOs.
+
config SUNXI_GPIO
bool "Allwinner GPIO driver"
depends on ARCH_SUNXI
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 863557e45ce..020e23c7252 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(PHASE_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_$(PHASE_)QCOM_PMIC_GPIO) += qcom_pmic_gpio.o qcom_spmi_gpio.o
+obj-$(CONFIG_$(PHASE_)SPACEMIT_GPIO) += spacemit_gpio.o
obj-$(CONFIG_MT7620_GPIO) += mt7620_gpio.o
obj-$(CONFIG_MT7621_GPIO) += mt7621_gpio.o
obj-$(CONFIG_MSCC_SGPIO) += mscc_sgpio.o
diff --git a/drivers/gpio/spacemit_gpio.c b/drivers/gpio/spacemit_gpio.c
new file mode 100644
index 00000000000..de71880df15
--- /dev/null
+++ b/drivers/gpio/spacemit_gpio.c
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025-2026 RISCstar Ltd.
+ */
+
+#include <asm/gpio.h>
+#include <clk.h>
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <dm/pinctrl.h>
+#include <dm/read.h>
+#include <dm/uclass.h>
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <log.h>
+
+#define GPIO_BANK_SIZE 32
+#define GPIO_TO_BANK(pin) ((pin) / GPIO_BANK_SIZE)
+#define GPIO_TO_BIT(pin) ((pin) % GPIO_BANK_SIZE)
+
+static inline int gpio_to_reg_offset(unsigned int pin)
+{
+ unsigned int bank = GPIO_TO_BANK(pin);
+
+ if (bank == 0)
+ return 0;
+ else if (bank == 1)
+ return 4;
+ else if (bank == 2)
+ return 8;
+ else if (bank == 3)
+ return 0x100;
+ log_warning("Use default GPIO bank for an invalid GPIO[%d].\n", pin);
+ return 0;
+}
+
+#define REG_PLR(pin) (0x00 + gpio_to_reg_offset(pin))
+#define REG_PDR(pin) (0x0c + gpio_to_reg_offset(pin))
+#define REG_PSR(pin) (0x18 + gpio_to_reg_offset(pin))
+#define REG_PCR(pin) (0x24 + gpio_to_reg_offset(pin))
+#define REG_SDR(pin) (0x54 + gpio_to_reg_offset(pin))
+#define REG_CDR(pin) (0x60 + gpio_to_reg_offset(pin))
+
+struct spacemit_gpio_data {
+ u16 gpio_base;
+ u16 gpio_count;
+ u8 num_banks;
+};
+
+struct spacemit_gpio_priv {
+ void __iomem *regs;
+};
+
+static int spacemit_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ struct spacemit_gpio_data *data;
+ u32 bank, offset, flags;
+
+ data = (struct spacemit_gpio_data *)dev_get_driver_data(dev);
+ if (args->args_count < 3) {
+ dev_err(dev, "Invalid args count: %d, expected 3\n",
+ args->args_count);
+ return -EINVAL;
+ }
+ bank = args->args[0];
+ offset = args->args[1];
+ flags = args->args[2];
+
+ if (bank >= data->num_banks) {
+ dev_err(dev, "Invalid gpio bank: %u (max %u)\n",
+ bank, data->num_banks - 1);
+ return -EINVAL;
+ }
+ if (offset >= GPIO_BANK_SIZE) {
+ dev_err(dev, "Invalid offset: %u (max 31)\n", offset);
+ return -EINVAL;
+ }
+ desc->offset = bank * GPIO_BANK_SIZE + offset;
+ desc->flags = gpio_flags_xlate(flags);
+ return 0;
+}
+
+static int spacemit_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr;
+ u32 value, mask;
+
+ addr = priv->regs + REG_PLR(offset);
+ value = readl(addr);
+ mask = 1 << GPIO_TO_BIT(offset);
+ return !!(value & mask);
+}
+
+static int spacemit_gpio_get_function(struct udevice *dev, unsigned int offset)
+{
+ struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr;
+ u32 value, mask;
+
+ addr = priv->regs + REG_PDR(offset);
+ value = readl(addr);
+ mask = 1 << GPIO_TO_BIT(offset);
+ if (value & mask)
+ return GPIOF_OUTPUT;
+ return GPIOF_INPUT;
+}
+
+static int spacemit_gpio_get_flags(struct udevice *dev, unsigned int offset,
+ ulong *flagsp)
+{
+ ulong flags = 0;
+ u32 dir;
+
+ dir = spacemit_gpio_get_function(dev, offset);
+ if (dir) {
+ flags |= GPIOD_IS_OUT;
+ if (spacemit_gpio_get_value(dev, offset))
+ flags |= GPIOD_IS_OUT_ACTIVE;
+ } else {
+ flags |= GPIOD_IS_IN;
+ }
+ *flagsp = flags;
+ return 0;
+}
+
+static int spacemit_gpio_set_flags(struct udevice *dev, unsigned int offset,
+ ulong flags)
+{
+ struct spacemit_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *addr;
+ int value;
+
+ value = (flags & GPIOD_IS_OUT_ACTIVE) ? 1 : 0;
+ if (flags & GPIOD_IS_IN) {
+ addr = priv->regs + REG_CDR(offset);
+ writel(1 << GPIO_TO_BIT(offset), addr);
+ }
+ if (flags & GPIOD_IS_OUT) {
+ if (value) {
+ addr = priv->regs + REG_PSR(offset);
+ writel(1 << GPIO_TO_BIT(offset), addr);
+ } else {
+ addr = priv->regs + REG_PCR(offset);
+ writel(1 << GPIO_TO_BIT(offset), addr);
+ }
+ addr = priv->regs + REG_SDR(offset);
+ writel(1 << GPIO_TO_BIT(offset), addr);
+ }
+ return 0;
+}
+
+static int spacemit_gpio_request(struct udevice *dev, unsigned int offset,
+ const char *label)
+{
+ const struct pinctrl_ops *ops;
+ struct udevice *pctldev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pctldev);
+ if (ret)
+ return ret;
+
+ ops = pinctrl_get_ops(pctldev);
+ if (!ops->gpio_request_enable)
+ return -ENOSYS;
+
+ return ops->gpio_request_enable(pctldev, offset);
+}
+
+static int spacemit_gpio_rfree(struct udevice *dev, unsigned int offset)
+{
+ const struct pinctrl_ops *ops;
+ struct udevice *pctldev;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_PINCTRL, &pctldev);
+ if (ret)
+ return ret;
+
+ ops = pinctrl_get_ops(pctldev);
+ if (!ops->gpio_disable_free)
+ return -ENOSYS;
+
+ return ops->gpio_disable_free(pctldev, offset);
+}
+
+static const struct dm_gpio_ops spacemit_gpio_ops = {
+ .request = spacemit_gpio_request,
+ .rfree = spacemit_gpio_rfree,
+ .xlate = spacemit_gpio_xlate,
+ .get_value = spacemit_gpio_get_value,
+ .get_function = spacemit_gpio_get_function,
+ .get_flags = spacemit_gpio_get_flags,
+ .set_flags = spacemit_gpio_set_flags,
+};
+
+static int spacemit_gpio_probe(struct udevice *dev)
+{
+ struct spacemit_gpio_priv *priv;
+ struct spacemit_gpio_data *data;
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk_bulk clks;
+ int ret;
+
+ data = (struct spacemit_gpio_data *)dev_get_driver_data(dev);
+ priv = dev_get_priv(dev);
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs) {
+ dev_err(dev, "Fail to get base address\n");
+ return -EINVAL;
+ }
+ uc_priv->bank_name = "GPIO";
+ uc_priv->gpio_count = data->gpio_count;
+ uc_priv->gpio_base = data->gpio_base;
+
+ ret = clk_get_bulk(dev, &clks);
+ if (ret) {
+ dev_err(dev, "Fail to get bulk clks\n");
+ return ret;
+ }
+ ret = clk_enable_bulk(&clks);
+ if (ret) {
+ dev_err(dev, "Fail to enable bulk clks\n");
+ goto out;
+ }
+ return 0;
+out:
+ clk_release_bulk(&clks);
+ return ret;
+}
+
+static const struct spacemit_gpio_data k1_gpio_data = {
+ .num_banks = 4,
+ .gpio_count = 128,
+ .gpio_base = 0,
+};
+
+static const struct udevice_id spacemit_gpio_ids[] = {
+ { .compatible = "spacemit,k1-gpio", .data = (uintptr_t)&k1_gpio_data, },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(k1_gpio) = {
+ .name = "spacemit_k1_gpio",
+ .id = UCLASS_GPIO,
+ .of_match = spacemit_gpio_ids,
+ .ops = &spacemit_gpio_ops,
+ .priv_auto = sizeof(struct spacemit_gpio_priv),
+ .probe = spacemit_gpio_probe,
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH v2 9/9] configs: k1: enable pinctrl and gpio
2026-05-20 10:45 [PATCH v2 0/9] riscv: spacemit: k1: add pinctrl/GPIO and SPI NOR support Guodong Xu
` (7 preceding siblings ...)
2026-05-20 10:45 ` [PATCH v2 8/9] gpio: add gpio " Guodong Xu
@ 2026-05-20 10:45 ` Guodong Xu
8 siblings, 0 replies; 16+ messages in thread
From: Guodong Xu @ 2026-05-20 10:45 UTC (permalink / raw)
To: Takahiro Kuwano, u-boot, u-boot-spacemit
Cc: Vignesh R, Tom Rini, Raymond Mao, Rick Chen, Leo, Huan Zhou,
Peng Fan, Sam Protsenko, Mayuresh Chitale, Yao Zi, Anis Chali,
Dan Carpenter, Sean Anderson, Heiko Schocher, Rasmus Villemoes,
Philip Molloy, Michal Simek, Yegor Yefremov, Eoin Dickson,
Tanmay Kathpalia, Sumit Garg, Casey Connolly, Neil Armstrong,
Guodong Xu, Rui Miguel Silva, Guodong Xu
Enable pinctrl and gpio configurations for Spacemit K1 SoC.
Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
v2:
- Also enable CONFIG_CLK and CONFIG_CLK_CCF (U-Boot proper).
---
board/spacemit/k1/MAINTAINERS | 3 +++
configs/spacemit_k1_defconfig | 8 +++++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/board/spacemit/k1/MAINTAINERS b/board/spacemit/k1/MAINTAINERS
index 8976c575dff..32d47ecc8f1 100644
--- a/board/spacemit/k1/MAINTAINERS
+++ b/board/spacemit/k1/MAINTAINERS
@@ -3,9 +3,12 @@ M: Huan Zhou <pericycle.cc@gmail.com>
M: Guodong Xu <guodong.xu@riscstar.com>
L: u-boot-spacemit@groups.io
S: Maintained
+F: arch/riscv/dts/k1-*-u-boot.dtsi
F: board/spacemit/k1/
F: configs/spacemit_k1_defconfig
F: doc/board/spacemit/bananapi-f3.rst
+F: drivers/gpio/spacemit_gpio.c
F: drivers/i2c/k1_i2c.c
+F: drivers/pinctrl/spacemit/
F: drivers/power/pmic/pmic_spacemit_p1.c
F: drivers/power/regulator/spacemit_p1_regulator.c
diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 465788cc2e5..0604c2feefc 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -49,6 +49,8 @@ CONFIG_OF_UPSTREAM=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
+CONFIG_CLK=y
+CONFIG_CLK_CCF=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_CLK_SPACEMIT=y
@@ -59,7 +61,11 @@ CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_SPACEMIT_K1=y
+CONFIG_GPIO=y
+CONFIG_DM_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_SPACEMIT_GPIO=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_SPACEMIT_P1=y
CONFIG_DM_REGULATOR=y
--
2.43.0
^ permalink raw reply related [flat|nested] 16+ messages in thread