[PATCH v2 0/7] qcom: qcs8300/monaco-evk: pinctrl, interconnect, RPMH clock and reboot-mode support

[PATCH v2 0/7] qcom: qcs8300/monaco-evk: pinctrl, interconnect, RPMH clock and reboot-mode support

[Balaji Selvanathan via U-Boot]

This series brings up the Monaco (QCS8300) EVK target with a dedicated
pinctrl driver, interconnect driver, a real sa8775p RPMH clock driver
(replacing the generic clk-stub no-op), and PON/SDAM-backed reboot-mode
support so "reboot bootloader" from Linux can be honored by U-Boot.
qcom_qcs8300_defconfig is switched over to the monaco-evk device tree.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
Changes in v2:
- clk: qcom: split RPMH clock support into a new standalone
  clock-rpmh.c driver shared by SM8550/SM8650/SA8775P instead of
  embedding it in the sa8775p GCC driver
- Link to v1: https://lore.kernel.org/r/20260806-b4-monaco-v1-0-8d7b4e2f4fe1@oss.qualcomm.com

---
Balaji Selvanathan (7):
      clk: qcom: Add shared RPMH clock driver for SM8550/SM8650/SA8775P
      clk: qcom: qcs8300: Extend GCC clock driver to full gate/RCG coverage
      pinctrl: qcom: Add QCS8300 pinctrl driver
      interconnect: qcom: Add QCS8300 interconnect driver
      arm64: dts: monaco-evk: Add reboot-mode support via PON/SDAM
      arm64: dts: monaco-evk: Force vreg_l8a always-on to protect UFS VCC
      configs: qcom_qcs8300: Switch to monaco-evk DT and enable new drivers

 arch/arm/dts/monaco-evk-u-boot.dtsi    |  40 +++
 configs/qcom_qcs8300_defconfig         |   6 +-
 drivers/clk/clk-stub.c                 |   3 -
 drivers/clk/qcom/Kconfig               |  12 +
 drivers/clk/qcom/Makefile              |   1 +
 drivers/clk/qcom/clock-qcs8300.c       | 545 +++++++++++++++++++++++++++++++--
 drivers/clk/qcom/clock-rpmh.c          |  61 ++++
 drivers/interconnect/qcom/Kconfig      |   6 +
 drivers/interconnect/qcom/Makefile     |   1 +
 drivers/interconnect/qcom/qcs8300.c    | 269 ++++++++++++++++
 drivers/interconnect/qcom/qcs8300.h    |  24 ++
 drivers/pinctrl/qcom/Kconfig           |   8 +
 drivers/pinctrl/qcom/Makefile          |   1 +
 drivers/pinctrl/qcom/pinctrl-qcs8300.c | 468 ++++++++++++++++++++++++++++
 14 files changed, 1421 insertions(+), 24 deletions(-)
---
base-commit: 3fb0c443c5b70f25168c98ad88f8a2c0123e2c82
change-id: 20260805-b4-monaco-26501bf7c863

Best regards,
-- 
Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>

[PATCH v2 1/7] clk: qcom: Add shared RPMH clock driver for SM8550/SM8650/SA8775P

[Balaji Selvanathan via U-Boot]

sa8775p was being handled by the generic clock stub, which just
no-ops every request. The RPMH_CXO_CLK (bi_tcxo_div2) it exposes is
identical on SM8550, SM8650 and SA8775P, so rather than bury it in the
sa8775p GCC driver, add a dedicated standalone RPMH clock driver shared
by all three SoCs. It reports the fixed CXO rate and accepts no-op
enable/set_rate requests.

Monaco-evk also uses the same RPMH clock driver as sa8775p (it's
rpmhcc DTS node has compatible "qcom,sa8775p-rpmh-clk").

Drop the sm8550/sm8650/sa8775p rpmh-clk compatibles from the generic
clock stub now that they are handled by the real driver.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/clk-stub.c        |  3 ---
 drivers/clk/qcom/Kconfig      | 12 +++++++++
 drivers/clk/qcom/Makefile     |  1 +
 drivers/clk/qcom/clock-rpmh.c | 61 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 74 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
index 4a6c71016da..85e54841386 100644
--- a/drivers/clk/clk-stub.c
+++ b/drivers/clk/clk-stub.c
@@ -51,7 +51,6 @@ static struct clk_ops stub_clk_ops = {
 static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,qcs615-rpmh-clk" },
 	{ .compatible = "qcom,rpmcc" },
-	{ .compatible = "qcom,sa8775p-rpmh-clk" },
 	{ .compatible = "qcom,sc7180-rpmh-clk" },
 	{ .compatible = "qcom,sc7280-rpmh-clk" },
 	{ .compatible = "qcom,sdm670-rpmh-clk" },
@@ -59,8 +58,6 @@ static const struct udevice_id stub_clk_ids[] = {
 	{ .compatible = "qcom,sm6350-rpmh-clk" },
 	{ .compatible = "qcom,sm8150-rpmh-clk" },
 	{ .compatible = "qcom,sm8250-rpmh-clk" },
-	{ .compatible = "qcom,sm8550-rpmh-clk" },
-	{ .compatible = "qcom,sm8650-rpmh-clk" },
 	{ }
 };
 
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9ad233c83ac..8596b93d4c4 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -87,9 +87,19 @@ config CLK_QCOM_QCS8300
 	  on the Snapdragon QCS8300 SoC. This driver supports the clocks
 	  and resets exposed by the GCC hardware block.
 
+config CLK_QCOM_RPMH
+	bool "Qualcomm RPMh clock driver"
+	depends on CLK
+	help
+	  Say Y here to enable support for the RPMh-managed clocks found on
+	  SoCs such as SM8550, SM8650 and SA8775P. These clocks are owned by
+	  the always-on subsystem; the driver only reports the fixed CXO rate
+	  (bi_tcxo_div2) and accepts no-op enable/set_rate requests.
+
 config CLK_QCOM_SA8775P
 	bool "Qualcomm SA8775 GCC"
 	select CLK_QCOM
+	select CLK_QCOM_RPMH
 	help
 	  Say Y here to enable support for the Global Clock Controller
 	  on the Snapdragon SA8775 SoC. This driver supports the clocks
@@ -153,6 +163,7 @@ config CLK_QCOM_SM8250
 config CLK_QCOM_SM8550
 	bool "Qualcomm SM8550 GCC"
 	select CLK_QCOM
+	select CLK_QCOM_RPMH
 	help
 	  Say Y here to enable support for the Global Clock Controller
 	  on the Snapdragon SM8550 SoC. This driver supports the clocks
@@ -161,6 +172,7 @@ config CLK_QCOM_SM8550
 config CLK_QCOM_SM8650
 	bool "Qualcomm SM8650 GCC"
 	select CLK_QCOM
+	select CLK_QCOM_RPMH
 	help
 	  Say Y here to enable support for the Global Clock Controller
 	  on the Snapdragon SM8650 SoC. This driver supports the clocks
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index c0d95a6300e..f5630ae0f9c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
 obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
 obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
 obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
+obj-$(CONFIG_CLK_QCOM_RPMH) += clock-rpmh.o
 obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
 obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
 obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
diff --git a/drivers/clk/qcom/clock-rpmh.c b/drivers/clk/qcom/clock-rpmh.c
new file mode 100644
index 00000000000..69f2a751441
--- /dev/null
+++ b/drivers/clk/qcom/clock-rpmh.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RPMh clock driver for Qualcomm SoCs
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+
+/* On-board TCXO */
+#define TCXO_RATE	38400000
+
+/* bi_tcxo_div2 divided after RPMh output */
+#define TCXO_DIV2_RATE	(TCXO_RATE / 2)
+
+static ulong qcom_rpmh_clk_set_rate(struct clk *clk, ulong rate)
+{
+	return (clk->rate = rate);
+}
+
+static ulong qcom_rpmh_clk_get_rate(struct clk *clk)
+{
+	ulong cxo_rate = dev_get_driver_data(clk->dev);
+
+	switch (clk->id) {
+	case RPMH_CXO_CLK:
+		return cxo_rate;
+	default:
+		return clk->rate;
+	}
+}
+
+static int qcom_rpmh_clk_nop(struct clk *clk)
+{
+	return 0;
+}
+
+static struct clk_ops qcom_rpmh_clk_ops = {
+	.set_rate = qcom_rpmh_clk_set_rate,
+	.get_rate = qcom_rpmh_clk_get_rate,
+	.enable = qcom_rpmh_clk_nop,
+	.disable = qcom_rpmh_clk_nop,
+};
+
+static const struct udevice_id qcom_rpmh_clk_ids[] = {
+	{ .compatible = "qcom,sa8775p-rpmh-clk", .data = TCXO_DIV2_RATE },
+	{ .compatible = "qcom,sm8550-rpmh-clk", .data = TCXO_DIV2_RATE },
+	{ .compatible = "qcom,sm8650-rpmh-clk", .data = TCXO_DIV2_RATE },
+	{ }
+};
+
+U_BOOT_DRIVER(qcom_rpmh_clk) = {
+	.name		= "qcom_rpmh_clk",
+	.id		= UCLASS_CLK,
+	.of_match	= qcom_rpmh_clk_ids,
+	.ops		= &qcom_rpmh_clk_ops,
+	.flags		= DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};

-- 
2.34.1

[PATCH v2 2/7] clk: qcom: qcs8300: Extend GCC clock driver to full gate/RCG coverage

[Balaji Selvanathan via U-Boot]

Extend the QCS8300 GCC driver with the remaining RCGs (USB2/USB3,
UFS PHY, SDCC1, QUPv3 wrap0/wrap1/wrap3 SE clocks, GP1-5, PDM2,
EMAC0, PCIe0/1) and their gate clocks.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/clk/qcom/clock-qcs8300.c | 545 +++++++++++++++++++++++++++++++++++++--
 1 file changed, 525 insertions(+), 20 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c
index cd8aecdf788..cd47b384f1f 100644
--- a/drivers/clk/qcom/clock-qcs8300.c
+++ b/drivers/clk/qcom/clock-qcs8300.c
@@ -14,12 +14,210 @@
 #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
 #include "clock-qcom.h"
 
-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
-#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR	0x1b040
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR		0x1b028
+#define USB3_PRIM_PHY_AUX_CMD_RCGR		0x1b06c
+#define USB20_MASTER_CLK_CMD_RCGR		0x1c028
+#define USB20_MOCK_UTMI_CLK_CMD_RCGR		0x1c040
+
+#define UFS_PHY_AXI_CLK_CMD_RCGR		0x8302c
+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR		0x83074
+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR		0x830a8
+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR	0x8308c
+
+#define SDCC1_APPS_CLK_CMD_RCGR			0x20014
+#define SDCC1_ICE_CORE_CLK_CMD_RCGR		0x2002c
+
+#define QUPV3_WRAP0_S0_CLK_CMD_RCGR		0x23154
+#define QUPV3_WRAP0_S1_CLK_CMD_RCGR		0x23288
+#define QUPV3_WRAP0_S2_CLK_CMD_RCGR		0x233bc
+#define QUPV3_WRAP0_S3_CLK_CMD_RCGR		0x234f0
+#define QUPV3_WRAP0_S4_CLK_CMD_RCGR		0x23624
+#define QUPV3_WRAP0_S5_CLK_CMD_RCGR		0x23758
+#define QUPV3_WRAP0_S6_CLK_CMD_RCGR		0x2388c
+#define QUPV3_WRAP0_S7_CLK_CMD_RCGR		0x239c0
+#define QUPV3_WRAP1_S0_CLK_CMD_RCGR		0x24154
+#define QUPV3_WRAP1_S1_CLK_CMD_RCGR		0x24288
+#define QUPV3_WRAP1_S2_CLK_CMD_RCGR		0x243bc
+#define QUPV3_WRAP1_S3_CLK_CMD_RCGR		0x244f0
+#define QUPV3_WRAP1_S4_CLK_CMD_RCGR		0x24624
+#define QUPV3_WRAP1_S5_CLK_CMD_RCGR		0x24758
+#define QUPV3_WRAP1_S6_CLK_CMD_RCGR		0x2488c
+#define QUPV3_WRAP1_S7_CLK_CMD_RCGR		0x249c0
+#define QUPV3_WRAP3_S0_CLK_CMD_RCGR		0xc4158
+
+#define GP1_CLK_CMD_RCGR			0x70004
+#define GP2_CLK_CMD_RCGR			0x71004
+#define GP3_CLK_CMD_RCGR			0x62004
+#define GP4_CLK_CMD_RCGR			0x1e004
+#define GP5_CLK_CMD_RCGR			0x1f004
+
+#define PDM2_CLK_CMD_RCGR			0x3f010
+
+#define EMAC0_PHY_AUX_CLK_CMD_RCGR		0xb6028
+#define EMAC0_PTP_CLK_CMD_RCGR			0xb6060
+#define EMAC0_RGMII_CLK_CMD_RCGR		0xb6048
+
+#define PCIE_0_AUX_CLK_CMD_RCGR			0xa9078
+#define PCIE_0_PHY_RCHNG_CLK_CMD_RCGR		0xa9054
+#define PCIE_1_AUX_CLK_CMD_RCGR			0x77078
+#define PCIE_1_PHY_RCHNG_CLK_CMD_RCGR		0x77054
+
+#define CFG_CLK_SRC_GPLL4_UFS_ICE_CORE		(3 << 8)
+#define CFG_CLK_SRC_GPLL7_EMAC0			(2 << 8)
+
+static struct pll_vote_clk gpll4_vote_clk = {
+	.status = 0x4000,
+	.status_bit = BIT(31),
+	.ena_vote = 0x4b028,
+	.vote_bit = BIT(4),
+};
+
+static struct pll_vote_clk gpll7_vote_clk = {
+	.status = 0x7000,
+	.status_bit = BIT(31),
+	.ena_vote = 0x4b028,
+	.vote_bit = BIT(7),
+};
+
+static struct pll_vote_clk gpll9_vote_clk = {
+	.status = 0x9000,
+	.status_bit = BIT(31),
+	.ena_vote = 0x4b028,
+	.vote_bit = BIT(9),
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap_s0_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+	F(120000000, CFG_CLK_SRC_GPLL0, 5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap_s2_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	F(403200000, CFG_CLK_SRC_GPLL4, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_gp_clk_src[] = {
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
+	F(60000000, CFG_CLK_SRC_GPLL0, 10, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
+	F(125000000, CFG_CLK_SRC_GPLL7_EMAC0, 8, 0, 0),
+	F(230400000, CFG_CLK_SRC_GPLL4, 3.5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
+	F(5000000, CFG_CLK_SRC_GPLL0_EVEN, 10, 1, 6),
+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+	F(125000000, CFG_CLK_SRC_GPLL7_EMAC0, 8, 0, 0),
+	F(250000000, CFG_CLK_SRC_GPLL7_EMAC0, 4, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
+	F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 1, 3),
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+	F(192000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
+	F(384000000, CFG_CLK_SRC_GPLL9, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(201600000, CFG_CLK_SRC_GPLL4_UFS_ICE_CORE, 4, 0, 0),
+	F(403200000, CFG_CLK_SRC_GPLL4_UFS_ICE_CORE, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
+	F(120000000, CFG_CLK_SRC_GPLL0, 5, 0, 0),
+	{ }
+};
+
+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
+	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
+	F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
+	{ }
+};
 
 static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+	const struct freq_tbl *freq;
 
 	if (clk->id < priv->data->num_clks)
 		debug("%s: %s, requested rate=%ld\n",
@@ -31,28 +229,315 @@ static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
 		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
 		return rate;
 	case GCC_USB30_PRIM_MASTER_CLK:
-		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
+		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
-				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
-		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
+		return freq->freq;
+	case GCC_USB20_MASTER_CLK:
+		freq = qcom_find_freq(ftbl_gcc_usb20_master_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, USB20_MASTER_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_USB20_MOCK_UTMI_CLK:
+		WARN(rate != 19200000, "Unexpected rate for USB20_MOCK_UTMI_CLK: %lu\n", rate);
+		clk_rcg_set_rate(priv->base, USB20_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
 		return rate;
+	case GCC_UFS_PHY_AXI_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
+		clk_rcg_set_rate(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
+				 freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_UFS_PHY_ICE_CORE_CLK:
+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
+		clk_rcg_set_rate(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
+				 freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_UFS_PHY_PHY_AUX_CLK:
+		clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
+	case GCC_SDCC1_APPS_CLK:
+		clk_enable_gpll0(priv->base, &gpll9_vote_clk);
+		freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
+	case GCC_SDCC1_ICE_CORE_CLK:
+		freq = qcom_find_freq(ftbl_gcc_sdcc1_ice_core_clk_src, rate);
+		clk_rcg_set_rate(priv->base, SDCC1_ICE_CORE_CLK_CMD_RCGR,
+				 freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S0_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S0_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S1_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S1_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S2_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S2_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S3_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S3_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S4_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S5_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S5_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S6_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S6_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP0_S7_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S7_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S0_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S0_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S1_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S1_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S2_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S2_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S3_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S3_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S4_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S4_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S5_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S5_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S6_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S6_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP1_S7_CLK:
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S7_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_QUPV3_WRAP3_S0_CLK:
+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap3_s0_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP3_S0_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_GP1_CLK:
+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
+		clk_rcg_set_rate(priv->base, GP1_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_GP2_CLK:
+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
+		clk_rcg_set_rate(priv->base, GP2_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_GP3_CLK:
+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
+		clk_rcg_set_rate(priv->base, GP3_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_GP4_CLK:
+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
+		clk_rcg_set_rate(priv->base, GP4_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_GP5_CLK:
+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
+		clk_rcg_set_rate(priv->base, GP5_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_PDM2_CLK:
+		freq = qcom_find_freq(ftbl_gcc_pdm2_clk_src, rate);
+		clk_rcg_set_rate(priv->base, PDM2_CLK_CMD_RCGR, freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_EMAC0_PHY_AUX_CLK:
+		clk_rcg_set_rate(priv->base, EMAC0_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
+	case GCC_EMAC0_PTP_CLK:
+		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
+		freq = qcom_find_freq(ftbl_gcc_emac0_ptp_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, EMAC0_PTP_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_EMAC0_RGMII_CLK:
+		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
+		freq = qcom_find_freq(ftbl_gcc_emac0_rgmii_clk_src, rate);
+		clk_rcg_set_rate_mnd(priv->base, EMAC0_RGMII_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
+		return freq->freq;
+	case GCC_PCIE_0_AUX_CLK:
+		clk_rcg_set_rate(priv->base, PCIE_0_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
+	case GCC_PCIE_0_PHY_RCHNG_CLK:
+		freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+		clk_rcg_set_rate(priv->base, PCIE_0_PHY_RCHNG_CLK_CMD_RCGR,
+				 freq->pre_div, freq->src);
+		return freq->freq;
+	case GCC_PCIE_1_AUX_CLK:
+		clk_rcg_set_rate(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
+		return 19200000;
+	case GCC_PCIE_1_PHY_RCHNG_CLK:
+		freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
+		clk_rcg_set_rate(priv->base, PCIE_1_PHY_RCHNG_CLK_CMD_RCGR,
+				 freq->pre_div, freq->src);
+		return freq->freq;
 	default:
 		return 0;
 	}
 }
 
 static const struct gate_clk qcs8300_clks[] = {
-	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0)),
-	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0)),
-	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0)),
-	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0)),
-	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0)),
+	GATE_CLK_POLLED(GCC_AGGRE_NOC_QUPV3_AXI_CLK, 0x4b000, BIT(28), 0x8e200),
+	GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0), 0x830d4),
+	GATE_CLK_POLLED(GCC_AGGRE_USB2_PRIM_AXI_CLK, 0x1c05c, BIT(0), 0x1c05c),
+	GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0), 0x1b084),
+	GATE_CLK_POLLED(GCC_AHB2PHY0_CLK, 0x76004, BIT(0), 0x76004),
+	GATE_CLK_POLLED(GCC_AHB2PHY2_CLK, 0x76008, BIT(0), 0x76008),
+	GATE_CLK_POLLED(GCC_AHB2PHY3_CLK, 0x7600c, BIT(0), 0x7600c),
+	GATE_CLK_POLLED(GCC_BOOT_ROM_AHB_CLK, 0x4b000, BIT(10), 0x44004),
+	GATE_CLK(GCC_CAMERA_HF_AXI_CLK, 0x32010, BIT(0)),
+	GATE_CLK(GCC_CAMERA_SF_AXI_CLK, 0x32018, BIT(0)),
+	GATE_CLK_POLLED(GCC_CAMERA_THROTTLE_XO_CLK, 0x32024, BIT(0), 0x32024),
+	GATE_CLK_POLLED(GCC_CFG_NOC_USB2_PRIM_AXI_CLK, 0x1c060, BIT(0), 0x1c060),
+	GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0), 0x1b088),
+	GATE_CLK_POLLED(GCC_DDRSS_GPU_AXI_CLK, 0x7d164, BIT(0), 0x7d164),
+	GATE_CLK_POLLED(GCC_DISP_HF_AXI_CLK, 0x33010, BIT(0), 0x33010),
+	GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, BIT(0)),
+	GATE_CLK_POLLED(GCC_EMAC0_AXI_CLK, 0xb6018, BIT(0), 0xb6018),
+	GATE_CLK_POLLED(GCC_EMAC0_PHY_AUX_CLK, 0xb6024, BIT(0), 0xb6024),
+	GATE_CLK_POLLED(GCC_EMAC0_PTP_CLK, 0xb6040, BIT(0), 0xb6040),
+	GATE_CLK_POLLED(GCC_EMAC0_RGMII_CLK, 0xb6044, BIT(0), 0xb6044),
+	GATE_CLK_POLLED(GCC_EMAC0_SLV_AHB_CLK, 0xb6020, BIT(0), 0xb6020),
+	GATE_CLK_POLLED(GCC_GP1_CLK, 0x70000, BIT(0), 0x70000),
+	GATE_CLK_POLLED(GCC_GP2_CLK, 0x71000, BIT(0), 0x71000),
+	GATE_CLK_POLLED(GCC_GP3_CLK, 0x62000, BIT(0), 0x62000),
+	GATE_CLK_POLLED(GCC_GP4_CLK, 0x1e000, BIT(0), 0x1e000),
+	GATE_CLK_POLLED(GCC_GP5_CLK, 0x1f000, BIT(0), 0x1f000),
+	GATE_CLK(GCC_GPU_GPLL0_CLK_SRC, 0x4b000, BIT(15)),
+	GATE_CLK(GCC_GPU_GPLL0_DIV_CLK_SRC, 0x4b000, BIT(16)),
+	GATE_CLK_POLLED(GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK, 0x7d160, BIT(0), 0x7d160),
+	GATE_CLK_POLLED(GCC_GPU_MEMNOC_GFX_CLK, 0x7d010, BIT(0), 0x7d010),
+	GATE_CLK(GCC_GPU_SNOC_DVM_GFX_CLK, 0x7d01c, BIT(0)),
+	GATE_CLK_POLLED(GCC_GPU_TCU_THROTTLE_AHB_CLK, 0x7d008, BIT(0), 0x7d008),
+	GATE_CLK_POLLED(GCC_GPU_TCU_THROTTLE_CLK, 0x7d014, BIT(0), 0x7d014),
+	GATE_CLK_POLLED(GCC_PCIE_0_AUX_CLK, 0x4b010, BIT(16), 0xa9038),
+	GATE_CLK_POLLED(GCC_PCIE_0_CFG_AHB_CLK, 0x4b010, BIT(12), 0xa902c),
+	GATE_CLK_POLLED(GCC_PCIE_0_MSTR_AXI_CLK, 0x4b010, BIT(11), 0xa9024),
+	GATE_CLK_POLLED(GCC_PCIE_0_PHY_AUX_CLK, 0x4b010, BIT(13), 0xa9030),
+	GATE_CLK_POLLED(GCC_PCIE_0_PHY_RCHNG_CLK, 0x4b010, BIT(15), 0xa9050),
+	GATE_CLK(GCC_PCIE_0_PIPE_CLK, 0x4b010, BIT(14)),
+	GATE_CLK(GCC_PCIE_0_PIPEDIV2_CLK, 0x4b018, BIT(22)),
+	GATE_CLK_POLLED(GCC_PCIE_0_SLV_AXI_CLK, 0x4b010, BIT(10), 0xa901c),
+	GATE_CLK_POLLED(GCC_PCIE_0_SLV_Q2A_AXI_CLK, 0x4b018, BIT(12), 0xa9018),
+	GATE_CLK_POLLED(GCC_PCIE_1_AUX_CLK, 0x4b000, BIT(31), 0x77038),
+	GATE_CLK_POLLED(GCC_PCIE_1_CFG_AHB_CLK, 0x4b008, BIT(2), 0x7702c),
+	GATE_CLK_POLLED(GCC_PCIE_1_MSTR_AXI_CLK, 0x4b008, BIT(1), 0x77024),
+	GATE_CLK_POLLED(GCC_PCIE_1_PHY_AUX_CLK, 0x4b008, BIT(3), 0x77030),
+	GATE_CLK_POLLED(GCC_PCIE_1_PHY_RCHNG_CLK, 0x4b000, BIT(22), 0x77050),
+	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x4b008, BIT(4)),
+	GATE_CLK(GCC_PCIE_1_PIPEDIV2_CLK, 0x4b018, BIT(16)),
+	GATE_CLK_POLLED(GCC_PCIE_1_SLV_AXI_CLK, 0x4b008, BIT(0), 0x7701c),
+	GATE_CLK_POLLED(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x4b008, BIT(5), 0x77018),
+	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x9746c, BIT(0)),
+	GATE_CLK_POLLED(GCC_PCIE_THROTTLE_CFG_CLK, 0x4b020, BIT(15), 0xb2034),
+	GATE_CLK_POLLED(GCC_PDM2_CLK, 0x3f00c, BIT(0), 0x3f00c),
+	GATE_CLK_POLLED(GCC_PDM_AHB_CLK, 0x3f004, BIT(0), 0x3f004),
+	GATE_CLK_POLLED(GCC_PDM_XO4_CLK, 0x3f008, BIT(0), 0x3f008),
+	GATE_CLK_POLLED(GCC_QMIP_CAMERA_NRT_AHB_CLK, 0x32008, BIT(0), 0x32008),
+	GATE_CLK_POLLED(GCC_QMIP_CAMERA_RT_AHB_CLK, 0x3200c, BIT(0), 0x3200c),
+	GATE_CLK_POLLED(GCC_QMIP_DISP_AHB_CLK, 0x33008, BIT(0), 0x33008),
+	GATE_CLK_POLLED(GCC_QMIP_DISP_ROT_AHB_CLK, 0x3300c, BIT(0), 0x3300c),
+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_CVP_AHB_CLK, 0x34008, BIT(0), 0x34008),
+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_VCODEC_AHB_CLK, 0x3400c, BIT(0), 0x3400c),
+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_VCPU_AHB_CLK, 0x34010, BIT(0), 0x34010),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x4b008, BIT(9), 0x23018),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_CLK, 0x4b008, BIT(8), 0x2300c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, BIT(10), 0x2314c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S1_CLK, 0x4b008, BIT(11), 0x23280),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S2_CLK, 0x4b008, BIT(12), 0x233b4),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S3_CLK, 0x4b008, BIT(13), 0x234e8),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S4_CLK, 0x4b008, BIT(14), 0x2361c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S5_CLK, 0x4b008, BIT(15), 0x23750),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S6_CLK, 0x4b008, BIT(16), 0x23884),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S7_CLK, 0x4b008, BIT(17), 0x239b8),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x4b008, BIT(18), 0x24018),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_CLK, 0x4b008, BIT(19), 0x2400c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S0_CLK, 0x4b008, BIT(22), 0x2414c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S1_CLK, 0x4b008, BIT(23), 0x24280),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S2_CLK, 0x4b008, BIT(24), 0x243b4),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S3_CLK, 0x4b008, BIT(25), 0x244e8),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S4_CLK, 0x4b008, BIT(26), 0x2461c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S5_CLK, 0x4b008, BIT(27), 0x24750),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S6_CLK, 0x4b018, BIT(27), 0x24884),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S7_CLK, 0x4b018, BIT(28), 0x249b8),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_2X_CLK, 0x4b000, BIT(24), 0xc4018),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_CLK, 0x4b000, BIT(23), 0xc400c),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_QSPI_CLK, 0x4b000, BIT(26), 0xc4284),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, BIT(25), 0xc4150),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x4b008, BIT(6), 0x23004),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x4b008, BIT(7), 0x23008),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x4b008, BIT(20), 0x24004),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x4b008, BIT(21), 0x24008),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_M_AHB_CLK, 0x4b000, BIT(27), 0xc4004),
+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_S_AHB_CLK, 0x4b000, BIT(20), 0xc4008),
+	GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0), 0x2000c),
+	GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0), 0x20004),
+	GATE_CLK_POLLED(GCC_SDCC1_ICE_CORE_CLK, 0x20044, BIT(0), 0x20044),
+	GATE_CLK(GCC_SGMI_CLKREF_EN, 0x97034, BIT(0)),
+	GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0), 0x83020),
+	GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0), 0x83018),
+	GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, BIT(0), 0x8306c),
+	GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, BIT(0), 0x830a4),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, BIT(0)),
+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, BIT(0)),
+	GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0), 0x83064),
+	GATE_CLK_POLLED(GCC_USB20_MASTER_CLK, 0x1c018, BIT(0), 0x1c018),
+	GATE_CLK_POLLED(GCC_USB20_MOCK_UTMI_CLK, 0x1c024, BIT(0), 0x1c024),
+	GATE_CLK_POLLED(GCC_USB20_SLEEP_CLK, 0x1c020, BIT(0), 0x1c020),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0), 0x1b018),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0), 0x1b024),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0), 0x1b020),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0), 0x1b05c),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0), 0x1b060),
+	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, BIT(0)),
+	GATE_CLK(GCC_USB_CLKREF_EN, 0x97468, BIT(0)),
+	GATE_CLK_POLLED(GCC_VIDEO_AXI0_CLK, 0x34014, BIT(0), 0x34014),
+	GATE_CLK_POLLED(GCC_VIDEO_AXI1_CLK, 0x3401c, BIT(0), 0x3401c),
 };
 
 static int qcs8300_enable(struct clk *clk)
@@ -74,11 +559,27 @@ static int qcs8300_enable(struct clk *clk)
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
 		break;
+	case GCC_QUPV3_WRAP0_S0_CLK ... GCC_QUPV3_WRAP0_S7_CLK:
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_0_M_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_0_S_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_2X_CLK);
+		break;
+	case GCC_QUPV3_WRAP1_S0_CLK ... GCC_QUPV3_WRAP1_S7_CLK:
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_1_M_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_1_S_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP1_CORE_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP1_CORE_2X_CLK);
+		break;
+	case GCC_QUPV3_WRAP3_S0_CLK:
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_3_M_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_3_S_AHB_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP3_CORE_CLK);
+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP3_CORE_2X_CLK);
+		break;
 	}
 
-	qcom_gate_clk_en(priv, clk->id);
-
-	return 0;
+	return qcom_gate_clk_en(priv, clk->id);
 }
 
 static const struct qcom_reset_map qcs8300_gcc_resets[] = {
@@ -112,8 +613,12 @@ static const struct qcom_reset_map qcs8300_gcc_resets[] = {
 };
 
 static const struct qcom_power_map qcs8300_gdscs[] = {
+	[GCC_EMAC0_GDSC] = { 0xb6004 },
+	[GCC_PCIE_0_GDSC] = { 0xa9004 },
+	[GCC_PCIE_1_GDSC] = { 0x77004 },
 	[GCC_UFS_PHY_GDSC] = { 0x83004 },
-	[GCC_USB30_PRIM_GDSC] = { 0x1B004 },
+	[GCC_USB20_PRIM_GDSC] = { 0x1c004 },
+	[GCC_USB30_PRIM_GDSC] = { 0x1b004 },
 };
 
 static struct msm_clk_data qcs8300_gcc_data = {

-- 
2.34.1

[PATCH v2 3/7] pinctrl: qcom: Add QCS8300 pinctrl driver

[Balaji Selvanathan via U-Boot]

Add pinctrl support for QCS8300.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/pinctrl/qcom/Kconfig           |   8 +
 drivers/pinctrl/qcom/Makefile          |   1 +
 drivers/pinctrl/qcom/pinctrl-qcs8300.c | 468 +++++++++++++++++++++++++++++++++
 3 files changed, 477 insertions(+)

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 0bea461fcc3..2af71945c4d 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -86,6 +86,14 @@ config PINCTRL_QCOM_QCS615
 	  Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC,
 	  as well as the associated GPIO driver.
 
+config PINCTRL_QCOM_QCS8300
+	bool "Qualcomm QCS8300 Pinctrl"
+	default y if PINCTRL_QCOM_GENERIC
+	select PINCTRL_QCOM
+	help
+	  Say Y here to enable support for pinctrl on the Snapdragon QCS8300 SoC,
+	  as well as the associated GPIO driver.
+
 config PINCTRL_QCOM_SA8775P
 	bool "Qualcomm SA8775P Pinctrl"
 	default y if PINCTRL_QCOM_GENERIC
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 87cb128c4d4..e10fbc3d3ec 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
 obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
 obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
+obj-$(CONFIG_PINCTRL_QCOM_QCS8300) += pinctrl-qcs8300.o
 obj-$(CONFIG_PINCTRL_QCOM_SA8775P) += pinctrl-sa8775p.o
 obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
 obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
new file mode 100644
index 00000000000..91f7c4fcf1e
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Qualcomm QCS8300 pinctrl
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <dm.h>
+
+#include "pinctrl-qcom.h"
+
+#define MAX_PIN_NAME_LEN 32
+#define MSM_PIN_FUNCTION_COUNT 12
+
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+typedef unsigned int msm_pin_function[MSM_PIN_FUNCTION_COUNT];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\
+	{\
+		msm_mux_gpio, /* gpio mode */\
+		msm_mux_##f1,\
+		msm_mux_##f2,\
+		msm_mux_##f3,\
+		msm_mux_##f4,\
+		msm_mux_##f5,\
+		msm_mux_##f6,\
+		msm_mux_##f7,\
+		msm_mux_##f8,\
+		msm_mux_##f9,\
+		msm_mux_##f10,\
+		msm_mux_##f11 /* egpio mode */\
+	}
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)\
+	{\
+		.name = pg_name,\
+		.ctl_reg = ctl,\
+		.io_reg = 0,\
+		.pull_bit = pull,\
+		.drv_bit = drv,\
+		.oe_bit = -1,\
+		.in_bit = -1,\
+		.out_bit = -1,\
+	}
+
+#define UFS_RESET(pg_name, ctl)\
+	{\
+		.name = pg_name,\
+		.ctl_reg = ctl,\
+		.io_reg = ctl + 0x4,\
+		.pull_bit = 3,\
+		.drv_bit = 0,\
+		.oe_bit = -1,\
+		.in_bit = -1,\
+		.out_bit = 0,\
+	}
+
+enum qcs8300_functions {
+	msm_mux_gpio,
+	msm_mux_aoss_cti,
+	msm_mux_atest_char,
+	msm_mux_atest_usb2,
+	msm_mux_audio_ref,
+	msm_mux_cam_mclk,
+	msm_mux_cci_async,
+	msm_mux_cci_i2c_scl,
+	msm_mux_cci_i2c_sda,
+	msm_mux_cci_timer,
+	msm_mux_cri_trng,
+	msm_mux_dbg_out,
+	msm_mux_ddr_bist,
+	msm_mux_ddr_pxi0,
+	msm_mux_ddr_pxi1,
+	msm_mux_ddr_pxi2,
+	msm_mux_ddr_pxi3,
+	msm_mux_edp0_hot,
+	msm_mux_edp0_lcd,
+	msm_mux_edp1_lcd,
+	msm_mux_egpio,
+	msm_mux_emac0_mcg0,
+	msm_mux_emac0_mcg1,
+	msm_mux_emac0_mcg2,
+	msm_mux_emac0_mcg3,
+	msm_mux_emac0_mdc,
+	msm_mux_emac0_mdio,
+	msm_mux_emac0_ptp_aux,
+	msm_mux_emac0_ptp_pps,
+	msm_mux_gcc_gp1,
+	msm_mux_gcc_gp2,
+	msm_mux_gcc_gp3,
+	msm_mux_gcc_gp4,
+	msm_mux_gcc_gp5,
+	msm_mux_hs0_mi2s,
+	msm_mux_hs1_mi2s,
+	msm_mux_hs2_mi2s,
+	msm_mux_ibi_i3c,
+	msm_mux_jitter_bist,
+	msm_mux_mdp0_vsync0,
+	msm_mux_mdp0_vsync1,
+	msm_mux_mdp0_vsync3,
+	msm_mux_mdp0_vsync6,
+	msm_mux_mdp0_vsync7,
+	msm_mux_mdp_vsync,
+	msm_mux_mi2s1_data0,
+	msm_mux_mi2s1_data1,
+	msm_mux_mi2s1_sck,
+	msm_mux_mi2s1_ws,
+	msm_mux_mi2s2_data0,
+	msm_mux_mi2s2_data1,
+	msm_mux_mi2s2_sck,
+	msm_mux_mi2s2_ws,
+	msm_mux_mi2s_mclk0,
+	msm_mux_mi2s_mclk1,
+	msm_mux_pcie0_clkreq,
+	msm_mux_pcie1_clkreq,
+	msm_mux_phase_flag,
+	msm_mux_pll_bist,
+	msm_mux_pll_clk,
+	msm_mux_prng_rosc0,
+	msm_mux_prng_rosc1,
+	msm_mux_prng_rosc2,
+	msm_mux_prng_rosc3,
+	msm_mux_qdss_cti,
+	msm_mux_qdss_gpio,
+	msm_mux_qup0_se0,
+	msm_mux_qup0_se1,
+	msm_mux_qup0_se2,
+	msm_mux_qup0_se3,
+	msm_mux_qup0_se4,
+	msm_mux_qup0_se5,
+	msm_mux_qup0_se6,
+	msm_mux_qup0_se7,
+	msm_mux_qup1_se0,
+	msm_mux_qup1_se1,
+	msm_mux_qup1_se2,
+	msm_mux_qup1_se3,
+	msm_mux_qup1_se4,
+	msm_mux_qup1_se5,
+	msm_mux_qup1_se6,
+	msm_mux_qup1_se7,
+	msm_mux_qup2_se0,
+	msm_mux_sailss_emac0,
+	msm_mux_sailss_ospi,
+	msm_mux_sgmii_phy,
+	msm_mux_tb_trig,
+	msm_mux_tgu_ch0,
+	msm_mux_tgu_ch1,
+	msm_mux_tgu_ch2,
+	msm_mux_tgu_ch3,
+	msm_mux_tsense_pwm1,
+	msm_mux_tsense_pwm2,
+	msm_mux_tsense_pwm3,
+	msm_mux_tsense_pwm4,
+	msm_mux_usb2phy_ac,
+	msm_mux_vsense_trigger,
+	msm_mux__,
+};
+
+#define MSM_PIN_FUNCTION(fname)\
+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	MSM_PIN_FUNCTION(gpio),
+	MSM_PIN_FUNCTION(aoss_cti),
+	MSM_PIN_FUNCTION(atest_char),
+	MSM_PIN_FUNCTION(atest_usb2),
+	MSM_PIN_FUNCTION(audio_ref),
+	MSM_PIN_FUNCTION(cam_mclk),
+	MSM_PIN_FUNCTION(cci_async),
+	MSM_PIN_FUNCTION(cci_i2c_scl),
+	MSM_PIN_FUNCTION(cci_i2c_sda),
+	MSM_PIN_FUNCTION(cci_timer),
+	MSM_PIN_FUNCTION(cri_trng),
+	MSM_PIN_FUNCTION(dbg_out),
+	MSM_PIN_FUNCTION(ddr_bist),
+	MSM_PIN_FUNCTION(ddr_pxi0),
+	MSM_PIN_FUNCTION(ddr_pxi1),
+	MSM_PIN_FUNCTION(ddr_pxi2),
+	MSM_PIN_FUNCTION(ddr_pxi3),
+	MSM_PIN_FUNCTION(edp0_hot),
+	MSM_PIN_FUNCTION(edp0_lcd),
+	MSM_PIN_FUNCTION(edp1_lcd),
+	MSM_PIN_FUNCTION(egpio),
+	MSM_PIN_FUNCTION(emac0_mcg0),
+	MSM_PIN_FUNCTION(emac0_mcg1),
+	MSM_PIN_FUNCTION(emac0_mcg2),
+	MSM_PIN_FUNCTION(emac0_mcg3),
+	MSM_PIN_FUNCTION(emac0_mdc),
+	MSM_PIN_FUNCTION(emac0_mdio),
+	MSM_PIN_FUNCTION(emac0_ptp_aux),
+	MSM_PIN_FUNCTION(emac0_ptp_pps),
+	MSM_PIN_FUNCTION(gcc_gp1),
+	MSM_PIN_FUNCTION(gcc_gp2),
+	MSM_PIN_FUNCTION(gcc_gp3),
+	MSM_PIN_FUNCTION(gcc_gp4),
+	MSM_PIN_FUNCTION(gcc_gp5),
+	MSM_PIN_FUNCTION(hs0_mi2s),
+	MSM_PIN_FUNCTION(hs1_mi2s),
+	MSM_PIN_FUNCTION(hs2_mi2s),
+	MSM_PIN_FUNCTION(ibi_i3c),
+	MSM_PIN_FUNCTION(jitter_bist),
+	MSM_PIN_FUNCTION(mdp0_vsync0),
+	MSM_PIN_FUNCTION(mdp0_vsync1),
+	MSM_PIN_FUNCTION(mdp0_vsync3),
+	MSM_PIN_FUNCTION(mdp0_vsync6),
+	MSM_PIN_FUNCTION(mdp0_vsync7),
+	MSM_PIN_FUNCTION(mdp_vsync),
+	MSM_PIN_FUNCTION(mi2s1_data0),
+	MSM_PIN_FUNCTION(mi2s1_data1),
+	MSM_PIN_FUNCTION(mi2s1_sck),
+	MSM_PIN_FUNCTION(mi2s1_ws),
+	MSM_PIN_FUNCTION(mi2s2_data0),
+	MSM_PIN_FUNCTION(mi2s2_data1),
+	MSM_PIN_FUNCTION(mi2s2_sck),
+	MSM_PIN_FUNCTION(mi2s2_ws),
+	MSM_PIN_FUNCTION(mi2s_mclk0),
+	MSM_PIN_FUNCTION(mi2s_mclk1),
+	MSM_PIN_FUNCTION(pcie0_clkreq),
+	MSM_PIN_FUNCTION(pcie1_clkreq),
+	MSM_PIN_FUNCTION(phase_flag),
+	MSM_PIN_FUNCTION(pll_bist),
+	MSM_PIN_FUNCTION(pll_clk),
+	MSM_PIN_FUNCTION(prng_rosc0),
+	MSM_PIN_FUNCTION(prng_rosc1),
+	MSM_PIN_FUNCTION(prng_rosc2),
+	MSM_PIN_FUNCTION(prng_rosc3),
+	MSM_PIN_FUNCTION(qdss_cti),
+	MSM_PIN_FUNCTION(qdss_gpio),
+	MSM_PIN_FUNCTION(qup0_se0),
+	MSM_PIN_FUNCTION(qup0_se1),
+	MSM_PIN_FUNCTION(qup0_se2),
+	MSM_PIN_FUNCTION(qup0_se3),
+	MSM_PIN_FUNCTION(qup0_se4),
+	MSM_PIN_FUNCTION(qup0_se5),
+	MSM_PIN_FUNCTION(qup0_se6),
+	MSM_PIN_FUNCTION(qup0_se7),
+	MSM_PIN_FUNCTION(qup1_se0),
+	MSM_PIN_FUNCTION(qup1_se1),
+	MSM_PIN_FUNCTION(qup1_se2),
+	MSM_PIN_FUNCTION(qup1_se3),
+	MSM_PIN_FUNCTION(qup1_se4),
+	MSM_PIN_FUNCTION(qup1_se5),
+	MSM_PIN_FUNCTION(qup1_se6),
+	MSM_PIN_FUNCTION(qup1_se7),
+	MSM_PIN_FUNCTION(qup2_se0),
+	MSM_PIN_FUNCTION(sailss_emac0),
+	MSM_PIN_FUNCTION(sailss_ospi),
+	MSM_PIN_FUNCTION(sgmii_phy),
+	MSM_PIN_FUNCTION(tb_trig),
+	MSM_PIN_FUNCTION(tgu_ch0),
+	MSM_PIN_FUNCTION(tgu_ch1),
+	MSM_PIN_FUNCTION(tgu_ch2),
+	MSM_PIN_FUNCTION(tgu_ch3),
+	MSM_PIN_FUNCTION(tsense_pwm1),
+	MSM_PIN_FUNCTION(tsense_pwm2),
+	MSM_PIN_FUNCTION(tsense_pwm3),
+	MSM_PIN_FUNCTION(tsense_pwm4),
+	MSM_PIN_FUNCTION(usb2phy_ac),
+	MSM_PIN_FUNCTION(vsense_trigger),
+};
+
+static const msm_pin_function qcs8300_pin_functions[] = {
+	[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _),
+	[1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _, _, _),
+	[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _),
+	[3] = PINGROUP(3, phase_flag, _, _, _, _, _, _, _, _, _, _),
+	[4] = PINGROUP(4, sgmii_phy, qdss_cti, _, _, _, _, _, _, _, _, _),
+	[5] = PINGROUP(5, emac0_mdc, qdss_cti, _, _, _, _, _, _, _, _, _),
+	[6] = PINGROUP(6, emac0_mdio, _, _, _, _, _, _, _, _, _, _),
+	[7] = PINGROUP(7, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
+	[8] = PINGROUP(8, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
+	[9] = PINGROUP(9, phase_flag, _, _, _, _, _, _, _, _, _, _),
+	[10] = PINGROUP(10, qup2_se0, emac0_mcg0, _, _, _, _, _, _, _, _, _),
+	[11] = PINGROUP(11, qup2_se0, emac0_mcg1, _, _, _, _, _, _, _, _, _),
+	[12] = PINGROUP(12, qup2_se0, _, _, _, _, _, _, _, _, _, _),
+	[13] = PINGROUP(13, qup2_se0, _, _, _, _, _, _, _, _, _, _),
+	[14] = PINGROUP(14, qup2_se0, tb_trig, _, _, _, _, _, _, _, _, _),
+	[15] = PINGROUP(15, qup2_se0, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _, _),
+	[16] = PINGROUP(16, qup2_se0, _, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _),
+	[17] = PINGROUP(17, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
+	[18] = PINGROUP(18, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
+	[19] = PINGROUP(19, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
+	[20] = PINGROUP(20, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
+	[21] = PINGROUP(21, qup0_se5, cci_timer, _, _, _, _, _, _, _, _, _),
+	[22] = PINGROUP(22, pcie1_clkreq, qup0_se5, cci_timer, _, _, _, _, _, _, _, _),
+	[23] = PINGROUP(23, qup0_se5, cci_timer, qdss_cti, _, _, _, _, _, _, _, _),
+	[24] = PINGROUP(24, qup0_se5, emac0_ptp_aux, emac0_ptp_pps, qdss_cti, emac0_mcg2, _, _, _, _, _, _),
+	[25] = PINGROUP(25, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
+	[26] = PINGROUP(26, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
+	[27] = PINGROUP(27, qup0_se3, _, _, _, _, _, _, _, _, _, _),
+	[28] = PINGROUP(28, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
+	[29] = PINGROUP(29, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_pps, tgu_ch2, _, _, _, _, _, _),
+	[30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, tgu_ch3, _, _, _, _, _, _),
+	[31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _),
+	[32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _),
+	[33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
+	[34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
+	[35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _),
+	[36] = PINGROUP(36, qup0_se2, gcc_gp2, qdss_gpio, _, _, _, _, _, _, _, _),
+	[37] = PINGROUP(37, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
+	[38] = PINGROUP(38, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
+	[39] = PINGROUP(39, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
+	[40] = PINGROUP(40, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
+	[41] = PINGROUP(41, qup1_se3, _, _, _, _, _, _, _, _, _, _),
+	[42] = PINGROUP(42, qup1_se3, _, mdp_vsync, _, _, _, _, _, _, _, _),
+	[43] = PINGROUP(43, qup0_se7, _, tgu_ch0, _, _, _, _, _, _, _, _),
+	[44] = PINGROUP(44, qup0_se7, _, tgu_ch1, _, _, _, _, _, _, _, _),
+	[45] = PINGROUP(45, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
+	[46] = PINGROUP(46, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
+	[47] = PINGROUP(47, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
+	[48] = PINGROUP(48, qup1_se4, hs1_mi2s, edp0_lcd, _, _, _, _, _, _, _, _),
+	[49] = PINGROUP(49, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, edp1_lcd, ddr_pxi1, _, _, _, _, _),
+	[50] = PINGROUP(50, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, _, ddr_pxi1, _, _, _, _, _),
+	[51] = PINGROUP(51, qup1_se5, hs2_mi2s, qdss_cti, _, _, _, _, _, _, _, _),
+	[52] = PINGROUP(52, qup1_se5, hs2_mi2s, qdss_cti, mdp_vsync, ddr_pxi2, _, _, _, _, _, _),
+	[53] = PINGROUP(53, ddr_bist, _, _, _, _, _, _, _, _, _, _),
+	[54] = PINGROUP(54, cci_i2c_sda, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
+	[55] = PINGROUP(55, cci_i2c_scl, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
+	[56] = PINGROUP(56, phase_flag, ddr_bist, _, _, _, _, _, _, _, _, _),
+	[57] = PINGROUP(57, cci_i2c_sda, prng_rosc0, qdss_gpio, _, _, _, _, _, _, _, _),
+	[58] = PINGROUP(58, cci_i2c_scl, prng_rosc1, qdss_gpio, _, _, _, _, _, _, _, _),
+	[59] = PINGROUP(59, cci_i2c_sda, prng_rosc2, qdss_gpio, _, _, _, _, _, _, _, _),
+	[60] = PINGROUP(60, cci_i2c_scl, prng_rosc3, qdss_gpio, _, _, _, _, _, _, _, _),
+	[61] = PINGROUP(61, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _),
+	[62] = PINGROUP(62, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _),
+	[63] = PINGROUP(63, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
+	[64] = PINGROUP(64, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
+	[65] = PINGROUP(65, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
+	[66] = PINGROUP(66, phase_flag, _, atest_char, _, _, _, _, _, _, _, _),
+	[67] = PINGROUP(67, cam_mclk, vsense_trigger, atest_usb2, _, _, _, _, _, _, _, _),
+	[68] = PINGROUP(68, cam_mclk, gcc_gp4, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
+	[69] = PINGROUP(69, cam_mclk, gcc_gp3, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
+	[70] = PINGROUP(70, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
+	[71] = PINGROUP(71, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
+	[72] = PINGROUP(72, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
+	[73] = PINGROUP(73, _, qdss_gpio, _, _, _, _, _, _, _, _, _),
+	[74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _),
+	[75] = PINGROUP(75, _, dbg_out, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
+	[76] = PINGROUP(76, gcc_gp5, tsense_pwm4, _, _, _, _, _, _, _, _, _),
+	[77] = PINGROUP(77, gcc_gp5, tsense_pwm3, _, _, _, _, _, _, _, _, _),
+	[78] = PINGROUP(78, tsense_pwm2, _, _, _, _, _, _, _, _, _, _),
+	[79] = PINGROUP(79, emac0_ptp_aux, emac0_ptp_pps, emac0_mcg3, _, tsense_pwm1, _, _, _, _, _, _),
+	[80] = PINGROUP(80, qup0_se6, mdp0_vsync6, _, atest_usb2, ddr_pxi3, _, _, _, _, _, _),
+	[81] = PINGROUP(81, qup0_se6, mdp0_vsync7, gcc_gp2, _, atest_usb2, ddr_pxi3, _, _, _, _, _),
+	[82] = PINGROUP(82, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _),
+	[83] = PINGROUP(83, qup0_se6, gcc_gp4, _, atest_usb2, ddr_pxi2, _, _, _, _, _, _),
+	[84] = PINGROUP(84, qup1_se2, gcc_gp1, _, atest_usb2, _, _, _, _, _, _, _),
+	[85] = PINGROUP(85, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
+	[86] = PINGROUP(86, qup1_se2, _, _, _, _, _, _, _, _, _, _),
+	[87] = PINGROUP(87, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
+	[88] = PINGROUP(88, qup1_se2, _, _, _, _, _, _, _, _, _, _),
+	[89] = PINGROUP(89, qup1_se6, qup1_se7, mdp0_vsync0, _, _, _, _, _, _, _, _),
+	[90] = PINGROUP(90, qup1_se6, qup1_se7, mdp0_vsync1, cri_trng, _, _, _, _, _, _, _),
+	[91] = PINGROUP(91, qup1_se7, qup1_se6, mdp0_vsync3, cri_trng, _, _, _, _, _, _, _),
+	[92] = PINGROUP(92, qup1_se7, qup1_se6, cri_trng, _, atest_usb2, _, _, _, _, _, _),
+	[93] = PINGROUP(93, atest_char, _, _, _, _, _, _, _, _, _, _),
+	[94] = PINGROUP(94, edp0_hot, _, _, _, _, _, _, _, _, _, _),
+	[95] = PINGROUP(95, _, _, _, _, _, _, _, _, _, _, _),
+	[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _),
+	[97] = PINGROUP(97, mi2s_mclk0, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _),
+	[98] = PINGROUP(98, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[99] = PINGROUP(99, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[100] = PINGROUP(100, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[101] = PINGROUP(101, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[102] = PINGROUP(102, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[103] = PINGROUP(103, mi2s2_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[104] = PINGROUP(104, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[105] = PINGROUP(105, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
+	[106] = PINGROUP(106, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[107] = PINGROUP(107, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
+	[108] = PINGROUP(108, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
+	[109] = PINGROUP(109, hs0_mi2s, mi2s_mclk1, qdss_gpio, _, _, _, _, _, _, _, _),
+	[110] = PINGROUP(110, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
+	[111] = PINGROUP(111, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
+	[112] = PINGROUP(112, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
+	[113] = PINGROUP(113, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
+	[114] = PINGROUP(114, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
+	[115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, egpio),
+	[116] = PINGROUP(116, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[117] = PINGROUP(117, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[118] = PINGROUP(118, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, egpio),
+	[120] = PINGROUP(120, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[121] = PINGROUP(121, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[122] = PINGROUP(122, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, egpio),
+	[124] = PINGROUP(124, _, _, _, _, _, _, _, _, _, _, egpio),
+	[125] = PINGROUP(125, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
+	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _, _, egpio),
+	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _, _, egpio),
+	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _, egpio),
+	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _, _, egpio),
+	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, egpio),
+	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _, egpio),
+	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio),
+};
+
+static const struct msm_special_pin_data qcs8300_special_pins_data[] = {
+	[0] = UFS_RESET("ufs_reset", 0x92000),
+	[1] = SDC_QDSD_PINGROUP("sdc1_rclk", 0x89000, 15, 0),
+	[2] = SDC_QDSD_PINGROUP("sdc1_clk", 0x89000, 13, 6),
+	[3] = SDC_QDSD_PINGROUP("sdc1_cmd", 0x89000, 11, 3),
+	[4] = SDC_QDSD_PINGROUP("sdc1_data", 0x89000, 9, 0),
+};
+
+static const char *qcs8300_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs8300_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector >= 133 && selector <= 137)
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "%s",
+			 qcs8300_special_pins_data[selector - 133].name);
+	else
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+
+	return pin_name;
+}
+
+static int qcs8300_get_function_mux(__maybe_unused unsigned int pin,
+				    unsigned int selector)
+{
+	unsigned int i;
+	const msm_pin_function *func = qcs8300_pin_functions + pin;
+
+	for (i = 0; i < MSM_PIN_FUNCTION_COUNT; i++)
+		if ((*func)[i] == selector)
+			return i;
+
+	pr_err("Can't find requested function for pin %u\n", pin);
+
+	return -EINVAL;
+}
+
+static const struct msm_pinctrl_data qcs8300_data = {
+	.pin_data = {
+		.pin_count = 138,
+		.special_pins_start = 133,
+		.special_pins_data = qcs8300_special_pins_data,
+	},
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = qcs8300_get_function_name,
+	.get_function_mux = qcs8300_get_function_mux,
+	.get_pin_name = qcs8300_get_pin_name,
+};
+
+static const struct udevice_id msm_pinctrl_ids[] = {
+	{
+		.compatible = "qcom,qcs8300-tlmm",
+		.data = (ulong)&qcs8300_data
+	},
+	{ /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(pinctrl_qcs8300) = {
+	.name		= "pinctrl_qcs8300",
+	.id		= UCLASS_NOP,
+	.of_match	= msm_pinctrl_ids,
+	.ops		= &msm_pinctrl_ops,
+	.bind		= msm_pinctrl_bind,
+	.flags		= DM_FLAG_PRE_RELOC,
+};

-- 
2.34.1

[PATCH v2 4/7] interconnect: qcom: Add QCS8300 interconnect driver

[Balaji Selvanathan via U-Boot]

Add the interconnect (NoC) driver for QCS8300.

Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 drivers/interconnect/qcom/Kconfig   |   6 +
 drivers/interconnect/qcom/Makefile  |   1 +
 drivers/interconnect/qcom/qcs8300.c | 269 ++++++++++++++++++++++++++++++++++++
 drivers/interconnect/qcom/qcs8300.h |  24 ++++
 4 files changed, 300 insertions(+)

diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index b105c3a1f9a..906f2fa604a 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -5,6 +5,12 @@ config INTERCONNECT_QCOM_RPMH
 	  Enable support for the interconnect helpers to vote with
 	  the RPMh subsystems in Qualcomm SoCs
 
+config INTERCONNECT_QCOM_QCS8300
+	bool "Enable interconnect support for QCS8300 SoC"
+	depends on INTERCONNECT_QCOM_RPMH
+	help
+	  Enable support for the interconnect driver for the QCS8300 SoC.
+
 config INTERCONNECT_QCOM_SM8650
 	bool "Enable interconnect support for SM8650 SoC"
 	depends on INTERCONNECT_QCOM_RPMH
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index a33a65bd82e..6ba69269621 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -4,4 +4,5 @@
 #
 
 obj-$(CONFIG_$(PHASE_)INTERCONNECT_QCOM_RPMH) += icc-rpmh.o bcm-voter.o
+obj-$(CONFIG_$(PHASE_)INTERCONNECT_QCOM_QCS8300) += qcs8300.o
 obj-$(CONFIG_$(PHASE_)INTERCONNECT_QCOM_SM8650) += sm8650.o
diff --git a/drivers/interconnect/qcom/qcs8300.c b/drivers/interconnect/qcom/qcs8300.c
new file mode 100644
index 00000000000..db5316af2cb
--- /dev/null
+++ b/drivers/interconnect/qcom/qcs8300.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ */
+
+#include <dm.h>
+#include <interconnect-uclass.h>
+#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h>
+
+#include "icc-rpmh.h"
+#include "qcs8300.h"
+
+static struct qcom_icc_node xm_ufs_mem = {
+	.name = "xm_ufs_mem",
+	.id = QCS8300_MASTER_UFS_MEM,
+	.channels = 1,
+	.buswidth = 8,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node qns_a1noc_snoc = {
+	.name = "qns_a1noc_snoc",
+	.id = QCS8300_SLAVE_A1NOC_SNOC,
+	.channels = 1,
+	.buswidth = 32,
+	.num_links = 1,
+	.links = { QCS8300_MASTER_A1NOC_SNOC },
+};
+
+static struct qcom_icc_node qnm_aggre1_noc = {
+	.name = "qnm_aggre1_noc",
+	.id = QCS8300_MASTER_A1NOC_SNOC,
+	.channels = 1,
+	.buswidth = 32,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_SNOC_GEM_NOC_SF },
+};
+
+static struct qcom_icc_node qns_gemnoc_sf = {
+	.name = "qns_gemnoc_sf",
+	.id = QCS8300_SLAVE_SNOC_GEM_NOC_SF,
+	.channels = 1,
+	.buswidth = 16,
+	.num_links = 1,
+	.links = { QCS8300_MASTER_SNOC_SF_MEM_NOC },
+};
+
+static struct qcom_icc_node qnm_snoc_sf = {
+	.name = "qnm_snoc_sf",
+	.id = QCS8300_MASTER_SNOC_SF_MEM_NOC,
+	.channels = 1,
+	.buswidth = 16,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_LLCC },
+};
+
+static struct qcom_icc_node chm_apps = {
+	.name = "chm_apps",
+	.id = QCS8300_MASTER_APPSS_PROC,
+	.channels = 4,
+	.buswidth = 32,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_GEM_NOC_CNOC },
+};
+
+static struct qcom_icc_node qns_gem_noc_cnoc = {
+	.name = "qns_gem_noc_cnoc",
+	.id = QCS8300_SLAVE_GEM_NOC_CNOC,
+	.channels = 1,
+	.buswidth = 16,
+	.num_links = 1,
+	.links = { QCS8300_MASTER_GEM_NOC_CNOC },
+};
+
+static struct qcom_icc_node qns_llcc = {
+	.name = "qns_llcc",
+	.id = QCS8300_SLAVE_LLCC,
+	.channels = 4,
+	.buswidth = 16,
+	.num_links = 1,
+	.links = { QCS8300_MASTER_LLCC },
+};
+
+static struct qcom_icc_node llcc_mc = {
+	.name = "llcc_mc",
+	.id = QCS8300_MASTER_LLCC,
+	.channels = 8,
+	.buswidth = 4,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_EBI1 },
+};
+
+static struct qcom_icc_node ebi = {
+	.name = "ebi",
+	.id = QCS8300_SLAVE_EBI1,
+	.channels = 8,
+	.buswidth = 4,
+	.num_links = 0,
+};
+
+static struct qcom_icc_node qnm_gemnoc_cnoc = {
+	.name = "qnm_gemnoc_cnoc",
+	.id = QCS8300_MASTER_GEM_NOC_CNOC,
+	.channels = 1,
+	.buswidth = 16,
+	.num_links = 1,
+	.links = { QCS8300_SLAVE_UFS_MEM_CFG },
+};
+
+static struct qcom_icc_node qhs_ufs_mem_cfg = {
+	.name = "qhs_ufs_mem_cfg",
+	.id = QCS8300_SLAVE_UFS_MEM_CFG,
+	.channels = 1,
+	.buswidth = 4,
+	.num_links = 0,
+};
+
+static struct qcom_icc_bcm bcm_sn3 = {
+	.name = "SN3",
+	.num_nodes = 2,
+	.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
+};
+
+static struct qcom_icc_bcm bcm_sn0 = {
+	.name = "SN0",
+	.keepalive = true,
+	.num_nodes = 1,
+	.nodes = { &qns_gemnoc_sf },
+};
+
+static struct qcom_icc_bcm bcm_sh0 = {
+	.name = "SH0",
+	.keepalive = true,
+	.num_nodes = 1,
+	.nodes = { &qns_llcc },
+};
+
+static struct qcom_icc_bcm bcm_sh2 = {
+	.name = "SH2",
+	.num_nodes = 1,
+	.nodes = { &chm_apps },
+};
+
+static struct qcom_icc_bcm bcm_acv = {
+	.name = "ACV",
+	.enable_mask = BIT(3),
+	.num_nodes = 1,
+	.nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_mc0 = {
+	.name = "MC0",
+	.keepalive = true,
+	.num_nodes = 1,
+	.nodes = { &ebi },
+};
+
+static struct qcom_icc_bcm bcm_cn0 = {
+	.name = "CN0",
+	.keepalive = true,
+	.num_nodes = 1,
+	.nodes = { &qnm_gemnoc_cnoc },
+};
+
+static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
+	&bcm_sn3,
+};
+
+static struct qcom_icc_node * const aggre1_noc_nodes[] = {
+	[MASTER_UFS_MEM] = &xm_ufs_mem,
+	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
+};
+
+static const struct qcom_icc_desc qcs8300_aggre1_noc = {
+	.nodes = aggre1_noc_nodes,
+	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
+	.bcms = aggre1_noc_bcms,
+	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const system_noc_bcms[] = {
+	&bcm_sn0,
+};
+
+static struct qcom_icc_node * const system_noc_nodes[] = {
+	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
+	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
+};
+
+static const struct qcom_icc_desc qcs8300_system_noc = {
+	.nodes = system_noc_nodes,
+	.num_nodes = ARRAY_SIZE(system_noc_nodes),
+	.bcms = system_noc_bcms,
+	.num_bcms = ARRAY_SIZE(system_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const gem_noc_bcms[] = {
+	&bcm_sh0,
+	&bcm_sh2,
+};
+
+static struct qcom_icc_node * const gem_noc_nodes[] = {
+	[MASTER_APPSS_PROC] = &chm_apps,
+	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
+	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
+	[SLAVE_LLCC] = &qns_llcc,
+};
+
+static const struct qcom_icc_desc qcs8300_gem_noc = {
+	.nodes = gem_noc_nodes,
+	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
+	.bcms = gem_noc_bcms,
+	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
+};
+
+static struct qcom_icc_bcm * const mc_virt_bcms[] = {
+	&bcm_acv,
+	&bcm_mc0,
+};
+
+static struct qcom_icc_node * const mc_virt_nodes[] = {
+	[MASTER_LLCC] = &llcc_mc,
+	[SLAVE_EBI1] = &ebi,
+};
+
+static const struct qcom_icc_desc qcs8300_mc_virt = {
+	.nodes = mc_virt_nodes,
+	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
+	.bcms = mc_virt_bcms,
+	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
+};
+
+static struct qcom_icc_bcm * const config_noc_bcms[] = {
+	&bcm_cn0,
+};
+
+static struct qcom_icc_node * const config_noc_nodes[] = {
+	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
+	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
+};
+
+static const struct qcom_icc_desc qcs8300_config_noc = {
+	.nodes = config_noc_nodes,
+	.num_nodes = ARRAY_SIZE(config_noc_nodes),
+	.bcms = config_noc_bcms,
+	.num_bcms = ARRAY_SIZE(config_noc_bcms),
+};
+
+static const struct udevice_id qnoc_of_match[] = {
+	{ .compatible = "qcom,qcs8300-aggre1-noc", .data = (ulong)&qcs8300_aggre1_noc },
+	{ .compatible = "qcom,qcs8300-system-noc", .data = (ulong)&qcs8300_system_noc },
+	{ .compatible = "qcom,qcs8300-gem-noc", .data = (ulong)&qcs8300_gem_noc },
+	{ .compatible = "qcom,qcs8300-mc-virt", .data = (ulong)&qcs8300_mc_virt },
+	{ .compatible = "qcom,qcs8300-config-noc", .data = (ulong)&qcs8300_config_noc },
+	{ }
+};
+
+U_BOOT_DRIVER(qnoc_qcs8300) = {
+	.name = "qnoc-qcs8300",
+	.id = UCLASS_INTERCONNECT,
+	.of_match = qnoc_of_match,
+	.probe = qcom_icc_rpmh_probe,
+	.bind = qcom_icc_rpmh_bind,
+	.unbind = qcom_icc_rpmh_unbind,
+	.ops = &qcom_icc_rpmh_ops,
+	.plat_auto = sizeof(struct qcom_icc_provider),
+};
diff --git a/drivers/interconnect/qcom/qcs8300.h b/drivers/interconnect/qcom/qcs8300.h
new file mode 100644
index 00000000000..2dc523d127e
--- /dev/null
+++ b/drivers/interconnect/qcom/qcs8300.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * QCS8300 interconnect IDs
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
+#define __DRIVERS_INTERCONNECT_QCOM_QCS8300_H
+
+#define QCS8300_MASTER_UFS_MEM			0
+#define QCS8300_SLAVE_A1NOC_SNOC		1
+#define QCS8300_MASTER_A1NOC_SNOC		2
+#define QCS8300_SLAVE_SNOC_GEM_NOC_SF		3
+#define QCS8300_MASTER_SNOC_SF_MEM_NOC		4
+#define QCS8300_SLAVE_LLCC			5
+#define QCS8300_MASTER_APPSS_PROC		6
+#define QCS8300_SLAVE_GEM_NOC_CNOC		7
+#define QCS8300_MASTER_GEM_NOC_CNOC		8
+#define QCS8300_MASTER_LLCC			9
+#define QCS8300_SLAVE_EBI1			10
+#define QCS8300_SLAVE_UFS_MEM_CFG		11
+
+#endif

-- 
2.34.1

[PATCH v2 5/7] arm64: dts: monaco-evk: Add reboot-mode support via PON/SDAM

[Balaji Selvanathan via U-Boot]

monaco-pmics.dtsi has no PON/SDAM reboot-reason storage, so
U-Boot can't read the reboot-reason to tell if it should stop in
fastboot instead of booting the kernel.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 arch/arm/dts/monaco-evk-u-boot.dtsi | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm/dts/monaco-evk-u-boot.dtsi b/arch/arm/dts/monaco-evk-u-boot.dtsi
new file mode 100644
index 00000000000..5520d111864
--- /dev/null
+++ b/arch/arm/dts/monaco-evk-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/ {
+	reboot-mode {
+		compatible = "nvmem-reboot-mode";
+		nvmem-cells = <&reboot_reason>;
+		nvmem-cell-names = "reboot-mode";
+
+		mode-bootloader = <0x02>;
+		mode-recovery   = <0x01>;
+	};
+};
+
+&pmm8620au_0 {
+	pmm8620au_0_pon: pon@1200 {
+		compatible = "qcom,pmk8350-pon";
+		reg = <0x1200>, <0x800>;
+		reg-names = "hlos", "pbs";
+	};
+
+	pmm8620au_0_sdam_0: nvram@7100 {
+		compatible = "qcom,spmi-sdam";
+		reg = <0x7100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x7100 0x100>;
+
+		reboot_reason: reboot-reason@48 {
+			reg = <0x48 0x1>;
+			bits = <1 7>;
+		};
+	};
+};

-- 
2.34.1

[PATCH v2 6/7] arm64: dts: monaco-evk: Force vreg_l8a always-on to protect UFS VCC

[Balaji Selvanathan via U-Boot]

vreg_l8a is the shared VCC rail for UFS (ufs_mem_hc vcc-supply) and
eMMC (sdhc_1 vmmc-supply). UFS holds no regulator vote of its own in
U-Boot, so nothing stops other consumers from disabling the rail
while UFS still needs it.

eMMC's power-cycle runs after UFS has already linked up and started
transferring data. Its power-off fires a real disable vote on
vreg_l8a, glitching UFS VCC while the link is live. UFS has no
recovery from this: every following command fails (OCS errors, UTP
timeouts, "Card did not respond to voltage select! : -110").

Force the rail always-on so the disable vote is rejected in
regulator_set_enable() (-EACCES) before it reaches the RPMh driver.
eMMC is non-removable and does not need a real power-cycle.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 arch/arm/dts/monaco-evk-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/monaco-evk-u-boot.dtsi b/arch/arm/dts/monaco-evk-u-boot.dtsi
index 5520d111864..8e9102eae4d 100644
--- a/arch/arm/dts/monaco-evk-u-boot.dtsi
+++ b/arch/arm/dts/monaco-evk-u-boot.dtsi
@@ -34,3 +34,7 @@
 		};
 	};
 };
+
+&vreg_l8a {
+	regulator-always-on;
+};

-- 
2.34.1

[PATCH v2 7/7] configs: qcom_qcs8300: Switch to monaco-evk DT and enable new drivers

[Balaji Selvanathan via U-Boot]

Point qcom_qcs8300_defconfig at the monaco-evk device tree and
turn on required drivers.

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
---
 configs/qcom_qcs8300_defconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/configs/qcom_qcs8300_defconfig b/configs/qcom_qcs8300_defconfig
index 5fffcddc16e..c8c4ccb9ab2 100644
--- a/configs/qcom_qcs8300_defconfig
+++ b/configs/qcom_qcs8300_defconfig
@@ -18,4 +18,8 @@ CONFIG_DEBUG_UART_CLOCK=14745600
 CONFIG_TEXT_BASE=0xaf000000
 CONFIG_REMAKE_ELF=y
 
-CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride"
+CONFIG_DEFAULT_DEVICE_TREE="qcom/monaco-evk"
+CONFIG_PINCTRL_QCOM_QCS8300=y
+CONFIG_INTERCONNECT_QCOM_QCS8300=y
+
+CONFIG_WATCHDOG_AUTOSTART=y

-- 
2.34.1

Re: [PATCH v2 1/7] clk: qcom: Add shared RPMH clock driver for SM8550/SM8650/SA8775P

[Neil Armstrong]

On 8/12/26 03:11, Balaji Selvanathan wrote:
> sa8775p was being handled by the generic clock stub, which just
> no-ops every request. The RPMH_CXO_CLK (bi_tcxo_div2) it exposes is
> identical on SM8550, SM8650 and SA8775P, so rather than bury it in the
> sa8775p GCC driver, add a dedicated standalone RPMH clock driver shared
> by all three SoCs. It reports the fixed CXO rate and accepts no-op
> enable/set_rate requests.
> 
> Monaco-evk also uses the same RPMH clock driver as sa8775p (it's
> rpmhcc DTS node has compatible "qcom,sa8775p-rpmh-clk").
> 
> Drop the sm8550/sm8650/sa8775p rpmh-clk compatibles from the generic
> clock stub now that they are handled by the real driver.
> 
> Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
> ---
>   drivers/clk/clk-stub.c        |  3 ---
>   drivers/clk/qcom/Kconfig      | 12 +++++++++
>   drivers/clk/qcom/Makefile     |  1 +
>   drivers/clk/qcom/clock-rpmh.c | 61 +++++++++++++++++++++++++++++++++++++++++++
>   4 files changed, 74 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c
> index 4a6c71016da..85e54841386 100644
> --- a/drivers/clk/clk-stub.c
> +++ b/drivers/clk/clk-stub.c
> @@ -51,7 +51,6 @@ static struct clk_ops stub_clk_ops = {
>   static const struct udevice_id stub_clk_ids[] = {
>   	{ .compatible = "qcom,qcs615-rpmh-clk" },
>   	{ .compatible = "qcom,rpmcc" },
> -	{ .compatible = "qcom,sa8775p-rpmh-clk" },
>   	{ .compatible = "qcom,sc7180-rpmh-clk" },
>   	{ .compatible = "qcom,sc7280-rpmh-clk" },
>   	{ .compatible = "qcom,sdm670-rpmh-clk" },
> @@ -59,8 +58,6 @@ static const struct udevice_id stub_clk_ids[] = {
>   	{ .compatible = "qcom,sm6350-rpmh-clk" },
>   	{ .compatible = "qcom,sm8150-rpmh-clk" },
>   	{ .compatible = "qcom,sm8250-rpmh-clk" },
> -	{ .compatible = "qcom,sm8550-rpmh-clk" },
> -	{ .compatible = "qcom,sm8650-rpmh-clk" },
>   	{ }
>   };
>   
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9ad233c83ac..8596b93d4c4 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -87,9 +87,19 @@ config CLK_QCOM_QCS8300
>   	  on the Snapdragon QCS8300 SoC. This driver supports the clocks
>   	  and resets exposed by the GCC hardware block.
>   
> +config CLK_QCOM_RPMH
> +	bool "Qualcomm RPMh clock driver"
> +	depends on CLK
> +	help
> +	  Say Y here to enable support for the RPMh-managed clocks found on
> +	  SoCs such as SM8550, SM8650 and SA8775P. These clocks are owned by
> +	  the always-on subsystem; the driver only reports the fixed CXO rate
> +	  (bi_tcxo_div2) and accepts no-op enable/set_rate requests.
> +
>   config CLK_QCOM_SA8775P
>   	bool "Qualcomm SA8775 GCC"
>   	select CLK_QCOM
> +	select CLK_QCOM_RPMH
>   	help
>   	  Say Y here to enable support for the Global Clock Controller
>   	  on the Snapdragon SA8775 SoC. This driver supports the clocks
> @@ -153,6 +163,7 @@ config CLK_QCOM_SM8250
>   config CLK_QCOM_SM8550
>   	bool "Qualcomm SM8550 GCC"
>   	select CLK_QCOM
> +	select CLK_QCOM_RPMH
>   	help
>   	  Say Y here to enable support for the Global Clock Controller
>   	  on the Snapdragon SM8550 SoC. This driver supports the clocks
> @@ -161,6 +172,7 @@ config CLK_QCOM_SM8550
>   config CLK_QCOM_SM8650
>   	bool "Qualcomm SM8650 GCC"
>   	select CLK_QCOM
> +	select CLK_QCOM_RPMH
>   	help
>   	  Say Y here to enable support for the Global Clock Controller
>   	  on the Snapdragon SM8650 SoC. This driver supports the clocks
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index c0d95a6300e..f5630ae0f9c 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_CLK_QCOM_QCM2290) += clock-qcm2290.o
>   obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o
>   obj-$(CONFIG_CLK_QCOM_QCS8300) += clock-qcs8300.o
>   obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o
> +obj-$(CONFIG_CLK_QCOM_RPMH) += clock-rpmh.o
>   obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o
>   obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o
>   obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o
> diff --git a/drivers/clk/qcom/clock-rpmh.c b/drivers/clk/qcom/clock-rpmh.c
> new file mode 100644
> index 00000000000..69f2a751441
> --- /dev/null
> +++ b/drivers/clk/qcom/clock-rpmh.c
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * RPMh clock driver for Qualcomm SoCs
> + *
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +
> +/* On-board TCXO */
> +#define TCXO_RATE	38400000
> +
> +/* bi_tcxo_div2 divided after RPMh output */
> +#define TCXO_DIV2_RATE	(TCXO_RATE / 2)
> +
> +static ulong qcom_rpmh_clk_set_rate(struct clk *clk, ulong rate)
> +{
> +	return (clk->rate = rate);
> +}
> +
> +static ulong qcom_rpmh_clk_get_rate(struct clk *clk)
> +{
> +	ulong cxo_rate = dev_get_driver_data(clk->dev);
> +
> +	switch (clk->id) {
> +	case RPMH_CXO_CLK:
> +		return cxo_rate;
> +	default:
> +		return clk->rate;
> +	}
> +}
> +
> +static int qcom_rpmh_clk_nop(struct clk *clk)
> +{
> +	return 0;
> +}
> +
> +static struct clk_ops qcom_rpmh_clk_ops = {
> +	.set_rate = qcom_rpmh_clk_set_rate,
> +	.get_rate = qcom_rpmh_clk_get_rate,
> +	.enable = qcom_rpmh_clk_nop,
> +	.disable = qcom_rpmh_clk_nop,
> +};
> +
> +static const struct udevice_id qcom_rpmh_clk_ids[] = {
> +	{ .compatible = "qcom,sa8775p-rpmh-clk", .data = TCXO_DIV2_RATE },
> +	{ .compatible = "qcom,sm8550-rpmh-clk", .data = TCXO_DIV2_RATE },
> +	{ .compatible = "qcom,sm8650-rpmh-clk", .data = TCXO_DIV2_RATE },
> +	{ }
> +};
> +
> +U_BOOT_DRIVER(qcom_rpmh_clk) = {
> +	.name		= "qcom_rpmh_clk",
> +	.id		= UCLASS_CLK,
> +	.of_match	= qcom_rpmh_clk_ids,
> +	.ops		= &qcom_rpmh_clk_ops,
> +	.flags		= DM_FLAG_DEFAULT_PD_CTRL_OFF,
> +};
> 

This looks better !

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 0/7] qcom: qcs8300/monaco-evk: pinctrl, interconnect, RPMH clock and reboot-mode support

[Neil Armstrong]

Hi,

On Wed, 12 Aug 2026 06:41:58 +0530, Balaji Selvanathan via U-Boot wrote:
> This series brings up the Monaco (QCS8300) EVK target with a dedicated
> pinctrl driver, interconnect driver, a real sa8775p RPMH clock driver
> (replacing the generic clk-stub no-op), and PON/SDAM-backed reboot-mode
> support so "reboot bootloader" from Linux can be honored by U-Boot.
> qcom_qcs8300_defconfig is switched over to the monaco-evk device tree.
> 
> 
> [...]

Thanks, Applied to https://git.u-boot-project.org/u-boot/custodians/neil.armstrong/u-boot-ufs (main)

[1/7] clk: qcom: Add shared RPMH clock driver for SM8550/SM8650/SA8775P
      (no commit info)
[2/7] clk: qcom: qcs8300: Extend GCC clock driver to full gate/RCG coverage
      (no commit info)
[3/7] pinctrl: qcom: Add QCS8300 pinctrl driver
      (no commit info)
[4/7] interconnect: qcom: Add QCS8300 interconnect driver
      https://git.u-boot-project.org/u-boot/custodians/neil.armstrong/u-boot-ufs/-/commit/9db5fb79c2630e9b4fcb0d17dd8b5f383c783cfb
[5/7] arm64: dts: monaco-evk: Add reboot-mode support via PON/SDAM
      (no commit info)
[6/7] arm64: dts: monaco-evk: Force vreg_l8a always-on to protect UFS VCC
      (no commit info)
[7/7] configs: qcom_qcs8300: Switch to monaco-evk DT and enable new drivers
      (no commit info)

-- 
Neil

Re: [PATCH v2 2/7] clk: qcom: qcs8300: Extend GCC clock driver to full gate/RCG coverage

[Sumit Garg]

On Wed, 12 Aug 2026 at 06:42:00 +0530, Balaji Selvanathan wrote:
>Extend the QCS8300 GCC driver with the remaining RCGs (USB2/USB3,
>UFS PHY, SDCC1, QUPv3 wrap0/wrap1/wrap3 SE clocks, GP1-5, PDM2,
>EMAC0, PCIe0/1) and their gate clocks.
>
>Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>---
> drivers/clk/qcom/clock-qcs8300.c | 545 +++++++++++++++++++++++++++++++++++++--
> 1 file changed, 525 insertions(+), 20 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

>diff --git a/drivers/clk/qcom/clock-qcs8300.c b/drivers/clk/qcom/clock-qcs8300.c
>index cd8aecdf788..cd47b384f1f 100644
>--- a/drivers/clk/qcom/clock-qcs8300.c
>+++ b/drivers/clk/qcom/clock-qcs8300.c
>@@ -14,12 +14,210 @@
> #include <dt-bindings/clock/qcom,qcs8300-gcc.h>
> #include "clock-qcom.h"
>
>-#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
>-#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
>+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR	0x1b040
>+#define USB30_PRIM_MASTER_CLK_CMD_RCGR		0x1b028
>+#define USB3_PRIM_PHY_AUX_CMD_RCGR		0x1b06c
>+#define USB20_MASTER_CLK_CMD_RCGR		0x1c028
>+#define USB20_MOCK_UTMI_CLK_CMD_RCGR		0x1c040
>+
>+#define UFS_PHY_AXI_CLK_CMD_RCGR		0x8302c
>+#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR		0x83074
>+#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR		0x830a8
>+#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR	0x8308c
>+
>+#define SDCC1_APPS_CLK_CMD_RCGR			0x20014
>+#define SDCC1_ICE_CORE_CLK_CMD_RCGR		0x2002c
>+
>+#define QUPV3_WRAP0_S0_CLK_CMD_RCGR		0x23154
>+#define QUPV3_WRAP0_S1_CLK_CMD_RCGR		0x23288
>+#define QUPV3_WRAP0_S2_CLK_CMD_RCGR		0x233bc
>+#define QUPV3_WRAP0_S3_CLK_CMD_RCGR		0x234f0
>+#define QUPV3_WRAP0_S4_CLK_CMD_RCGR		0x23624
>+#define QUPV3_WRAP0_S5_CLK_CMD_RCGR		0x23758
>+#define QUPV3_WRAP0_S6_CLK_CMD_RCGR		0x2388c
>+#define QUPV3_WRAP0_S7_CLK_CMD_RCGR		0x239c0
>+#define QUPV3_WRAP1_S0_CLK_CMD_RCGR		0x24154
>+#define QUPV3_WRAP1_S1_CLK_CMD_RCGR		0x24288
>+#define QUPV3_WRAP1_S2_CLK_CMD_RCGR		0x243bc
>+#define QUPV3_WRAP1_S3_CLK_CMD_RCGR		0x244f0
>+#define QUPV3_WRAP1_S4_CLK_CMD_RCGR		0x24624
>+#define QUPV3_WRAP1_S5_CLK_CMD_RCGR		0x24758
>+#define QUPV3_WRAP1_S6_CLK_CMD_RCGR		0x2488c
>+#define QUPV3_WRAP1_S7_CLK_CMD_RCGR		0x249c0
>+#define QUPV3_WRAP3_S0_CLK_CMD_RCGR		0xc4158
>+
>+#define GP1_CLK_CMD_RCGR			0x70004
>+#define GP2_CLK_CMD_RCGR			0x71004
>+#define GP3_CLK_CMD_RCGR			0x62004
>+#define GP4_CLK_CMD_RCGR			0x1e004
>+#define GP5_CLK_CMD_RCGR			0x1f004
>+
>+#define PDM2_CLK_CMD_RCGR			0x3f010
>+
>+#define EMAC0_PHY_AUX_CLK_CMD_RCGR		0xb6028
>+#define EMAC0_PTP_CLK_CMD_RCGR			0xb6060
>+#define EMAC0_RGMII_CLK_CMD_RCGR		0xb6048
>+
>+#define PCIE_0_AUX_CLK_CMD_RCGR			0xa9078
>+#define PCIE_0_PHY_RCHNG_CLK_CMD_RCGR		0xa9054
>+#define PCIE_1_AUX_CLK_CMD_RCGR			0x77078
>+#define PCIE_1_PHY_RCHNG_CLK_CMD_RCGR		0x77054
>+
>+#define CFG_CLK_SRC_GPLL4_UFS_ICE_CORE		(3 << 8)
>+#define CFG_CLK_SRC_GPLL7_EMAC0			(2 << 8)
>+
>+static struct pll_vote_clk gpll4_vote_clk = {
>+	.status = 0x4000,
>+	.status_bit = BIT(31),
>+	.ena_vote = 0x4b028,
>+	.vote_bit = BIT(4),
>+};
>+
>+static struct pll_vote_clk gpll7_vote_clk = {
>+	.status = 0x7000,
>+	.status_bit = BIT(31),
>+	.ena_vote = 0x4b028,
>+	.vote_bit = BIT(7),
>+};
>+
>+static struct pll_vote_clk gpll9_vote_clk = {
>+	.status = 0x9000,
>+	.status_bit = BIT(31),
>+	.ena_vote = 0x4b028,
>+	.vote_bit = BIT(9),
>+};
>+
>+static const struct freq_tbl ftbl_gcc_qupv3_wrap_s0_clk_src[] = {
>+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
>+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
>+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
>+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
>+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
>+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
>+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
>+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
>+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
>+	F(120000000, CFG_CLK_SRC_GPLL0, 5, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_qupv3_wrap_s2_clk_src[] = {
>+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
>+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
>+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
>+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
>+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
>+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
>+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
>+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
>+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
>+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_qupv3_wrap3_s0_clk_src[] = {
>+	F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
>+	F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
>+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
>+	F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
>+	F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
>+	F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
>+	F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
>+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
>+	F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
>+	F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
>+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
>+	F(403200000, CFG_CLK_SRC_GPLL4, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_gp_clk_src[] = {
>+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
>+	F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
>+	F(60000000, CFG_CLK_SRC_GPLL0, 10, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_emac0_ptp_clk_src[] = {
>+	F(125000000, CFG_CLK_SRC_GPLL7_EMAC0, 8, 0, 0),
>+	F(230400000, CFG_CLK_SRC_GPLL4, 3.5, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_emac0_rgmii_clk_src[] = {
>+	F(5000000, CFG_CLK_SRC_GPLL0_EVEN, 10, 1, 6),
>+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
>+	F(125000000, CFG_CLK_SRC_GPLL7_EMAC0, 8, 0, 0),
>+	F(250000000, CFG_CLK_SRC_GPLL7_EMAC0, 4, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
>+	F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
>+	F(144000, CFG_CLK_SRC_CXO, 16, 3, 25),
>+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
>+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
>+	F(20000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 1, 3),
>+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
>+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
>+	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
>+	F(192000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
>+	F(384000000, CFG_CLK_SRC_GPLL9, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
>+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
>+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
>+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
>+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
>+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
>+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
>+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
>+	F(201600000, CFG_CLK_SRC_GPLL4_UFS_ICE_CORE, 4, 0, 0),
>+	F(403200000, CFG_CLK_SRC_GPLL4_UFS_ICE_CORE, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
>+	F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0),
>+	F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0),
>+	F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_usb20_master_clk_src[] = {
>+	F(120000000, CFG_CLK_SRC_GPLL0, 5, 0, 0),
>+	{ }
>+};
>+
>+static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
>+	F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
>+	F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0),
>+	F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
>+	{ }
>+};
>
> static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
> {
> 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
>+	const struct freq_tbl *freq;
>
> 	if (clk->id < priv->data->num_clks)
> 		debug("%s: %s, requested rate=%ld\n",
>@@ -31,28 +229,315 @@ static ulong qcs8300_set_rate(struct clk *clk, ulong rate)
> 		clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> 		return rate;
> 	case GCC_USB30_PRIM_MASTER_CLK:
>-		WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
>+		freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
> 		clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
>-				     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
>-		clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
>+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
>+		clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0);
>+		return freq->freq;
>+	case GCC_USB20_MASTER_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_usb20_master_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, USB20_MASTER_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
>+		return freq->freq;
>+	case GCC_USB20_MOCK_UTMI_CLK:
>+		WARN(rate != 19200000, "Unexpected rate for USB20_MOCK_UTMI_CLK: %lu\n", rate);
>+		clk_rcg_set_rate(priv->base, USB20_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
> 		return rate;
>+	case GCC_UFS_PHY_AXI_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
>+		return freq->freq;
>+	case GCC_UFS_PHY_UNIPRO_CORE_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
>+				 freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_UFS_PHY_ICE_CORE_CLK:
>+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
>+		freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR,
>+				 freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_UFS_PHY_PHY_AUX_CLK:
>+		clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
>+		return 19200000;
>+	case GCC_SDCC1_APPS_CLK:
>+		clk_enable_gpll0(priv->base, &gpll9_vote_clk);
>+		freq = qcom_find_freq(ftbl_gcc_sdcc1_apps_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, SDCC1_APPS_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
>+		return freq->freq;
>+	case GCC_SDCC1_ICE_CORE_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_sdcc1_ice_core_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, SDCC1_ICE_CORE_CLK_CMD_RCGR,
>+				 freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S0_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S0_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S1_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S1_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S2_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S2_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S3_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S3_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S4_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S5_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S5_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S6_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S6_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP0_S7_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S7_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S0_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S0_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S1_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s0_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S1_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S2_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S2_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S3_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S3_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S4_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S4_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S5_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S5_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S6_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S6_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP1_S7_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap_s2_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP1_S7_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_QUPV3_WRAP3_S0_CLK:
>+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
>+		freq = qcom_find_freq(ftbl_gcc_qupv3_wrap3_s0_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP3_S0_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_GP1_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, GP1_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_GP2_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, GP2_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_GP3_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, GP3_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_GP4_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, GP4_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_GP5_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_gp_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, GP5_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_PDM2_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_pdm2_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, PDM2_CLK_CMD_RCGR, freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_EMAC0_PHY_AUX_CLK:
>+		clk_rcg_set_rate(priv->base, EMAC0_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
>+		return 19200000;
>+	case GCC_EMAC0_PTP_CLK:
>+		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
>+		clk_enable_gpll0(priv->base, &gpll4_vote_clk);
>+		freq = qcom_find_freq(ftbl_gcc_emac0_ptp_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, EMAC0_PTP_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_EMAC0_RGMII_CLK:
>+		clk_enable_gpll0(priv->base, &gpll7_vote_clk);
>+		freq = qcom_find_freq(ftbl_gcc_emac0_rgmii_clk_src, rate);
>+		clk_rcg_set_rate_mnd(priv->base, EMAC0_RGMII_CLK_CMD_RCGR,
>+				     freq->pre_div, freq->m, freq->n, freq->src, 16);
>+		return freq->freq;
>+	case GCC_PCIE_0_AUX_CLK:
>+		clk_rcg_set_rate(priv->base, PCIE_0_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
>+		return 19200000;
>+	case GCC_PCIE_0_PHY_RCHNG_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, PCIE_0_PHY_RCHNG_CLK_CMD_RCGR,
>+				 freq->pre_div, freq->src);
>+		return freq->freq;
>+	case GCC_PCIE_1_AUX_CLK:
>+		clk_rcg_set_rate(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
>+		return 19200000;
>+	case GCC_PCIE_1_PHY_RCHNG_CLK:
>+		freq = qcom_find_freq(ftbl_gcc_pcie_0_phy_rchng_clk_src, rate);
>+		clk_rcg_set_rate(priv->base, PCIE_1_PHY_RCHNG_CLK_CMD_RCGR,
>+				 freq->pre_div, freq->src);
>+		return freq->freq;
> 	default:
> 		return 0;
> 	}
> }
>
> static const struct gate_clk qcs8300_clks[] = {
>-	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0)),
>-	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0)),
>-	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0)),
>-	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0)),
>-	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0)),
>-	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0)),
>-	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0)),
>-	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0)),
>-	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0)),
>-	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0)),
>-	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0)),
>+	GATE_CLK_POLLED(GCC_AGGRE_NOC_QUPV3_AXI_CLK, 0x4b000, BIT(28), 0x8e200),
>+	GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, BIT(0), 0x830d4),
>+	GATE_CLK_POLLED(GCC_AGGRE_USB2_PRIM_AXI_CLK, 0x1c05c, BIT(0), 0x1c05c),
>+	GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, BIT(0), 0x1b084),
>+	GATE_CLK_POLLED(GCC_AHB2PHY0_CLK, 0x76004, BIT(0), 0x76004),
>+	GATE_CLK_POLLED(GCC_AHB2PHY2_CLK, 0x76008, BIT(0), 0x76008),
>+	GATE_CLK_POLLED(GCC_AHB2PHY3_CLK, 0x7600c, BIT(0), 0x7600c),
>+	GATE_CLK_POLLED(GCC_BOOT_ROM_AHB_CLK, 0x4b000, BIT(10), 0x44004),
>+	GATE_CLK(GCC_CAMERA_HF_AXI_CLK, 0x32010, BIT(0)),
>+	GATE_CLK(GCC_CAMERA_SF_AXI_CLK, 0x32018, BIT(0)),
>+	GATE_CLK_POLLED(GCC_CAMERA_THROTTLE_XO_CLK, 0x32024, BIT(0), 0x32024),
>+	GATE_CLK_POLLED(GCC_CFG_NOC_USB2_PRIM_AXI_CLK, 0x1c060, BIT(0), 0x1c060),
>+	GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, BIT(0), 0x1b088),
>+	GATE_CLK_POLLED(GCC_DDRSS_GPU_AXI_CLK, 0x7d164, BIT(0), 0x7d164),
>+	GATE_CLK_POLLED(GCC_DISP_HF_AXI_CLK, 0x33010, BIT(0), 0x33010),
>+	GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, BIT(0)),
>+	GATE_CLK_POLLED(GCC_EMAC0_AXI_CLK, 0xb6018, BIT(0), 0xb6018),
>+	GATE_CLK_POLLED(GCC_EMAC0_PHY_AUX_CLK, 0xb6024, BIT(0), 0xb6024),
>+	GATE_CLK_POLLED(GCC_EMAC0_PTP_CLK, 0xb6040, BIT(0), 0xb6040),
>+	GATE_CLK_POLLED(GCC_EMAC0_RGMII_CLK, 0xb6044, BIT(0), 0xb6044),
>+	GATE_CLK_POLLED(GCC_EMAC0_SLV_AHB_CLK, 0xb6020, BIT(0), 0xb6020),
>+	GATE_CLK_POLLED(GCC_GP1_CLK, 0x70000, BIT(0), 0x70000),
>+	GATE_CLK_POLLED(GCC_GP2_CLK, 0x71000, BIT(0), 0x71000),
>+	GATE_CLK_POLLED(GCC_GP3_CLK, 0x62000, BIT(0), 0x62000),
>+	GATE_CLK_POLLED(GCC_GP4_CLK, 0x1e000, BIT(0), 0x1e000),
>+	GATE_CLK_POLLED(GCC_GP5_CLK, 0x1f000, BIT(0), 0x1f000),
>+	GATE_CLK(GCC_GPU_GPLL0_CLK_SRC, 0x4b000, BIT(15)),
>+	GATE_CLK(GCC_GPU_GPLL0_DIV_CLK_SRC, 0x4b000, BIT(16)),
>+	GATE_CLK_POLLED(GCC_GPU_MEMNOC_GFX_CENTER_PIPELINE_CLK, 0x7d160, BIT(0), 0x7d160),
>+	GATE_CLK_POLLED(GCC_GPU_MEMNOC_GFX_CLK, 0x7d010, BIT(0), 0x7d010),
>+	GATE_CLK(GCC_GPU_SNOC_DVM_GFX_CLK, 0x7d01c, BIT(0)),
>+	GATE_CLK_POLLED(GCC_GPU_TCU_THROTTLE_AHB_CLK, 0x7d008, BIT(0), 0x7d008),
>+	GATE_CLK_POLLED(GCC_GPU_TCU_THROTTLE_CLK, 0x7d014, BIT(0), 0x7d014),
>+	GATE_CLK_POLLED(GCC_PCIE_0_AUX_CLK, 0x4b010, BIT(16), 0xa9038),
>+	GATE_CLK_POLLED(GCC_PCIE_0_CFG_AHB_CLK, 0x4b010, BIT(12), 0xa902c),
>+	GATE_CLK_POLLED(GCC_PCIE_0_MSTR_AXI_CLK, 0x4b010, BIT(11), 0xa9024),
>+	GATE_CLK_POLLED(GCC_PCIE_0_PHY_AUX_CLK, 0x4b010, BIT(13), 0xa9030),
>+	GATE_CLK_POLLED(GCC_PCIE_0_PHY_RCHNG_CLK, 0x4b010, BIT(15), 0xa9050),
>+	GATE_CLK(GCC_PCIE_0_PIPE_CLK, 0x4b010, BIT(14)),
>+	GATE_CLK(GCC_PCIE_0_PIPEDIV2_CLK, 0x4b018, BIT(22)),
>+	GATE_CLK_POLLED(GCC_PCIE_0_SLV_AXI_CLK, 0x4b010, BIT(10), 0xa901c),
>+	GATE_CLK_POLLED(GCC_PCIE_0_SLV_Q2A_AXI_CLK, 0x4b018, BIT(12), 0xa9018),
>+	GATE_CLK_POLLED(GCC_PCIE_1_AUX_CLK, 0x4b000, BIT(31), 0x77038),
>+	GATE_CLK_POLLED(GCC_PCIE_1_CFG_AHB_CLK, 0x4b008, BIT(2), 0x7702c),
>+	GATE_CLK_POLLED(GCC_PCIE_1_MSTR_AXI_CLK, 0x4b008, BIT(1), 0x77024),
>+	GATE_CLK_POLLED(GCC_PCIE_1_PHY_AUX_CLK, 0x4b008, BIT(3), 0x77030),
>+	GATE_CLK_POLLED(GCC_PCIE_1_PHY_RCHNG_CLK, 0x4b000, BIT(22), 0x77050),
>+	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x4b008, BIT(4)),
>+	GATE_CLK(GCC_PCIE_1_PIPEDIV2_CLK, 0x4b018, BIT(16)),
>+	GATE_CLK_POLLED(GCC_PCIE_1_SLV_AXI_CLK, 0x4b008, BIT(0), 0x7701c),
>+	GATE_CLK_POLLED(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x4b008, BIT(5), 0x77018),
>+	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x9746c, BIT(0)),
>+	GATE_CLK_POLLED(GCC_PCIE_THROTTLE_CFG_CLK, 0x4b020, BIT(15), 0xb2034),
>+	GATE_CLK_POLLED(GCC_PDM2_CLK, 0x3f00c, BIT(0), 0x3f00c),
>+	GATE_CLK_POLLED(GCC_PDM_AHB_CLK, 0x3f004, BIT(0), 0x3f004),
>+	GATE_CLK_POLLED(GCC_PDM_XO4_CLK, 0x3f008, BIT(0), 0x3f008),
>+	GATE_CLK_POLLED(GCC_QMIP_CAMERA_NRT_AHB_CLK, 0x32008, BIT(0), 0x32008),
>+	GATE_CLK_POLLED(GCC_QMIP_CAMERA_RT_AHB_CLK, 0x3200c, BIT(0), 0x3200c),
>+	GATE_CLK_POLLED(GCC_QMIP_DISP_AHB_CLK, 0x33008, BIT(0), 0x33008),
>+	GATE_CLK_POLLED(GCC_QMIP_DISP_ROT_AHB_CLK, 0x3300c, BIT(0), 0x3300c),
>+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_CVP_AHB_CLK, 0x34008, BIT(0), 0x34008),
>+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_VCODEC_AHB_CLK, 0x3400c, BIT(0), 0x3400c),
>+	GATE_CLK_POLLED(GCC_QMIP_VIDEO_VCPU_AHB_CLK, 0x34010, BIT(0), 0x34010),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x4b008, BIT(9), 0x23018),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_CORE_CLK, 0x4b008, BIT(8), 0x2300c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S0_CLK, 0x4b008, BIT(10), 0x2314c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S1_CLK, 0x4b008, BIT(11), 0x23280),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S2_CLK, 0x4b008, BIT(12), 0x233b4),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S3_CLK, 0x4b008, BIT(13), 0x234e8),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S4_CLK, 0x4b008, BIT(14), 0x2361c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S5_CLK, 0x4b008, BIT(15), 0x23750),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S6_CLK, 0x4b008, BIT(16), 0x23884),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP0_S7_CLK, 0x4b008, BIT(17), 0x239b8),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_2X_CLK, 0x4b008, BIT(18), 0x24018),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_CORE_CLK, 0x4b008, BIT(19), 0x2400c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S0_CLK, 0x4b008, BIT(22), 0x2414c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S1_CLK, 0x4b008, BIT(23), 0x24280),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S2_CLK, 0x4b008, BIT(24), 0x243b4),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S3_CLK, 0x4b008, BIT(25), 0x244e8),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S4_CLK, 0x4b008, BIT(26), 0x2461c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S5_CLK, 0x4b008, BIT(27), 0x24750),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S6_CLK, 0x4b018, BIT(27), 0x24884),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP1_S7_CLK, 0x4b018, BIT(28), 0x249b8),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_2X_CLK, 0x4b000, BIT(24), 0xc4018),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_CORE_CLK, 0x4b000, BIT(23), 0xc400c),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_QSPI_CLK, 0x4b000, BIT(26), 0xc4284),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, BIT(25), 0xc4150),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x4b008, BIT(6), 0x23004),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x4b008, BIT(7), 0x23008),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x4b008, BIT(20), 0x24004),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x4b008, BIT(21), 0x24008),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_M_AHB_CLK, 0x4b000, BIT(27), 0xc4004),
>+	GATE_CLK_POLLED(GCC_QUPV3_WRAP_3_S_AHB_CLK, 0x4b000, BIT(20), 0xc4008),
>+	GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK, 0x2000c, BIT(0), 0x2000c),
>+	GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x20004, BIT(0), 0x20004),
>+	GATE_CLK_POLLED(GCC_SDCC1_ICE_CORE_CLK, 0x20044, BIT(0), 0x20044),
>+	GATE_CLK(GCC_SGMI_CLKREF_EN, 0x97034, BIT(0)),
>+	GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x83020, BIT(0), 0x83020),
>+	GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x83018, BIT(0), 0x83018),
>+	GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, BIT(0), 0x8306c),
>+	GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, BIT(0), 0x830a4),
>+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, BIT(0)),
>+	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, BIT(0)),
>+	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, BIT(0)),
>+	GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, BIT(0), 0x83064),
>+	GATE_CLK_POLLED(GCC_USB20_MASTER_CLK, 0x1c018, BIT(0), 0x1c018),
>+	GATE_CLK_POLLED(GCC_USB20_MOCK_UTMI_CLK, 0x1c024, BIT(0), 0x1c024),
>+	GATE_CLK_POLLED(GCC_USB20_SLEEP_CLK, 0x1c020, BIT(0), 0x1c020),
>+	GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, BIT(0), 0x1b018),
>+	GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, BIT(0), 0x1b024),
>+	GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, BIT(0), 0x1b020),
>+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, BIT(0), 0x1b05c),
>+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, BIT(0), 0x1b060),
>+	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1b064, BIT(0)),
>+	GATE_CLK(GCC_USB_CLKREF_EN, 0x97468, BIT(0)),
>+	GATE_CLK_POLLED(GCC_VIDEO_AXI0_CLK, 0x34014, BIT(0), 0x34014),
>+	GATE_CLK_POLLED(GCC_VIDEO_AXI1_CLK, 0x3401c, BIT(0), 0x3401c),
> };
>
> static int qcs8300_enable(struct clk *clk)
>@@ -74,11 +559,27 @@ static int qcs8300_enable(struct clk *clk)
> 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
> 		qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
> 		break;
>+	case GCC_QUPV3_WRAP0_S0_CLK ... GCC_QUPV3_WRAP0_S7_CLK:
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_0_M_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_0_S_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP0_CORE_2X_CLK);
>+		break;
>+	case GCC_QUPV3_WRAP1_S0_CLK ... GCC_QUPV3_WRAP1_S7_CLK:
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_1_M_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_1_S_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP1_CORE_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP1_CORE_2X_CLK);
>+		break;
>+	case GCC_QUPV3_WRAP3_S0_CLK:
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_3_M_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP_3_S_AHB_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP3_CORE_CLK);
>+		qcom_gate_clk_en(priv, GCC_QUPV3_WRAP3_CORE_2X_CLK);
>+		break;
> 	}
>
>-	qcom_gate_clk_en(priv, clk->id);
>-
>-	return 0;
>+	return qcom_gate_clk_en(priv, clk->id);
> }
>
> static const struct qcom_reset_map qcs8300_gcc_resets[] = {
>@@ -112,8 +613,12 @@ static const struct qcom_reset_map qcs8300_gcc_resets[] = {
> };
>
> static const struct qcom_power_map qcs8300_gdscs[] = {
>+	[GCC_EMAC0_GDSC] = { 0xb6004 },
>+	[GCC_PCIE_0_GDSC] = { 0xa9004 },
>+	[GCC_PCIE_1_GDSC] = { 0x77004 },
> 	[GCC_UFS_PHY_GDSC] = { 0x83004 },
>-	[GCC_USB30_PRIM_GDSC] = { 0x1B004 },
>+	[GCC_USB20_PRIM_GDSC] = { 0x1c004 },
>+	[GCC_USB30_PRIM_GDSC] = { 0x1b004 },
> };
>
> static struct msm_clk_data qcs8300_gcc_data = {
>
>-- 
>2.34.1
>

Re: [PATCH v2 3/7] pinctrl: qcom: Add QCS8300 pinctrl driver

[Sumit Garg]

On Wed, 12 Aug 2026 at 06:42:01 +0530, Balaji Selvanathan wrote:
>Add pinctrl support for QCS8300.
>
>Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>---
> drivers/pinctrl/qcom/Kconfig           |   8 +
> drivers/pinctrl/qcom/Makefile          |   1 +
> drivers/pinctrl/qcom/pinctrl-qcs8300.c | 468 +++++++++++++++++++++++++++++++++
> 3 files changed, 477 insertions(+)

Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

-Sumit

>
>diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>index 0bea461fcc3..2af71945c4d 100644
>--- a/drivers/pinctrl/qcom/Kconfig
>+++ b/drivers/pinctrl/qcom/Kconfig
>@@ -86,6 +86,14 @@ config PINCTRL_QCOM_QCS615
> 	  Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC,
> 	  as well as the associated GPIO driver.
>
>+config PINCTRL_QCOM_QCS8300
>+	bool "Qualcomm QCS8300 Pinctrl"
>+	default y if PINCTRL_QCOM_GENERIC
>+	select PINCTRL_QCOM
>+	help
>+	  Say Y here to enable support for pinctrl on the Snapdragon QCS8300 SoC,
>+	  as well as the associated GPIO driver.
>+
> config PINCTRL_QCOM_SA8775P
> 	bool "Qualcomm SA8775P Pinctrl"
> 	default y if PINCTRL_QCOM_GENERIC
>diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
>index 87cb128c4d4..e10fbc3d3ec 100644
>--- a/drivers/pinctrl/qcom/Makefile
>+++ b/drivers/pinctrl/qcom/Makefile
>@@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_QCOM_MILOS) += pinctrl-milos.o
> obj-$(CONFIG_PINCTRL_QCOM_QCM2290) += pinctrl-qcm2290.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o
> obj-$(CONFIG_PINCTRL_QCOM_QCS615) += pinctrl-qcs615.o
>+obj-$(CONFIG_PINCTRL_QCOM_QCS8300) += pinctrl-qcs8300.o
> obj-$(CONFIG_PINCTRL_QCOM_SA8775P) += pinctrl-sa8775p.o
> obj-$(CONFIG_PINCTRL_QCOM_SC7280) += pinctrl-sc7280.o
> obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o
>diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
>new file mode 100644
>index 00000000000..91f7c4fcf1e
>--- /dev/null
>+++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c
>@@ -0,0 +1,468 @@
>+// SPDX-License-Identifier: GPL-2.0-only
>+/*
>+ * Qualcomm QCS8300 pinctrl
>+ *
>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>+ *
>+ */
>+
>+#include <dm.h>
>+
>+#include "pinctrl-qcom.h"
>+
>+#define MAX_PIN_NAME_LEN 32
>+#define MSM_PIN_FUNCTION_COUNT 12
>+
>+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
>+
>+typedef unsigned int msm_pin_function[MSM_PIN_FUNCTION_COUNT];
>+
>+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11)\
>+	{\
>+		msm_mux_gpio, /* gpio mode */\
>+		msm_mux_##f1,\
>+		msm_mux_##f2,\
>+		msm_mux_##f3,\
>+		msm_mux_##f4,\
>+		msm_mux_##f5,\
>+		msm_mux_##f6,\
>+		msm_mux_##f7,\
>+		msm_mux_##f8,\
>+		msm_mux_##f9,\
>+		msm_mux_##f10,\
>+		msm_mux_##f11 /* egpio mode */\
>+	}
>+
>+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)\
>+	{\
>+		.name = pg_name,\
>+		.ctl_reg = ctl,\
>+		.io_reg = 0,\
>+		.pull_bit = pull,\
>+		.drv_bit = drv,\
>+		.oe_bit = -1,\
>+		.in_bit = -1,\
>+		.out_bit = -1,\
>+	}
>+
>+#define UFS_RESET(pg_name, ctl)\
>+	{\
>+		.name = pg_name,\
>+		.ctl_reg = ctl,\
>+		.io_reg = ctl + 0x4,\
>+		.pull_bit = 3,\
>+		.drv_bit = 0,\
>+		.oe_bit = -1,\
>+		.in_bit = -1,\
>+		.out_bit = 0,\
>+	}
>+
>+enum qcs8300_functions {
>+	msm_mux_gpio,
>+	msm_mux_aoss_cti,
>+	msm_mux_atest_char,
>+	msm_mux_atest_usb2,
>+	msm_mux_audio_ref,
>+	msm_mux_cam_mclk,
>+	msm_mux_cci_async,
>+	msm_mux_cci_i2c_scl,
>+	msm_mux_cci_i2c_sda,
>+	msm_mux_cci_timer,
>+	msm_mux_cri_trng,
>+	msm_mux_dbg_out,
>+	msm_mux_ddr_bist,
>+	msm_mux_ddr_pxi0,
>+	msm_mux_ddr_pxi1,
>+	msm_mux_ddr_pxi2,
>+	msm_mux_ddr_pxi3,
>+	msm_mux_edp0_hot,
>+	msm_mux_edp0_lcd,
>+	msm_mux_edp1_lcd,
>+	msm_mux_egpio,
>+	msm_mux_emac0_mcg0,
>+	msm_mux_emac0_mcg1,
>+	msm_mux_emac0_mcg2,
>+	msm_mux_emac0_mcg3,
>+	msm_mux_emac0_mdc,
>+	msm_mux_emac0_mdio,
>+	msm_mux_emac0_ptp_aux,
>+	msm_mux_emac0_ptp_pps,
>+	msm_mux_gcc_gp1,
>+	msm_mux_gcc_gp2,
>+	msm_mux_gcc_gp3,
>+	msm_mux_gcc_gp4,
>+	msm_mux_gcc_gp5,
>+	msm_mux_hs0_mi2s,
>+	msm_mux_hs1_mi2s,
>+	msm_mux_hs2_mi2s,
>+	msm_mux_ibi_i3c,
>+	msm_mux_jitter_bist,
>+	msm_mux_mdp0_vsync0,
>+	msm_mux_mdp0_vsync1,
>+	msm_mux_mdp0_vsync3,
>+	msm_mux_mdp0_vsync6,
>+	msm_mux_mdp0_vsync7,
>+	msm_mux_mdp_vsync,
>+	msm_mux_mi2s1_data0,
>+	msm_mux_mi2s1_data1,
>+	msm_mux_mi2s1_sck,
>+	msm_mux_mi2s1_ws,
>+	msm_mux_mi2s2_data0,
>+	msm_mux_mi2s2_data1,
>+	msm_mux_mi2s2_sck,
>+	msm_mux_mi2s2_ws,
>+	msm_mux_mi2s_mclk0,
>+	msm_mux_mi2s_mclk1,
>+	msm_mux_pcie0_clkreq,
>+	msm_mux_pcie1_clkreq,
>+	msm_mux_phase_flag,
>+	msm_mux_pll_bist,
>+	msm_mux_pll_clk,
>+	msm_mux_prng_rosc0,
>+	msm_mux_prng_rosc1,
>+	msm_mux_prng_rosc2,
>+	msm_mux_prng_rosc3,
>+	msm_mux_qdss_cti,
>+	msm_mux_qdss_gpio,
>+	msm_mux_qup0_se0,
>+	msm_mux_qup0_se1,
>+	msm_mux_qup0_se2,
>+	msm_mux_qup0_se3,
>+	msm_mux_qup0_se4,
>+	msm_mux_qup0_se5,
>+	msm_mux_qup0_se6,
>+	msm_mux_qup0_se7,
>+	msm_mux_qup1_se0,
>+	msm_mux_qup1_se1,
>+	msm_mux_qup1_se2,
>+	msm_mux_qup1_se3,
>+	msm_mux_qup1_se4,
>+	msm_mux_qup1_se5,
>+	msm_mux_qup1_se6,
>+	msm_mux_qup1_se7,
>+	msm_mux_qup2_se0,
>+	msm_mux_sailss_emac0,
>+	msm_mux_sailss_ospi,
>+	msm_mux_sgmii_phy,
>+	msm_mux_tb_trig,
>+	msm_mux_tgu_ch0,
>+	msm_mux_tgu_ch1,
>+	msm_mux_tgu_ch2,
>+	msm_mux_tgu_ch3,
>+	msm_mux_tsense_pwm1,
>+	msm_mux_tsense_pwm2,
>+	msm_mux_tsense_pwm3,
>+	msm_mux_tsense_pwm4,
>+	msm_mux_usb2phy_ac,
>+	msm_mux_vsense_trigger,
>+	msm_mux__,
>+};
>+
>+#define MSM_PIN_FUNCTION(fname)\
>+	[msm_mux_##fname] = {#fname, msm_mux_##fname}
>+
>+static const struct pinctrl_function msm_pinctrl_functions[] = {
>+	MSM_PIN_FUNCTION(gpio),
>+	MSM_PIN_FUNCTION(aoss_cti),
>+	MSM_PIN_FUNCTION(atest_char),
>+	MSM_PIN_FUNCTION(atest_usb2),
>+	MSM_PIN_FUNCTION(audio_ref),
>+	MSM_PIN_FUNCTION(cam_mclk),
>+	MSM_PIN_FUNCTION(cci_async),
>+	MSM_PIN_FUNCTION(cci_i2c_scl),
>+	MSM_PIN_FUNCTION(cci_i2c_sda),
>+	MSM_PIN_FUNCTION(cci_timer),
>+	MSM_PIN_FUNCTION(cri_trng),
>+	MSM_PIN_FUNCTION(dbg_out),
>+	MSM_PIN_FUNCTION(ddr_bist),
>+	MSM_PIN_FUNCTION(ddr_pxi0),
>+	MSM_PIN_FUNCTION(ddr_pxi1),
>+	MSM_PIN_FUNCTION(ddr_pxi2),
>+	MSM_PIN_FUNCTION(ddr_pxi3),
>+	MSM_PIN_FUNCTION(edp0_hot),
>+	MSM_PIN_FUNCTION(edp0_lcd),
>+	MSM_PIN_FUNCTION(edp1_lcd),
>+	MSM_PIN_FUNCTION(egpio),
>+	MSM_PIN_FUNCTION(emac0_mcg0),
>+	MSM_PIN_FUNCTION(emac0_mcg1),
>+	MSM_PIN_FUNCTION(emac0_mcg2),
>+	MSM_PIN_FUNCTION(emac0_mcg3),
>+	MSM_PIN_FUNCTION(emac0_mdc),
>+	MSM_PIN_FUNCTION(emac0_mdio),
>+	MSM_PIN_FUNCTION(emac0_ptp_aux),
>+	MSM_PIN_FUNCTION(emac0_ptp_pps),
>+	MSM_PIN_FUNCTION(gcc_gp1),
>+	MSM_PIN_FUNCTION(gcc_gp2),
>+	MSM_PIN_FUNCTION(gcc_gp3),
>+	MSM_PIN_FUNCTION(gcc_gp4),
>+	MSM_PIN_FUNCTION(gcc_gp5),
>+	MSM_PIN_FUNCTION(hs0_mi2s),
>+	MSM_PIN_FUNCTION(hs1_mi2s),
>+	MSM_PIN_FUNCTION(hs2_mi2s),
>+	MSM_PIN_FUNCTION(ibi_i3c),
>+	MSM_PIN_FUNCTION(jitter_bist),
>+	MSM_PIN_FUNCTION(mdp0_vsync0),
>+	MSM_PIN_FUNCTION(mdp0_vsync1),
>+	MSM_PIN_FUNCTION(mdp0_vsync3),
>+	MSM_PIN_FUNCTION(mdp0_vsync6),
>+	MSM_PIN_FUNCTION(mdp0_vsync7),
>+	MSM_PIN_FUNCTION(mdp_vsync),
>+	MSM_PIN_FUNCTION(mi2s1_data0),
>+	MSM_PIN_FUNCTION(mi2s1_data1),
>+	MSM_PIN_FUNCTION(mi2s1_sck),
>+	MSM_PIN_FUNCTION(mi2s1_ws),
>+	MSM_PIN_FUNCTION(mi2s2_data0),
>+	MSM_PIN_FUNCTION(mi2s2_data1),
>+	MSM_PIN_FUNCTION(mi2s2_sck),
>+	MSM_PIN_FUNCTION(mi2s2_ws),
>+	MSM_PIN_FUNCTION(mi2s_mclk0),
>+	MSM_PIN_FUNCTION(mi2s_mclk1),
>+	MSM_PIN_FUNCTION(pcie0_clkreq),
>+	MSM_PIN_FUNCTION(pcie1_clkreq),
>+	MSM_PIN_FUNCTION(phase_flag),
>+	MSM_PIN_FUNCTION(pll_bist),
>+	MSM_PIN_FUNCTION(pll_clk),
>+	MSM_PIN_FUNCTION(prng_rosc0),
>+	MSM_PIN_FUNCTION(prng_rosc1),
>+	MSM_PIN_FUNCTION(prng_rosc2),
>+	MSM_PIN_FUNCTION(prng_rosc3),
>+	MSM_PIN_FUNCTION(qdss_cti),
>+	MSM_PIN_FUNCTION(qdss_gpio),
>+	MSM_PIN_FUNCTION(qup0_se0),
>+	MSM_PIN_FUNCTION(qup0_se1),
>+	MSM_PIN_FUNCTION(qup0_se2),
>+	MSM_PIN_FUNCTION(qup0_se3),
>+	MSM_PIN_FUNCTION(qup0_se4),
>+	MSM_PIN_FUNCTION(qup0_se5),
>+	MSM_PIN_FUNCTION(qup0_se6),
>+	MSM_PIN_FUNCTION(qup0_se7),
>+	MSM_PIN_FUNCTION(qup1_se0),
>+	MSM_PIN_FUNCTION(qup1_se1),
>+	MSM_PIN_FUNCTION(qup1_se2),
>+	MSM_PIN_FUNCTION(qup1_se3),
>+	MSM_PIN_FUNCTION(qup1_se4),
>+	MSM_PIN_FUNCTION(qup1_se5),
>+	MSM_PIN_FUNCTION(qup1_se6),
>+	MSM_PIN_FUNCTION(qup1_se7),
>+	MSM_PIN_FUNCTION(qup2_se0),
>+	MSM_PIN_FUNCTION(sailss_emac0),
>+	MSM_PIN_FUNCTION(sailss_ospi),
>+	MSM_PIN_FUNCTION(sgmii_phy),
>+	MSM_PIN_FUNCTION(tb_trig),
>+	MSM_PIN_FUNCTION(tgu_ch0),
>+	MSM_PIN_FUNCTION(tgu_ch1),
>+	MSM_PIN_FUNCTION(tgu_ch2),
>+	MSM_PIN_FUNCTION(tgu_ch3),
>+	MSM_PIN_FUNCTION(tsense_pwm1),
>+	MSM_PIN_FUNCTION(tsense_pwm2),
>+	MSM_PIN_FUNCTION(tsense_pwm3),
>+	MSM_PIN_FUNCTION(tsense_pwm4),
>+	MSM_PIN_FUNCTION(usb2phy_ac),
>+	MSM_PIN_FUNCTION(vsense_trigger),
>+};
>+
>+static const msm_pin_function qcs8300_pin_functions[] = {
>+	[0] = PINGROUP(0, _, _, _, _, _, _, _, _, _, _, _),
>+	[1] = PINGROUP(1, pcie0_clkreq, _, _, _, _, _, _, _, _, _, _),
>+	[2] = PINGROUP(2, _, _, _, _, _, _, _, _, _, _, _),
>+	[3] = PINGROUP(3, phase_flag, _, _, _, _, _, _, _, _, _, _),
>+	[4] = PINGROUP(4, sgmii_phy, qdss_cti, _, _, _, _, _, _, _, _, _),
>+	[5] = PINGROUP(5, emac0_mdc, qdss_cti, _, _, _, _, _, _, _, _, _),
>+	[6] = PINGROUP(6, emac0_mdio, _, _, _, _, _, _, _, _, _, _),
>+	[7] = PINGROUP(7, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
>+	[8] = PINGROUP(8, usb2phy_ac, _, _, _, _, _, _, _, _, _, _),
>+	[9] = PINGROUP(9, phase_flag, _, _, _, _, _, _, _, _, _, _),
>+	[10] = PINGROUP(10, qup2_se0, emac0_mcg0, _, _, _, _, _, _, _, _, _),
>+	[11] = PINGROUP(11, qup2_se0, emac0_mcg1, _, _, _, _, _, _, _, _, _),
>+	[12] = PINGROUP(12, qup2_se0, _, _, _, _, _, _, _, _, _, _),
>+	[13] = PINGROUP(13, qup2_se0, _, _, _, _, _, _, _, _, _, _),
>+	[14] = PINGROUP(14, qup2_se0, tb_trig, _, _, _, _, _, _, _, _, _),
>+	[15] = PINGROUP(15, qup2_se0, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _, _),
>+	[16] = PINGROUP(16, qup2_se0, _, _, sailss_ospi, sailss_emac0, _, _, _, _, _, _),
>+	[17] = PINGROUP(17, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
>+	[18] = PINGROUP(18, qup0_se0, qup0_se1, ibi_i3c, _, _, _, _, _, _, _, _),
>+	[19] = PINGROUP(19, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
>+	[20] = PINGROUP(20, qup0_se1, qup0_se0, cci_timer, ibi_i3c, _, _, _, _, _, _, _),
>+	[21] = PINGROUP(21, qup0_se5, cci_timer, _, _, _, _, _, _, _, _, _),
>+	[22] = PINGROUP(22, pcie1_clkreq, qup0_se5, cci_timer, _, _, _, _, _, _, _, _),
>+	[23] = PINGROUP(23, qup0_se5, cci_timer, qdss_cti, _, _, _, _, _, _, _, _),
>+	[24] = PINGROUP(24, qup0_se5, emac0_ptp_aux, emac0_ptp_pps, qdss_cti, emac0_mcg2, _, _, _, _, _, _),
>+	[25] = PINGROUP(25, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
>+	[26] = PINGROUP(26, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
>+	[27] = PINGROUP(27, qup0_se3, _, _, _, _, _, _, _, _, _, _),
>+	[28] = PINGROUP(28, qup0_se3, phase_flag, _, _, _, _, _, _, _, _, _),
>+	[29] = PINGROUP(29, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_pps, tgu_ch2, _, _, _, _, _, _),
>+	[30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, tgu_ch3, _, _, _, _, _, _),
>+	[31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _),
>+	[32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _),
>+	[33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
>+	[34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _),
>+	[35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _),
>+	[36] = PINGROUP(36, qup0_se2, gcc_gp2, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[37] = PINGROUP(37, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
>+	[38] = PINGROUP(38, qup1_se0, ibi_i3c, qup1_se1, aoss_cti, _, _, _, _, _, _, _),
>+	[39] = PINGROUP(39, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
>+	[40] = PINGROUP(40, qup1_se1, ibi_i3c, qup1_se0, aoss_cti, _, _, _, _, _, _, _),
>+	[41] = PINGROUP(41, qup1_se3, _, _, _, _, _, _, _, _, _, _),
>+	[42] = PINGROUP(42, qup1_se3, _, mdp_vsync, _, _, _, _, _, _, _, _),
>+	[43] = PINGROUP(43, qup0_se7, _, tgu_ch0, _, _, _, _, _, _, _, _),
>+	[44] = PINGROUP(44, qup0_se7, _, tgu_ch1, _, _, _, _, _, _, _, _),
>+	[45] = PINGROUP(45, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
>+	[46] = PINGROUP(46, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
>+	[47] = PINGROUP(47, qup1_se4, hs1_mi2s, _, _, _, _, _, _, _, _, _),
>+	[48] = PINGROUP(48, qup1_se4, hs1_mi2s, edp0_lcd, _, _, _, _, _, _, _, _),
>+	[49] = PINGROUP(49, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, edp1_lcd, ddr_pxi1, _, _, _, _, _),
>+	[50] = PINGROUP(50, qup1_se5, hs2_mi2s, cci_timer, qdss_cti, _, ddr_pxi1, _, _, _, _, _),
>+	[51] = PINGROUP(51, qup1_se5, hs2_mi2s, qdss_cti, _, _, _, _, _, _, _, _),
>+	[52] = PINGROUP(52, qup1_se5, hs2_mi2s, qdss_cti, mdp_vsync, ddr_pxi2, _, _, _, _, _, _),
>+	[53] = PINGROUP(53, ddr_bist, _, _, _, _, _, _, _, _, _, _),
>+	[54] = PINGROUP(54, cci_i2c_sda, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
>+	[55] = PINGROUP(55, cci_i2c_scl, phase_flag, ddr_bist, _, _, _, _, _, _, _, _),
>+	[56] = PINGROUP(56, phase_flag, ddr_bist, _, _, _, _, _, _, _, _, _),
>+	[57] = PINGROUP(57, cci_i2c_sda, prng_rosc0, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[58] = PINGROUP(58, cci_i2c_scl, prng_rosc1, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[59] = PINGROUP(59, cci_i2c_sda, prng_rosc2, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[60] = PINGROUP(60, cci_i2c_scl, prng_rosc3, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[61] = PINGROUP(61, cci_i2c_sda, qdss_gpio, _, _, _, _, _, _, _, _, _),
>+	[62] = PINGROUP(62, cci_i2c_scl, qdss_gpio, _, _, _, _, _, _, _, _, _),
>+	[63] = PINGROUP(63, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
>+	[64] = PINGROUP(64, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
>+	[65] = PINGROUP(65, cci_timer, cci_async, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
>+	[66] = PINGROUP(66, phase_flag, _, atest_char, _, _, _, _, _, _, _, _),
>+	[67] = PINGROUP(67, cam_mclk, vsense_trigger, atest_usb2, _, _, _, _, _, _, _, _),
>+	[68] = PINGROUP(68, cam_mclk, gcc_gp4, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
>+	[69] = PINGROUP(69, cam_mclk, gcc_gp3, atest_usb2, ddr_pxi0, _, _, _, _, _, _, _),
>+	[70] = PINGROUP(70, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
>+	[71] = PINGROUP(71, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
>+	[72] = PINGROUP(72, qdss_gpio, atest_char, _, _, _, _, _, _, _, _, _),
>+	[73] = PINGROUP(73, _, qdss_gpio, _, _, _, _, _, _, _, _, _),
>+	[74] = PINGROUP(74, pll_clk, qdss_gpio, atest_usb2, _, _, _, _, _, _, _, _),
>+	[75] = PINGROUP(75, _, dbg_out, qdss_gpio, atest_usb2, _, _, _, _, _, _, _),
>+	[76] = PINGROUP(76, gcc_gp5, tsense_pwm4, _, _, _, _, _, _, _, _, _),
>+	[77] = PINGROUP(77, gcc_gp5, tsense_pwm3, _, _, _, _, _, _, _, _, _),
>+	[78] = PINGROUP(78, tsense_pwm2, _, _, _, _, _, _, _, _, _, _),
>+	[79] = PINGROUP(79, emac0_ptp_aux, emac0_ptp_pps, emac0_mcg3, _, tsense_pwm1, _, _, _, _, _, _),
>+	[80] = PINGROUP(80, qup0_se6, mdp0_vsync6, _, atest_usb2, ddr_pxi3, _, _, _, _, _, _),
>+	[81] = PINGROUP(81, qup0_se6, mdp0_vsync7, gcc_gp2, _, atest_usb2, ddr_pxi3, _, _, _, _, _),
>+	[82] = PINGROUP(82, qup0_se6, gcc_gp3, _, _, _, _, _, _, _, _, _),
>+	[83] = PINGROUP(83, qup0_se6, gcc_gp4, _, atest_usb2, ddr_pxi2, _, _, _, _, _, _),
>+	[84] = PINGROUP(84, qup1_se2, gcc_gp1, _, atest_usb2, _, _, _, _, _, _, _),
>+	[85] = PINGROUP(85, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
>+	[86] = PINGROUP(86, qup1_se2, _, _, _, _, _, _, _, _, _, _),
>+	[87] = PINGROUP(87, qup1_se2, _, atest_usb2, _, _, _, _, _, _, _, _),
>+	[88] = PINGROUP(88, qup1_se2, _, _, _, _, _, _, _, _, _, _),
>+	[89] = PINGROUP(89, qup1_se6, qup1_se7, mdp0_vsync0, _, _, _, _, _, _, _, _),
>+	[90] = PINGROUP(90, qup1_se6, qup1_se7, mdp0_vsync1, cri_trng, _, _, _, _, _, _, _),
>+	[91] = PINGROUP(91, qup1_se7, qup1_se6, mdp0_vsync3, cri_trng, _, _, _, _, _, _, _),
>+	[92] = PINGROUP(92, qup1_se7, qup1_se6, cri_trng, _, atest_usb2, _, _, _, _, _, _),
>+	[93] = PINGROUP(93, atest_char, _, _, _, _, _, _, _, _, _, _),
>+	[94] = PINGROUP(94, edp0_hot, _, _, _, _, _, _, _, _, _, _),
>+	[95] = PINGROUP(95, _, _, _, _, _, _, _, _, _, _, _),
>+	[96] = PINGROUP(96, _, _, _, _, _, _, _, _, _, _, _),
>+	[97] = PINGROUP(97, mi2s_mclk0, jitter_bist, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[98] = PINGROUP(98, mi2s1_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[99] = PINGROUP(99, mi2s1_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[100] = PINGROUP(100, mi2s1_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[101] = PINGROUP(101, mi2s1_data1, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[102] = PINGROUP(102, mi2s2_sck, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[103] = PINGROUP(103, mi2s2_ws, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[104] = PINGROUP(104, mi2s2_data0, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[105] = PINGROUP(105, mi2s2_data1, audio_ref, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
>+	[106] = PINGROUP(106, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[107] = PINGROUP(107, hs0_mi2s, pll_bist, phase_flag, _, qdss_gpio, _, _, _, _, _, _),
>+	[108] = PINGROUP(108, hs0_mi2s, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _),
>+	[109] = PINGROUP(109, hs0_mi2s, mi2s_mclk1, qdss_gpio, _, _, _, _, _, _, _, _),
>+	[110] = PINGROUP(110, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
>+	[111] = PINGROUP(111, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
>+	[112] = PINGROUP(112, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
>+	[113] = PINGROUP(113, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
>+	[114] = PINGROUP(114, phase_flag, _, qdss_gpio, _, _, _, _, _, _, _, egpio),
>+	[115] = PINGROUP(115, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[116] = PINGROUP(116, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[117] = PINGROUP(117, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[118] = PINGROUP(118, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[119] = PINGROUP(119, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[120] = PINGROUP(120, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[121] = PINGROUP(121, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[122] = PINGROUP(122, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[123] = PINGROUP(123, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[124] = PINGROUP(124, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[125] = PINGROUP(125, phase_flag, _, _, _, _, _, _, _, _, _, egpio),
>+	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _, _, egpio),
>+	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _, _, egpio),
>+};
>+
>+static const struct msm_special_pin_data qcs8300_special_pins_data[] = {
>+	[0] = UFS_RESET("ufs_reset", 0x92000),
>+	[1] = SDC_QDSD_PINGROUP("sdc1_rclk", 0x89000, 15, 0),
>+	[2] = SDC_QDSD_PINGROUP("sdc1_clk", 0x89000, 13, 6),
>+	[3] = SDC_QDSD_PINGROUP("sdc1_cmd", 0x89000, 11, 3),
>+	[4] = SDC_QDSD_PINGROUP("sdc1_data", 0x89000, 9, 0),
>+};
>+
>+static const char *qcs8300_get_function_name(struct udevice *dev,
>+					     unsigned int selector)
>+{
>+	return msm_pinctrl_functions[selector].name;
>+}
>+
>+static const char *qcs8300_get_pin_name(struct udevice *dev,
>+					unsigned int selector)
>+{
>+	if (selector >= 133 && selector <= 137)
>+		snprintf(pin_name, MAX_PIN_NAME_LEN, "%s",
>+			 qcs8300_special_pins_data[selector - 133].name);
>+	else
>+		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
>+
>+	return pin_name;
>+}
>+
>+static int qcs8300_get_function_mux(__maybe_unused unsigned int pin,
>+				    unsigned int selector)
>+{
>+	unsigned int i;
>+	const msm_pin_function *func = qcs8300_pin_functions + pin;
>+
>+	for (i = 0; i < MSM_PIN_FUNCTION_COUNT; i++)
>+		if ((*func)[i] == selector)
>+			return i;
>+
>+	pr_err("Can't find requested function for pin %u\n", pin);
>+
>+	return -EINVAL;
>+}
>+
>+static const struct msm_pinctrl_data qcs8300_data = {
>+	.pin_data = {
>+		.pin_count = 138,
>+		.special_pins_start = 133,
>+		.special_pins_data = qcs8300_special_pins_data,
>+	},
>+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
>+	.get_function_name = qcs8300_get_function_name,
>+	.get_function_mux = qcs8300_get_function_mux,
>+	.get_pin_name = qcs8300_get_pin_name,
>+};
>+
>+static const struct udevice_id msm_pinctrl_ids[] = {
>+	{
>+		.compatible = "qcom,qcs8300-tlmm",
>+		.data = (ulong)&qcs8300_data
>+	},
>+	{ /* Sentinel */ }
>+};
>+
>+U_BOOT_DRIVER(pinctrl_qcs8300) = {
>+	.name		= "pinctrl_qcs8300",
>+	.id		= UCLASS_NOP,
>+	.of_match	= msm_pinctrl_ids,
>+	.ops		= &msm_pinctrl_ops,
>+	.bind		= msm_pinctrl_bind,
>+	.flags		= DM_FLAG_PRE_RELOC,
>+};
>
>-- 
>2.34.1
>

Re: [PATCH v2 5/7] arm64: dts: monaco-evk: Add reboot-mode support via PON/SDAM

[Sumit Garg]

On Wed, 12 Aug 2026 at 06:42:03 +0530, Balaji Selvanathan wrote:
>monaco-pmics.dtsi has no PON/SDAM reboot-reason storage, so
>U-Boot can't read the reboot-reason to tell if it should stop in
>fastboot instead of booting the kernel.
>
>Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>---
> arch/arm/dts/monaco-evk-u-boot.dtsi | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)

Avoid adding DTS changes for targets that aren't yet accepted upstream.
Try to keep patch-sets independent such that they are easier to land.

-Sumit

>
>diff --git a/arch/arm/dts/monaco-evk-u-boot.dtsi b/arch/arm/dts/monaco-evk-u-boot.dtsi
>new file mode 100644
>index 00000000000..5520d111864
>--- /dev/null
>+++ b/arch/arm/dts/monaco-evk-u-boot.dtsi
>@@ -0,0 +1,36 @@
>+// SPDX-License-Identifier: BSD-3-Clause
>+/*
>+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
>+ */
>+
>+/ {
>+	reboot-mode {
>+		compatible = "nvmem-reboot-mode";
>+		nvmem-cells = <&reboot_reason>;
>+		nvmem-cell-names = "reboot-mode";
>+
>+		mode-bootloader = <0x02>;
>+		mode-recovery   = <0x01>;
>+	};
>+};
>+
>+&pmm8620au_0 {
>+	pmm8620au_0_pon: pon@1200 {
>+		compatible = "qcom,pmk8350-pon";
>+		reg = <0x1200>, <0x800>;
>+		reg-names = "hlos", "pbs";
>+	};
>+
>+	pmm8620au_0_sdam_0: nvram@7100 {
>+		compatible = "qcom,spmi-sdam";
>+		reg = <0x7100>;
>+		#address-cells = <1>;
>+		#size-cells = <1>;
>+		ranges = <0x0 0x7100 0x100>;
>+
>+		reboot_reason: reboot-reason@48 {
>+			reg = <0x48 0x1>;
>+			bits = <1 7>;
>+		};
>+	};
>+};
>
>-- 
>2.34.1
>

Re: [PATCH v2 6/7] arm64: dts: monaco-evk: Force vreg_l8a always-on to protect UFS VCC

[Sumit Garg]

On Wed, 12 Aug 2026 at 06:42:04 +0530, Balaji Selvanathan wrote:
>vreg_l8a is the shared VCC rail for UFS (ufs_mem_hc vcc-supply) and
>eMMC (sdhc_1 vmmc-supply). UFS holds no regulator vote of its own in
>U-Boot, so nothing stops other consumers from disabling the rail
>while UFS still needs it.

Why not teach UFS driver to keep it's regulator vote intact? Don't add
DT workarounds for this.

-Sumit

>
>eMMC's power-cycle runs after UFS has already linked up and started
>transferring data. Its power-off fires a real disable vote on
>vreg_l8a, glitching UFS VCC while the link is live. UFS has no
>recovery from this: every following command fails (OCS errors, UTP
>timeouts, "Card did not respond to voltage select! : -110").
>
>Force the rail always-on so the disable vote is rejected in
>regulator_set_enable() (-EACCES) before it reaches the RPMh driver.
>eMMC is non-removable and does not need a real power-cycle.
>
>Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>---
> arch/arm/dts/monaco-evk-u-boot.dtsi | 4 ++++
> 1 file changed, 4 insertions(+)
>
>diff --git a/arch/arm/dts/monaco-evk-u-boot.dtsi b/arch/arm/dts/monaco-evk-u-boot.dtsi
>index 5520d111864..8e9102eae4d 100644
>--- a/arch/arm/dts/monaco-evk-u-boot.dtsi
>+++ b/arch/arm/dts/monaco-evk-u-boot.dtsi
>@@ -34,3 +34,7 @@
> 		};
> 	};
> };
>+
>+&vreg_l8a {
>+	regulator-always-on;
>+};
>
>-- 
>2.34.1
>

Re: [PATCH v2 7/7] configs: qcom_qcs8300: Switch to monaco-evk DT and enable new drivers

[Sumit Garg]

On Wed, 12 Aug 2026 at 06:42:05 +0530, Balaji Selvanathan wrote:
>Point qcom_qcs8300_defconfig at the monaco-evk device tree and
>turn on required drivers.
>
>Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
>---
> configs/qcom_qcs8300_defconfig | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
>diff --git a/configs/qcom_qcs8300_defconfig b/configs/qcom_qcs8300_defconfig
>index 5fffcddc16e..c8c4ccb9ab2 100644
>--- a/configs/qcom_qcs8300_defconfig
>+++ b/configs/qcom_qcs8300_defconfig

Why not rename this too as qcom_monaco_defconfig like you are doing for
lemans?

>@@ -18,4 +18,8 @@ CONFIG_DEBUG_UART_CLOCK=14745600
> CONFIG_TEXT_BASE=0xaf000000
> CONFIG_REMAKE_ELF=y
>
>-CONFIG_DEFAULT_DEVICE_TREE="qcom/qcs8300-ride"
>+CONFIG_DEFAULT_DEVICE_TREE="qcom/monaco-evk"
>+CONFIG_PINCTRL_QCOM_QCS8300=y
>+CONFIG_INTERCONNECT_QCOM_QCS8300=y
>+
>+CONFIG_WATCHDOG_AUTOSTART=y

I see another series dropping watchdog support, so why add it in the
first place?

-Sumit