Re: [PATCH 4/8] board: sophgo: milkv_duo: add SPL support

[Yao Zi <me@ziyao.cc>]

On Wed, Oct 21, 2026 at 09:54:20AM -0300, Hiago De Franco wrote:
> Wire up SPL for the Milk-V Duo so it no longer depends on the vendor
> FSBL.
> 
> The SPL uses the BootROM ROMAPI to load the FIT image with OpenSBI,
> U-Boot and the device tree, from offset 0x40000 of fip.bin.
> 
> The BootROM loads the SPL into the 100 KiB VC SRAM at 0x3bc00000 and
> jumps past the 32-byte BL2 header, so SPL_TEXT_BASE is 0x3bc00020.
> SPL_MAX_SIZE (0x13fe0) is exactly SPL_BSS_START_ADDR (0x3bc14000) minus
> SPL_TEXT_BASE, so the SPL image cannot grow into its own BSS.
> SPL_BSS_MAX_SIZE (0x1000) caps that 4 KiB BSS, ending at 0x3bc15000, and
> SPL_STACK (0x3bc19000) is the end of the SRAM, leaving 16 KiB below it
> for the stack, the pre-relocation malloc_f pool (SPL_SYS_MALLOC_F_LEN, 8
> KiB) and the global data, as the generic SPL board_init_f flow expects.

Thanks for the helpful explanation, I think it would be better to add
some documentation for the SoC bootflow.

> In DRAM, SPL_OPENSBI_LOAD_ADDR (0x80000000) is the base of RAM: the
> fixed link address OpenSBI's "generic" platform uses for fw_dynamic, and
> the load address given to it in the FIT. SPL_CUSTOM_SYS_MALLOC_ADDR
> (0x81000000) moves the SPL heap into DRAM once it is up, 16 MiB in,
> clear of SYS_LOAD_ADDR (0x80080000), U-Boot's default load address, and
> of TEXT_BASE (0x80200000).
> 
> SPL_SMP is disabled, as only one hart is brought up, and
> SPL_OPENSBI_SCRATCH_OPTIONS is cleared so that OpenSBI prints its boot
> banner, which the default (SBI_SCRATCH_NO_BOOT_PRINTS) hides.

Should we avoid this to keep aligned with other RISC-V boards? The
banner, IMHO, is only meaningful for debugging purpose.

> Signed-off-by: Hiago De Franco <hfranco@baylibre.com>
> ---
>  arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi  | 92 +++++++++++++++++++++++++++
>  arch/riscv/include/asm/arch-cv1800b/rom_api.h | 36 +++++++++++
>  board/sophgo/milkv_duo/Kconfig                |  5 ++
>  board/sophgo/milkv_duo/MAINTAINERS            |  5 +-
>  board/sophgo/milkv_duo/Makefile               |  1 +
>  board/sophgo/milkv_duo/spl.c                  | 76 ++++++++++++++++++++++
>  configs/milkv_duo_defconfig                   | 18 ++++++
>  7 files changed, 232 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi b/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi
> new file mode 100644
> index 00000000000..7f9a7a03c5d
> --- /dev/null
> +++ b/arch/riscv/dts/cv1800b-milkv-duo-u-boot.dtsi
> @@ -0,0 +1,92 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2026, Hiago De Franco <hfranco@baylibre.com>
> + */

...

> +&uart0 {
> +	bootph-pre-ram;
> +	clock-frequency = <25000000>;

The upstream UART 8250 binding disallows clocks and clock-frequency
to co-exist, and with current Linux drivers, it does cause issues, see
this series[1].

If you worry about the burden of introducing clock related stuff to SPL,
consider define CFG_SYS_NS16550_CLK in the board configuration header
instead.

...

Best regards,
Yao Zi

[1]: https://lore.kernel.org/all/20250623093445.62327-1-ziyao@disroot.org/