Re: [PATCH 6/8] board: sophgo: milkv_duo: enable RTC power and reset

[Yao Zi <me@ziyao.cc>]

On Tue, Nov 03, 2026 at 02:31:51PM -0300, João Paulo Gonçalves wrote:
> On Wed, Oct 21, 2026 at 09:54:22AM -0300, Hiago De Franco wrote:
> > Let the RTC power domain handle shutdown, warm reset, power-cycle and
> > watchdog reset requests, and stop the board from powering back on by
> > itself after a power off.
> > 
> > Without this, the reset and poweroff paths are left in their BootROM
> > defaults, which do not match what the vendor FSBL configures.
> > 
> > Signed-off-by: Hiago De Franco <hfranco@baylibre.com>
> > ---
> >  board/sophgo/milkv_duo/spl.c | 53 +++++++++++++++++++++++++++++++++++++++++++-
> >  1 file changed, 52 insertions(+), 1 deletion(-)
> > 
> > diff --git a/board/sophgo/milkv_duo/spl.c b/board/sophgo/milkv_duo/spl.c
> > index 8b2dc2756ae..97681e5a61b 100644
> > --- a/board/sophgo/milkv_duo/spl.c
> > +++ b/board/sophgo/milkv_duo/spl.c
> > @@ -2,7 +2,7 @@
> >  /*
> >   * Copyright (c) 2026, Hiago De Franco <hfranco@baylibre.com>
> >   *
> > - * PLL setup based on the Sophgo FSBL (https://github.com/sophgo/fsbl),
> > + * PLL and RTC setup based on the Sophgo FSBL (https://github.com/sophgo/fsbl),
> >   * plat/cv180x/platform.c.
> >   */
> >  
> > @@ -13,7 +13,9 @@
> >  #include <hang.h>
> >  #include <linux/bitops.h>
> >  #include <linux/delay.h>
> > +#include <linux/iopoll.h>
> >  #include <linux/kernel.h>
> > +#include <log.h>
> >  #include <spl.h>
> >  #include <spl_load.h>
> >  
> > @@ -52,6 +54,25 @@
> >  #define CLK_DIV(div, src)		(((div) << 16) | ((src) << 8) | BIT(3) | BIT(0))
> >  #define clkgen_reg(off)			((void __iomem *)(CLKGEN_BASE + (off)))
> >  
> > +#define RTC_BASE			0x05026000UL
> > +#define RTC_EN_SHDN_REQ			0x0c0
> > +#define RTC_EN_PWR_CYC_REQ		0x0c8
> > +#define RTC_EN_WARM_RST_REQ		0x0cc
> > +#define RTC_EN_PWR_VBAT_DET		0x0d0
> > +#define  RTC_EN_PWR_VBAT_DET_PWR_UP	BIT(2)
> > +#define RTC_EN_WDT_RST_REQ		0x0e0
> > +#define RTC_CTRL_BASE			0x05025000UL
> > +#define RTC_CTRL0_UNLOCKKEY		0x004
> > +#define  RTC_CTRL0_UNLOCKKEY_VAL	0xab18
> > +#define RTC_CTRL0			0x008
> > +#define  RTC_CTRL0_WRITE_MASK		GENMASK(31, 16)
> > +#define  RTC_CTRL0_HW_WDG_RST_EN	BIT(11)
> > +#define RTC_POR_RST_CTRL		0x0ac
> > +#define RTC_EN_REQ_TIMEOUT_US		100000
> > +
> > +#define rtc_reg(off)			((void __iomem *)(RTC_BASE + (off)))
> > +#define rtc_ctrl_reg(off)		((void __iomem *)(RTC_CTRL_BASE + (off)))
> 
> Instead of hardcoding the bases here, could we get them from the DT? The
> upstream cv18xx.dtsi already has the RTC node (rtc@5025000, with
> "syscon" in its compatible), and its range covers both RTC_CTRL_BASE and
> RTC_BASE. Also, use syscon/regmap in SPL (CONFIG_SPL_SYSCON and
> CONFIG_SPL_REGMAP) to read/write the registers.
> 
> Just a suggestion though, I'll leave it to the maintainers to decide.

I'll second the idea of handling RTC stuff in its driver, and I think it
doesn't even need being configured at the SPL stage, right?

...

> Best regards,
> João Paulo Gonçalves

Regards,
Yao Zi