* [PATCH] ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers
@ 2025-03-20 9:13 Michal Simek
2025-03-28 14:55 ` Michal Simek
0 siblings, 1 reply; 2+ messages in thread
From: Michal Simek @ 2025-03-20 9:13 UTC (permalink / raw)
To: u-boot, git
Cc: Venkatesh Yadav Abbarapu, Bhupesh Sharma, Ilias Apalodimas,
Neha Malcom Francis, Neil Armstrong, Prasad Kummari, Simon Glass,
Tom Rini
From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
read/write to the pmc_iou_slcr and efuse_cache registers. Replace
these raw reads/writes with the xilinx_pm_request() API with the
correct arguments once the PM related changes are done.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
---
arch/arm/mach-versal2/include/mach/hardware.h | 6 ++
drivers/firmware/firmware-zynqmp.c | 28 ++++++++
drivers/ufs/ufs-amd-versal2.c | 66 ++++---------------
include/zynqmp_firmware.h | 4 ++
4 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
index a961032b4d5b..7ca2bbb7550f 100644
--- a/arch/arm/mach-versal2/include/mach/hardware.h
+++ b/arch/arm/mach-versal2/include/mach/hardware.h
@@ -97,3 +97,9 @@ enum versal2_platform {
#define MIO_PIN_12 0xF1060030
#define BANK0_OUTPUT 0xF1020040
#define BANK0_TRI 0xF1060200
+
+#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000
+#define PMXC_SLCR_BASE_ADDRESS 0xF1061000
+#define PMXC_UFS_CAL_1_OFFSET 0xBE8
+#define PMXC_SRAM_CSR 0x4C
+#define PMXC_TX_RX_CFG_RDY 0x54
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 584397ba29a3..2940181e83e9 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -5,6 +5,8 @@
* Copyright (C) 2018-2019 Xilinx, Inc.
*/
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
#include <cpu_func.h>
#include <dm.h>
#include <dm/device_compat.h>
@@ -169,6 +171,32 @@ unsigned int zynqmp_firmware_version(void)
return pm_api_version;
};
+#if defined(CONFIG_ARCH_VERSAL2)
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_read(u32 *value)
+{
+ *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_sram_csr_write(u32 *value)
+{
+ writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
+ return 0;
+}
+
+int zynqmp_pm_ufs_cal_reg(u32 *value)
+{
+ *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET);
+ return 0;
+}
+#endif
+
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value)
{
int ret;
diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c
index bfd844e41938..1c5ed538370e 100644
--- a/drivers/ufs/ufs-amd-versal2.c
+++ b/drivers/ufs/ufs-amd-versal2.c
@@ -19,8 +19,6 @@
#include "ufshcd-dwc.h"
#include "ufshci-dwc.h"
-#define VERSAL2_UFS_DEVICE_ID 4
-
#define SRAM_CSR_INIT_DONE_MASK BIT(0)
#define SRAM_CSR_EXT_LD_DONE_MASK BIT(1)
#define SRAM_CSR_BYPASS_MASK BIT(2)
@@ -32,19 +30,12 @@
#define TIMEOUT_MICROSEC 1000000L
-#define IOCTL_UFS_TXRX_CFGRDY_GET 40
-#define IOCTL_UFS_SRAM_CSR_SEL 41
-
-#define PM_UFS_SRAM_CSR_WRITE 0
-#define PM_UFS_SRAM_CSR_READ 1
-
struct ufs_versal2_priv {
struct ufs_hba *hba;
struct reset_ctl *rstc;
struct reset_ctl *rstphy;
u32 phy_mode;
u32 host_clk;
- u32 pd_dev_id;
u8 attcompval0;
u8 attcompval1;
u8 ctlecompval0;
@@ -102,41 +93,6 @@ static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
return 0;
}
-int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET,
- 0, 0, ret_payload);
- *value = ret_payload[1];
-
- return ret;
-}
-
-int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value)
-{
- u32 ret_payload[PAYLOAD_ARG_CNT];
- int ret;
-
- if (!value)
- return -EINVAL;
-
- if (type == PM_UFS_SRAM_CSR_READ) {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, 0, ret_payload);
- *value = ret_payload[1];
- } else {
- ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
- type, *value, 0);
- }
-
- return ret;
-}
-
static int ufs_versal2_enable_phy(struct ufs_hba *hba)
{
u32 offset, reg;
@@ -281,7 +237,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba)
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®);
+ ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®);
if (ret)
return ret;
@@ -312,8 +268,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba)
time_left = TIMEOUT_MICROSEC;
do {
time_left--;
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, ®);
+ ret = zynqmp_pm_ufs_sram_csr_read(®);
if (ret)
return ret;
@@ -341,10 +296,10 @@ static int ufs_versal2_init(struct ufs_hba *hba)
struct ufs_versal2_priv *priv = dev_get_priv(hba->dev);
struct clk clk;
unsigned long core_clk_rate = 0;
+ u32 cal;
int ret = 0;
priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
- priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID;
ret = clk_get_by_name(hba->dev, "core_clk", &clk);
if (ret) {
@@ -371,6 +326,15 @@ static int ufs_versal2_init(struct ufs_hba *hba)
return PTR_ERR(priv->rstphy);
}
+ ret = zynqmp_pm_ufs_cal_reg(&cal);
+ if (ret)
+ return ret;
+
+ priv->attcompval0 = (u8)cal;
+ priv->attcompval1 = (u8)(cal >> 8);
+ priv->ctlecompval0 = (u8)(cal >> 16);
+ priv->ctlecompval1 = (u8)(cal >> 24);
+
return ret;
}
@@ -397,8 +361,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba,
return ret;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_READ, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr);
if (ret)
return ret;
@@ -410,8 +373,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba,
return -EINVAL;
}
- ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
- PM_UFS_SRAM_CSR_WRITE, &sram_csr);
+ ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr);
if (ret)
return ret;
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 82781dfd16bc..dc06abc52fce 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -458,6 +458,10 @@ int zynqmp_mmio_read(const u32 address, u32 *value);
int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_pm_feature(const u32 api_id);
u32 zynqmp_pm_get_bootmode_reg(void);
+int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value);
+int zynqmp_pm_ufs_sram_csr_read(u32 *value);
+int zynqmp_pm_ufs_sram_csr_write(u32 *value);
+int zynqmp_pm_ufs_cal_reg(u32 *value);
u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
/* Type of Config Object */
--
2.43.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers
2025-03-20 9:13 [PATCH] ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers Michal Simek
@ 2025-03-28 14:55 ` Michal Simek
0 siblings, 0 replies; 2+ messages in thread
From: Michal Simek @ 2025-03-28 14:55 UTC (permalink / raw)
To: u-boot, git
Cc: Venkatesh Yadav Abbarapu, Bhupesh Sharma, Ilias Apalodimas,
Neha Malcom Francis, Neil Armstrong, Prasad Kummari, Simon Glass,
Tom Rini
On 3/20/25 10:13, Michal Simek wrote:
> From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
>
> Update the firmware driver UFS APIs zynqmp_pm_ufs_* to directly
> read/write to the pmc_iou_slcr and efuse_cache registers. Replace
> these raw reads/writes with the xilinx_pm_request() API with the
> correct arguments once the PM related changes are done.
>
> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
>
> arch/arm/mach-versal2/include/mach/hardware.h | 6 ++
> drivers/firmware/firmware-zynqmp.c | 28 ++++++++
> drivers/ufs/ufs-amd-versal2.c | 66 ++++---------------
> include/zynqmp_firmware.h | 4 ++
> 4 files changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h
> index a961032b4d5b..7ca2bbb7550f 100644
> --- a/arch/arm/mach-versal2/include/mach/hardware.h
> +++ b/arch/arm/mach-versal2/include/mach/hardware.h
> @@ -97,3 +97,9 @@ enum versal2_platform {
> #define MIO_PIN_12 0xF1060030
> #define BANK0_OUTPUT 0xF1020040
> #define BANK0_TRI 0xF1060200
> +
> +#define PMXC_EFUSE_CACHE_BASE_ADDRESS 0xF1250000
> +#define PMXC_SLCR_BASE_ADDRESS 0xF1061000
> +#define PMXC_UFS_CAL_1_OFFSET 0xBE8
> +#define PMXC_SRAM_CSR 0x4C
> +#define PMXC_TX_RX_CFG_RDY 0x54
> diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
> index 584397ba29a3..2940181e83e9 100644
> --- a/drivers/firmware/firmware-zynqmp.c
> +++ b/drivers/firmware/firmware-zynqmp.c
> @@ -5,6 +5,8 @@
> * Copyright (C) 2018-2019 Xilinx, Inc.
> */
>
> +#include <asm/arch/hardware.h>
> +#include <asm/io.h>
> #include <cpu_func.h>
> #include <dm.h>
> #include <dm/device_compat.h>
> @@ -169,6 +171,32 @@ unsigned int zynqmp_firmware_version(void)
> return pm_api_version;
> };
>
> +#if defined(CONFIG_ARCH_VERSAL2)
> +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value)
> +{
> + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_TX_RX_CFG_RDY);
> + return 0;
> +}
> +
> +int zynqmp_pm_ufs_sram_csr_read(u32 *value)
> +{
> + *value = readl(PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
> + return 0;
> +}
> +
> +int zynqmp_pm_ufs_sram_csr_write(u32 *value)
> +{
> + writel(*value, PMXC_SLCR_BASE_ADDRESS + PMXC_SRAM_CSR);
> + return 0;
> +}
> +
> +int zynqmp_pm_ufs_cal_reg(u32 *value)
> +{
> + *value = readl(PMXC_EFUSE_CACHE_BASE_ADDRESS + PMXC_UFS_CAL_1_OFFSET);
> + return 0;
> +}
> +#endif
> +
> int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value)
> {
> int ret;
> diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c
> index bfd844e41938..1c5ed538370e 100644
> --- a/drivers/ufs/ufs-amd-versal2.c
> +++ b/drivers/ufs/ufs-amd-versal2.c
> @@ -19,8 +19,6 @@
> #include "ufshcd-dwc.h"
> #include "ufshci-dwc.h"
>
> -#define VERSAL2_UFS_DEVICE_ID 4
> -
> #define SRAM_CSR_INIT_DONE_MASK BIT(0)
> #define SRAM_CSR_EXT_LD_DONE_MASK BIT(1)
> #define SRAM_CSR_BYPASS_MASK BIT(2)
> @@ -32,19 +30,12 @@
>
> #define TIMEOUT_MICROSEC 1000000L
>
> -#define IOCTL_UFS_TXRX_CFGRDY_GET 40
> -#define IOCTL_UFS_SRAM_CSR_SEL 41
> -
> -#define PM_UFS_SRAM_CSR_WRITE 0
> -#define PM_UFS_SRAM_CSR_READ 1
> -
> struct ufs_versal2_priv {
> struct ufs_hba *hba;
> struct reset_ctl *rstc;
> struct reset_ctl *rstphy;
> u32 phy_mode;
> u32 host_clk;
> - u32 pd_dev_id;
> u8 attcompval0;
> u8 attcompval1;
> u8 ctlecompval0;
> @@ -102,41 +93,6 @@ static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val)
> return 0;
> }
>
> -int versal2_pm_ufs_get_txrx_cfgrdy(u32 node_id, u32 *value)
> -{
> - u32 ret_payload[PAYLOAD_ARG_CNT];
> - int ret;
> -
> - if (!value)
> - return -EINVAL;
> -
> - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_TXRX_CFGRDY_GET,
> - 0, 0, ret_payload);
> - *value = ret_payload[1];
> -
> - return ret;
> -}
> -
> -int versal2_pm_ufs_sram_csr_sel(u32 node_id, u32 type, u32 *value)
> -{
> - u32 ret_payload[PAYLOAD_ARG_CNT];
> - int ret;
> -
> - if (!value)
> - return -EINVAL;
> -
> - if (type == PM_UFS_SRAM_CSR_READ) {
> - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
> - type, 0, ret_payload);
> - *value = ret_payload[1];
> - } else {
> - ret = xilinx_pm_request(PM_IOCTL, node_id, IOCTL_UFS_SRAM_CSR_SEL,
> - type, *value, 0);
> - }
> -
> - return ret;
> -}
> -
> static int ufs_versal2_enable_phy(struct ufs_hba *hba)
> {
> u32 offset, reg;
> @@ -281,7 +237,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba)
> time_left = TIMEOUT_MICROSEC;
> do {
> time_left--;
> - ret = versal2_pm_ufs_get_txrx_cfgrdy(priv->pd_dev_id, ®);
> + ret = zynqmp_pm_ufs_get_txrx_cfgrdy(®);
> if (ret)
> return ret;
>
> @@ -312,8 +268,7 @@ static int ufs_versal2_phy_init(struct ufs_hba *hba)
> time_left = TIMEOUT_MICROSEC;
> do {
> time_left--;
> - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
> - PM_UFS_SRAM_CSR_READ, ®);
> + ret = zynqmp_pm_ufs_sram_csr_read(®);
> if (ret)
> return ret;
>
> @@ -341,10 +296,10 @@ static int ufs_versal2_init(struct ufs_hba *hba)
> struct ufs_versal2_priv *priv = dev_get_priv(hba->dev);
> struct clk clk;
> unsigned long core_clk_rate = 0;
> + u32 cal;
> int ret = 0;
>
> priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
> - priv->pd_dev_id = VERSAL2_UFS_DEVICE_ID;
>
> ret = clk_get_by_name(hba->dev, "core_clk", &clk);
> if (ret) {
> @@ -371,6 +326,15 @@ static int ufs_versal2_init(struct ufs_hba *hba)
> return PTR_ERR(priv->rstphy);
> }
>
> + ret = zynqmp_pm_ufs_cal_reg(&cal);
> + if (ret)
> + return ret;
> +
> + priv->attcompval0 = (u8)cal;
> + priv->attcompval1 = (u8)(cal >> 8);
> + priv->ctlecompval0 = (u8)(cal >> 16);
> + priv->ctlecompval1 = (u8)(cal >> 24);
> +
> return ret;
> }
>
> @@ -397,8 +361,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba,
> return ret;
> }
>
> - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
> - PM_UFS_SRAM_CSR_READ, &sram_csr);
> + ret = zynqmp_pm_ufs_sram_csr_read(&sram_csr);
> if (ret)
> return ret;
>
> @@ -410,8 +373,7 @@ static int ufs_versal2_hce_enable_notify(struct ufs_hba *hba,
> return -EINVAL;
> }
>
> - ret = versal2_pm_ufs_sram_csr_sel(priv->pd_dev_id,
> - PM_UFS_SRAM_CSR_WRITE, &sram_csr);
> + ret = zynqmp_pm_ufs_sram_csr_write(&sram_csr);
> if (ret)
> return ret;
>
> diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
> index 82781dfd16bc..dc06abc52fce 100644
> --- a/include/zynqmp_firmware.h
> +++ b/include/zynqmp_firmware.h
> @@ -458,6 +458,10 @@ int zynqmp_mmio_read(const u32 address, u32 *value);
> int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
> int zynqmp_pm_feature(const u32 api_id);
> u32 zynqmp_pm_get_bootmode_reg(void);
> +int zynqmp_pm_ufs_get_txrx_cfgrdy(u32 *value);
> +int zynqmp_pm_ufs_sram_csr_read(u32 *value);
> +int zynqmp_pm_ufs_sram_csr_write(u32 *value);
> +int zynqmp_pm_ufs_cal_reg(u32 *value);
> u32 zynqmp_pm_get_pmc_multi_boot_reg(void);
>
> /* Type of Config Object */
Applied.
M
^ permalink raw reply [flat|nested] 2+ messages in thread
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2025-03-20 9:13 [PATCH] ufs: amd-versal2: Use raw read/write for SLCR/CACHE registers Michal Simek
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