[PATCH v2 0/2] drivers: clk: n5x: Fix and clean up EMAC clock source selection

[PATCH v2 0/2] drivers: clk: n5x: Fix and clean up EMAC clock source selection

[Chen Huei Lok]

This series fixes the EMAC clock source selection in the N5X clock
driver and then cleans it up to match the Agilex clock driver.

Patch 1 is the functional fix that was sent as v1: the mask was applied
after the shift instead of before, so EMAC always read the clock source
as emaca_free_clk. Patch 2 is a follow-up readability change that
replaces the open-coded mask-and-shift with FIELD_GET(), as suggested by
Tien Fong on the v1 review, aligning N5X with the existing Agilex usage.

Tested on Intel SoCFPGA N5X SoCDK hardware.

v1->v2:
--------
- No functional change to the fix (patch 1).
- New patch 2: use FIELD_GET() for the EMAC clock source select field,
  for consistency with the Agilex clock driver (Tien Fong's review nit).

History:
--------
[v1] https://patchwork.ozlabs.org/project/uboot/patch/20260507090215.18074-1-chen.huei.lok@altera.com/

Chen Huei Lok (2):
  drivers: clk: n5x: Fix incorrect EMAC clock source selection
  drivers: clk: n5x: Use FIELD_GET for EMAC clock source selection

 drivers/clk/altera/clk-n5x.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

--
2.43.7

[PATCH v2 1/2] drivers: clk: n5x: Fix incorrect EMAC clock source selection

[Chen Huei Lok]

Fix the incorrect bit masking and bit shift that caused EMAC to always
get the clock source from emaca_free_clk. The mask must be applied
before shifting, not after.

Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
---

Changes in v2:
- No functional change; resent as patch 1/2 of the series.

 drivers/clk/altera/clk-n5x.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
index 185c9028a78..e0ddaa8e944 100644
--- a/drivers/clk/altera/clk-n5x.c
+++ b/drivers/clk/altera/clk-n5x.c
@@ -325,14 +325,14 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
 	/* Get EMAC clock source */
 	ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
 	if (emac_id == N5X_EMAC0_CLK)
-		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
+		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >>
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET;
 	else if (emac_id == N5X_EMAC1_CLK)
-		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
+		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >>
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET;
 	else if (emac_id == N5X_EMAC2_CLK)
-		ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
+		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >>
+		       CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET;
 	else
 		return 0;
 
-- 
2.43.7

[PATCH v2 2/2] drivers: clk: n5x: Use FIELD_GET for EMAC clock source selection

[Chen Huei Lok]

Replace the open-coded mask-and-shift with FIELD_GET() to extract the
EMAC clock source select bit. This is purely a readability change and
aligns the N5X clock driver with the Agilex clock driver, which already
uses FIELD_GET() for the same register field.

Signed-off-by: Chen Huei Lok <chen.huei.lok@altera.com>
---

Changes in v2:
- New patch: use FIELD_GET() for the EMAC clock source select field, for
  consistency with the Agilex clock driver (Tien Fong's v1 review nit).

 drivers/clk/altera/clk-n5x.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
index e0ddaa8e944..d75c77d5a38 100644
--- a/drivers/clk/altera/clk-n5x.c
+++ b/drivers/clk/altera/clk-n5x.c
@@ -10,6 +10,7 @@
 #include <dm/lists.h>
 #include <dm/util.h>
 #include <dt-bindings/clock/n5x-clock.h>
+#include <linux/bitfield.h>
 
 struct socfpga_clk_plat {
 	void __iomem *regs;
@@ -325,14 +326,11 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
 	/* Get EMAC clock source */
 	ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
 	if (emac_id == N5X_EMAC0_CLK)
-		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK) >>
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET;
+		ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK, ctl);
 	else if (emac_id == N5X_EMAC1_CLK)
-		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK) >>
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET;
+		ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK, ctl);
 	else if (emac_id == N5X_EMAC2_CLK)
-		ctl = (ctl & CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK) >>
-		       CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET;
+		ctl = FIELD_GET(CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK, ctl);
 	else
 		return 0;
 
-- 
2.43.7